1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_execbuf_util.h> 59 60 #include <drm/amdgpu_drm.h> 61 #include <drm/drm_gem.h> 62 #include <drm/drm_ioctl.h> 63 #include <drm/gpu_scheduler.h> 64 65 #include <kgd_kfd_interface.h> 66 #include "dm_pp_interface.h" 67 #include "kgd_pp_interface.h" 68 69 #include "amd_shared.h" 70 #include "amdgpu_mode.h" 71 #include "amdgpu_ih.h" 72 #include "amdgpu_irq.h" 73 #include "amdgpu_ucode.h" 74 #include "amdgpu_ttm.h" 75 #include "amdgpu_psp.h" 76 #include "amdgpu_gds.h" 77 #include "amdgpu_sync.h" 78 #include "amdgpu_ring.h" 79 #include "amdgpu_vm.h" 80 #include "amdgpu_dpm.h" 81 #include "amdgpu_acp.h" 82 #include "amdgpu_uvd.h" 83 #include "amdgpu_vce.h" 84 #include "amdgpu_vcn.h" 85 #include "amdgpu_jpeg.h" 86 #include "amdgpu_mn.h" 87 #include "amdgpu_gmc.h" 88 #include "amdgpu_gfx.h" 89 #include "amdgpu_sdma.h" 90 #include "amdgpu_nbio.h" 91 #include "amdgpu_hdp.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_smu.h" 103 #include "amdgpu_discovery.h" 104 #include "amdgpu_mes.h" 105 #include "amdgpu_umc.h" 106 #include "amdgpu_mmhub.h" 107 #include "amdgpu_gfxhub.h" 108 #include "amdgpu_df.h" 109 #include "amdgpu_smuio.h" 110 #include "amdgpu_hdp.h" 111 112 #define MAX_GPU_INSTANCE 16 113 114 struct amdgpu_gpu_instance 115 { 116 struct amdgpu_device *adev; 117 int mgpu_fan_enabled; 118 }; 119 120 struct amdgpu_mgpu_info 121 { 122 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 123 struct mutex mutex; 124 uint32_t num_gpu; 125 uint32_t num_dgpu; 126 uint32_t num_apu; 127 }; 128 129 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 130 131 /* 132 * Modules parameters. 133 */ 134 extern int amdgpu_modeset; 135 extern int amdgpu_vram_limit; 136 extern int amdgpu_vis_vram_limit; 137 extern int amdgpu_gart_size; 138 extern int amdgpu_gtt_size; 139 extern int amdgpu_moverate; 140 extern int amdgpu_benchmarking; 141 extern int amdgpu_testing; 142 extern int amdgpu_audio; 143 extern int amdgpu_disp_priority; 144 extern int amdgpu_hw_i2c; 145 extern int amdgpu_pcie_gen2; 146 extern int amdgpu_msi; 147 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 148 extern int amdgpu_dpm; 149 extern int amdgpu_fw_load_type; 150 extern int amdgpu_aspm; 151 extern int amdgpu_runtime_pm; 152 extern uint amdgpu_ip_block_mask; 153 extern int amdgpu_bapm; 154 extern int amdgpu_deep_color; 155 extern int amdgpu_vm_size; 156 extern int amdgpu_vm_block_size; 157 extern int amdgpu_vm_fragment_size; 158 extern int amdgpu_vm_fault_stop; 159 extern int amdgpu_vm_debug; 160 extern int amdgpu_vm_update_mode; 161 extern int amdgpu_exp_hw_support; 162 extern int amdgpu_dc; 163 extern int amdgpu_sched_jobs; 164 extern int amdgpu_sched_hw_submission; 165 extern uint amdgpu_pcie_gen_cap; 166 extern uint amdgpu_pcie_lane_cap; 167 extern uint amdgpu_cg_mask; 168 extern uint amdgpu_pg_mask; 169 extern uint amdgpu_sdma_phase_quantum; 170 extern char *amdgpu_disable_cu; 171 extern char *amdgpu_virtual_display; 172 extern uint amdgpu_pp_feature_mask; 173 extern uint amdgpu_force_long_training; 174 extern int amdgpu_job_hang_limit; 175 extern int amdgpu_lbpw; 176 extern int amdgpu_compute_multipipe; 177 extern int amdgpu_gpu_recovery; 178 extern int amdgpu_emu_mode; 179 extern uint amdgpu_smu_memory_pool_size; 180 extern uint amdgpu_dc_feature_mask; 181 extern uint amdgpu_freesync_vid_mode; 182 extern uint amdgpu_dc_debug_mask; 183 extern uint amdgpu_dm_abm_level; 184 extern struct amdgpu_mgpu_info mgpu_info; 185 extern int amdgpu_ras_enable; 186 extern uint amdgpu_ras_mask; 187 extern int amdgpu_bad_page_threshold; 188 extern int amdgpu_async_gfx_ring; 189 extern int amdgpu_mcbp; 190 extern int amdgpu_discovery; 191 extern int amdgpu_mes; 192 extern int amdgpu_noretry; 193 extern int amdgpu_force_asic_type; 194 #ifdef CONFIG_HSA_AMD 195 extern int sched_policy; 196 extern bool debug_evictions; 197 extern bool no_system_mem_limit; 198 #else 199 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 200 static const bool __maybe_unused debug_evictions; /* = false */ 201 static const bool __maybe_unused no_system_mem_limit; 202 #endif 203 204 extern int amdgpu_tmz; 205 extern int amdgpu_reset_method; 206 207 #ifdef CONFIG_DRM_AMDGPU_SI 208 extern int amdgpu_si_support; 209 #endif 210 #ifdef CONFIG_DRM_AMDGPU_CIK 211 extern int amdgpu_cik_support; 212 #endif 213 extern int amdgpu_num_kcq; 214 215 #define AMDGPU_VM_MAX_NUM_CTX 4096 216 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 217 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 218 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 219 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 220 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 221 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 222 #define AMDGPUFB_CONN_LIMIT 4 223 #define AMDGPU_BIOS_NUM_SCRATCH 16 224 225 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 226 227 /* hard reset data */ 228 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 229 230 /* reset flags */ 231 #define AMDGPU_RESET_GFX (1 << 0) 232 #define AMDGPU_RESET_COMPUTE (1 << 1) 233 #define AMDGPU_RESET_DMA (1 << 2) 234 #define AMDGPU_RESET_CP (1 << 3) 235 #define AMDGPU_RESET_GRBM (1 << 4) 236 #define AMDGPU_RESET_DMA1 (1 << 5) 237 #define AMDGPU_RESET_RLC (1 << 6) 238 #define AMDGPU_RESET_SEM (1 << 7) 239 #define AMDGPU_RESET_IH (1 << 8) 240 #define AMDGPU_RESET_VMC (1 << 9) 241 #define AMDGPU_RESET_MC (1 << 10) 242 #define AMDGPU_RESET_DISPLAY (1 << 11) 243 #define AMDGPU_RESET_UVD (1 << 12) 244 #define AMDGPU_RESET_VCE (1 << 13) 245 #define AMDGPU_RESET_VCE1 (1 << 14) 246 247 /* max cursor sizes (in pixels) */ 248 #define CIK_CURSOR_WIDTH 128 249 #define CIK_CURSOR_HEIGHT 128 250 251 struct amdgpu_device; 252 struct amdgpu_ib; 253 struct amdgpu_cs_parser; 254 struct amdgpu_job; 255 struct amdgpu_irq_src; 256 struct amdgpu_fpriv; 257 struct amdgpu_bo_va_mapping; 258 struct amdgpu_atif; 259 struct kfd_vm_fault_info; 260 struct amdgpu_hive_info; 261 262 enum amdgpu_cp_irq { 263 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 264 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 265 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 266 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 267 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 268 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 269 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 270 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 271 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 272 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 273 274 AMDGPU_CP_IRQ_LAST 275 }; 276 277 enum amdgpu_thermal_irq { 278 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 279 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 280 281 AMDGPU_THERMAL_IRQ_LAST 282 }; 283 284 enum amdgpu_kiq_irq { 285 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 286 AMDGPU_CP_KIQ_IRQ_LAST 287 }; 288 289 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 290 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 291 #define MAX_KIQ_REG_TRY 1000 292 293 int amdgpu_device_ip_set_clockgating_state(void *dev, 294 enum amd_ip_block_type block_type, 295 enum amd_clockgating_state state); 296 int amdgpu_device_ip_set_powergating_state(void *dev, 297 enum amd_ip_block_type block_type, 298 enum amd_powergating_state state); 299 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 300 u32 *flags); 301 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 302 enum amd_ip_block_type block_type); 303 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 304 enum amd_ip_block_type block_type); 305 306 #define AMDGPU_MAX_IP_NUM 16 307 308 struct amdgpu_ip_block_status { 309 bool valid; 310 bool sw; 311 bool hw; 312 bool late_initialized; 313 bool hang; 314 }; 315 316 struct amdgpu_ip_block_version { 317 const enum amd_ip_block_type type; 318 const u32 major; 319 const u32 minor; 320 const u32 rev; 321 const struct amd_ip_funcs *funcs; 322 }; 323 324 #define HW_REV(_Major, _Minor, _Rev) \ 325 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 326 327 struct amdgpu_ip_block { 328 struct amdgpu_ip_block_status status; 329 const struct amdgpu_ip_block_version *version; 330 }; 331 332 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 333 enum amd_ip_block_type type, 334 u32 major, u32 minor); 335 336 struct amdgpu_ip_block * 337 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 338 enum amd_ip_block_type type); 339 340 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 341 const struct amdgpu_ip_block_version *ip_block_version); 342 343 /* 344 * BIOS. 345 */ 346 bool amdgpu_get_bios(struct amdgpu_device *adev); 347 bool amdgpu_read_bios(struct amdgpu_device *adev); 348 349 /* 350 * Clocks 351 */ 352 353 #define AMDGPU_MAX_PPLL 3 354 355 struct amdgpu_clock { 356 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 357 struct amdgpu_pll spll; 358 struct amdgpu_pll mpll; 359 /* 10 Khz units */ 360 uint32_t default_mclk; 361 uint32_t default_sclk; 362 uint32_t default_dispclk; 363 uint32_t current_dispclk; 364 uint32_t dp_extclk; 365 uint32_t max_pixel_clock; 366 }; 367 368 /* sub-allocation manager, it has to be protected by another lock. 369 * By conception this is an helper for other part of the driver 370 * like the indirect buffer or semaphore, which both have their 371 * locking. 372 * 373 * Principe is simple, we keep a list of sub allocation in offset 374 * order (first entry has offset == 0, last entry has the highest 375 * offset). 376 * 377 * When allocating new object we first check if there is room at 378 * the end total_size - (last_object_offset + last_object_size) >= 379 * alloc_size. If so we allocate new object there. 380 * 381 * When there is not enough room at the end, we start waiting for 382 * each sub object until we reach object_offset+object_size >= 383 * alloc_size, this object then become the sub object we return. 384 * 385 * Alignment can't be bigger than page size. 386 * 387 * Hole are not considered for allocation to keep things simple. 388 * Assumption is that there won't be hole (all object on same 389 * alignment). 390 */ 391 392 #define AMDGPU_SA_NUM_FENCE_LISTS 32 393 394 struct amdgpu_sa_manager { 395 wait_queue_head_t wq; 396 struct amdgpu_bo *bo; 397 struct list_head *hole; 398 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 399 struct list_head olist; 400 unsigned size; 401 uint64_t gpu_addr; 402 void *cpu_ptr; 403 uint32_t domain; 404 uint32_t align; 405 }; 406 407 /* sub-allocation buffer */ 408 struct amdgpu_sa_bo { 409 struct list_head olist; 410 struct list_head flist; 411 struct amdgpu_sa_manager *manager; 412 unsigned soffset; 413 unsigned eoffset; 414 struct dma_fence *fence; 415 }; 416 417 int amdgpu_fence_slab_init(void); 418 void amdgpu_fence_slab_fini(void); 419 420 /* 421 * IRQS. 422 */ 423 424 struct amdgpu_flip_work { 425 struct delayed_work flip_work; 426 struct work_struct unpin_work; 427 struct amdgpu_device *adev; 428 int crtc_id; 429 u32 target_vblank; 430 uint64_t base; 431 struct drm_pending_vblank_event *event; 432 struct amdgpu_bo *old_abo; 433 struct dma_fence *excl; 434 unsigned shared_count; 435 struct dma_fence **shared; 436 struct dma_fence_cb cb; 437 bool async; 438 }; 439 440 441 /* 442 * CP & rings. 443 */ 444 445 struct amdgpu_ib { 446 struct amdgpu_sa_bo *sa_bo; 447 uint32_t length_dw; 448 uint64_t gpu_addr; 449 uint32_t *ptr; 450 uint32_t flags; 451 }; 452 453 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 454 455 /* 456 * file private structure 457 */ 458 459 struct amdgpu_fpriv { 460 struct amdgpu_vm vm; 461 struct amdgpu_bo_va *prt_va; 462 struct amdgpu_bo_va *csa_va; 463 struct mutex bo_list_lock; 464 struct idr bo_list_handles; 465 struct amdgpu_ctx_mgr ctx_mgr; 466 }; 467 468 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 469 470 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 471 unsigned size, 472 enum amdgpu_ib_pool_type pool, 473 struct amdgpu_ib *ib); 474 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 475 struct dma_fence *f); 476 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 477 struct amdgpu_ib *ibs, struct amdgpu_job *job, 478 struct dma_fence **f); 479 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 480 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 481 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 482 483 /* 484 * CS. 485 */ 486 struct amdgpu_cs_chunk { 487 uint32_t chunk_id; 488 uint32_t length_dw; 489 void *kdata; 490 }; 491 492 struct amdgpu_cs_post_dep { 493 struct drm_syncobj *syncobj; 494 struct dma_fence_chain *chain; 495 u64 point; 496 }; 497 498 struct amdgpu_cs_parser { 499 struct amdgpu_device *adev; 500 struct drm_file *filp; 501 struct amdgpu_ctx *ctx; 502 503 /* chunks */ 504 unsigned nchunks; 505 struct amdgpu_cs_chunk *chunks; 506 507 /* scheduler job object */ 508 struct amdgpu_job *job; 509 struct drm_sched_entity *entity; 510 511 /* buffer objects */ 512 struct ww_acquire_ctx ticket; 513 struct amdgpu_bo_list *bo_list; 514 struct amdgpu_mn *mn; 515 struct amdgpu_bo_list_entry vm_pd; 516 struct list_head validated; 517 struct dma_fence *fence; 518 uint64_t bytes_moved_threshold; 519 uint64_t bytes_moved_vis_threshold; 520 uint64_t bytes_moved; 521 uint64_t bytes_moved_vis; 522 523 /* user fence */ 524 struct amdgpu_bo_list_entry uf_entry; 525 526 unsigned num_post_deps; 527 struct amdgpu_cs_post_dep *post_deps; 528 }; 529 530 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 531 uint32_t ib_idx, int idx) 532 { 533 return p->job->ibs[ib_idx].ptr[idx]; 534 } 535 536 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 537 uint32_t ib_idx, int idx, 538 uint32_t value) 539 { 540 p->job->ibs[ib_idx].ptr[idx] = value; 541 } 542 543 /* 544 * Writeback 545 */ 546 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 547 548 struct amdgpu_wb { 549 struct amdgpu_bo *wb_obj; 550 volatile uint32_t *wb; 551 uint64_t gpu_addr; 552 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 553 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 554 }; 555 556 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 557 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 558 559 /* 560 * Benchmarking 561 */ 562 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 563 564 565 /* 566 * Testing 567 */ 568 void amdgpu_test_moves(struct amdgpu_device *adev); 569 570 /* 571 * ASIC specific register table accessible by UMD 572 */ 573 struct amdgpu_allowed_register_entry { 574 uint32_t reg_offset; 575 bool grbm_indexed; 576 }; 577 578 enum amd_reset_method { 579 AMD_RESET_METHOD_LEGACY = 0, 580 AMD_RESET_METHOD_MODE0, 581 AMD_RESET_METHOD_MODE1, 582 AMD_RESET_METHOD_MODE2, 583 AMD_RESET_METHOD_BACO, 584 AMD_RESET_METHOD_PCI, 585 }; 586 587 struct amdgpu_video_codec_info { 588 u32 codec_type; 589 u32 max_width; 590 u32 max_height; 591 u32 max_pixels_per_frame; 592 u32 max_level; 593 }; 594 595 struct amdgpu_video_codecs { 596 const u32 codec_count; 597 const struct amdgpu_video_codec_info *codec_array; 598 }; 599 600 /* 601 * ASIC specific functions. 602 */ 603 struct amdgpu_asic_funcs { 604 bool (*read_disabled_bios)(struct amdgpu_device *adev); 605 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 606 u8 *bios, u32 length_bytes); 607 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 608 u32 sh_num, u32 reg_offset, u32 *value); 609 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 610 int (*reset)(struct amdgpu_device *adev); 611 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 612 /* get the reference clock */ 613 u32 (*get_xclk)(struct amdgpu_device *adev); 614 /* MM block clocks */ 615 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 616 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 617 /* static power management */ 618 int (*get_pcie_lanes)(struct amdgpu_device *adev); 619 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 620 /* get config memsize register */ 621 u32 (*get_config_memsize)(struct amdgpu_device *adev); 622 /* flush hdp write queue */ 623 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 624 /* invalidate hdp read cache */ 625 void (*invalidate_hdp)(struct amdgpu_device *adev, 626 struct amdgpu_ring *ring); 627 /* check if the asic needs a full reset of if soft reset will work */ 628 bool (*need_full_reset)(struct amdgpu_device *adev); 629 /* initialize doorbell layout for specific asic*/ 630 void (*init_doorbell_index)(struct amdgpu_device *adev); 631 /* PCIe bandwidth usage */ 632 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 633 uint64_t *count1); 634 /* do we need to reset the asic at init time (e.g., kexec) */ 635 bool (*need_reset_on_init)(struct amdgpu_device *adev); 636 /* PCIe replay counter */ 637 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 638 /* device supports BACO */ 639 bool (*supports_baco)(struct amdgpu_device *adev); 640 /* pre asic_init quirks */ 641 void (*pre_asic_init)(struct amdgpu_device *adev); 642 /* enter/exit umd stable pstate */ 643 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 644 /* query video codecs */ 645 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 646 const struct amdgpu_video_codecs **codecs); 647 }; 648 649 /* 650 * IOCTL. 651 */ 652 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 653 struct drm_file *filp); 654 655 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 656 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 657 struct drm_file *filp); 658 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 659 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 660 struct drm_file *filp); 661 662 /* VRAM scratch page for HDP bug, default vram page */ 663 struct amdgpu_vram_scratch { 664 struct amdgpu_bo *robj; 665 volatile uint32_t *ptr; 666 u64 gpu_addr; 667 }; 668 669 /* 670 * ACPI 671 */ 672 struct amdgpu_atcs_functions { 673 bool get_ext_state; 674 bool pcie_perf_req; 675 bool pcie_dev_rdy; 676 bool pcie_bus_width; 677 }; 678 679 struct amdgpu_atcs { 680 struct amdgpu_atcs_functions functions; 681 }; 682 683 /* 684 * CGS 685 */ 686 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 687 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 688 689 /* 690 * Core structure, functions and helpers. 691 */ 692 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 693 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 694 695 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 696 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 697 698 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 699 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 700 701 struct amdgpu_mmio_remap { 702 u32 reg_offset; 703 resource_size_t bus_addr; 704 }; 705 706 /* Define the HW IP blocks will be used in driver , add more if necessary */ 707 enum amd_hw_ip_block_type { 708 GC_HWIP = 1, 709 HDP_HWIP, 710 SDMA0_HWIP, 711 SDMA1_HWIP, 712 SDMA2_HWIP, 713 SDMA3_HWIP, 714 SDMA4_HWIP, 715 SDMA5_HWIP, 716 SDMA6_HWIP, 717 SDMA7_HWIP, 718 MMHUB_HWIP, 719 ATHUB_HWIP, 720 NBIO_HWIP, 721 MP0_HWIP, 722 MP1_HWIP, 723 UVD_HWIP, 724 VCN_HWIP = UVD_HWIP, 725 JPEG_HWIP = VCN_HWIP, 726 VCE_HWIP, 727 DF_HWIP, 728 DCE_HWIP, 729 OSSSYS_HWIP, 730 SMUIO_HWIP, 731 PWR_HWIP, 732 NBIF_HWIP, 733 THM_HWIP, 734 CLK_HWIP, 735 UMC_HWIP, 736 RSMU_HWIP, 737 MAX_HWIP 738 }; 739 740 #define HWIP_MAX_INSTANCE 8 741 742 struct amd_powerplay { 743 void *pp_handle; 744 const struct amd_pm_funcs *pp_funcs; 745 }; 746 747 /* polaris10 kickers */ 748 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 749 ((rid == 0xE3) || \ 750 (rid == 0xE4) || \ 751 (rid == 0xE5) || \ 752 (rid == 0xE7) || \ 753 (rid == 0xEF))) || \ 754 ((did == 0x6FDF) && \ 755 ((rid == 0xE7) || \ 756 (rid == 0xEF) || \ 757 (rid == 0xFF)))) 758 759 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 760 ((rid == 0xE1) || \ 761 (rid == 0xF7))) 762 763 /* polaris11 kickers */ 764 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 765 ((rid == 0xE0) || \ 766 (rid == 0xE5))) || \ 767 ((did == 0x67FF) && \ 768 ((rid == 0xCF) || \ 769 (rid == 0xEF) || \ 770 (rid == 0xFF)))) 771 772 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 773 ((rid == 0xE2))) 774 775 /* polaris12 kickers */ 776 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 777 ((rid == 0xC0) || \ 778 (rid == 0xC1) || \ 779 (rid == 0xC3) || \ 780 (rid == 0xC7))) || \ 781 ((did == 0x6981) && \ 782 ((rid == 0x00) || \ 783 (rid == 0x01) || \ 784 (rid == 0x10)))) 785 786 #define AMDGPU_RESET_MAGIC_NUM 64 787 #define AMDGPU_MAX_DF_PERFMONS 4 788 struct amdgpu_device { 789 struct device *dev; 790 struct pci_dev *pdev; 791 struct drm_device ddev; 792 793 #ifdef CONFIG_DRM_AMD_ACP 794 struct amdgpu_acp acp; 795 #endif 796 struct amdgpu_hive_info *hive; 797 /* ASIC */ 798 enum amd_asic_type asic_type; 799 uint32_t family; 800 uint32_t rev_id; 801 uint32_t external_rev_id; 802 unsigned long flags; 803 unsigned long apu_flags; 804 int usec_timeout; 805 const struct amdgpu_asic_funcs *asic_funcs; 806 bool shutdown; 807 bool need_swiotlb; 808 bool accel_working; 809 struct notifier_block acpi_nb; 810 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 811 struct debugfs_blob_wrapper debugfs_vbios_blob; 812 struct amdgpu_atif *atif; 813 struct amdgpu_atcs atcs; 814 struct mutex srbm_mutex; 815 /* GRBM index mutex. Protects concurrent access to GRBM index */ 816 struct mutex grbm_idx_mutex; 817 struct dev_pm_domain vga_pm_domain; 818 bool have_disp_power_ref; 819 bool have_atomics_support; 820 821 /* BIOS */ 822 bool is_atom_fw; 823 uint8_t *bios; 824 uint32_t bios_size; 825 uint32_t bios_scratch_reg_offset; 826 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 827 828 /* Register/doorbell mmio */ 829 resource_size_t rmmio_base; 830 resource_size_t rmmio_size; 831 void __iomem *rmmio; 832 /* protects concurrent MM_INDEX/DATA based register access */ 833 spinlock_t mmio_idx_lock; 834 struct amdgpu_mmio_remap rmmio_remap; 835 /* protects concurrent SMC based register access */ 836 spinlock_t smc_idx_lock; 837 amdgpu_rreg_t smc_rreg; 838 amdgpu_wreg_t smc_wreg; 839 /* protects concurrent PCIE register access */ 840 spinlock_t pcie_idx_lock; 841 amdgpu_rreg_t pcie_rreg; 842 amdgpu_wreg_t pcie_wreg; 843 amdgpu_rreg_t pciep_rreg; 844 amdgpu_wreg_t pciep_wreg; 845 amdgpu_rreg64_t pcie_rreg64; 846 amdgpu_wreg64_t pcie_wreg64; 847 /* protects concurrent UVD register access */ 848 spinlock_t uvd_ctx_idx_lock; 849 amdgpu_rreg_t uvd_ctx_rreg; 850 amdgpu_wreg_t uvd_ctx_wreg; 851 /* protects concurrent DIDT register access */ 852 spinlock_t didt_idx_lock; 853 amdgpu_rreg_t didt_rreg; 854 amdgpu_wreg_t didt_wreg; 855 /* protects concurrent gc_cac register access */ 856 spinlock_t gc_cac_idx_lock; 857 amdgpu_rreg_t gc_cac_rreg; 858 amdgpu_wreg_t gc_cac_wreg; 859 /* protects concurrent se_cac register access */ 860 spinlock_t se_cac_idx_lock; 861 amdgpu_rreg_t se_cac_rreg; 862 amdgpu_wreg_t se_cac_wreg; 863 /* protects concurrent ENDPOINT (audio) register access */ 864 spinlock_t audio_endpt_idx_lock; 865 amdgpu_block_rreg_t audio_endpt_rreg; 866 amdgpu_block_wreg_t audio_endpt_wreg; 867 void __iomem *rio_mem; 868 resource_size_t rio_mem_size; 869 struct amdgpu_doorbell doorbell; 870 871 /* clock/pll info */ 872 struct amdgpu_clock clock; 873 874 /* MC */ 875 struct amdgpu_gmc gmc; 876 struct amdgpu_gart gart; 877 dma_addr_t dummy_page_addr; 878 struct amdgpu_vm_manager vm_manager; 879 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 880 unsigned num_vmhubs; 881 882 /* memory management */ 883 struct amdgpu_mman mman; 884 struct amdgpu_vram_scratch vram_scratch; 885 struct amdgpu_wb wb; 886 atomic64_t num_bytes_moved; 887 atomic64_t num_evictions; 888 atomic64_t num_vram_cpu_page_faults; 889 atomic_t gpu_reset_counter; 890 atomic_t vram_lost_counter; 891 892 /* data for buffer migration throttling */ 893 struct { 894 spinlock_t lock; 895 s64 last_update_us; 896 s64 accum_us; /* accumulated microseconds */ 897 s64 accum_us_vis; /* for visible VRAM */ 898 u32 log2_max_MBps; 899 } mm_stats; 900 901 /* display */ 902 bool enable_virtual_display; 903 struct amdgpu_mode_info mode_info; 904 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 905 struct work_struct hotplug_work; 906 struct amdgpu_irq_src crtc_irq; 907 struct amdgpu_irq_src vline0_irq; 908 struct amdgpu_irq_src vupdate_irq; 909 struct amdgpu_irq_src pageflip_irq; 910 struct amdgpu_irq_src hpd_irq; 911 struct amdgpu_irq_src dmub_trace_irq; 912 913 /* rings */ 914 u64 fence_context; 915 unsigned num_rings; 916 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 917 bool ib_pool_ready; 918 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 919 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 920 921 /* interrupts */ 922 struct amdgpu_irq irq; 923 924 /* powerplay */ 925 struct amd_powerplay powerplay; 926 bool pp_force_state_enabled; 927 928 /* smu */ 929 struct smu_context smu; 930 931 /* dpm */ 932 struct amdgpu_pm pm; 933 u32 cg_flags; 934 u32 pg_flags; 935 936 /* nbio */ 937 struct amdgpu_nbio nbio; 938 939 /* hdp */ 940 struct amdgpu_hdp hdp; 941 942 /* smuio */ 943 struct amdgpu_smuio smuio; 944 945 /* mmhub */ 946 struct amdgpu_mmhub mmhub; 947 948 /* gfxhub */ 949 struct amdgpu_gfxhub gfxhub; 950 951 /* gfx */ 952 struct amdgpu_gfx gfx; 953 954 /* sdma */ 955 struct amdgpu_sdma sdma; 956 957 /* uvd */ 958 struct amdgpu_uvd uvd; 959 960 /* vce */ 961 struct amdgpu_vce vce; 962 963 /* vcn */ 964 struct amdgpu_vcn vcn; 965 966 /* jpeg */ 967 struct amdgpu_jpeg jpeg; 968 969 /* firmwares */ 970 struct amdgpu_firmware firmware; 971 972 /* PSP */ 973 struct psp_context psp; 974 975 /* GDS */ 976 struct amdgpu_gds gds; 977 978 /* KFD */ 979 struct amdgpu_kfd_dev kfd; 980 981 /* UMC */ 982 struct amdgpu_umc umc; 983 984 /* display related functionality */ 985 struct amdgpu_display_manager dm; 986 987 /* mes */ 988 bool enable_mes; 989 struct amdgpu_mes mes; 990 991 /* df */ 992 struct amdgpu_df df; 993 994 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 995 int num_ip_blocks; 996 struct mutex mn_lock; 997 DECLARE_HASHTABLE(mn_hash, 7); 998 999 /* tracking pinned memory */ 1000 atomic64_t vram_pin_size; 1001 atomic64_t visible_pin_size; 1002 atomic64_t gart_pin_size; 1003 1004 /* soc15 register offset based on ip, instance and segment */ 1005 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1006 1007 /* delayed work_func for deferring clockgating during resume */ 1008 struct delayed_work delayed_init_work; 1009 1010 struct amdgpu_virt virt; 1011 1012 /* link all shadow bo */ 1013 struct list_head shadow_list; 1014 struct mutex shadow_list_lock; 1015 1016 /* record hw reset is performed */ 1017 bool has_hw_reset; 1018 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1019 1020 /* s3/s4 mask */ 1021 bool in_suspend; 1022 bool in_hibernate; 1023 1024 /* 1025 * The combination flag in_poweroff_reboot_com used to identify the poweroff 1026 * and reboot opt in the s0i3 system-wide suspend. 1027 */ 1028 bool in_poweroff_reboot_com; 1029 1030 atomic_t in_gpu_reset; 1031 enum pp_mp1_state mp1_state; 1032 struct rw_semaphore reset_sem; 1033 struct amdgpu_doorbell_index doorbell_index; 1034 1035 struct mutex notifier_lock; 1036 1037 int asic_reset_res; 1038 struct work_struct xgmi_reset_work; 1039 1040 long gfx_timeout; 1041 long sdma_timeout; 1042 long video_timeout; 1043 long compute_timeout; 1044 1045 uint64_t unique_id; 1046 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1047 1048 /* enable runtime pm on the device */ 1049 bool runpm; 1050 bool in_runpm; 1051 bool has_pr3; 1052 1053 bool pm_sysfs_en; 1054 bool ucode_sysfs_en; 1055 1056 /* Chip product information */ 1057 char product_number[16]; 1058 char product_name[32]; 1059 char serial[20]; 1060 1061 struct amdgpu_autodump autodump; 1062 1063 atomic_t throttling_logging_enabled; 1064 struct ratelimit_state throttling_logging_rs; 1065 uint32_t ras_features; 1066 1067 bool in_pci_err_recovery; 1068 struct pci_saved_state *pci_state; 1069 }; 1070 1071 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1072 { 1073 return container_of(ddev, struct amdgpu_device, ddev); 1074 } 1075 1076 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1077 { 1078 return &adev->ddev; 1079 } 1080 1081 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1082 { 1083 return container_of(bdev, struct amdgpu_device, mman.bdev); 1084 } 1085 1086 int amdgpu_device_init(struct amdgpu_device *adev, 1087 uint32_t flags); 1088 void amdgpu_device_fini(struct amdgpu_device *adev); 1089 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1090 1091 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1092 uint32_t *buf, size_t size, bool write); 1093 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1094 uint32_t reg, uint32_t acc_flags); 1095 void amdgpu_device_wreg(struct amdgpu_device *adev, 1096 uint32_t reg, uint32_t v, 1097 uint32_t acc_flags); 1098 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1099 uint32_t reg, uint32_t v); 1100 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1101 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1102 1103 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1104 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1105 1106 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1107 u32 pcie_index, u32 pcie_data, 1108 u32 reg_addr); 1109 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1110 u32 pcie_index, u32 pcie_data, 1111 u32 reg_addr); 1112 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1113 u32 pcie_index, u32 pcie_data, 1114 u32 reg_addr, u32 reg_data); 1115 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1116 u32 pcie_index, u32 pcie_data, 1117 u32 reg_addr, u64 reg_data); 1118 1119 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1120 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1121 1122 int emu_soc_asic_init(struct amdgpu_device *adev); 1123 1124 /* 1125 * Registers read & write functions. 1126 */ 1127 #define AMDGPU_REGS_NO_KIQ (1<<1) 1128 1129 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1130 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1131 1132 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1133 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1134 1135 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1136 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1137 1138 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1139 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1140 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1141 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1142 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1143 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1144 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1145 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1146 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1147 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1148 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1149 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1150 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1151 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1152 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1153 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1154 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1155 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1156 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1157 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1158 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1159 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1160 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1161 #define WREG32_P(reg, val, mask) \ 1162 do { \ 1163 uint32_t tmp_ = RREG32(reg); \ 1164 tmp_ &= (mask); \ 1165 tmp_ |= ((val) & ~(mask)); \ 1166 WREG32(reg, tmp_); \ 1167 } while (0) 1168 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1169 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1170 #define WREG32_PLL_P(reg, val, mask) \ 1171 do { \ 1172 uint32_t tmp_ = RREG32_PLL(reg); \ 1173 tmp_ &= (mask); \ 1174 tmp_ |= ((val) & ~(mask)); \ 1175 WREG32_PLL(reg, tmp_); \ 1176 } while (0) 1177 1178 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1179 do { \ 1180 u32 tmp = RREG32_SMC(_Reg); \ 1181 tmp &= (_Mask); \ 1182 tmp |= ((_Val) & ~(_Mask)); \ 1183 WREG32_SMC(_Reg, tmp); \ 1184 } while (0) 1185 1186 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1187 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1188 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1189 1190 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1191 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1192 1193 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1194 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1195 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1196 1197 #define REG_GET_FIELD(value, reg, field) \ 1198 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1199 1200 #define WREG32_FIELD(reg, field, val) \ 1201 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1202 1203 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1204 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1205 1206 /* 1207 * BIOS helpers. 1208 */ 1209 #define RBIOS8(i) (adev->bios[i]) 1210 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1211 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1212 1213 /* 1214 * ASICs macro. 1215 */ 1216 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1217 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1218 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1219 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1220 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1221 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1222 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1223 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1224 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1225 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1226 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1227 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1228 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1229 #define amdgpu_asic_flush_hdp(adev, r) \ 1230 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1231 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1232 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r))) 1233 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1234 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1235 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1236 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1237 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1238 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1239 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1240 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1241 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1242 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1243 1244 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1245 1246 /* Common functions */ 1247 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1248 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1249 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1250 struct amdgpu_job* job); 1251 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1252 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1253 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1254 1255 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1256 u64 num_vis_bytes); 1257 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1258 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1259 const u32 *registers, 1260 const u32 array_size); 1261 1262 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1263 bool amdgpu_device_supports_boco(struct drm_device *dev); 1264 bool amdgpu_device_supports_baco(struct drm_device *dev); 1265 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1266 struct amdgpu_device *peer_adev); 1267 int amdgpu_device_baco_enter(struct drm_device *dev); 1268 int amdgpu_device_baco_exit(struct drm_device *dev); 1269 1270 /* atpx handler */ 1271 #if defined(CONFIG_VGA_SWITCHEROO) 1272 void amdgpu_register_atpx_handler(void); 1273 void amdgpu_unregister_atpx_handler(void); 1274 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1275 bool amdgpu_is_atpx_hybrid(void); 1276 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1277 bool amdgpu_has_atpx(void); 1278 #else 1279 static inline void amdgpu_register_atpx_handler(void) {} 1280 static inline void amdgpu_unregister_atpx_handler(void) {} 1281 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1282 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1283 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1284 static inline bool amdgpu_has_atpx(void) { return false; } 1285 #endif 1286 1287 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1288 void *amdgpu_atpx_get_dhandle(void); 1289 #else 1290 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1291 #endif 1292 1293 /* 1294 * KMS 1295 */ 1296 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1297 extern const int amdgpu_max_kms_ioctl; 1298 1299 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1300 void amdgpu_driver_unload_kms(struct drm_device *dev); 1301 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1302 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1303 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1304 struct drm_file *file_priv); 1305 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1306 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1307 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1308 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1309 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1310 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1311 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1312 unsigned long arg); 1313 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1314 struct drm_file *filp); 1315 1316 /* 1317 * functions used by amdgpu_encoder.c 1318 */ 1319 struct amdgpu_afmt_acr { 1320 u32 clock; 1321 1322 int n_32khz; 1323 int cts_32khz; 1324 1325 int n_44_1khz; 1326 int cts_44_1khz; 1327 1328 int n_48khz; 1329 int cts_48khz; 1330 1331 }; 1332 1333 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1334 1335 /* amdgpu_acpi.c */ 1336 #if defined(CONFIG_ACPI) 1337 int amdgpu_acpi_init(struct amdgpu_device *adev); 1338 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1339 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1340 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1341 u8 perf_req, bool advertise); 1342 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1343 1344 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1345 struct amdgpu_dm_backlight_caps *caps); 1346 bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev); 1347 #else 1348 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1349 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1350 static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; } 1351 #endif 1352 1353 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1354 uint64_t addr, struct amdgpu_bo **bo, 1355 struct amdgpu_bo_va_mapping **mapping); 1356 1357 #if defined(CONFIG_DRM_AMD_DC) 1358 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1359 #else 1360 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1361 #endif 1362 1363 1364 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1365 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1366 1367 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1368 pci_channel_state_t state); 1369 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1370 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1371 void amdgpu_pci_resume(struct pci_dev *pdev); 1372 1373 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1374 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1375 1376 #include "amdgpu_object.h" 1377 1378 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1379 { 1380 return adev->gmc.tmz_enabled; 1381 } 1382 1383 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1384 { 1385 return atomic_read(&adev->in_gpu_reset); 1386 } 1387 #endif 1388