1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/rbtree.h> 36 #include <linux/hashtable.h> 37 #include <linux/dma-fence.h> 38 39 #include <drm/ttm/ttm_bo_api.h> 40 #include <drm/ttm/ttm_bo_driver.h> 41 #include <drm/ttm/ttm_placement.h> 42 #include <drm/ttm/ttm_module.h> 43 #include <drm/ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 #include <drm/gpu_scheduler.h> 49 50 #include <kgd_kfd_interface.h> 51 #include "dm_pp_interface.h" 52 #include "kgd_pp_interface.h" 53 54 #include "amd_shared.h" 55 #include "amdgpu_mode.h" 56 #include "amdgpu_ih.h" 57 #include "amdgpu_irq.h" 58 #include "amdgpu_ucode.h" 59 #include "amdgpu_ttm.h" 60 #include "amdgpu_psp.h" 61 #include "amdgpu_gds.h" 62 #include "amdgpu_sync.h" 63 #include "amdgpu_ring.h" 64 #include "amdgpu_vm.h" 65 #include "amdgpu_dpm.h" 66 #include "amdgpu_acp.h" 67 #include "amdgpu_uvd.h" 68 #include "amdgpu_vce.h" 69 #include "amdgpu_vcn.h" 70 #include "amdgpu_mn.h" 71 #include "amdgpu_gmc.h" 72 #include "amdgpu_gfx.h" 73 #include "amdgpu_sdma.h" 74 #include "amdgpu_dm.h" 75 #include "amdgpu_virt.h" 76 #include "amdgpu_gart.h" 77 #include "amdgpu_debugfs.h" 78 #include "amdgpu_job.h" 79 #include "amdgpu_bo_list.h" 80 #include "amdgpu_gem.h" 81 82 /* 83 * Modules parameters. 84 */ 85 extern int amdgpu_modeset; 86 extern int amdgpu_vram_limit; 87 extern int amdgpu_vis_vram_limit; 88 extern int amdgpu_gart_size; 89 extern int amdgpu_gtt_size; 90 extern int amdgpu_moverate; 91 extern int amdgpu_benchmarking; 92 extern int amdgpu_testing; 93 extern int amdgpu_audio; 94 extern int amdgpu_disp_priority; 95 extern int amdgpu_hw_i2c; 96 extern int amdgpu_pcie_gen2; 97 extern int amdgpu_msi; 98 extern int amdgpu_lockup_timeout; 99 extern int amdgpu_dpm; 100 extern int amdgpu_fw_load_type; 101 extern int amdgpu_aspm; 102 extern int amdgpu_runtime_pm; 103 extern uint amdgpu_ip_block_mask; 104 extern int amdgpu_bapm; 105 extern int amdgpu_deep_color; 106 extern int amdgpu_vm_size; 107 extern int amdgpu_vm_block_size; 108 extern int amdgpu_vm_fragment_size; 109 extern int amdgpu_vm_fault_stop; 110 extern int amdgpu_vm_debug; 111 extern int amdgpu_vm_update_mode; 112 extern int amdgpu_dc; 113 extern int amdgpu_sched_jobs; 114 extern int amdgpu_sched_hw_submission; 115 extern uint amdgpu_pcie_gen_cap; 116 extern uint amdgpu_pcie_lane_cap; 117 extern uint amdgpu_cg_mask; 118 extern uint amdgpu_pg_mask; 119 extern uint amdgpu_sdma_phase_quantum; 120 extern char *amdgpu_disable_cu; 121 extern char *amdgpu_virtual_display; 122 extern uint amdgpu_pp_feature_mask; 123 extern int amdgpu_vram_page_split; 124 extern int amdgpu_ngg; 125 extern int amdgpu_prim_buf_per_se; 126 extern int amdgpu_pos_buf_per_se; 127 extern int amdgpu_cntl_sb_buf_per_se; 128 extern int amdgpu_param_buf_per_se; 129 extern int amdgpu_job_hang_limit; 130 extern int amdgpu_lbpw; 131 extern int amdgpu_compute_multipipe; 132 extern int amdgpu_gpu_recovery; 133 extern int amdgpu_emu_mode; 134 extern uint amdgpu_smu_memory_pool_size; 135 136 #ifdef CONFIG_DRM_AMDGPU_SI 137 extern int amdgpu_si_support; 138 #endif 139 #ifdef CONFIG_DRM_AMDGPU_CIK 140 extern int amdgpu_cik_support; 141 #endif 142 143 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 144 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 145 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 146 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 147 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 148 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 149 #define AMDGPU_IB_POOL_SIZE 16 150 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 151 #define AMDGPUFB_CONN_LIMIT 4 152 #define AMDGPU_BIOS_NUM_SCRATCH 16 153 154 /* hard reset data */ 155 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 156 157 /* reset flags */ 158 #define AMDGPU_RESET_GFX (1 << 0) 159 #define AMDGPU_RESET_COMPUTE (1 << 1) 160 #define AMDGPU_RESET_DMA (1 << 2) 161 #define AMDGPU_RESET_CP (1 << 3) 162 #define AMDGPU_RESET_GRBM (1 << 4) 163 #define AMDGPU_RESET_DMA1 (1 << 5) 164 #define AMDGPU_RESET_RLC (1 << 6) 165 #define AMDGPU_RESET_SEM (1 << 7) 166 #define AMDGPU_RESET_IH (1 << 8) 167 #define AMDGPU_RESET_VMC (1 << 9) 168 #define AMDGPU_RESET_MC (1 << 10) 169 #define AMDGPU_RESET_DISPLAY (1 << 11) 170 #define AMDGPU_RESET_UVD (1 << 12) 171 #define AMDGPU_RESET_VCE (1 << 13) 172 #define AMDGPU_RESET_VCE1 (1 << 14) 173 174 /* max cursor sizes (in pixels) */ 175 #define CIK_CURSOR_WIDTH 128 176 #define CIK_CURSOR_HEIGHT 128 177 178 struct amdgpu_device; 179 struct amdgpu_ib; 180 struct amdgpu_cs_parser; 181 struct amdgpu_job; 182 struct amdgpu_irq_src; 183 struct amdgpu_fpriv; 184 struct amdgpu_bo_va_mapping; 185 struct amdgpu_atif; 186 187 enum amdgpu_cp_irq { 188 AMDGPU_CP_IRQ_GFX_EOP = 0, 189 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 190 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 191 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 192 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 193 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 194 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 195 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 196 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 197 198 AMDGPU_CP_IRQ_LAST 199 }; 200 201 enum amdgpu_thermal_irq { 202 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 203 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 204 205 AMDGPU_THERMAL_IRQ_LAST 206 }; 207 208 enum amdgpu_kiq_irq { 209 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 210 AMDGPU_CP_KIQ_IRQ_LAST 211 }; 212 213 int amdgpu_device_ip_set_clockgating_state(void *dev, 214 enum amd_ip_block_type block_type, 215 enum amd_clockgating_state state); 216 int amdgpu_device_ip_set_powergating_state(void *dev, 217 enum amd_ip_block_type block_type, 218 enum amd_powergating_state state); 219 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 220 u32 *flags); 221 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 222 enum amd_ip_block_type block_type); 223 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 224 enum amd_ip_block_type block_type); 225 226 #define AMDGPU_MAX_IP_NUM 16 227 228 struct amdgpu_ip_block_status { 229 bool valid; 230 bool sw; 231 bool hw; 232 bool late_initialized; 233 bool hang; 234 }; 235 236 struct amdgpu_ip_block_version { 237 const enum amd_ip_block_type type; 238 const u32 major; 239 const u32 minor; 240 const u32 rev; 241 const struct amd_ip_funcs *funcs; 242 }; 243 244 struct amdgpu_ip_block { 245 struct amdgpu_ip_block_status status; 246 const struct amdgpu_ip_block_version *version; 247 }; 248 249 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 250 enum amd_ip_block_type type, 251 u32 major, u32 minor); 252 253 struct amdgpu_ip_block * 254 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 255 enum amd_ip_block_type type); 256 257 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 258 const struct amdgpu_ip_block_version *ip_block_version); 259 260 /* 261 * BIOS. 262 */ 263 bool amdgpu_get_bios(struct amdgpu_device *adev); 264 bool amdgpu_read_bios(struct amdgpu_device *adev); 265 266 /* 267 * Clocks 268 */ 269 270 #define AMDGPU_MAX_PPLL 3 271 272 struct amdgpu_clock { 273 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 274 struct amdgpu_pll spll; 275 struct amdgpu_pll mpll; 276 /* 10 Khz units */ 277 uint32_t default_mclk; 278 uint32_t default_sclk; 279 uint32_t default_dispclk; 280 uint32_t current_dispclk; 281 uint32_t dp_extclk; 282 uint32_t max_pixel_clock; 283 }; 284 285 /* sub-allocation manager, it has to be protected by another lock. 286 * By conception this is an helper for other part of the driver 287 * like the indirect buffer or semaphore, which both have their 288 * locking. 289 * 290 * Principe is simple, we keep a list of sub allocation in offset 291 * order (first entry has offset == 0, last entry has the highest 292 * offset). 293 * 294 * When allocating new object we first check if there is room at 295 * the end total_size - (last_object_offset + last_object_size) >= 296 * alloc_size. If so we allocate new object there. 297 * 298 * When there is not enough room at the end, we start waiting for 299 * each sub object until we reach object_offset+object_size >= 300 * alloc_size, this object then become the sub object we return. 301 * 302 * Alignment can't be bigger than page size. 303 * 304 * Hole are not considered for allocation to keep things simple. 305 * Assumption is that there won't be hole (all object on same 306 * alignment). 307 */ 308 309 #define AMDGPU_SA_NUM_FENCE_LISTS 32 310 311 struct amdgpu_sa_manager { 312 wait_queue_head_t wq; 313 struct amdgpu_bo *bo; 314 struct list_head *hole; 315 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 316 struct list_head olist; 317 unsigned size; 318 uint64_t gpu_addr; 319 void *cpu_ptr; 320 uint32_t domain; 321 uint32_t align; 322 }; 323 324 /* sub-allocation buffer */ 325 struct amdgpu_sa_bo { 326 struct list_head olist; 327 struct list_head flist; 328 struct amdgpu_sa_manager *manager; 329 unsigned soffset; 330 unsigned eoffset; 331 struct dma_fence *fence; 332 }; 333 334 int amdgpu_fence_slab_init(void); 335 void amdgpu_fence_slab_fini(void); 336 337 /* 338 * GPU doorbell structures, functions & helpers 339 */ 340 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 341 { 342 AMDGPU_DOORBELL_KIQ = 0x000, 343 AMDGPU_DOORBELL_HIQ = 0x001, 344 AMDGPU_DOORBELL_DIQ = 0x002, 345 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 346 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 347 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 348 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 349 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 350 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 351 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 352 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 353 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 354 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 355 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 356 AMDGPU_DOORBELL_IH = 0x1E8, 357 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 358 AMDGPU_DOORBELL_INVALID = 0xFFFF 359 } AMDGPU_DOORBELL_ASSIGNMENT; 360 361 struct amdgpu_doorbell { 362 /* doorbell mmio */ 363 resource_size_t base; 364 resource_size_t size; 365 u32 __iomem *ptr; 366 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 367 }; 368 369 /* 370 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 371 */ 372 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 373 { 374 /* 375 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 376 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 377 * Compute related doorbells are allocated from 0x00 to 0x8a 378 */ 379 380 381 /* kernel scheduling */ 382 AMDGPU_DOORBELL64_KIQ = 0x00, 383 384 /* HSA interface queue and debug queue */ 385 AMDGPU_DOORBELL64_HIQ = 0x01, 386 AMDGPU_DOORBELL64_DIQ = 0x02, 387 388 /* Compute engines */ 389 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 390 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 391 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 392 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 393 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 394 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 395 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 396 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 397 398 /* User queue doorbell range (128 doorbells) */ 399 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 400 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 401 402 /* Graphics engine */ 403 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 404 405 /* 406 * Other graphics doorbells can be allocated here: from 0x8c to 0xef 407 * Graphics voltage island aperture 1 408 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive 409 */ 410 411 /* sDMA engines */ 412 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 413 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 414 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 415 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 416 417 /* Interrupt handler */ 418 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 419 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 420 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 421 422 /* VCN engine use 32 bits doorbell */ 423 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 424 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 425 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 426 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 427 428 /* overlap the doorbell assignment with VCN as they are mutually exclusive 429 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 430 */ 431 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 432 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 433 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 434 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 435 436 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 437 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 438 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 439 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 440 441 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 442 AMDGPU_DOORBELL64_INVALID = 0xFFFF 443 } AMDGPU_DOORBELL64_ASSIGNMENT; 444 445 /* 446 * IRQS. 447 */ 448 449 struct amdgpu_flip_work { 450 struct delayed_work flip_work; 451 struct work_struct unpin_work; 452 struct amdgpu_device *adev; 453 int crtc_id; 454 u32 target_vblank; 455 uint64_t base; 456 struct drm_pending_vblank_event *event; 457 struct amdgpu_bo *old_abo; 458 struct dma_fence *excl; 459 unsigned shared_count; 460 struct dma_fence **shared; 461 struct dma_fence_cb cb; 462 bool async; 463 }; 464 465 466 /* 467 * CP & rings. 468 */ 469 470 struct amdgpu_ib { 471 struct amdgpu_sa_bo *sa_bo; 472 uint32_t length_dw; 473 uint64_t gpu_addr; 474 uint32_t *ptr; 475 uint32_t flags; 476 }; 477 478 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 479 480 /* 481 * Queue manager 482 */ 483 struct amdgpu_queue_mapper { 484 int hw_ip; 485 struct mutex lock; 486 /* protected by lock */ 487 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS]; 488 }; 489 490 struct amdgpu_queue_mgr { 491 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM]; 492 }; 493 494 int amdgpu_queue_mgr_init(struct amdgpu_device *adev, 495 struct amdgpu_queue_mgr *mgr); 496 int amdgpu_queue_mgr_fini(struct amdgpu_device *adev, 497 struct amdgpu_queue_mgr *mgr); 498 int amdgpu_queue_mgr_map(struct amdgpu_device *adev, 499 struct amdgpu_queue_mgr *mgr, 500 u32 hw_ip, u32 instance, u32 ring, 501 struct amdgpu_ring **out_ring); 502 503 /* 504 * context related structures 505 */ 506 507 struct amdgpu_ctx_ring { 508 uint64_t sequence; 509 struct dma_fence **fences; 510 struct drm_sched_entity entity; 511 }; 512 513 struct amdgpu_ctx { 514 struct kref refcount; 515 struct amdgpu_device *adev; 516 struct amdgpu_queue_mgr queue_mgr; 517 unsigned reset_counter; 518 unsigned reset_counter_query; 519 uint32_t vram_lost_counter; 520 spinlock_t ring_lock; 521 struct dma_fence **fences; 522 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 523 bool preamble_presented; 524 enum drm_sched_priority init_priority; 525 enum drm_sched_priority override_priority; 526 struct mutex lock; 527 atomic_t guilty; 528 }; 529 530 struct amdgpu_ctx_mgr { 531 struct amdgpu_device *adev; 532 struct mutex lock; 533 /* protected by lock */ 534 struct idr ctx_handles; 535 }; 536 537 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 538 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 539 540 int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 541 struct dma_fence *fence, uint64_t *seq); 542 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 543 struct amdgpu_ring *ring, uint64_t seq); 544 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, 545 enum drm_sched_priority priority); 546 547 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 548 struct drm_file *filp); 549 550 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id); 551 552 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 553 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr); 554 void amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr); 555 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 556 557 558 /* 559 * file private structure 560 */ 561 562 struct amdgpu_fpriv { 563 struct amdgpu_vm vm; 564 struct amdgpu_bo_va *prt_va; 565 struct amdgpu_bo_va *csa_va; 566 struct mutex bo_list_lock; 567 struct idr bo_list_handles; 568 struct amdgpu_ctx_mgr ctx_mgr; 569 }; 570 571 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 572 unsigned size, struct amdgpu_ib *ib); 573 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 574 struct dma_fence *f); 575 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 576 struct amdgpu_ib *ibs, struct amdgpu_job *job, 577 struct dma_fence **f); 578 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 579 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 580 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 581 582 /* 583 * CS. 584 */ 585 struct amdgpu_cs_chunk { 586 uint32_t chunk_id; 587 uint32_t length_dw; 588 void *kdata; 589 }; 590 591 struct amdgpu_cs_parser { 592 struct amdgpu_device *adev; 593 struct drm_file *filp; 594 struct amdgpu_ctx *ctx; 595 596 /* chunks */ 597 unsigned nchunks; 598 struct amdgpu_cs_chunk *chunks; 599 600 /* scheduler job object */ 601 struct amdgpu_job *job; 602 struct amdgpu_ring *ring; 603 604 /* buffer objects */ 605 struct ww_acquire_ctx ticket; 606 struct amdgpu_bo_list *bo_list; 607 struct amdgpu_mn *mn; 608 struct amdgpu_bo_list_entry vm_pd; 609 struct list_head validated; 610 struct dma_fence *fence; 611 uint64_t bytes_moved_threshold; 612 uint64_t bytes_moved_vis_threshold; 613 uint64_t bytes_moved; 614 uint64_t bytes_moved_vis; 615 struct amdgpu_bo_list_entry *evictable; 616 617 /* user fence */ 618 struct amdgpu_bo_list_entry uf_entry; 619 620 unsigned num_post_dep_syncobjs; 621 struct drm_syncobj **post_dep_syncobjs; 622 }; 623 624 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 625 uint32_t ib_idx, int idx) 626 { 627 return p->job->ibs[ib_idx].ptr[idx]; 628 } 629 630 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 631 uint32_t ib_idx, int idx, 632 uint32_t value) 633 { 634 p->job->ibs[ib_idx].ptr[idx] = value; 635 } 636 637 /* 638 * Writeback 639 */ 640 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 641 642 struct amdgpu_wb { 643 struct amdgpu_bo *wb_obj; 644 volatile uint32_t *wb; 645 uint64_t gpu_addr; 646 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 647 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 648 }; 649 650 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 651 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 652 653 /* 654 * Benchmarking 655 */ 656 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 657 658 659 /* 660 * Testing 661 */ 662 void amdgpu_test_moves(struct amdgpu_device *adev); 663 664 665 /* 666 * amdgpu smumgr functions 667 */ 668 struct amdgpu_smumgr_funcs { 669 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 670 int (*request_smu_load_fw)(struct amdgpu_device *adev); 671 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 672 }; 673 674 /* 675 * amdgpu smumgr 676 */ 677 struct amdgpu_smumgr { 678 struct amdgpu_bo *toc_buf; 679 struct amdgpu_bo *smu_buf; 680 /* asic priv smu data */ 681 void *priv; 682 spinlock_t smu_lock; 683 /* smumgr functions */ 684 const struct amdgpu_smumgr_funcs *smumgr_funcs; 685 /* ucode loading complete flag */ 686 uint32_t fw_flags; 687 }; 688 689 /* 690 * ASIC specific register table accessible by UMD 691 */ 692 struct amdgpu_allowed_register_entry { 693 uint32_t reg_offset; 694 bool grbm_indexed; 695 }; 696 697 /* 698 * ASIC specific functions. 699 */ 700 struct amdgpu_asic_funcs { 701 bool (*read_disabled_bios)(struct amdgpu_device *adev); 702 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 703 u8 *bios, u32 length_bytes); 704 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 705 u32 sh_num, u32 reg_offset, u32 *value); 706 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 707 int (*reset)(struct amdgpu_device *adev); 708 /* get the reference clock */ 709 u32 (*get_xclk)(struct amdgpu_device *adev); 710 /* MM block clocks */ 711 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 712 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 713 /* static power management */ 714 int (*get_pcie_lanes)(struct amdgpu_device *adev); 715 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 716 /* get config memsize register */ 717 u32 (*get_config_memsize)(struct amdgpu_device *adev); 718 /* flush hdp write queue */ 719 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 720 /* invalidate hdp read cache */ 721 void (*invalidate_hdp)(struct amdgpu_device *adev, 722 struct amdgpu_ring *ring); 723 /* check if the asic needs a full reset of if soft reset will work */ 724 bool (*need_full_reset)(struct amdgpu_device *adev); 725 }; 726 727 /* 728 * IOCTL. 729 */ 730 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 731 struct drm_file *filp); 732 733 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 734 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 735 struct drm_file *filp); 736 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 737 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 738 struct drm_file *filp); 739 740 /* VRAM scratch page for HDP bug, default vram page */ 741 struct amdgpu_vram_scratch { 742 struct amdgpu_bo *robj; 743 volatile uint32_t *ptr; 744 u64 gpu_addr; 745 }; 746 747 /* 748 * ACPI 749 */ 750 struct amdgpu_atcs_functions { 751 bool get_ext_state; 752 bool pcie_perf_req; 753 bool pcie_dev_rdy; 754 bool pcie_bus_width; 755 }; 756 757 struct amdgpu_atcs { 758 struct amdgpu_atcs_functions functions; 759 }; 760 761 /* 762 * Firmware VRAM reservation 763 */ 764 struct amdgpu_fw_vram_usage { 765 u64 start_offset; 766 u64 size; 767 struct amdgpu_bo *reserved_bo; 768 void *va; 769 }; 770 771 /* 772 * CGS 773 */ 774 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 775 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 776 777 /* 778 * Core structure, functions and helpers. 779 */ 780 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 781 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 782 783 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 784 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 785 786 787 /* 788 * amdgpu nbio functions 789 * 790 */ 791 struct nbio_hdp_flush_reg { 792 u32 ref_and_mask_cp0; 793 u32 ref_and_mask_cp1; 794 u32 ref_and_mask_cp2; 795 u32 ref_and_mask_cp3; 796 u32 ref_and_mask_cp4; 797 u32 ref_and_mask_cp5; 798 u32 ref_and_mask_cp6; 799 u32 ref_and_mask_cp7; 800 u32 ref_and_mask_cp8; 801 u32 ref_and_mask_cp9; 802 u32 ref_and_mask_sdma0; 803 u32 ref_and_mask_sdma1; 804 }; 805 806 struct amdgpu_nbio_funcs { 807 const struct nbio_hdp_flush_reg *hdp_flush_reg; 808 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 809 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 810 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 811 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 812 u32 (*get_rev_id)(struct amdgpu_device *adev); 813 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 814 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 815 u32 (*get_memsize)(struct amdgpu_device *adev); 816 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 817 bool use_doorbell, int doorbell_index); 818 void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 819 bool enable); 820 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 821 bool enable); 822 void (*ih_doorbell_range)(struct amdgpu_device *adev, 823 bool use_doorbell, int doorbell_index); 824 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 825 bool enable); 826 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 827 bool enable); 828 void (*get_clockgating_state)(struct amdgpu_device *adev, 829 u32 *flags); 830 void (*ih_control)(struct amdgpu_device *adev); 831 void (*init_registers)(struct amdgpu_device *adev); 832 void (*detect_hw_virt)(struct amdgpu_device *adev); 833 }; 834 835 struct amdgpu_df_funcs { 836 void (*init)(struct amdgpu_device *adev); 837 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 838 bool enable); 839 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 840 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 841 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 842 bool enable); 843 void (*get_clockgating_state)(struct amdgpu_device *adev, 844 u32 *flags); 845 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 846 bool enable); 847 }; 848 /* Define the HW IP blocks will be used in driver , add more if necessary */ 849 enum amd_hw_ip_block_type { 850 GC_HWIP = 1, 851 HDP_HWIP, 852 SDMA0_HWIP, 853 SDMA1_HWIP, 854 MMHUB_HWIP, 855 ATHUB_HWIP, 856 NBIO_HWIP, 857 MP0_HWIP, 858 MP1_HWIP, 859 UVD_HWIP, 860 VCN_HWIP = UVD_HWIP, 861 VCE_HWIP, 862 DF_HWIP, 863 DCE_HWIP, 864 OSSSYS_HWIP, 865 SMUIO_HWIP, 866 PWR_HWIP, 867 NBIF_HWIP, 868 THM_HWIP, 869 CLK_HWIP, 870 MAX_HWIP 871 }; 872 873 #define HWIP_MAX_INSTANCE 6 874 875 struct amd_powerplay { 876 void *pp_handle; 877 const struct amd_pm_funcs *pp_funcs; 878 uint32_t pp_feature; 879 }; 880 881 #define AMDGPU_RESET_MAGIC_NUM 64 882 struct amdgpu_device { 883 struct device *dev; 884 struct drm_device *ddev; 885 struct pci_dev *pdev; 886 887 #ifdef CONFIG_DRM_AMD_ACP 888 struct amdgpu_acp acp; 889 #endif 890 891 /* ASIC */ 892 enum amd_asic_type asic_type; 893 uint32_t family; 894 uint32_t rev_id; 895 uint32_t external_rev_id; 896 unsigned long flags; 897 int usec_timeout; 898 const struct amdgpu_asic_funcs *asic_funcs; 899 bool shutdown; 900 bool need_dma32; 901 bool need_swiotlb; 902 bool accel_working; 903 struct work_struct reset_work; 904 struct notifier_block acpi_nb; 905 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 906 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 907 unsigned debugfs_count; 908 #if defined(CONFIG_DEBUG_FS) 909 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 910 #endif 911 struct amdgpu_atif *atif; 912 struct amdgpu_atcs atcs; 913 struct mutex srbm_mutex; 914 /* GRBM index mutex. Protects concurrent access to GRBM index */ 915 struct mutex grbm_idx_mutex; 916 struct dev_pm_domain vga_pm_domain; 917 bool have_disp_power_ref; 918 919 /* BIOS */ 920 bool is_atom_fw; 921 uint8_t *bios; 922 uint32_t bios_size; 923 struct amdgpu_bo *stolen_vga_memory; 924 uint32_t bios_scratch_reg_offset; 925 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 926 927 /* Register/doorbell mmio */ 928 resource_size_t rmmio_base; 929 resource_size_t rmmio_size; 930 void __iomem *rmmio; 931 /* protects concurrent MM_INDEX/DATA based register access */ 932 spinlock_t mmio_idx_lock; 933 /* protects concurrent SMC based register access */ 934 spinlock_t smc_idx_lock; 935 amdgpu_rreg_t smc_rreg; 936 amdgpu_wreg_t smc_wreg; 937 /* protects concurrent PCIE register access */ 938 spinlock_t pcie_idx_lock; 939 amdgpu_rreg_t pcie_rreg; 940 amdgpu_wreg_t pcie_wreg; 941 amdgpu_rreg_t pciep_rreg; 942 amdgpu_wreg_t pciep_wreg; 943 /* protects concurrent UVD register access */ 944 spinlock_t uvd_ctx_idx_lock; 945 amdgpu_rreg_t uvd_ctx_rreg; 946 amdgpu_wreg_t uvd_ctx_wreg; 947 /* protects concurrent DIDT register access */ 948 spinlock_t didt_idx_lock; 949 amdgpu_rreg_t didt_rreg; 950 amdgpu_wreg_t didt_wreg; 951 /* protects concurrent gc_cac register access */ 952 spinlock_t gc_cac_idx_lock; 953 amdgpu_rreg_t gc_cac_rreg; 954 amdgpu_wreg_t gc_cac_wreg; 955 /* protects concurrent se_cac register access */ 956 spinlock_t se_cac_idx_lock; 957 amdgpu_rreg_t se_cac_rreg; 958 amdgpu_wreg_t se_cac_wreg; 959 /* protects concurrent ENDPOINT (audio) register access */ 960 spinlock_t audio_endpt_idx_lock; 961 amdgpu_block_rreg_t audio_endpt_rreg; 962 amdgpu_block_wreg_t audio_endpt_wreg; 963 void __iomem *rio_mem; 964 resource_size_t rio_mem_size; 965 struct amdgpu_doorbell doorbell; 966 967 /* clock/pll info */ 968 struct amdgpu_clock clock; 969 970 /* MC */ 971 struct amdgpu_gmc gmc; 972 struct amdgpu_gart gart; 973 dma_addr_t dummy_page_addr; 974 struct amdgpu_vm_manager vm_manager; 975 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 976 977 /* memory management */ 978 struct amdgpu_mman mman; 979 struct amdgpu_vram_scratch vram_scratch; 980 struct amdgpu_wb wb; 981 atomic64_t num_bytes_moved; 982 atomic64_t num_evictions; 983 atomic64_t num_vram_cpu_page_faults; 984 atomic_t gpu_reset_counter; 985 atomic_t vram_lost_counter; 986 987 /* data for buffer migration throttling */ 988 struct { 989 spinlock_t lock; 990 s64 last_update_us; 991 s64 accum_us; /* accumulated microseconds */ 992 s64 accum_us_vis; /* for visible VRAM */ 993 u32 log2_max_MBps; 994 } mm_stats; 995 996 /* display */ 997 bool enable_virtual_display; 998 struct amdgpu_mode_info mode_info; 999 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 1000 struct work_struct hotplug_work; 1001 struct amdgpu_irq_src crtc_irq; 1002 struct amdgpu_irq_src pageflip_irq; 1003 struct amdgpu_irq_src hpd_irq; 1004 1005 /* rings */ 1006 u64 fence_context; 1007 unsigned num_rings; 1008 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1009 bool ib_pool_ready; 1010 struct amdgpu_sa_manager ring_tmp_bo; 1011 1012 /* interrupts */ 1013 struct amdgpu_irq irq; 1014 1015 /* powerplay */ 1016 struct amd_powerplay powerplay; 1017 bool pp_force_state_enabled; 1018 1019 /* dpm */ 1020 struct amdgpu_pm pm; 1021 u32 cg_flags; 1022 u32 pg_flags; 1023 1024 /* amdgpu smumgr */ 1025 struct amdgpu_smumgr smu; 1026 1027 /* gfx */ 1028 struct amdgpu_gfx gfx; 1029 1030 /* sdma */ 1031 struct amdgpu_sdma sdma; 1032 1033 /* uvd */ 1034 struct amdgpu_uvd uvd; 1035 1036 /* vce */ 1037 struct amdgpu_vce vce; 1038 1039 /* vcn */ 1040 struct amdgpu_vcn vcn; 1041 1042 /* firmwares */ 1043 struct amdgpu_firmware firmware; 1044 1045 /* PSP */ 1046 struct psp_context psp; 1047 1048 /* GDS */ 1049 struct amdgpu_gds gds; 1050 1051 /* display related functionality */ 1052 struct amdgpu_display_manager dm; 1053 1054 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1055 int num_ip_blocks; 1056 struct mutex mn_lock; 1057 DECLARE_HASHTABLE(mn_hash, 7); 1058 1059 /* tracking pinned memory */ 1060 atomic64_t vram_pin_size; 1061 atomic64_t visible_pin_size; 1062 atomic64_t gart_pin_size; 1063 1064 /* amdkfd interface */ 1065 struct kfd_dev *kfd; 1066 1067 /* soc15 register offset based on ip, instance and segment */ 1068 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1069 1070 const struct amdgpu_nbio_funcs *nbio_funcs; 1071 const struct amdgpu_df_funcs *df_funcs; 1072 1073 /* delayed work_func for deferring clockgating during resume */ 1074 struct delayed_work late_init_work; 1075 1076 struct amdgpu_virt virt; 1077 /* firmware VRAM reservation */ 1078 struct amdgpu_fw_vram_usage fw_vram_usage; 1079 1080 /* link all shadow bo */ 1081 struct list_head shadow_list; 1082 struct mutex shadow_list_lock; 1083 /* keep an lru list of rings by HW IP */ 1084 struct list_head ring_lru_list; 1085 spinlock_t ring_lru_list_lock; 1086 1087 /* record hw reset is performed */ 1088 bool has_hw_reset; 1089 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1090 1091 /* record last mm index being written through WREG32*/ 1092 unsigned long last_mm_index; 1093 bool in_gpu_reset; 1094 struct mutex lock_reset; 1095 }; 1096 1097 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1098 { 1099 return container_of(bdev, struct amdgpu_device, mman.bdev); 1100 } 1101 1102 int amdgpu_device_init(struct amdgpu_device *adev, 1103 struct drm_device *ddev, 1104 struct pci_dev *pdev, 1105 uint32_t flags); 1106 void amdgpu_device_fini(struct amdgpu_device *adev); 1107 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1108 1109 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1110 uint32_t acc_flags); 1111 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1112 uint32_t acc_flags); 1113 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1114 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1115 1116 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1117 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1118 1119 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 1120 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1121 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 1122 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 1123 1124 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1125 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1126 1127 int emu_soc_asic_init(struct amdgpu_device *adev); 1128 1129 /* 1130 * Registers read & write functions. 1131 */ 1132 1133 #define AMDGPU_REGS_IDX (1<<0) 1134 #define AMDGPU_REGS_NO_KIQ (1<<1) 1135 1136 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1137 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1138 1139 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1140 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1141 1142 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1143 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1144 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1145 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1146 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1147 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1148 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1149 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1150 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1151 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1152 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1153 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1154 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1155 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1156 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1157 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1158 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1159 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1160 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1161 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1162 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1163 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1164 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1165 #define WREG32_P(reg, val, mask) \ 1166 do { \ 1167 uint32_t tmp_ = RREG32(reg); \ 1168 tmp_ &= (mask); \ 1169 tmp_ |= ((val) & ~(mask)); \ 1170 WREG32(reg, tmp_); \ 1171 } while (0) 1172 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1173 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1174 #define WREG32_PLL_P(reg, val, mask) \ 1175 do { \ 1176 uint32_t tmp_ = RREG32_PLL(reg); \ 1177 tmp_ &= (mask); \ 1178 tmp_ |= ((val) & ~(mask)); \ 1179 WREG32_PLL(reg, tmp_); \ 1180 } while (0) 1181 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1182 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1183 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1184 1185 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 1186 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1187 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 1188 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 1189 1190 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1191 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1192 1193 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1194 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1195 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1196 1197 #define REG_GET_FIELD(value, reg, field) \ 1198 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1199 1200 #define WREG32_FIELD(reg, field, val) \ 1201 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1202 1203 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1204 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1205 1206 /* 1207 * BIOS helpers. 1208 */ 1209 #define RBIOS8(i) (adev->bios[i]) 1210 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1211 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1212 1213 /* 1214 * ASICs macro. 1215 */ 1216 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1217 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1218 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1219 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1220 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1221 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1222 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1223 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1224 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1225 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1226 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1227 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1228 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1229 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1230 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1231 1232 /* Common functions */ 1233 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1234 struct amdgpu_job* job, bool force); 1235 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1236 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1237 1238 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1239 u64 num_vis_bytes); 1240 void amdgpu_device_vram_location(struct amdgpu_device *adev, 1241 struct amdgpu_gmc *mc, u64 base); 1242 void amdgpu_device_gart_location(struct amdgpu_device *adev, 1243 struct amdgpu_gmc *mc); 1244 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1245 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1246 const u32 *registers, 1247 const u32 array_size); 1248 1249 bool amdgpu_device_is_px(struct drm_device *dev); 1250 /* atpx handler */ 1251 #if defined(CONFIG_VGA_SWITCHEROO) 1252 void amdgpu_register_atpx_handler(void); 1253 void amdgpu_unregister_atpx_handler(void); 1254 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1255 bool amdgpu_is_atpx_hybrid(void); 1256 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1257 bool amdgpu_has_atpx(void); 1258 #else 1259 static inline void amdgpu_register_atpx_handler(void) {} 1260 static inline void amdgpu_unregister_atpx_handler(void) {} 1261 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1262 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1263 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1264 static inline bool amdgpu_has_atpx(void) { return false; } 1265 #endif 1266 1267 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1268 void *amdgpu_atpx_get_dhandle(void); 1269 #else 1270 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1271 #endif 1272 1273 /* 1274 * KMS 1275 */ 1276 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1277 extern const int amdgpu_max_kms_ioctl; 1278 1279 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1280 void amdgpu_driver_unload_kms(struct drm_device *dev); 1281 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1282 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1283 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1284 struct drm_file *file_priv); 1285 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1286 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1287 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1288 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1289 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1290 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1291 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1292 unsigned long arg); 1293 1294 /* 1295 * functions used by amdgpu_encoder.c 1296 */ 1297 struct amdgpu_afmt_acr { 1298 u32 clock; 1299 1300 int n_32khz; 1301 int cts_32khz; 1302 1303 int n_44_1khz; 1304 int cts_44_1khz; 1305 1306 int n_48khz; 1307 int cts_48khz; 1308 1309 }; 1310 1311 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1312 1313 /* amdgpu_acpi.c */ 1314 #if defined(CONFIG_ACPI) 1315 int amdgpu_acpi_init(struct amdgpu_device *adev); 1316 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1317 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1318 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1319 u8 perf_req, bool advertise); 1320 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1321 #else 1322 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1323 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1324 #endif 1325 1326 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1327 uint64_t addr, struct amdgpu_bo **bo, 1328 struct amdgpu_bo_va_mapping **mapping); 1329 1330 #if defined(CONFIG_DRM_AMD_DC) 1331 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1332 #else 1333 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1334 #endif 1335 1336 #include "amdgpu_object.h" 1337 #endif 1338