1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_execbuf_util.h> 59 60 #include <drm/amdgpu_drm.h> 61 #include <drm/drm_gem.h> 62 #include <drm/drm_ioctl.h> 63 #include <drm/gpu_scheduler.h> 64 65 #include <kgd_kfd_interface.h> 66 #include "dm_pp_interface.h" 67 #include "kgd_pp_interface.h" 68 69 #include "amd_shared.h" 70 #include "amdgpu_mode.h" 71 #include "amdgpu_ih.h" 72 #include "amdgpu_irq.h" 73 #include "amdgpu_ucode.h" 74 #include "amdgpu_ttm.h" 75 #include "amdgpu_psp.h" 76 #include "amdgpu_gds.h" 77 #include "amdgpu_sync.h" 78 #include "amdgpu_ring.h" 79 #include "amdgpu_vm.h" 80 #include "amdgpu_dpm.h" 81 #include "amdgpu_acp.h" 82 #include "amdgpu_uvd.h" 83 #include "amdgpu_vce.h" 84 #include "amdgpu_vcn.h" 85 #include "amdgpu_jpeg.h" 86 #include "amdgpu_mn.h" 87 #include "amdgpu_gmc.h" 88 #include "amdgpu_gfx.h" 89 #include "amdgpu_sdma.h" 90 #include "amdgpu_nbio.h" 91 #include "amdgpu_hdp.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_smu.h" 103 #include "amdgpu_discovery.h" 104 #include "amdgpu_mes.h" 105 #include "amdgpu_umc.h" 106 #include "amdgpu_mmhub.h" 107 #include "amdgpu_gfxhub.h" 108 #include "amdgpu_df.h" 109 #include "amdgpu_smuio.h" 110 #include "amdgpu_hdp.h" 111 112 #define MAX_GPU_INSTANCE 16 113 114 struct amdgpu_gpu_instance 115 { 116 struct amdgpu_device *adev; 117 int mgpu_fan_enabled; 118 }; 119 120 struct amdgpu_mgpu_info 121 { 122 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 123 struct mutex mutex; 124 uint32_t num_gpu; 125 uint32_t num_dgpu; 126 uint32_t num_apu; 127 }; 128 129 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 130 131 /* 132 * Modules parameters. 133 */ 134 extern int amdgpu_modeset; 135 extern int amdgpu_vram_limit; 136 extern int amdgpu_vis_vram_limit; 137 extern int amdgpu_gart_size; 138 extern int amdgpu_gtt_size; 139 extern int amdgpu_moverate; 140 extern int amdgpu_benchmarking; 141 extern int amdgpu_testing; 142 extern int amdgpu_audio; 143 extern int amdgpu_disp_priority; 144 extern int amdgpu_hw_i2c; 145 extern int amdgpu_pcie_gen2; 146 extern int amdgpu_msi; 147 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 148 extern int amdgpu_dpm; 149 extern int amdgpu_fw_load_type; 150 extern int amdgpu_aspm; 151 extern int amdgpu_runtime_pm; 152 extern uint amdgpu_ip_block_mask; 153 extern int amdgpu_bapm; 154 extern int amdgpu_deep_color; 155 extern int amdgpu_vm_size; 156 extern int amdgpu_vm_block_size; 157 extern int amdgpu_vm_fragment_size; 158 extern int amdgpu_vm_fault_stop; 159 extern int amdgpu_vm_debug; 160 extern int amdgpu_vm_update_mode; 161 extern int amdgpu_exp_hw_support; 162 extern int amdgpu_dc; 163 extern int amdgpu_sched_jobs; 164 extern int amdgpu_sched_hw_submission; 165 extern uint amdgpu_pcie_gen_cap; 166 extern uint amdgpu_pcie_lane_cap; 167 extern uint amdgpu_cg_mask; 168 extern uint amdgpu_pg_mask; 169 extern uint amdgpu_sdma_phase_quantum; 170 extern char *amdgpu_disable_cu; 171 extern char *amdgpu_virtual_display; 172 extern uint amdgpu_pp_feature_mask; 173 extern uint amdgpu_force_long_training; 174 extern int amdgpu_job_hang_limit; 175 extern int amdgpu_lbpw; 176 extern int amdgpu_compute_multipipe; 177 extern int amdgpu_gpu_recovery; 178 extern int amdgpu_emu_mode; 179 extern uint amdgpu_smu_memory_pool_size; 180 extern uint amdgpu_dc_feature_mask; 181 extern uint amdgpu_freesync_vid_mode; 182 extern uint amdgpu_dc_debug_mask; 183 extern uint amdgpu_dm_abm_level; 184 extern int amdgpu_backlight; 185 extern struct amdgpu_mgpu_info mgpu_info; 186 extern int amdgpu_ras_enable; 187 extern uint amdgpu_ras_mask; 188 extern int amdgpu_bad_page_threshold; 189 extern int amdgpu_async_gfx_ring; 190 extern int amdgpu_mcbp; 191 extern int amdgpu_discovery; 192 extern int amdgpu_mes; 193 extern int amdgpu_noretry; 194 extern int amdgpu_force_asic_type; 195 #ifdef CONFIG_HSA_AMD 196 extern int sched_policy; 197 extern bool debug_evictions; 198 extern bool no_system_mem_limit; 199 #else 200 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 201 static const bool __maybe_unused debug_evictions; /* = false */ 202 static const bool __maybe_unused no_system_mem_limit; 203 #endif 204 205 extern int amdgpu_tmz; 206 extern int amdgpu_reset_method; 207 208 #ifdef CONFIG_DRM_AMDGPU_SI 209 extern int amdgpu_si_support; 210 #endif 211 #ifdef CONFIG_DRM_AMDGPU_CIK 212 extern int amdgpu_cik_support; 213 #endif 214 extern int amdgpu_num_kcq; 215 216 #define AMDGPU_VM_MAX_NUM_CTX 4096 217 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 218 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 219 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 220 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 221 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 222 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 223 #define AMDGPUFB_CONN_LIMIT 4 224 #define AMDGPU_BIOS_NUM_SCRATCH 16 225 226 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 227 228 /* hard reset data */ 229 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 230 231 /* reset flags */ 232 #define AMDGPU_RESET_GFX (1 << 0) 233 #define AMDGPU_RESET_COMPUTE (1 << 1) 234 #define AMDGPU_RESET_DMA (1 << 2) 235 #define AMDGPU_RESET_CP (1 << 3) 236 #define AMDGPU_RESET_GRBM (1 << 4) 237 #define AMDGPU_RESET_DMA1 (1 << 5) 238 #define AMDGPU_RESET_RLC (1 << 6) 239 #define AMDGPU_RESET_SEM (1 << 7) 240 #define AMDGPU_RESET_IH (1 << 8) 241 #define AMDGPU_RESET_VMC (1 << 9) 242 #define AMDGPU_RESET_MC (1 << 10) 243 #define AMDGPU_RESET_DISPLAY (1 << 11) 244 #define AMDGPU_RESET_UVD (1 << 12) 245 #define AMDGPU_RESET_VCE (1 << 13) 246 #define AMDGPU_RESET_VCE1 (1 << 14) 247 248 /* max cursor sizes (in pixels) */ 249 #define CIK_CURSOR_WIDTH 128 250 #define CIK_CURSOR_HEIGHT 128 251 252 struct amdgpu_device; 253 struct amdgpu_ib; 254 struct amdgpu_cs_parser; 255 struct amdgpu_job; 256 struct amdgpu_irq_src; 257 struct amdgpu_fpriv; 258 struct amdgpu_bo_va_mapping; 259 struct amdgpu_atif; 260 struct kfd_vm_fault_info; 261 struct amdgpu_hive_info; 262 263 enum amdgpu_cp_irq { 264 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 265 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 266 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 267 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 268 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 269 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 270 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 271 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 272 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 273 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 274 275 AMDGPU_CP_IRQ_LAST 276 }; 277 278 enum amdgpu_thermal_irq { 279 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 280 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 281 282 AMDGPU_THERMAL_IRQ_LAST 283 }; 284 285 enum amdgpu_kiq_irq { 286 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 287 AMDGPU_CP_KIQ_IRQ_LAST 288 }; 289 290 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 291 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 292 #define MAX_KIQ_REG_TRY 1000 293 294 int amdgpu_device_ip_set_clockgating_state(void *dev, 295 enum amd_ip_block_type block_type, 296 enum amd_clockgating_state state); 297 int amdgpu_device_ip_set_powergating_state(void *dev, 298 enum amd_ip_block_type block_type, 299 enum amd_powergating_state state); 300 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 301 u32 *flags); 302 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 303 enum amd_ip_block_type block_type); 304 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 305 enum amd_ip_block_type block_type); 306 307 #define AMDGPU_MAX_IP_NUM 16 308 309 struct amdgpu_ip_block_status { 310 bool valid; 311 bool sw; 312 bool hw; 313 bool late_initialized; 314 bool hang; 315 }; 316 317 struct amdgpu_ip_block_version { 318 const enum amd_ip_block_type type; 319 const u32 major; 320 const u32 minor; 321 const u32 rev; 322 const struct amd_ip_funcs *funcs; 323 }; 324 325 #define HW_REV(_Major, _Minor, _Rev) \ 326 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 327 328 struct amdgpu_ip_block { 329 struct amdgpu_ip_block_status status; 330 const struct amdgpu_ip_block_version *version; 331 }; 332 333 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 334 enum amd_ip_block_type type, 335 u32 major, u32 minor); 336 337 struct amdgpu_ip_block * 338 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 339 enum amd_ip_block_type type); 340 341 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 342 const struct amdgpu_ip_block_version *ip_block_version); 343 344 /* 345 * BIOS. 346 */ 347 bool amdgpu_get_bios(struct amdgpu_device *adev); 348 bool amdgpu_read_bios(struct amdgpu_device *adev); 349 350 /* 351 * Clocks 352 */ 353 354 #define AMDGPU_MAX_PPLL 3 355 356 struct amdgpu_clock { 357 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 358 struct amdgpu_pll spll; 359 struct amdgpu_pll mpll; 360 /* 10 Khz units */ 361 uint32_t default_mclk; 362 uint32_t default_sclk; 363 uint32_t default_dispclk; 364 uint32_t current_dispclk; 365 uint32_t dp_extclk; 366 uint32_t max_pixel_clock; 367 }; 368 369 /* sub-allocation manager, it has to be protected by another lock. 370 * By conception this is an helper for other part of the driver 371 * like the indirect buffer or semaphore, which both have their 372 * locking. 373 * 374 * Principe is simple, we keep a list of sub allocation in offset 375 * order (first entry has offset == 0, last entry has the highest 376 * offset). 377 * 378 * When allocating new object we first check if there is room at 379 * the end total_size - (last_object_offset + last_object_size) >= 380 * alloc_size. If so we allocate new object there. 381 * 382 * When there is not enough room at the end, we start waiting for 383 * each sub object until we reach object_offset+object_size >= 384 * alloc_size, this object then become the sub object we return. 385 * 386 * Alignment can't be bigger than page size. 387 * 388 * Hole are not considered for allocation to keep things simple. 389 * Assumption is that there won't be hole (all object on same 390 * alignment). 391 */ 392 393 #define AMDGPU_SA_NUM_FENCE_LISTS 32 394 395 struct amdgpu_sa_manager { 396 wait_queue_head_t wq; 397 struct amdgpu_bo *bo; 398 struct list_head *hole; 399 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 400 struct list_head olist; 401 unsigned size; 402 uint64_t gpu_addr; 403 void *cpu_ptr; 404 uint32_t domain; 405 uint32_t align; 406 }; 407 408 /* sub-allocation buffer */ 409 struct amdgpu_sa_bo { 410 struct list_head olist; 411 struct list_head flist; 412 struct amdgpu_sa_manager *manager; 413 unsigned soffset; 414 unsigned eoffset; 415 struct dma_fence *fence; 416 }; 417 418 int amdgpu_fence_slab_init(void); 419 void amdgpu_fence_slab_fini(void); 420 421 /* 422 * IRQS. 423 */ 424 425 struct amdgpu_flip_work { 426 struct delayed_work flip_work; 427 struct work_struct unpin_work; 428 struct amdgpu_device *adev; 429 int crtc_id; 430 u32 target_vblank; 431 uint64_t base; 432 struct drm_pending_vblank_event *event; 433 struct amdgpu_bo *old_abo; 434 struct dma_fence *excl; 435 unsigned shared_count; 436 struct dma_fence **shared; 437 struct dma_fence_cb cb; 438 bool async; 439 }; 440 441 442 /* 443 * CP & rings. 444 */ 445 446 struct amdgpu_ib { 447 struct amdgpu_sa_bo *sa_bo; 448 uint32_t length_dw; 449 uint64_t gpu_addr; 450 uint32_t *ptr; 451 uint32_t flags; 452 }; 453 454 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 455 456 /* 457 * file private structure 458 */ 459 460 struct amdgpu_fpriv { 461 struct amdgpu_vm vm; 462 struct amdgpu_bo_va *prt_va; 463 struct amdgpu_bo_va *csa_va; 464 struct mutex bo_list_lock; 465 struct idr bo_list_handles; 466 struct amdgpu_ctx_mgr ctx_mgr; 467 }; 468 469 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 470 471 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 472 unsigned size, 473 enum amdgpu_ib_pool_type pool, 474 struct amdgpu_ib *ib); 475 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 476 struct dma_fence *f); 477 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 478 struct amdgpu_ib *ibs, struct amdgpu_job *job, 479 struct dma_fence **f); 480 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 481 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 482 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 483 484 /* 485 * CS. 486 */ 487 struct amdgpu_cs_chunk { 488 uint32_t chunk_id; 489 uint32_t length_dw; 490 void *kdata; 491 }; 492 493 struct amdgpu_cs_post_dep { 494 struct drm_syncobj *syncobj; 495 struct dma_fence_chain *chain; 496 u64 point; 497 }; 498 499 struct amdgpu_cs_parser { 500 struct amdgpu_device *adev; 501 struct drm_file *filp; 502 struct amdgpu_ctx *ctx; 503 504 /* chunks */ 505 unsigned nchunks; 506 struct amdgpu_cs_chunk *chunks; 507 508 /* scheduler job object */ 509 struct amdgpu_job *job; 510 struct drm_sched_entity *entity; 511 512 /* buffer objects */ 513 struct ww_acquire_ctx ticket; 514 struct amdgpu_bo_list *bo_list; 515 struct amdgpu_mn *mn; 516 struct amdgpu_bo_list_entry vm_pd; 517 struct list_head validated; 518 struct dma_fence *fence; 519 uint64_t bytes_moved_threshold; 520 uint64_t bytes_moved_vis_threshold; 521 uint64_t bytes_moved; 522 uint64_t bytes_moved_vis; 523 524 /* user fence */ 525 struct amdgpu_bo_list_entry uf_entry; 526 527 unsigned num_post_deps; 528 struct amdgpu_cs_post_dep *post_deps; 529 }; 530 531 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 532 uint32_t ib_idx, int idx) 533 { 534 return p->job->ibs[ib_idx].ptr[idx]; 535 } 536 537 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 538 uint32_t ib_idx, int idx, 539 uint32_t value) 540 { 541 p->job->ibs[ib_idx].ptr[idx] = value; 542 } 543 544 /* 545 * Writeback 546 */ 547 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 548 549 struct amdgpu_wb { 550 struct amdgpu_bo *wb_obj; 551 volatile uint32_t *wb; 552 uint64_t gpu_addr; 553 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 554 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 555 }; 556 557 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 558 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 559 560 /* 561 * Benchmarking 562 */ 563 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 564 565 566 /* 567 * Testing 568 */ 569 void amdgpu_test_moves(struct amdgpu_device *adev); 570 571 /* 572 * ASIC specific register table accessible by UMD 573 */ 574 struct amdgpu_allowed_register_entry { 575 uint32_t reg_offset; 576 bool grbm_indexed; 577 }; 578 579 enum amd_reset_method { 580 AMD_RESET_METHOD_LEGACY = 0, 581 AMD_RESET_METHOD_MODE0, 582 AMD_RESET_METHOD_MODE1, 583 AMD_RESET_METHOD_MODE2, 584 AMD_RESET_METHOD_BACO, 585 AMD_RESET_METHOD_PCI, 586 }; 587 588 struct amdgpu_video_codec_info { 589 u32 codec_type; 590 u32 max_width; 591 u32 max_height; 592 u32 max_pixels_per_frame; 593 u32 max_level; 594 }; 595 596 struct amdgpu_video_codecs { 597 const u32 codec_count; 598 const struct amdgpu_video_codec_info *codec_array; 599 }; 600 601 /* 602 * ASIC specific functions. 603 */ 604 struct amdgpu_asic_funcs { 605 bool (*read_disabled_bios)(struct amdgpu_device *adev); 606 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 607 u8 *bios, u32 length_bytes); 608 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 609 u32 sh_num, u32 reg_offset, u32 *value); 610 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 611 int (*reset)(struct amdgpu_device *adev); 612 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 613 /* get the reference clock */ 614 u32 (*get_xclk)(struct amdgpu_device *adev); 615 /* MM block clocks */ 616 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 617 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 618 /* static power management */ 619 int (*get_pcie_lanes)(struct amdgpu_device *adev); 620 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 621 /* get config memsize register */ 622 u32 (*get_config_memsize)(struct amdgpu_device *adev); 623 /* flush hdp write queue */ 624 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 625 /* invalidate hdp read cache */ 626 void (*invalidate_hdp)(struct amdgpu_device *adev, 627 struct amdgpu_ring *ring); 628 /* check if the asic needs a full reset of if soft reset will work */ 629 bool (*need_full_reset)(struct amdgpu_device *adev); 630 /* initialize doorbell layout for specific asic*/ 631 void (*init_doorbell_index)(struct amdgpu_device *adev); 632 /* PCIe bandwidth usage */ 633 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 634 uint64_t *count1); 635 /* do we need to reset the asic at init time (e.g., kexec) */ 636 bool (*need_reset_on_init)(struct amdgpu_device *adev); 637 /* PCIe replay counter */ 638 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 639 /* device supports BACO */ 640 bool (*supports_baco)(struct amdgpu_device *adev); 641 /* pre asic_init quirks */ 642 void (*pre_asic_init)(struct amdgpu_device *adev); 643 /* enter/exit umd stable pstate */ 644 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 645 /* query video codecs */ 646 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 647 const struct amdgpu_video_codecs **codecs); 648 }; 649 650 /* 651 * IOCTL. 652 */ 653 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 654 struct drm_file *filp); 655 656 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 657 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 658 struct drm_file *filp); 659 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 660 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 661 struct drm_file *filp); 662 663 /* VRAM scratch page for HDP bug, default vram page */ 664 struct amdgpu_vram_scratch { 665 struct amdgpu_bo *robj; 666 volatile uint32_t *ptr; 667 u64 gpu_addr; 668 }; 669 670 /* 671 * ACPI 672 */ 673 struct amdgpu_atcs_functions { 674 bool get_ext_state; 675 bool pcie_perf_req; 676 bool pcie_dev_rdy; 677 bool pcie_bus_width; 678 }; 679 680 struct amdgpu_atcs { 681 struct amdgpu_atcs_functions functions; 682 }; 683 684 /* 685 * CGS 686 */ 687 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 688 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 689 690 /* 691 * Core structure, functions and helpers. 692 */ 693 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 694 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 695 696 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 697 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 698 699 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 700 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 701 702 struct amdgpu_mmio_remap { 703 u32 reg_offset; 704 resource_size_t bus_addr; 705 }; 706 707 /* Define the HW IP blocks will be used in driver , add more if necessary */ 708 enum amd_hw_ip_block_type { 709 GC_HWIP = 1, 710 HDP_HWIP, 711 SDMA0_HWIP, 712 SDMA1_HWIP, 713 SDMA2_HWIP, 714 SDMA3_HWIP, 715 SDMA4_HWIP, 716 SDMA5_HWIP, 717 SDMA6_HWIP, 718 SDMA7_HWIP, 719 MMHUB_HWIP, 720 ATHUB_HWIP, 721 NBIO_HWIP, 722 MP0_HWIP, 723 MP1_HWIP, 724 UVD_HWIP, 725 VCN_HWIP = UVD_HWIP, 726 JPEG_HWIP = VCN_HWIP, 727 VCE_HWIP, 728 DF_HWIP, 729 DCE_HWIP, 730 OSSSYS_HWIP, 731 SMUIO_HWIP, 732 PWR_HWIP, 733 NBIF_HWIP, 734 THM_HWIP, 735 CLK_HWIP, 736 UMC_HWIP, 737 RSMU_HWIP, 738 MAX_HWIP 739 }; 740 741 #define HWIP_MAX_INSTANCE 8 742 743 struct amd_powerplay { 744 void *pp_handle; 745 const struct amd_pm_funcs *pp_funcs; 746 }; 747 748 /* polaris10 kickers */ 749 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 750 ((rid == 0xE3) || \ 751 (rid == 0xE4) || \ 752 (rid == 0xE5) || \ 753 (rid == 0xE7) || \ 754 (rid == 0xEF))) || \ 755 ((did == 0x6FDF) && \ 756 ((rid == 0xE7) || \ 757 (rid == 0xEF) || \ 758 (rid == 0xFF)))) 759 760 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 761 ((rid == 0xE1) || \ 762 (rid == 0xF7))) 763 764 /* polaris11 kickers */ 765 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 766 ((rid == 0xE0) || \ 767 (rid == 0xE5))) || \ 768 ((did == 0x67FF) && \ 769 ((rid == 0xCF) || \ 770 (rid == 0xEF) || \ 771 (rid == 0xFF)))) 772 773 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 774 ((rid == 0xE2))) 775 776 /* polaris12 kickers */ 777 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 778 ((rid == 0xC0) || \ 779 (rid == 0xC1) || \ 780 (rid == 0xC3) || \ 781 (rid == 0xC7))) || \ 782 ((did == 0x6981) && \ 783 ((rid == 0x00) || \ 784 (rid == 0x01) || \ 785 (rid == 0x10)))) 786 787 #define AMDGPU_RESET_MAGIC_NUM 64 788 #define AMDGPU_MAX_DF_PERFMONS 4 789 struct amdgpu_device { 790 struct device *dev; 791 struct pci_dev *pdev; 792 struct drm_device ddev; 793 794 #ifdef CONFIG_DRM_AMD_ACP 795 struct amdgpu_acp acp; 796 #endif 797 struct amdgpu_hive_info *hive; 798 /* ASIC */ 799 enum amd_asic_type asic_type; 800 uint32_t family; 801 uint32_t rev_id; 802 uint32_t external_rev_id; 803 unsigned long flags; 804 unsigned long apu_flags; 805 int usec_timeout; 806 const struct amdgpu_asic_funcs *asic_funcs; 807 bool shutdown; 808 bool need_swiotlb; 809 bool accel_working; 810 struct notifier_block acpi_nb; 811 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 812 struct debugfs_blob_wrapper debugfs_vbios_blob; 813 struct amdgpu_atif *atif; 814 struct amdgpu_atcs atcs; 815 struct mutex srbm_mutex; 816 /* GRBM index mutex. Protects concurrent access to GRBM index */ 817 struct mutex grbm_idx_mutex; 818 struct dev_pm_domain vga_pm_domain; 819 bool have_disp_power_ref; 820 bool have_atomics_support; 821 822 /* BIOS */ 823 bool is_atom_fw; 824 uint8_t *bios; 825 uint32_t bios_size; 826 uint32_t bios_scratch_reg_offset; 827 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 828 829 /* Register/doorbell mmio */ 830 resource_size_t rmmio_base; 831 resource_size_t rmmio_size; 832 void __iomem *rmmio; 833 /* protects concurrent MM_INDEX/DATA based register access */ 834 spinlock_t mmio_idx_lock; 835 struct amdgpu_mmio_remap rmmio_remap; 836 /* protects concurrent SMC based register access */ 837 spinlock_t smc_idx_lock; 838 amdgpu_rreg_t smc_rreg; 839 amdgpu_wreg_t smc_wreg; 840 /* protects concurrent PCIE register access */ 841 spinlock_t pcie_idx_lock; 842 amdgpu_rreg_t pcie_rreg; 843 amdgpu_wreg_t pcie_wreg; 844 amdgpu_rreg_t pciep_rreg; 845 amdgpu_wreg_t pciep_wreg; 846 amdgpu_rreg64_t pcie_rreg64; 847 amdgpu_wreg64_t pcie_wreg64; 848 /* protects concurrent UVD register access */ 849 spinlock_t uvd_ctx_idx_lock; 850 amdgpu_rreg_t uvd_ctx_rreg; 851 amdgpu_wreg_t uvd_ctx_wreg; 852 /* protects concurrent DIDT register access */ 853 spinlock_t didt_idx_lock; 854 amdgpu_rreg_t didt_rreg; 855 amdgpu_wreg_t didt_wreg; 856 /* protects concurrent gc_cac register access */ 857 spinlock_t gc_cac_idx_lock; 858 amdgpu_rreg_t gc_cac_rreg; 859 amdgpu_wreg_t gc_cac_wreg; 860 /* protects concurrent se_cac register access */ 861 spinlock_t se_cac_idx_lock; 862 amdgpu_rreg_t se_cac_rreg; 863 amdgpu_wreg_t se_cac_wreg; 864 /* protects concurrent ENDPOINT (audio) register access */ 865 spinlock_t audio_endpt_idx_lock; 866 amdgpu_block_rreg_t audio_endpt_rreg; 867 amdgpu_block_wreg_t audio_endpt_wreg; 868 void __iomem *rio_mem; 869 resource_size_t rio_mem_size; 870 struct amdgpu_doorbell doorbell; 871 872 /* clock/pll info */ 873 struct amdgpu_clock clock; 874 875 /* MC */ 876 struct amdgpu_gmc gmc; 877 struct amdgpu_gart gart; 878 dma_addr_t dummy_page_addr; 879 struct amdgpu_vm_manager vm_manager; 880 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 881 unsigned num_vmhubs; 882 883 /* memory management */ 884 struct amdgpu_mman mman; 885 struct amdgpu_vram_scratch vram_scratch; 886 struct amdgpu_wb wb; 887 atomic64_t num_bytes_moved; 888 atomic64_t num_evictions; 889 atomic64_t num_vram_cpu_page_faults; 890 atomic_t gpu_reset_counter; 891 atomic_t vram_lost_counter; 892 893 /* data for buffer migration throttling */ 894 struct { 895 spinlock_t lock; 896 s64 last_update_us; 897 s64 accum_us; /* accumulated microseconds */ 898 s64 accum_us_vis; /* for visible VRAM */ 899 u32 log2_max_MBps; 900 } mm_stats; 901 902 /* display */ 903 bool enable_virtual_display; 904 struct amdgpu_mode_info mode_info; 905 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 906 struct work_struct hotplug_work; 907 struct amdgpu_irq_src crtc_irq; 908 struct amdgpu_irq_src vline0_irq; 909 struct amdgpu_irq_src vupdate_irq; 910 struct amdgpu_irq_src pageflip_irq; 911 struct amdgpu_irq_src hpd_irq; 912 struct amdgpu_irq_src dmub_trace_irq; 913 914 /* rings */ 915 u64 fence_context; 916 unsigned num_rings; 917 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 918 bool ib_pool_ready; 919 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 920 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 921 922 /* interrupts */ 923 struct amdgpu_irq irq; 924 925 /* powerplay */ 926 struct amd_powerplay powerplay; 927 bool pp_force_state_enabled; 928 929 /* smu */ 930 struct smu_context smu; 931 932 /* dpm */ 933 struct amdgpu_pm pm; 934 u32 cg_flags; 935 u32 pg_flags; 936 937 /* nbio */ 938 struct amdgpu_nbio nbio; 939 940 /* hdp */ 941 struct amdgpu_hdp hdp; 942 943 /* smuio */ 944 struct amdgpu_smuio smuio; 945 946 /* mmhub */ 947 struct amdgpu_mmhub mmhub; 948 949 /* gfxhub */ 950 struct amdgpu_gfxhub gfxhub; 951 952 /* gfx */ 953 struct amdgpu_gfx gfx; 954 955 /* sdma */ 956 struct amdgpu_sdma sdma; 957 958 /* uvd */ 959 struct amdgpu_uvd uvd; 960 961 /* vce */ 962 struct amdgpu_vce vce; 963 964 /* vcn */ 965 struct amdgpu_vcn vcn; 966 967 /* jpeg */ 968 struct amdgpu_jpeg jpeg; 969 970 /* firmwares */ 971 struct amdgpu_firmware firmware; 972 973 /* PSP */ 974 struct psp_context psp; 975 976 /* GDS */ 977 struct amdgpu_gds gds; 978 979 /* KFD */ 980 struct amdgpu_kfd_dev kfd; 981 982 /* UMC */ 983 struct amdgpu_umc umc; 984 985 /* display related functionality */ 986 struct amdgpu_display_manager dm; 987 988 /* mes */ 989 bool enable_mes; 990 struct amdgpu_mes mes; 991 992 /* df */ 993 struct amdgpu_df df; 994 995 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 996 int num_ip_blocks; 997 struct mutex mn_lock; 998 DECLARE_HASHTABLE(mn_hash, 7); 999 1000 /* tracking pinned memory */ 1001 atomic64_t vram_pin_size; 1002 atomic64_t visible_pin_size; 1003 atomic64_t gart_pin_size; 1004 1005 /* soc15 register offset based on ip, instance and segment */ 1006 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1007 1008 /* delayed work_func for deferring clockgating during resume */ 1009 struct delayed_work delayed_init_work; 1010 1011 struct amdgpu_virt virt; 1012 1013 /* link all shadow bo */ 1014 struct list_head shadow_list; 1015 struct mutex shadow_list_lock; 1016 1017 /* record hw reset is performed */ 1018 bool has_hw_reset; 1019 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1020 1021 /* s3/s4 mask */ 1022 bool in_suspend; 1023 bool in_hibernate; 1024 1025 /* 1026 * The combination flag in_poweroff_reboot_com used to identify the poweroff 1027 * and reboot opt in the s0i3 system-wide suspend. 1028 */ 1029 bool in_poweroff_reboot_com; 1030 1031 atomic_t in_gpu_reset; 1032 enum pp_mp1_state mp1_state; 1033 struct rw_semaphore reset_sem; 1034 struct amdgpu_doorbell_index doorbell_index; 1035 1036 struct mutex notifier_lock; 1037 1038 int asic_reset_res; 1039 struct work_struct xgmi_reset_work; 1040 1041 long gfx_timeout; 1042 long sdma_timeout; 1043 long video_timeout; 1044 long compute_timeout; 1045 1046 uint64_t unique_id; 1047 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1048 1049 /* enable runtime pm on the device */ 1050 bool runpm; 1051 bool in_runpm; 1052 bool has_pr3; 1053 1054 bool pm_sysfs_en; 1055 bool ucode_sysfs_en; 1056 1057 /* Chip product information */ 1058 char product_number[16]; 1059 char product_name[32]; 1060 char serial[20]; 1061 1062 struct amdgpu_autodump autodump; 1063 1064 atomic_t throttling_logging_enabled; 1065 struct ratelimit_state throttling_logging_rs; 1066 uint32_t ras_features; 1067 1068 bool in_pci_err_recovery; 1069 struct pci_saved_state *pci_state; 1070 }; 1071 1072 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1073 { 1074 return container_of(ddev, struct amdgpu_device, ddev); 1075 } 1076 1077 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1078 { 1079 return &adev->ddev; 1080 } 1081 1082 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1083 { 1084 return container_of(bdev, struct amdgpu_device, mman.bdev); 1085 } 1086 1087 int amdgpu_device_init(struct amdgpu_device *adev, 1088 uint32_t flags); 1089 void amdgpu_device_fini(struct amdgpu_device *adev); 1090 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1091 1092 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1093 uint32_t *buf, size_t size, bool write); 1094 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1095 uint32_t reg, uint32_t acc_flags); 1096 void amdgpu_device_wreg(struct amdgpu_device *adev, 1097 uint32_t reg, uint32_t v, 1098 uint32_t acc_flags); 1099 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1100 uint32_t reg, uint32_t v); 1101 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1102 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1103 1104 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1105 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1106 1107 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1108 u32 pcie_index, u32 pcie_data, 1109 u32 reg_addr); 1110 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1111 u32 pcie_index, u32 pcie_data, 1112 u32 reg_addr); 1113 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1114 u32 pcie_index, u32 pcie_data, 1115 u32 reg_addr, u32 reg_data); 1116 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1117 u32 pcie_index, u32 pcie_data, 1118 u32 reg_addr, u64 reg_data); 1119 1120 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1121 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1122 1123 int emu_soc_asic_init(struct amdgpu_device *adev); 1124 1125 /* 1126 * Registers read & write functions. 1127 */ 1128 #define AMDGPU_REGS_NO_KIQ (1<<1) 1129 1130 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1131 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1132 1133 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1134 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1135 1136 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1137 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1138 1139 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1140 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1141 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1142 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1143 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1144 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1145 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1146 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1147 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1148 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1149 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1150 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1151 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1152 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1153 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1154 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1155 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1156 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1157 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1158 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1159 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1160 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1161 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1162 #define WREG32_P(reg, val, mask) \ 1163 do { \ 1164 uint32_t tmp_ = RREG32(reg); \ 1165 tmp_ &= (mask); \ 1166 tmp_ |= ((val) & ~(mask)); \ 1167 WREG32(reg, tmp_); \ 1168 } while (0) 1169 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1170 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1171 #define WREG32_PLL_P(reg, val, mask) \ 1172 do { \ 1173 uint32_t tmp_ = RREG32_PLL(reg); \ 1174 tmp_ &= (mask); \ 1175 tmp_ |= ((val) & ~(mask)); \ 1176 WREG32_PLL(reg, tmp_); \ 1177 } while (0) 1178 1179 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1180 do { \ 1181 u32 tmp = RREG32_SMC(_Reg); \ 1182 tmp &= (_Mask); \ 1183 tmp |= ((_Val) & ~(_Mask)); \ 1184 WREG32_SMC(_Reg, tmp); \ 1185 } while (0) 1186 1187 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1188 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1189 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1190 1191 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1192 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1193 1194 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1195 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1196 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1197 1198 #define REG_GET_FIELD(value, reg, field) \ 1199 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1200 1201 #define WREG32_FIELD(reg, field, val) \ 1202 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1203 1204 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1205 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1206 1207 /* 1208 * BIOS helpers. 1209 */ 1210 #define RBIOS8(i) (adev->bios[i]) 1211 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1212 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1213 1214 /* 1215 * ASICs macro. 1216 */ 1217 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1218 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1219 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1220 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1221 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1222 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1223 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1224 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1225 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1226 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1227 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1228 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1229 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1230 #define amdgpu_asic_flush_hdp(adev, r) \ 1231 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1232 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1233 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r))) 1234 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1235 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1236 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1237 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1238 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1239 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1240 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1241 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1242 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1243 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1244 1245 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1246 1247 /* Common functions */ 1248 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1249 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1250 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1251 struct amdgpu_job* job); 1252 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1253 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1254 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1255 1256 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1257 u64 num_vis_bytes); 1258 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1259 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1260 const u32 *registers, 1261 const u32 array_size); 1262 1263 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1264 bool amdgpu_device_supports_boco(struct drm_device *dev); 1265 bool amdgpu_device_supports_baco(struct drm_device *dev); 1266 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1267 struct amdgpu_device *peer_adev); 1268 int amdgpu_device_baco_enter(struct drm_device *dev); 1269 int amdgpu_device_baco_exit(struct drm_device *dev); 1270 1271 /* atpx handler */ 1272 #if defined(CONFIG_VGA_SWITCHEROO) 1273 void amdgpu_register_atpx_handler(void); 1274 void amdgpu_unregister_atpx_handler(void); 1275 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1276 bool amdgpu_is_atpx_hybrid(void); 1277 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1278 bool amdgpu_has_atpx(void); 1279 #else 1280 static inline void amdgpu_register_atpx_handler(void) {} 1281 static inline void amdgpu_unregister_atpx_handler(void) {} 1282 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1283 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1284 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1285 static inline bool amdgpu_has_atpx(void) { return false; } 1286 #endif 1287 1288 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1289 void *amdgpu_atpx_get_dhandle(void); 1290 #else 1291 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1292 #endif 1293 1294 /* 1295 * KMS 1296 */ 1297 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1298 extern const int amdgpu_max_kms_ioctl; 1299 1300 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1301 void amdgpu_driver_unload_kms(struct drm_device *dev); 1302 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1303 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1304 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1305 struct drm_file *file_priv); 1306 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1307 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1308 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1309 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1310 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1311 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1312 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1313 unsigned long arg); 1314 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1315 struct drm_file *filp); 1316 1317 /* 1318 * functions used by amdgpu_encoder.c 1319 */ 1320 struct amdgpu_afmt_acr { 1321 u32 clock; 1322 1323 int n_32khz; 1324 int cts_32khz; 1325 1326 int n_44_1khz; 1327 int cts_44_1khz; 1328 1329 int n_48khz; 1330 int cts_48khz; 1331 1332 }; 1333 1334 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1335 1336 /* amdgpu_acpi.c */ 1337 #if defined(CONFIG_ACPI) 1338 int amdgpu_acpi_init(struct amdgpu_device *adev); 1339 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1340 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1341 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1342 u8 perf_req, bool advertise); 1343 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1344 1345 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1346 struct amdgpu_dm_backlight_caps *caps); 1347 bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev); 1348 #else 1349 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1350 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1351 static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; } 1352 #endif 1353 1354 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1355 uint64_t addr, struct amdgpu_bo **bo, 1356 struct amdgpu_bo_va_mapping **mapping); 1357 1358 #if defined(CONFIG_DRM_AMD_DC) 1359 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1360 #else 1361 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1362 #endif 1363 1364 1365 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1366 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1367 1368 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1369 pci_channel_state_t state); 1370 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1371 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1372 void amdgpu_pci_resume(struct pci_dev *pdev); 1373 1374 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1375 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1376 1377 #include "amdgpu_object.h" 1378 1379 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1380 { 1381 return adev->gmc.tmz_enabled; 1382 } 1383 1384 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1385 { 1386 return atomic_read(&adev->in_gpu_reset); 1387 } 1388 #endif 1389