1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include "amdgpu_ctx.h" 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/rbtree.h> 38 #include <linux/hashtable.h> 39 #include <linux/dma-fence.h> 40 41 #include <drm/ttm/ttm_bo_api.h> 42 #include <drm/ttm/ttm_bo_driver.h> 43 #include <drm/ttm/ttm_placement.h> 44 #include <drm/ttm/ttm_module.h> 45 #include <drm/ttm/ttm_execbuf_util.h> 46 47 #include <drm/amdgpu_drm.h> 48 #include <drm/drm_gem.h> 49 #include <drm/drm_ioctl.h> 50 #include <drm/gpu_scheduler.h> 51 52 #include <kgd_kfd_interface.h> 53 #include "dm_pp_interface.h" 54 #include "kgd_pp_interface.h" 55 56 #include "amd_shared.h" 57 #include "amdgpu_mode.h" 58 #include "amdgpu_ih.h" 59 #include "amdgpu_irq.h" 60 #include "amdgpu_ucode.h" 61 #include "amdgpu_ttm.h" 62 #include "amdgpu_psp.h" 63 #include "amdgpu_gds.h" 64 #include "amdgpu_sync.h" 65 #include "amdgpu_ring.h" 66 #include "amdgpu_vm.h" 67 #include "amdgpu_dpm.h" 68 #include "amdgpu_acp.h" 69 #include "amdgpu_uvd.h" 70 #include "amdgpu_vce.h" 71 #include "amdgpu_vcn.h" 72 #include "amdgpu_mn.h" 73 #include "amdgpu_gmc.h" 74 #include "amdgpu_gfx.h" 75 #include "amdgpu_sdma.h" 76 #include "amdgpu_nbio.h" 77 #include "amdgpu_dm.h" 78 #include "amdgpu_virt.h" 79 #include "amdgpu_csa.h" 80 #include "amdgpu_gart.h" 81 #include "amdgpu_debugfs.h" 82 #include "amdgpu_job.h" 83 #include "amdgpu_bo_list.h" 84 #include "amdgpu_gem.h" 85 #include "amdgpu_doorbell.h" 86 #include "amdgpu_amdkfd.h" 87 #include "amdgpu_smu.h" 88 #include "amdgpu_discovery.h" 89 #include "amdgpu_mes.h" 90 #include "amdgpu_umc.h" 91 #include "amdgpu_mmhub.h" 92 93 #define MAX_GPU_INSTANCE 16 94 95 struct amdgpu_gpu_instance 96 { 97 struct amdgpu_device *adev; 98 int mgpu_fan_enabled; 99 }; 100 101 struct amdgpu_mgpu_info 102 { 103 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 104 struct mutex mutex; 105 uint32_t num_gpu; 106 uint32_t num_dgpu; 107 uint32_t num_apu; 108 }; 109 110 /* 111 * Modules parameters. 112 */ 113 extern int amdgpu_modeset; 114 extern int amdgpu_vram_limit; 115 extern int amdgpu_vis_vram_limit; 116 extern int amdgpu_gart_size; 117 extern int amdgpu_gtt_size; 118 extern int amdgpu_moverate; 119 extern int amdgpu_benchmarking; 120 extern int amdgpu_testing; 121 extern int amdgpu_audio; 122 extern int amdgpu_disp_priority; 123 extern int amdgpu_hw_i2c; 124 extern int amdgpu_pcie_gen2; 125 extern int amdgpu_msi; 126 extern int amdgpu_dpm; 127 extern int amdgpu_fw_load_type; 128 extern int amdgpu_aspm; 129 extern int amdgpu_runtime_pm; 130 extern uint amdgpu_ip_block_mask; 131 extern int amdgpu_bapm; 132 extern int amdgpu_deep_color; 133 extern int amdgpu_vm_size; 134 extern int amdgpu_vm_block_size; 135 extern int amdgpu_vm_fragment_size; 136 extern int amdgpu_vm_fault_stop; 137 extern int amdgpu_vm_debug; 138 extern int amdgpu_vm_update_mode; 139 extern int amdgpu_dc; 140 extern int amdgpu_sched_jobs; 141 extern int amdgpu_sched_hw_submission; 142 extern uint amdgpu_pcie_gen_cap; 143 extern uint amdgpu_pcie_lane_cap; 144 extern uint amdgpu_cg_mask; 145 extern uint amdgpu_pg_mask; 146 extern uint amdgpu_sdma_phase_quantum; 147 extern char *amdgpu_disable_cu; 148 extern char *amdgpu_virtual_display; 149 extern uint amdgpu_pp_feature_mask; 150 extern int amdgpu_ngg; 151 extern int amdgpu_prim_buf_per_se; 152 extern int amdgpu_pos_buf_per_se; 153 extern int amdgpu_cntl_sb_buf_per_se; 154 extern int amdgpu_param_buf_per_se; 155 extern int amdgpu_job_hang_limit; 156 extern int amdgpu_lbpw; 157 extern int amdgpu_compute_multipipe; 158 extern int amdgpu_gpu_recovery; 159 extern int amdgpu_emu_mode; 160 extern uint amdgpu_smu_memory_pool_size; 161 extern uint amdgpu_dc_feature_mask; 162 extern uint amdgpu_dm_abm_level; 163 extern struct amdgpu_mgpu_info mgpu_info; 164 extern int amdgpu_ras_enable; 165 extern uint amdgpu_ras_mask; 166 extern int amdgpu_async_gfx_ring; 167 extern int amdgpu_mcbp; 168 extern int amdgpu_discovery; 169 extern int amdgpu_mes; 170 extern int amdgpu_noretry; 171 172 #ifdef CONFIG_DRM_AMDGPU_SI 173 extern int amdgpu_si_support; 174 #endif 175 #ifdef CONFIG_DRM_AMDGPU_CIK 176 extern int amdgpu_cik_support; 177 #endif 178 179 #define AMDGPU_VM_MAX_NUM_CTX 4096 180 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 181 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 182 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 183 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 184 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 185 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 186 #define AMDGPU_IB_POOL_SIZE 16 187 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 188 #define AMDGPUFB_CONN_LIMIT 4 189 #define AMDGPU_BIOS_NUM_SCRATCH 16 190 191 /* hard reset data */ 192 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 193 194 /* reset flags */ 195 #define AMDGPU_RESET_GFX (1 << 0) 196 #define AMDGPU_RESET_COMPUTE (1 << 1) 197 #define AMDGPU_RESET_DMA (1 << 2) 198 #define AMDGPU_RESET_CP (1 << 3) 199 #define AMDGPU_RESET_GRBM (1 << 4) 200 #define AMDGPU_RESET_DMA1 (1 << 5) 201 #define AMDGPU_RESET_RLC (1 << 6) 202 #define AMDGPU_RESET_SEM (1 << 7) 203 #define AMDGPU_RESET_IH (1 << 8) 204 #define AMDGPU_RESET_VMC (1 << 9) 205 #define AMDGPU_RESET_MC (1 << 10) 206 #define AMDGPU_RESET_DISPLAY (1 << 11) 207 #define AMDGPU_RESET_UVD (1 << 12) 208 #define AMDGPU_RESET_VCE (1 << 13) 209 #define AMDGPU_RESET_VCE1 (1 << 14) 210 211 /* max cursor sizes (in pixels) */ 212 #define CIK_CURSOR_WIDTH 128 213 #define CIK_CURSOR_HEIGHT 128 214 215 struct amdgpu_device; 216 struct amdgpu_ib; 217 struct amdgpu_cs_parser; 218 struct amdgpu_job; 219 struct amdgpu_irq_src; 220 struct amdgpu_fpriv; 221 struct amdgpu_bo_va_mapping; 222 struct amdgpu_atif; 223 struct kfd_vm_fault_info; 224 225 enum amdgpu_cp_irq { 226 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 227 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 228 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 229 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 230 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 231 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 232 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 233 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 234 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 235 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 236 237 AMDGPU_CP_IRQ_LAST 238 }; 239 240 enum amdgpu_thermal_irq { 241 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 242 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 243 244 AMDGPU_THERMAL_IRQ_LAST 245 }; 246 247 enum amdgpu_kiq_irq { 248 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 249 AMDGPU_CP_KIQ_IRQ_LAST 250 }; 251 252 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 253 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 254 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 255 256 int amdgpu_device_ip_set_clockgating_state(void *dev, 257 enum amd_ip_block_type block_type, 258 enum amd_clockgating_state state); 259 int amdgpu_device_ip_set_powergating_state(void *dev, 260 enum amd_ip_block_type block_type, 261 enum amd_powergating_state state); 262 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 263 u32 *flags); 264 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 265 enum amd_ip_block_type block_type); 266 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 267 enum amd_ip_block_type block_type); 268 269 #define AMDGPU_MAX_IP_NUM 16 270 271 struct amdgpu_ip_block_status { 272 bool valid; 273 bool sw; 274 bool hw; 275 bool late_initialized; 276 bool hang; 277 }; 278 279 struct amdgpu_ip_block_version { 280 const enum amd_ip_block_type type; 281 const u32 major; 282 const u32 minor; 283 const u32 rev; 284 const struct amd_ip_funcs *funcs; 285 }; 286 287 struct amdgpu_ip_block { 288 struct amdgpu_ip_block_status status; 289 const struct amdgpu_ip_block_version *version; 290 }; 291 292 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 293 enum amd_ip_block_type type, 294 u32 major, u32 minor); 295 296 struct amdgpu_ip_block * 297 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 298 enum amd_ip_block_type type); 299 300 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 301 const struct amdgpu_ip_block_version *ip_block_version); 302 303 /* 304 * BIOS. 305 */ 306 bool amdgpu_get_bios(struct amdgpu_device *adev); 307 bool amdgpu_read_bios(struct amdgpu_device *adev); 308 309 /* 310 * Clocks 311 */ 312 313 #define AMDGPU_MAX_PPLL 3 314 315 struct amdgpu_clock { 316 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 317 struct amdgpu_pll spll; 318 struct amdgpu_pll mpll; 319 /* 10 Khz units */ 320 uint32_t default_mclk; 321 uint32_t default_sclk; 322 uint32_t default_dispclk; 323 uint32_t current_dispclk; 324 uint32_t dp_extclk; 325 uint32_t max_pixel_clock; 326 }; 327 328 /* sub-allocation manager, it has to be protected by another lock. 329 * By conception this is an helper for other part of the driver 330 * like the indirect buffer or semaphore, which both have their 331 * locking. 332 * 333 * Principe is simple, we keep a list of sub allocation in offset 334 * order (first entry has offset == 0, last entry has the highest 335 * offset). 336 * 337 * When allocating new object we first check if there is room at 338 * the end total_size - (last_object_offset + last_object_size) >= 339 * alloc_size. If so we allocate new object there. 340 * 341 * When there is not enough room at the end, we start waiting for 342 * each sub object until we reach object_offset+object_size >= 343 * alloc_size, this object then become the sub object we return. 344 * 345 * Alignment can't be bigger than page size. 346 * 347 * Hole are not considered for allocation to keep things simple. 348 * Assumption is that there won't be hole (all object on same 349 * alignment). 350 */ 351 352 #define AMDGPU_SA_NUM_FENCE_LISTS 32 353 354 struct amdgpu_sa_manager { 355 wait_queue_head_t wq; 356 struct amdgpu_bo *bo; 357 struct list_head *hole; 358 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 359 struct list_head olist; 360 unsigned size; 361 uint64_t gpu_addr; 362 void *cpu_ptr; 363 uint32_t domain; 364 uint32_t align; 365 }; 366 367 /* sub-allocation buffer */ 368 struct amdgpu_sa_bo { 369 struct list_head olist; 370 struct list_head flist; 371 struct amdgpu_sa_manager *manager; 372 unsigned soffset; 373 unsigned eoffset; 374 struct dma_fence *fence; 375 }; 376 377 int amdgpu_fence_slab_init(void); 378 void amdgpu_fence_slab_fini(void); 379 380 /* 381 * IRQS. 382 */ 383 384 struct amdgpu_flip_work { 385 struct delayed_work flip_work; 386 struct work_struct unpin_work; 387 struct amdgpu_device *adev; 388 int crtc_id; 389 u32 target_vblank; 390 uint64_t base; 391 struct drm_pending_vblank_event *event; 392 struct amdgpu_bo *old_abo; 393 struct dma_fence *excl; 394 unsigned shared_count; 395 struct dma_fence **shared; 396 struct dma_fence_cb cb; 397 bool async; 398 }; 399 400 401 /* 402 * CP & rings. 403 */ 404 405 struct amdgpu_ib { 406 struct amdgpu_sa_bo *sa_bo; 407 uint32_t length_dw; 408 uint64_t gpu_addr; 409 uint32_t *ptr; 410 uint32_t flags; 411 }; 412 413 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 414 415 /* 416 * file private structure 417 */ 418 419 struct amdgpu_fpriv { 420 struct amdgpu_vm vm; 421 struct amdgpu_bo_va *prt_va; 422 struct amdgpu_bo_va *csa_va; 423 struct mutex bo_list_lock; 424 struct idr bo_list_handles; 425 struct amdgpu_ctx_mgr ctx_mgr; 426 }; 427 428 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 429 int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev); 430 431 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 432 unsigned size, struct amdgpu_ib *ib); 433 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 434 struct dma_fence *f); 435 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 436 struct amdgpu_ib *ibs, struct amdgpu_job *job, 437 struct dma_fence **f); 438 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 439 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 440 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 441 442 /* 443 * CS. 444 */ 445 struct amdgpu_cs_chunk { 446 uint32_t chunk_id; 447 uint32_t length_dw; 448 void *kdata; 449 }; 450 451 struct amdgpu_cs_post_dep { 452 struct drm_syncobj *syncobj; 453 struct dma_fence_chain *chain; 454 u64 point; 455 }; 456 457 struct amdgpu_cs_parser { 458 struct amdgpu_device *adev; 459 struct drm_file *filp; 460 struct amdgpu_ctx *ctx; 461 462 /* chunks */ 463 unsigned nchunks; 464 struct amdgpu_cs_chunk *chunks; 465 466 /* scheduler job object */ 467 struct amdgpu_job *job; 468 struct drm_sched_entity *entity; 469 470 /* buffer objects */ 471 struct ww_acquire_ctx ticket; 472 struct amdgpu_bo_list *bo_list; 473 struct amdgpu_mn *mn; 474 struct amdgpu_bo_list_entry vm_pd; 475 struct list_head validated; 476 struct dma_fence *fence; 477 uint64_t bytes_moved_threshold; 478 uint64_t bytes_moved_vis_threshold; 479 uint64_t bytes_moved; 480 uint64_t bytes_moved_vis; 481 struct amdgpu_bo_list_entry *evictable; 482 483 /* user fence */ 484 struct amdgpu_bo_list_entry uf_entry; 485 486 unsigned num_post_deps; 487 struct amdgpu_cs_post_dep *post_deps; 488 }; 489 490 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 491 uint32_t ib_idx, int idx) 492 { 493 return p->job->ibs[ib_idx].ptr[idx]; 494 } 495 496 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 497 uint32_t ib_idx, int idx, 498 uint32_t value) 499 { 500 p->job->ibs[ib_idx].ptr[idx] = value; 501 } 502 503 /* 504 * Writeback 505 */ 506 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 507 508 struct amdgpu_wb { 509 struct amdgpu_bo *wb_obj; 510 volatile uint32_t *wb; 511 uint64_t gpu_addr; 512 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 513 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 514 }; 515 516 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 517 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 518 519 /* 520 * Benchmarking 521 */ 522 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 523 524 525 /* 526 * Testing 527 */ 528 void amdgpu_test_moves(struct amdgpu_device *adev); 529 530 /* 531 * ASIC specific register table accessible by UMD 532 */ 533 struct amdgpu_allowed_register_entry { 534 uint32_t reg_offset; 535 bool grbm_indexed; 536 }; 537 538 enum amd_reset_method { 539 AMD_RESET_METHOD_LEGACY = 0, 540 AMD_RESET_METHOD_MODE0, 541 AMD_RESET_METHOD_MODE1, 542 AMD_RESET_METHOD_MODE2, 543 AMD_RESET_METHOD_BACO 544 }; 545 546 /* 547 * ASIC specific functions. 548 */ 549 struct amdgpu_asic_funcs { 550 bool (*read_disabled_bios)(struct amdgpu_device *adev); 551 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 552 u8 *bios, u32 length_bytes); 553 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 554 u32 sh_num, u32 reg_offset, u32 *value); 555 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 556 int (*reset)(struct amdgpu_device *adev); 557 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 558 /* get the reference clock */ 559 u32 (*get_xclk)(struct amdgpu_device *adev); 560 /* MM block clocks */ 561 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 562 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 563 /* static power management */ 564 int (*get_pcie_lanes)(struct amdgpu_device *adev); 565 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 566 /* get config memsize register */ 567 u32 (*get_config_memsize)(struct amdgpu_device *adev); 568 /* flush hdp write queue */ 569 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 570 /* invalidate hdp read cache */ 571 void (*invalidate_hdp)(struct amdgpu_device *adev, 572 struct amdgpu_ring *ring); 573 /* check if the asic needs a full reset of if soft reset will work */ 574 bool (*need_full_reset)(struct amdgpu_device *adev); 575 /* initialize doorbell layout for specific asic*/ 576 void (*init_doorbell_index)(struct amdgpu_device *adev); 577 /* PCIe bandwidth usage */ 578 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 579 uint64_t *count1); 580 /* do we need to reset the asic at init time (e.g., kexec) */ 581 bool (*need_reset_on_init)(struct amdgpu_device *adev); 582 /* PCIe replay counter */ 583 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 584 }; 585 586 /* 587 * IOCTL. 588 */ 589 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 590 struct drm_file *filp); 591 592 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 593 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 594 struct drm_file *filp); 595 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 596 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 597 struct drm_file *filp); 598 599 /* VRAM scratch page for HDP bug, default vram page */ 600 struct amdgpu_vram_scratch { 601 struct amdgpu_bo *robj; 602 volatile uint32_t *ptr; 603 u64 gpu_addr; 604 }; 605 606 /* 607 * ACPI 608 */ 609 struct amdgpu_atcs_functions { 610 bool get_ext_state; 611 bool pcie_perf_req; 612 bool pcie_dev_rdy; 613 bool pcie_bus_width; 614 }; 615 616 struct amdgpu_atcs { 617 struct amdgpu_atcs_functions functions; 618 }; 619 620 /* 621 * Firmware VRAM reservation 622 */ 623 struct amdgpu_fw_vram_usage { 624 u64 start_offset; 625 u64 size; 626 struct amdgpu_bo *reserved_bo; 627 void *va; 628 }; 629 630 /* 631 * CGS 632 */ 633 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 634 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 635 636 /* 637 * Core structure, functions and helpers. 638 */ 639 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 640 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 641 642 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 643 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 644 645 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 646 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 647 648 struct amdgpu_mmio_remap { 649 u32 reg_offset; 650 resource_size_t bus_addr; 651 }; 652 653 struct amdgpu_df_funcs { 654 void (*sw_init)(struct amdgpu_device *adev); 655 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 656 bool enable); 657 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 658 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 659 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 660 bool enable); 661 void (*get_clockgating_state)(struct amdgpu_device *adev, 662 u32 *flags); 663 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 664 bool enable); 665 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config, 666 int is_enable); 667 int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config, 668 int is_disable); 669 void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config, 670 uint64_t *count); 671 uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val); 672 void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val, 673 uint32_t ficadl_val, uint32_t ficadh_val); 674 }; 675 /* Define the HW IP blocks will be used in driver , add more if necessary */ 676 enum amd_hw_ip_block_type { 677 GC_HWIP = 1, 678 HDP_HWIP, 679 SDMA0_HWIP, 680 SDMA1_HWIP, 681 SDMA2_HWIP, 682 SDMA3_HWIP, 683 SDMA4_HWIP, 684 SDMA5_HWIP, 685 SDMA6_HWIP, 686 SDMA7_HWIP, 687 MMHUB_HWIP, 688 ATHUB_HWIP, 689 NBIO_HWIP, 690 MP0_HWIP, 691 MP1_HWIP, 692 UVD_HWIP, 693 VCN_HWIP = UVD_HWIP, 694 VCE_HWIP, 695 DF_HWIP, 696 DCE_HWIP, 697 OSSSYS_HWIP, 698 SMUIO_HWIP, 699 PWR_HWIP, 700 NBIF_HWIP, 701 THM_HWIP, 702 CLK_HWIP, 703 UMC_HWIP, 704 RSMU_HWIP, 705 MAX_HWIP 706 }; 707 708 #define HWIP_MAX_INSTANCE 8 709 710 struct amd_powerplay { 711 void *pp_handle; 712 const struct amd_pm_funcs *pp_funcs; 713 }; 714 715 #define AMDGPU_RESET_MAGIC_NUM 64 716 #define AMDGPU_MAX_DF_PERFMONS 4 717 struct amdgpu_device { 718 struct device *dev; 719 struct drm_device *ddev; 720 struct pci_dev *pdev; 721 722 #ifdef CONFIG_DRM_AMD_ACP 723 struct amdgpu_acp acp; 724 #endif 725 726 /* ASIC */ 727 enum amd_asic_type asic_type; 728 uint32_t family; 729 uint32_t rev_id; 730 uint32_t external_rev_id; 731 unsigned long flags; 732 int usec_timeout; 733 const struct amdgpu_asic_funcs *asic_funcs; 734 bool shutdown; 735 bool need_swiotlb; 736 bool accel_working; 737 struct notifier_block acpi_nb; 738 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 739 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 740 unsigned debugfs_count; 741 #if defined(CONFIG_DEBUG_FS) 742 struct dentry *debugfs_preempt; 743 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 744 #endif 745 struct amdgpu_atif *atif; 746 struct amdgpu_atcs atcs; 747 struct mutex srbm_mutex; 748 /* GRBM index mutex. Protects concurrent access to GRBM index */ 749 struct mutex grbm_idx_mutex; 750 struct dev_pm_domain vga_pm_domain; 751 bool have_disp_power_ref; 752 bool have_atomics_support; 753 754 /* BIOS */ 755 bool is_atom_fw; 756 uint8_t *bios; 757 uint32_t bios_size; 758 struct amdgpu_bo *stolen_vga_memory; 759 uint32_t bios_scratch_reg_offset; 760 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 761 762 /* Register/doorbell mmio */ 763 resource_size_t rmmio_base; 764 resource_size_t rmmio_size; 765 void __iomem *rmmio; 766 /* protects concurrent MM_INDEX/DATA based register access */ 767 spinlock_t mmio_idx_lock; 768 struct amdgpu_mmio_remap rmmio_remap; 769 /* protects concurrent SMC based register access */ 770 spinlock_t smc_idx_lock; 771 amdgpu_rreg_t smc_rreg; 772 amdgpu_wreg_t smc_wreg; 773 /* protects concurrent PCIE register access */ 774 spinlock_t pcie_idx_lock; 775 amdgpu_rreg_t pcie_rreg; 776 amdgpu_wreg_t pcie_wreg; 777 amdgpu_rreg_t pciep_rreg; 778 amdgpu_wreg_t pciep_wreg; 779 amdgpu_rreg64_t pcie_rreg64; 780 amdgpu_wreg64_t pcie_wreg64; 781 /* protects concurrent UVD register access */ 782 spinlock_t uvd_ctx_idx_lock; 783 amdgpu_rreg_t uvd_ctx_rreg; 784 amdgpu_wreg_t uvd_ctx_wreg; 785 /* protects concurrent DIDT register access */ 786 spinlock_t didt_idx_lock; 787 amdgpu_rreg_t didt_rreg; 788 amdgpu_wreg_t didt_wreg; 789 /* protects concurrent gc_cac register access */ 790 spinlock_t gc_cac_idx_lock; 791 amdgpu_rreg_t gc_cac_rreg; 792 amdgpu_wreg_t gc_cac_wreg; 793 /* protects concurrent se_cac register access */ 794 spinlock_t se_cac_idx_lock; 795 amdgpu_rreg_t se_cac_rreg; 796 amdgpu_wreg_t se_cac_wreg; 797 /* protects concurrent ENDPOINT (audio) register access */ 798 spinlock_t audio_endpt_idx_lock; 799 amdgpu_block_rreg_t audio_endpt_rreg; 800 amdgpu_block_wreg_t audio_endpt_wreg; 801 void __iomem *rio_mem; 802 resource_size_t rio_mem_size; 803 struct amdgpu_doorbell doorbell; 804 805 /* clock/pll info */ 806 struct amdgpu_clock clock; 807 808 /* MC */ 809 struct amdgpu_gmc gmc; 810 struct amdgpu_gart gart; 811 dma_addr_t dummy_page_addr; 812 struct amdgpu_vm_manager vm_manager; 813 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 814 unsigned num_vmhubs; 815 816 /* memory management */ 817 struct amdgpu_mman mman; 818 struct amdgpu_vram_scratch vram_scratch; 819 struct amdgpu_wb wb; 820 atomic64_t num_bytes_moved; 821 atomic64_t num_evictions; 822 atomic64_t num_vram_cpu_page_faults; 823 atomic_t gpu_reset_counter; 824 atomic_t vram_lost_counter; 825 826 /* data for buffer migration throttling */ 827 struct { 828 spinlock_t lock; 829 s64 last_update_us; 830 s64 accum_us; /* accumulated microseconds */ 831 s64 accum_us_vis; /* for visible VRAM */ 832 u32 log2_max_MBps; 833 } mm_stats; 834 835 /* display */ 836 bool enable_virtual_display; 837 struct amdgpu_mode_info mode_info; 838 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 839 struct work_struct hotplug_work; 840 struct amdgpu_irq_src crtc_irq; 841 struct amdgpu_irq_src vupdate_irq; 842 struct amdgpu_irq_src pageflip_irq; 843 struct amdgpu_irq_src hpd_irq; 844 845 /* rings */ 846 u64 fence_context; 847 unsigned num_rings; 848 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 849 bool ib_pool_ready; 850 struct amdgpu_sa_manager ring_tmp_bo; 851 852 /* interrupts */ 853 struct amdgpu_irq irq; 854 855 /* powerplay */ 856 struct amd_powerplay powerplay; 857 bool pp_force_state_enabled; 858 859 /* smu */ 860 struct smu_context smu; 861 862 /* dpm */ 863 struct amdgpu_pm pm; 864 u32 cg_flags; 865 u32 pg_flags; 866 867 /* nbio */ 868 struct amdgpu_nbio nbio; 869 870 /* gfx */ 871 struct amdgpu_gfx gfx; 872 873 /* sdma */ 874 struct amdgpu_sdma sdma; 875 876 /* uvd */ 877 struct amdgpu_uvd uvd; 878 879 /* vce */ 880 struct amdgpu_vce vce; 881 882 /* vcn */ 883 struct amdgpu_vcn vcn; 884 885 /* firmwares */ 886 struct amdgpu_firmware firmware; 887 888 /* PSP */ 889 struct psp_context psp; 890 891 /* GDS */ 892 struct amdgpu_gds gds; 893 894 /* KFD */ 895 struct amdgpu_kfd_dev kfd; 896 897 /* UMC */ 898 struct amdgpu_umc umc; 899 900 /* display related functionality */ 901 struct amdgpu_display_manager dm; 902 903 /* discovery */ 904 uint8_t *discovery; 905 906 /* mes */ 907 bool enable_mes; 908 struct amdgpu_mes mes; 909 910 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 911 int num_ip_blocks; 912 struct mutex mn_lock; 913 DECLARE_HASHTABLE(mn_hash, 7); 914 915 /* tracking pinned memory */ 916 atomic64_t vram_pin_size; 917 atomic64_t visible_pin_size; 918 atomic64_t gart_pin_size; 919 920 /* soc15 register offset based on ip, instance and segment */ 921 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 922 923 const struct amdgpu_df_funcs *df_funcs; 924 const struct amdgpu_mmhub_funcs *mmhub_funcs; 925 926 /* delayed work_func for deferring clockgating during resume */ 927 struct delayed_work delayed_init_work; 928 929 struct amdgpu_virt virt; 930 /* firmware VRAM reservation */ 931 struct amdgpu_fw_vram_usage fw_vram_usage; 932 933 /* link all shadow bo */ 934 struct list_head shadow_list; 935 struct mutex shadow_list_lock; 936 /* keep an lru list of rings by HW IP */ 937 struct list_head ring_lru_list; 938 spinlock_t ring_lru_list_lock; 939 940 /* record hw reset is performed */ 941 bool has_hw_reset; 942 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 943 944 /* s3/s4 mask */ 945 bool in_suspend; 946 947 /* record last mm index being written through WREG32*/ 948 unsigned long last_mm_index; 949 bool in_gpu_reset; 950 enum pp_mp1_state mp1_state; 951 struct mutex lock_reset; 952 struct amdgpu_doorbell_index doorbell_index; 953 954 int asic_reset_res; 955 struct work_struct xgmi_reset_work; 956 957 bool in_baco_reset; 958 959 long gfx_timeout; 960 long sdma_timeout; 961 long video_timeout; 962 long compute_timeout; 963 964 uint64_t unique_id; 965 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 966 }; 967 968 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 969 { 970 return container_of(bdev, struct amdgpu_device, mman.bdev); 971 } 972 973 int amdgpu_device_init(struct amdgpu_device *adev, 974 struct drm_device *ddev, 975 struct pci_dev *pdev, 976 uint32_t flags); 977 void amdgpu_device_fini(struct amdgpu_device *adev); 978 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 979 980 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 981 uint32_t acc_flags); 982 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 983 uint32_t acc_flags); 984 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 985 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 986 987 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 988 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 989 990 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 991 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 992 993 int emu_soc_asic_init(struct amdgpu_device *adev); 994 995 /* 996 * Registers read & write functions. 997 */ 998 999 #define AMDGPU_REGS_IDX (1<<0) 1000 #define AMDGPU_REGS_NO_KIQ (1<<1) 1001 1002 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1003 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1004 1005 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1006 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1007 1008 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1009 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1010 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1011 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1012 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1013 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1014 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1015 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1016 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1017 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1018 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1019 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1020 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1021 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1022 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1023 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1024 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1025 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1026 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1027 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1028 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1029 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1030 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1031 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1032 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1033 #define WREG32_P(reg, val, mask) \ 1034 do { \ 1035 uint32_t tmp_ = RREG32(reg); \ 1036 tmp_ &= (mask); \ 1037 tmp_ |= ((val) & ~(mask)); \ 1038 WREG32(reg, tmp_); \ 1039 } while (0) 1040 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1041 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1042 #define WREG32_PLL_P(reg, val, mask) \ 1043 do { \ 1044 uint32_t tmp_ = RREG32_PLL(reg); \ 1045 tmp_ &= (mask); \ 1046 tmp_ |= ((val) & ~(mask)); \ 1047 WREG32_PLL(reg, tmp_); \ 1048 } while (0) 1049 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1050 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1051 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1052 1053 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1054 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1055 1056 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1057 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1058 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1059 1060 #define REG_GET_FIELD(value, reg, field) \ 1061 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1062 1063 #define WREG32_FIELD(reg, field, val) \ 1064 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1065 1066 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1067 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1068 1069 /* 1070 * BIOS helpers. 1071 */ 1072 #define RBIOS8(i) (adev->bios[i]) 1073 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1074 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1075 1076 /* 1077 * ASICs macro. 1078 */ 1079 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1080 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1081 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1082 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1083 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1084 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1085 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1086 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1087 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1088 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1089 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1090 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1091 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1092 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1093 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1094 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1095 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1096 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1097 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1098 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1099 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1100 1101 /* Common functions */ 1102 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1103 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1104 struct amdgpu_job* job); 1105 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1106 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1107 1108 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1109 u64 num_vis_bytes); 1110 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1111 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1112 const u32 *registers, 1113 const u32 array_size); 1114 1115 bool amdgpu_device_is_px(struct drm_device *dev); 1116 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1117 struct amdgpu_device *peer_adev); 1118 1119 /* atpx handler */ 1120 #if defined(CONFIG_VGA_SWITCHEROO) 1121 void amdgpu_register_atpx_handler(void); 1122 void amdgpu_unregister_atpx_handler(void); 1123 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1124 bool amdgpu_is_atpx_hybrid(void); 1125 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1126 bool amdgpu_has_atpx(void); 1127 #else 1128 static inline void amdgpu_register_atpx_handler(void) {} 1129 static inline void amdgpu_unregister_atpx_handler(void) {} 1130 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1131 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1132 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1133 static inline bool amdgpu_has_atpx(void) { return false; } 1134 #endif 1135 1136 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1137 void *amdgpu_atpx_get_dhandle(void); 1138 #else 1139 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1140 #endif 1141 1142 /* 1143 * KMS 1144 */ 1145 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1146 extern const int amdgpu_max_kms_ioctl; 1147 1148 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1149 void amdgpu_driver_unload_kms(struct drm_device *dev); 1150 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1151 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1152 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1153 struct drm_file *file_priv); 1154 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1155 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1156 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1157 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1158 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1159 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1160 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1161 unsigned long arg); 1162 1163 /* 1164 * functions used by amdgpu_encoder.c 1165 */ 1166 struct amdgpu_afmt_acr { 1167 u32 clock; 1168 1169 int n_32khz; 1170 int cts_32khz; 1171 1172 int n_44_1khz; 1173 int cts_44_1khz; 1174 1175 int n_48khz; 1176 int cts_48khz; 1177 1178 }; 1179 1180 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1181 1182 /* amdgpu_acpi.c */ 1183 #if defined(CONFIG_ACPI) 1184 int amdgpu_acpi_init(struct amdgpu_device *adev); 1185 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1186 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1187 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1188 u8 perf_req, bool advertise); 1189 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1190 1191 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1192 struct amdgpu_dm_backlight_caps *caps); 1193 #else 1194 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1195 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1196 #endif 1197 1198 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1199 uint64_t addr, struct amdgpu_bo **bo, 1200 struct amdgpu_bo_va_mapping **mapping); 1201 1202 #if defined(CONFIG_DRM_AMD_DC) 1203 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1204 #else 1205 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1206 #endif 1207 1208 1209 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1210 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1211 1212 #include "amdgpu_object.h" 1213 1214 /* used by df_v3_6.c and amdgpu_pmu.c */ 1215 #define AMDGPU_PMU_ATTR(_name, _object) \ 1216 static ssize_t \ 1217 _name##_show(struct device *dev, \ 1218 struct device_attribute *attr, \ 1219 char *page) \ 1220 { \ 1221 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1222 return sprintf(page, _object "\n"); \ 1223 } \ 1224 \ 1225 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1226 1227 #endif 1228 1229