1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_module.h> 59 #include <drm/ttm/ttm_execbuf_util.h> 60 61 #include <drm/amdgpu_drm.h> 62 #include <drm/drm_gem.h> 63 #include <drm/drm_ioctl.h> 64 #include <drm/gpu_scheduler.h> 65 66 #include <kgd_kfd_interface.h> 67 #include "dm_pp_interface.h" 68 #include "kgd_pp_interface.h" 69 70 #include "amd_shared.h" 71 #include "amdgpu_mode.h" 72 #include "amdgpu_ih.h" 73 #include "amdgpu_irq.h" 74 #include "amdgpu_ucode.h" 75 #include "amdgpu_ttm.h" 76 #include "amdgpu_psp.h" 77 #include "amdgpu_gds.h" 78 #include "amdgpu_sync.h" 79 #include "amdgpu_ring.h" 80 #include "amdgpu_vm.h" 81 #include "amdgpu_dpm.h" 82 #include "amdgpu_acp.h" 83 #include "amdgpu_uvd.h" 84 #include "amdgpu_vce.h" 85 #include "amdgpu_vcn.h" 86 #include "amdgpu_jpeg.h" 87 #include "amdgpu_mn.h" 88 #include "amdgpu_gmc.h" 89 #include "amdgpu_gfx.h" 90 #include "amdgpu_sdma.h" 91 #include "amdgpu_nbio.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_smu.h" 103 #include "amdgpu_discovery.h" 104 #include "amdgpu_mes.h" 105 #include "amdgpu_umc.h" 106 #include "amdgpu_mmhub.h" 107 #include "amdgpu_gfxhub.h" 108 #include "amdgpu_df.h" 109 110 #define MAX_GPU_INSTANCE 16 111 112 struct amdgpu_gpu_instance 113 { 114 struct amdgpu_device *adev; 115 int mgpu_fan_enabled; 116 }; 117 118 struct amdgpu_mgpu_info 119 { 120 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 121 struct mutex mutex; 122 uint32_t num_gpu; 123 uint32_t num_dgpu; 124 uint32_t num_apu; 125 }; 126 127 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 128 129 /* 130 * Modules parameters. 131 */ 132 extern int amdgpu_modeset; 133 extern int amdgpu_vram_limit; 134 extern int amdgpu_vis_vram_limit; 135 extern int amdgpu_gart_size; 136 extern int amdgpu_gtt_size; 137 extern int amdgpu_moverate; 138 extern int amdgpu_benchmarking; 139 extern int amdgpu_testing; 140 extern int amdgpu_audio; 141 extern int amdgpu_disp_priority; 142 extern int amdgpu_hw_i2c; 143 extern int amdgpu_pcie_gen2; 144 extern int amdgpu_msi; 145 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 146 extern int amdgpu_dpm; 147 extern int amdgpu_fw_load_type; 148 extern int amdgpu_aspm; 149 extern int amdgpu_runtime_pm; 150 extern uint amdgpu_ip_block_mask; 151 extern int amdgpu_bapm; 152 extern int amdgpu_deep_color; 153 extern int amdgpu_vm_size; 154 extern int amdgpu_vm_block_size; 155 extern int amdgpu_vm_fragment_size; 156 extern int amdgpu_vm_fault_stop; 157 extern int amdgpu_vm_debug; 158 extern int amdgpu_vm_update_mode; 159 extern int amdgpu_exp_hw_support; 160 extern int amdgpu_dc; 161 extern int amdgpu_sched_jobs; 162 extern int amdgpu_sched_hw_submission; 163 extern uint amdgpu_pcie_gen_cap; 164 extern uint amdgpu_pcie_lane_cap; 165 extern uint amdgpu_cg_mask; 166 extern uint amdgpu_pg_mask; 167 extern uint amdgpu_sdma_phase_quantum; 168 extern char *amdgpu_disable_cu; 169 extern char *amdgpu_virtual_display; 170 extern uint amdgpu_pp_feature_mask; 171 extern uint amdgpu_force_long_training; 172 extern int amdgpu_job_hang_limit; 173 extern int amdgpu_lbpw; 174 extern int amdgpu_compute_multipipe; 175 extern int amdgpu_gpu_recovery; 176 extern int amdgpu_emu_mode; 177 extern uint amdgpu_smu_memory_pool_size; 178 extern uint amdgpu_dc_feature_mask; 179 extern uint amdgpu_dc_debug_mask; 180 extern uint amdgpu_dm_abm_level; 181 extern struct amdgpu_mgpu_info mgpu_info; 182 extern int amdgpu_ras_enable; 183 extern uint amdgpu_ras_mask; 184 extern int amdgpu_bad_page_threshold; 185 extern int amdgpu_async_gfx_ring; 186 extern int amdgpu_mcbp; 187 extern int amdgpu_discovery; 188 extern int amdgpu_mes; 189 extern int amdgpu_noretry; 190 extern int amdgpu_force_asic_type; 191 #ifdef CONFIG_HSA_AMD 192 extern int sched_policy; 193 extern bool debug_evictions; 194 extern bool no_system_mem_limit; 195 #else 196 static const int sched_policy = KFD_SCHED_POLICY_HWS; 197 static const bool debug_evictions; /* = false */ 198 static const bool no_system_mem_limit; 199 #endif 200 201 extern int amdgpu_tmz; 202 extern int amdgpu_reset_method; 203 204 #ifdef CONFIG_DRM_AMDGPU_SI 205 extern int amdgpu_si_support; 206 #endif 207 #ifdef CONFIG_DRM_AMDGPU_CIK 208 extern int amdgpu_cik_support; 209 #endif 210 extern int amdgpu_num_kcq; 211 212 #define AMDGPU_VM_MAX_NUM_CTX 4096 213 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 214 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 215 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 216 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 217 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 218 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 219 #define AMDGPUFB_CONN_LIMIT 4 220 #define AMDGPU_BIOS_NUM_SCRATCH 16 221 222 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 223 224 /* hard reset data */ 225 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 226 227 /* reset flags */ 228 #define AMDGPU_RESET_GFX (1 << 0) 229 #define AMDGPU_RESET_COMPUTE (1 << 1) 230 #define AMDGPU_RESET_DMA (1 << 2) 231 #define AMDGPU_RESET_CP (1 << 3) 232 #define AMDGPU_RESET_GRBM (1 << 4) 233 #define AMDGPU_RESET_DMA1 (1 << 5) 234 #define AMDGPU_RESET_RLC (1 << 6) 235 #define AMDGPU_RESET_SEM (1 << 7) 236 #define AMDGPU_RESET_IH (1 << 8) 237 #define AMDGPU_RESET_VMC (1 << 9) 238 #define AMDGPU_RESET_MC (1 << 10) 239 #define AMDGPU_RESET_DISPLAY (1 << 11) 240 #define AMDGPU_RESET_UVD (1 << 12) 241 #define AMDGPU_RESET_VCE (1 << 13) 242 #define AMDGPU_RESET_VCE1 (1 << 14) 243 244 /* max cursor sizes (in pixels) */ 245 #define CIK_CURSOR_WIDTH 128 246 #define CIK_CURSOR_HEIGHT 128 247 248 struct amdgpu_device; 249 struct amdgpu_ib; 250 struct amdgpu_cs_parser; 251 struct amdgpu_job; 252 struct amdgpu_irq_src; 253 struct amdgpu_fpriv; 254 struct amdgpu_bo_va_mapping; 255 struct amdgpu_atif; 256 struct kfd_vm_fault_info; 257 struct amdgpu_hive_info; 258 259 enum amdgpu_cp_irq { 260 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 261 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 262 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 263 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 264 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 265 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 266 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 267 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 268 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 269 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 270 271 AMDGPU_CP_IRQ_LAST 272 }; 273 274 enum amdgpu_thermal_irq { 275 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 276 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 277 278 AMDGPU_THERMAL_IRQ_LAST 279 }; 280 281 enum amdgpu_kiq_irq { 282 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 283 AMDGPU_CP_KIQ_IRQ_LAST 284 }; 285 286 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 287 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 288 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 289 290 int amdgpu_device_ip_set_clockgating_state(void *dev, 291 enum amd_ip_block_type block_type, 292 enum amd_clockgating_state state); 293 int amdgpu_device_ip_set_powergating_state(void *dev, 294 enum amd_ip_block_type block_type, 295 enum amd_powergating_state state); 296 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 297 u32 *flags); 298 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 299 enum amd_ip_block_type block_type); 300 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 301 enum amd_ip_block_type block_type); 302 303 #define AMDGPU_MAX_IP_NUM 16 304 305 struct amdgpu_ip_block_status { 306 bool valid; 307 bool sw; 308 bool hw; 309 bool late_initialized; 310 bool hang; 311 }; 312 313 struct amdgpu_ip_block_version { 314 const enum amd_ip_block_type type; 315 const u32 major; 316 const u32 minor; 317 const u32 rev; 318 const struct amd_ip_funcs *funcs; 319 }; 320 321 #define HW_REV(_Major, _Minor, _Rev) \ 322 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 323 324 struct amdgpu_ip_block { 325 struct amdgpu_ip_block_status status; 326 const struct amdgpu_ip_block_version *version; 327 }; 328 329 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 330 enum amd_ip_block_type type, 331 u32 major, u32 minor); 332 333 struct amdgpu_ip_block * 334 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 335 enum amd_ip_block_type type); 336 337 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 338 const struct amdgpu_ip_block_version *ip_block_version); 339 340 /* 341 * BIOS. 342 */ 343 bool amdgpu_get_bios(struct amdgpu_device *adev); 344 bool amdgpu_read_bios(struct amdgpu_device *adev); 345 346 /* 347 * Clocks 348 */ 349 350 #define AMDGPU_MAX_PPLL 3 351 352 struct amdgpu_clock { 353 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 354 struct amdgpu_pll spll; 355 struct amdgpu_pll mpll; 356 /* 10 Khz units */ 357 uint32_t default_mclk; 358 uint32_t default_sclk; 359 uint32_t default_dispclk; 360 uint32_t current_dispclk; 361 uint32_t dp_extclk; 362 uint32_t max_pixel_clock; 363 }; 364 365 /* sub-allocation manager, it has to be protected by another lock. 366 * By conception this is an helper for other part of the driver 367 * like the indirect buffer or semaphore, which both have their 368 * locking. 369 * 370 * Principe is simple, we keep a list of sub allocation in offset 371 * order (first entry has offset == 0, last entry has the highest 372 * offset). 373 * 374 * When allocating new object we first check if there is room at 375 * the end total_size - (last_object_offset + last_object_size) >= 376 * alloc_size. If so we allocate new object there. 377 * 378 * When there is not enough room at the end, we start waiting for 379 * each sub object until we reach object_offset+object_size >= 380 * alloc_size, this object then become the sub object we return. 381 * 382 * Alignment can't be bigger than page size. 383 * 384 * Hole are not considered for allocation to keep things simple. 385 * Assumption is that there won't be hole (all object on same 386 * alignment). 387 */ 388 389 #define AMDGPU_SA_NUM_FENCE_LISTS 32 390 391 struct amdgpu_sa_manager { 392 wait_queue_head_t wq; 393 struct amdgpu_bo *bo; 394 struct list_head *hole; 395 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 396 struct list_head olist; 397 unsigned size; 398 uint64_t gpu_addr; 399 void *cpu_ptr; 400 uint32_t domain; 401 uint32_t align; 402 }; 403 404 /* sub-allocation buffer */ 405 struct amdgpu_sa_bo { 406 struct list_head olist; 407 struct list_head flist; 408 struct amdgpu_sa_manager *manager; 409 unsigned soffset; 410 unsigned eoffset; 411 struct dma_fence *fence; 412 }; 413 414 int amdgpu_fence_slab_init(void); 415 void amdgpu_fence_slab_fini(void); 416 417 /* 418 * IRQS. 419 */ 420 421 struct amdgpu_flip_work { 422 struct delayed_work flip_work; 423 struct work_struct unpin_work; 424 struct amdgpu_device *adev; 425 int crtc_id; 426 u32 target_vblank; 427 uint64_t base; 428 struct drm_pending_vblank_event *event; 429 struct amdgpu_bo *old_abo; 430 struct dma_fence *excl; 431 unsigned shared_count; 432 struct dma_fence **shared; 433 struct dma_fence_cb cb; 434 bool async; 435 }; 436 437 438 /* 439 * CP & rings. 440 */ 441 442 struct amdgpu_ib { 443 struct amdgpu_sa_bo *sa_bo; 444 uint32_t length_dw; 445 uint64_t gpu_addr; 446 uint32_t *ptr; 447 uint32_t flags; 448 }; 449 450 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 451 452 /* 453 * file private structure 454 */ 455 456 struct amdgpu_fpriv { 457 struct amdgpu_vm vm; 458 struct amdgpu_bo_va *prt_va; 459 struct amdgpu_bo_va *csa_va; 460 struct mutex bo_list_lock; 461 struct idr bo_list_handles; 462 struct amdgpu_ctx_mgr ctx_mgr; 463 }; 464 465 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 466 467 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 468 unsigned size, 469 enum amdgpu_ib_pool_type pool, 470 struct amdgpu_ib *ib); 471 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 472 struct dma_fence *f); 473 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 474 struct amdgpu_ib *ibs, struct amdgpu_job *job, 475 struct dma_fence **f); 476 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 477 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 478 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 479 480 /* 481 * CS. 482 */ 483 struct amdgpu_cs_chunk { 484 uint32_t chunk_id; 485 uint32_t length_dw; 486 void *kdata; 487 }; 488 489 struct amdgpu_cs_post_dep { 490 struct drm_syncobj *syncobj; 491 struct dma_fence_chain *chain; 492 u64 point; 493 }; 494 495 struct amdgpu_cs_parser { 496 struct amdgpu_device *adev; 497 struct drm_file *filp; 498 struct amdgpu_ctx *ctx; 499 500 /* chunks */ 501 unsigned nchunks; 502 struct amdgpu_cs_chunk *chunks; 503 504 /* scheduler job object */ 505 struct amdgpu_job *job; 506 struct drm_sched_entity *entity; 507 508 /* buffer objects */ 509 struct ww_acquire_ctx ticket; 510 struct amdgpu_bo_list *bo_list; 511 struct amdgpu_mn *mn; 512 struct amdgpu_bo_list_entry vm_pd; 513 struct list_head validated; 514 struct dma_fence *fence; 515 uint64_t bytes_moved_threshold; 516 uint64_t bytes_moved_vis_threshold; 517 uint64_t bytes_moved; 518 uint64_t bytes_moved_vis; 519 520 /* user fence */ 521 struct amdgpu_bo_list_entry uf_entry; 522 523 unsigned num_post_deps; 524 struct amdgpu_cs_post_dep *post_deps; 525 }; 526 527 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 528 uint32_t ib_idx, int idx) 529 { 530 return p->job->ibs[ib_idx].ptr[idx]; 531 } 532 533 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 534 uint32_t ib_idx, int idx, 535 uint32_t value) 536 { 537 p->job->ibs[ib_idx].ptr[idx] = value; 538 } 539 540 /* 541 * Writeback 542 */ 543 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 544 545 struct amdgpu_wb { 546 struct amdgpu_bo *wb_obj; 547 volatile uint32_t *wb; 548 uint64_t gpu_addr; 549 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 550 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 551 }; 552 553 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 554 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 555 556 /* 557 * Benchmarking 558 */ 559 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 560 561 562 /* 563 * Testing 564 */ 565 void amdgpu_test_moves(struct amdgpu_device *adev); 566 567 /* 568 * ASIC specific register table accessible by UMD 569 */ 570 struct amdgpu_allowed_register_entry { 571 uint32_t reg_offset; 572 bool grbm_indexed; 573 }; 574 575 enum amd_reset_method { 576 AMD_RESET_METHOD_LEGACY = 0, 577 AMD_RESET_METHOD_MODE0, 578 AMD_RESET_METHOD_MODE1, 579 AMD_RESET_METHOD_MODE2, 580 AMD_RESET_METHOD_BACO 581 }; 582 583 /* 584 * ASIC specific functions. 585 */ 586 struct amdgpu_asic_funcs { 587 bool (*read_disabled_bios)(struct amdgpu_device *adev); 588 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 589 u8 *bios, u32 length_bytes); 590 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 591 u32 sh_num, u32 reg_offset, u32 *value); 592 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 593 int (*reset)(struct amdgpu_device *adev); 594 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 595 /* get the reference clock */ 596 u32 (*get_xclk)(struct amdgpu_device *adev); 597 /* MM block clocks */ 598 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 599 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 600 /* static power management */ 601 int (*get_pcie_lanes)(struct amdgpu_device *adev); 602 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 603 /* get config memsize register */ 604 u32 (*get_config_memsize)(struct amdgpu_device *adev); 605 /* flush hdp write queue */ 606 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 607 /* invalidate hdp read cache */ 608 void (*invalidate_hdp)(struct amdgpu_device *adev, 609 struct amdgpu_ring *ring); 610 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev); 611 /* check if the asic needs a full reset of if soft reset will work */ 612 bool (*need_full_reset)(struct amdgpu_device *adev); 613 /* initialize doorbell layout for specific asic*/ 614 void (*init_doorbell_index)(struct amdgpu_device *adev); 615 /* PCIe bandwidth usage */ 616 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 617 uint64_t *count1); 618 /* do we need to reset the asic at init time (e.g., kexec) */ 619 bool (*need_reset_on_init)(struct amdgpu_device *adev); 620 /* PCIe replay counter */ 621 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 622 /* device supports BACO */ 623 bool (*supports_baco)(struct amdgpu_device *adev); 624 /* pre asic_init quirks */ 625 void (*pre_asic_init)(struct amdgpu_device *adev); 626 }; 627 628 /* 629 * IOCTL. 630 */ 631 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 632 struct drm_file *filp); 633 634 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 635 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 636 struct drm_file *filp); 637 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 638 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 639 struct drm_file *filp); 640 641 /* VRAM scratch page for HDP bug, default vram page */ 642 struct amdgpu_vram_scratch { 643 struct amdgpu_bo *robj; 644 volatile uint32_t *ptr; 645 u64 gpu_addr; 646 }; 647 648 /* 649 * ACPI 650 */ 651 struct amdgpu_atcs_functions { 652 bool get_ext_state; 653 bool pcie_perf_req; 654 bool pcie_dev_rdy; 655 bool pcie_bus_width; 656 }; 657 658 struct amdgpu_atcs { 659 struct amdgpu_atcs_functions functions; 660 }; 661 662 /* 663 * CGS 664 */ 665 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 666 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 667 668 /* 669 * Core structure, functions and helpers. 670 */ 671 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 672 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 673 674 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 675 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 676 677 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 678 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 679 680 struct amdgpu_mmio_remap { 681 u32 reg_offset; 682 resource_size_t bus_addr; 683 }; 684 685 /* Define the HW IP blocks will be used in driver , add more if necessary */ 686 enum amd_hw_ip_block_type { 687 GC_HWIP = 1, 688 HDP_HWIP, 689 SDMA0_HWIP, 690 SDMA1_HWIP, 691 SDMA2_HWIP, 692 SDMA3_HWIP, 693 SDMA4_HWIP, 694 SDMA5_HWIP, 695 SDMA6_HWIP, 696 SDMA7_HWIP, 697 MMHUB_HWIP, 698 ATHUB_HWIP, 699 NBIO_HWIP, 700 MP0_HWIP, 701 MP1_HWIP, 702 UVD_HWIP, 703 VCN_HWIP = UVD_HWIP, 704 JPEG_HWIP = VCN_HWIP, 705 VCE_HWIP, 706 DF_HWIP, 707 DCE_HWIP, 708 OSSSYS_HWIP, 709 SMUIO_HWIP, 710 PWR_HWIP, 711 NBIF_HWIP, 712 THM_HWIP, 713 CLK_HWIP, 714 UMC_HWIP, 715 RSMU_HWIP, 716 MAX_HWIP 717 }; 718 719 #define HWIP_MAX_INSTANCE 8 720 721 struct amd_powerplay { 722 void *pp_handle; 723 const struct amd_pm_funcs *pp_funcs; 724 }; 725 726 #define AMDGPU_RESET_MAGIC_NUM 64 727 #define AMDGPU_MAX_DF_PERFMONS 4 728 struct amdgpu_device { 729 struct device *dev; 730 struct pci_dev *pdev; 731 struct drm_device ddev; 732 733 #ifdef CONFIG_DRM_AMD_ACP 734 struct amdgpu_acp acp; 735 #endif 736 struct amdgpu_hive_info *hive; 737 /* ASIC */ 738 enum amd_asic_type asic_type; 739 uint32_t family; 740 uint32_t rev_id; 741 uint32_t external_rev_id; 742 unsigned long flags; 743 unsigned long apu_flags; 744 int usec_timeout; 745 const struct amdgpu_asic_funcs *asic_funcs; 746 bool shutdown; 747 bool need_swiotlb; 748 bool accel_working; 749 struct notifier_block acpi_nb; 750 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 751 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 752 unsigned debugfs_count; 753 #if defined(CONFIG_DEBUG_FS) 754 struct dentry *debugfs_preempt; 755 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 756 #endif 757 struct amdgpu_atif *atif; 758 struct amdgpu_atcs atcs; 759 struct mutex srbm_mutex; 760 /* GRBM index mutex. Protects concurrent access to GRBM index */ 761 struct mutex grbm_idx_mutex; 762 struct dev_pm_domain vga_pm_domain; 763 bool have_disp_power_ref; 764 bool have_atomics_support; 765 766 /* BIOS */ 767 bool is_atom_fw; 768 uint8_t *bios; 769 uint32_t bios_size; 770 uint32_t bios_scratch_reg_offset; 771 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 772 773 /* Register/doorbell mmio */ 774 resource_size_t rmmio_base; 775 resource_size_t rmmio_size; 776 void __iomem *rmmio; 777 /* protects concurrent MM_INDEX/DATA based register access */ 778 spinlock_t mmio_idx_lock; 779 struct amdgpu_mmio_remap rmmio_remap; 780 /* protects concurrent SMC based register access */ 781 spinlock_t smc_idx_lock; 782 amdgpu_rreg_t smc_rreg; 783 amdgpu_wreg_t smc_wreg; 784 /* protects concurrent PCIE register access */ 785 spinlock_t pcie_idx_lock; 786 amdgpu_rreg_t pcie_rreg; 787 amdgpu_wreg_t pcie_wreg; 788 amdgpu_rreg_t pciep_rreg; 789 amdgpu_wreg_t pciep_wreg; 790 amdgpu_rreg64_t pcie_rreg64; 791 amdgpu_wreg64_t pcie_wreg64; 792 /* protects concurrent UVD register access */ 793 spinlock_t uvd_ctx_idx_lock; 794 amdgpu_rreg_t uvd_ctx_rreg; 795 amdgpu_wreg_t uvd_ctx_wreg; 796 /* protects concurrent DIDT register access */ 797 spinlock_t didt_idx_lock; 798 amdgpu_rreg_t didt_rreg; 799 amdgpu_wreg_t didt_wreg; 800 /* protects concurrent gc_cac register access */ 801 spinlock_t gc_cac_idx_lock; 802 amdgpu_rreg_t gc_cac_rreg; 803 amdgpu_wreg_t gc_cac_wreg; 804 /* protects concurrent se_cac register access */ 805 spinlock_t se_cac_idx_lock; 806 amdgpu_rreg_t se_cac_rreg; 807 amdgpu_wreg_t se_cac_wreg; 808 /* protects concurrent ENDPOINT (audio) register access */ 809 spinlock_t audio_endpt_idx_lock; 810 amdgpu_block_rreg_t audio_endpt_rreg; 811 amdgpu_block_wreg_t audio_endpt_wreg; 812 void __iomem *rio_mem; 813 resource_size_t rio_mem_size; 814 struct amdgpu_doorbell doorbell; 815 816 /* clock/pll info */ 817 struct amdgpu_clock clock; 818 819 /* MC */ 820 struct amdgpu_gmc gmc; 821 struct amdgpu_gart gart; 822 dma_addr_t dummy_page_addr; 823 struct amdgpu_vm_manager vm_manager; 824 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 825 unsigned num_vmhubs; 826 827 /* memory management */ 828 struct amdgpu_mman mman; 829 struct amdgpu_vram_scratch vram_scratch; 830 struct amdgpu_wb wb; 831 atomic64_t num_bytes_moved; 832 atomic64_t num_evictions; 833 atomic64_t num_vram_cpu_page_faults; 834 atomic_t gpu_reset_counter; 835 atomic_t vram_lost_counter; 836 837 /* data for buffer migration throttling */ 838 struct { 839 spinlock_t lock; 840 s64 last_update_us; 841 s64 accum_us; /* accumulated microseconds */ 842 s64 accum_us_vis; /* for visible VRAM */ 843 u32 log2_max_MBps; 844 } mm_stats; 845 846 /* display */ 847 bool enable_virtual_display; 848 struct amdgpu_mode_info mode_info; 849 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 850 struct work_struct hotplug_work; 851 struct amdgpu_irq_src crtc_irq; 852 struct amdgpu_irq_src vupdate_irq; 853 struct amdgpu_irq_src pageflip_irq; 854 struct amdgpu_irq_src hpd_irq; 855 856 /* rings */ 857 u64 fence_context; 858 unsigned num_rings; 859 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 860 bool ib_pool_ready; 861 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 862 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 863 864 /* interrupts */ 865 struct amdgpu_irq irq; 866 867 /* powerplay */ 868 struct amd_powerplay powerplay; 869 bool pp_force_state_enabled; 870 871 /* smu */ 872 struct smu_context smu; 873 874 /* dpm */ 875 struct amdgpu_pm pm; 876 u32 cg_flags; 877 u32 pg_flags; 878 879 /* nbio */ 880 struct amdgpu_nbio nbio; 881 882 /* mmhub */ 883 struct amdgpu_mmhub mmhub; 884 885 /* gfxhub */ 886 struct amdgpu_gfxhub gfxhub; 887 888 /* gfx */ 889 struct amdgpu_gfx gfx; 890 891 /* sdma */ 892 struct amdgpu_sdma sdma; 893 894 /* uvd */ 895 struct amdgpu_uvd uvd; 896 897 /* vce */ 898 struct amdgpu_vce vce; 899 900 /* vcn */ 901 struct amdgpu_vcn vcn; 902 903 /* jpeg */ 904 struct amdgpu_jpeg jpeg; 905 906 /* firmwares */ 907 struct amdgpu_firmware firmware; 908 909 /* PSP */ 910 struct psp_context psp; 911 912 /* GDS */ 913 struct amdgpu_gds gds; 914 915 /* KFD */ 916 struct amdgpu_kfd_dev kfd; 917 918 /* UMC */ 919 struct amdgpu_umc umc; 920 921 /* display related functionality */ 922 struct amdgpu_display_manager dm; 923 924 /* mes */ 925 bool enable_mes; 926 struct amdgpu_mes mes; 927 928 /* df */ 929 struct amdgpu_df df; 930 931 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 932 int num_ip_blocks; 933 struct mutex mn_lock; 934 DECLARE_HASHTABLE(mn_hash, 7); 935 936 /* tracking pinned memory */ 937 atomic64_t vram_pin_size; 938 atomic64_t visible_pin_size; 939 atomic64_t gart_pin_size; 940 941 /* soc15 register offset based on ip, instance and segment */ 942 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 943 944 /* delayed work_func for deferring clockgating during resume */ 945 struct delayed_work delayed_init_work; 946 947 struct amdgpu_virt virt; 948 949 /* link all shadow bo */ 950 struct list_head shadow_list; 951 struct mutex shadow_list_lock; 952 953 /* record hw reset is performed */ 954 bool has_hw_reset; 955 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 956 957 /* s3/s4 mask */ 958 bool in_suspend; 959 bool in_hibernate; 960 961 atomic_t in_gpu_reset; 962 enum pp_mp1_state mp1_state; 963 struct rw_semaphore reset_sem; 964 struct amdgpu_doorbell_index doorbell_index; 965 966 struct mutex notifier_lock; 967 968 int asic_reset_res; 969 struct work_struct xgmi_reset_work; 970 971 long gfx_timeout; 972 long sdma_timeout; 973 long video_timeout; 974 long compute_timeout; 975 976 uint64_t unique_id; 977 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 978 979 /* enable runtime pm on the device */ 980 bool runpm; 981 bool in_runpm; 982 983 bool pm_sysfs_en; 984 bool ucode_sysfs_en; 985 986 /* Chip product information */ 987 char product_number[16]; 988 char product_name[32]; 989 char serial[20]; 990 991 struct amdgpu_autodump autodump; 992 993 atomic_t throttling_logging_enabled; 994 struct ratelimit_state throttling_logging_rs; 995 uint32_t ras_features; 996 997 bool in_pci_err_recovery; 998 struct pci_saved_state *pci_state; 999 }; 1000 1001 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1002 { 1003 return container_of(ddev, struct amdgpu_device, ddev); 1004 } 1005 1006 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1007 { 1008 return &adev->ddev; 1009 } 1010 1011 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1012 { 1013 return container_of(bdev, struct amdgpu_device, mman.bdev); 1014 } 1015 1016 int amdgpu_device_init(struct amdgpu_device *adev, 1017 uint32_t flags); 1018 void amdgpu_device_fini(struct amdgpu_device *adev); 1019 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1020 1021 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1022 uint32_t *buf, size_t size, bool write); 1023 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1024 uint32_t reg, uint32_t acc_flags); 1025 void amdgpu_device_wreg(struct amdgpu_device *adev, 1026 uint32_t reg, uint32_t v, 1027 uint32_t acc_flags); 1028 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1029 uint32_t reg, uint32_t v); 1030 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1031 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1032 1033 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1034 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1035 1036 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1037 u32 pcie_index, u32 pcie_data, 1038 u32 reg_addr); 1039 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1040 u32 pcie_index, u32 pcie_data, 1041 u32 reg_addr); 1042 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1043 u32 pcie_index, u32 pcie_data, 1044 u32 reg_addr, u32 reg_data); 1045 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1046 u32 pcie_index, u32 pcie_data, 1047 u32 reg_addr, u64 reg_data); 1048 1049 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1050 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1051 1052 int emu_soc_asic_init(struct amdgpu_device *adev); 1053 1054 /* 1055 * Registers read & write functions. 1056 */ 1057 #define AMDGPU_REGS_NO_KIQ (1<<1) 1058 1059 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1060 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1061 1062 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1063 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1064 1065 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1066 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1067 1068 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1069 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1070 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1071 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1072 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1073 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1074 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1075 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1076 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1077 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1078 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1079 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1080 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1081 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1082 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1083 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1084 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1085 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1086 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1087 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1088 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1089 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1090 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1091 #define WREG32_P(reg, val, mask) \ 1092 do { \ 1093 uint32_t tmp_ = RREG32(reg); \ 1094 tmp_ &= (mask); \ 1095 tmp_ |= ((val) & ~(mask)); \ 1096 WREG32(reg, tmp_); \ 1097 } while (0) 1098 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1099 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1100 #define WREG32_PLL_P(reg, val, mask) \ 1101 do { \ 1102 uint32_t tmp_ = RREG32_PLL(reg); \ 1103 tmp_ &= (mask); \ 1104 tmp_ |= ((val) & ~(mask)); \ 1105 WREG32_PLL(reg, tmp_); \ 1106 } while (0) 1107 1108 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1109 do { \ 1110 u32 tmp = RREG32_SMC(_Reg); \ 1111 tmp &= (_Mask); \ 1112 tmp |= ((_Val) & ~(_Mask)); \ 1113 WREG32_SMC(_Reg, tmp); \ 1114 } while (0) 1115 1116 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1117 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1118 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1119 1120 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1121 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1122 1123 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1124 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1125 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1126 1127 #define REG_GET_FIELD(value, reg, field) \ 1128 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1129 1130 #define WREG32_FIELD(reg, field, val) \ 1131 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1132 1133 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1134 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1135 1136 /* 1137 * BIOS helpers. 1138 */ 1139 #define RBIOS8(i) (adev->bios[i]) 1140 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1141 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1142 1143 /* 1144 * ASICs macro. 1145 */ 1146 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1147 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1148 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1149 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1150 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1151 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1152 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1153 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1154 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1155 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1156 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1157 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1158 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1159 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1160 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1161 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1162 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1163 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1164 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1165 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1166 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1167 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1168 1169 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1170 1171 /* Common functions */ 1172 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1173 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1174 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1175 struct amdgpu_job* job); 1176 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1177 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1178 1179 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1180 u64 num_vis_bytes); 1181 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1182 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1183 const u32 *registers, 1184 const u32 array_size); 1185 1186 bool amdgpu_device_supports_boco(struct drm_device *dev); 1187 bool amdgpu_device_supports_baco(struct drm_device *dev); 1188 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1189 struct amdgpu_device *peer_adev); 1190 int amdgpu_device_baco_enter(struct drm_device *dev); 1191 int amdgpu_device_baco_exit(struct drm_device *dev); 1192 1193 /* atpx handler */ 1194 #if defined(CONFIG_VGA_SWITCHEROO) 1195 void amdgpu_register_atpx_handler(void); 1196 void amdgpu_unregister_atpx_handler(void); 1197 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1198 bool amdgpu_is_atpx_hybrid(void); 1199 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1200 bool amdgpu_has_atpx(void); 1201 #else 1202 static inline void amdgpu_register_atpx_handler(void) {} 1203 static inline void amdgpu_unregister_atpx_handler(void) {} 1204 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1205 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1206 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1207 static inline bool amdgpu_has_atpx(void) { return false; } 1208 #endif 1209 1210 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1211 void *amdgpu_atpx_get_dhandle(void); 1212 #else 1213 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1214 #endif 1215 1216 /* 1217 * KMS 1218 */ 1219 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1220 extern const int amdgpu_max_kms_ioctl; 1221 1222 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1223 void amdgpu_driver_unload_kms(struct drm_device *dev); 1224 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1225 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1226 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1227 struct drm_file *file_priv); 1228 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1229 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1230 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1231 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1232 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1233 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1234 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1235 unsigned long arg); 1236 1237 /* 1238 * functions used by amdgpu_encoder.c 1239 */ 1240 struct amdgpu_afmt_acr { 1241 u32 clock; 1242 1243 int n_32khz; 1244 int cts_32khz; 1245 1246 int n_44_1khz; 1247 int cts_44_1khz; 1248 1249 int n_48khz; 1250 int cts_48khz; 1251 1252 }; 1253 1254 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1255 1256 /* amdgpu_acpi.c */ 1257 #if defined(CONFIG_ACPI) 1258 int amdgpu_acpi_init(struct amdgpu_device *adev); 1259 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1260 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1261 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1262 u8 perf_req, bool advertise); 1263 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1264 1265 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1266 struct amdgpu_dm_backlight_caps *caps); 1267 #else 1268 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1269 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1270 #endif 1271 1272 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1273 uint64_t addr, struct amdgpu_bo **bo, 1274 struct amdgpu_bo_va_mapping **mapping); 1275 1276 #if defined(CONFIG_DRM_AMD_DC) 1277 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1278 #else 1279 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1280 #endif 1281 1282 1283 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1284 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1285 1286 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1287 pci_channel_state_t state); 1288 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1289 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1290 void amdgpu_pci_resume(struct pci_dev *pdev); 1291 1292 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1293 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1294 1295 #include "amdgpu_object.h" 1296 1297 /* used by df_v3_6.c and amdgpu_pmu.c */ 1298 #define AMDGPU_PMU_ATTR(_name, _object) \ 1299 static ssize_t \ 1300 _name##_show(struct device *dev, \ 1301 struct device_attribute *attr, \ 1302 char *page) \ 1303 { \ 1304 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1305 return sprintf(page, _object "\n"); \ 1306 } \ 1307 \ 1308 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1309 1310 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1311 { 1312 return adev->gmc.tmz_enabled; 1313 } 1314 1315 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1316 { 1317 return atomic_read(&adev->in_gpu_reset); 1318 } 1319 #endif 1320