1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_gds.h" 55 56 #include "gpu_scheduler.h" 57 58 /* 59 * Modules parameters. 60 */ 61 extern int amdgpu_modeset; 62 extern int amdgpu_vram_limit; 63 extern int amdgpu_gart_size; 64 extern int amdgpu_benchmarking; 65 extern int amdgpu_testing; 66 extern int amdgpu_audio; 67 extern int amdgpu_disp_priority; 68 extern int amdgpu_hw_i2c; 69 extern int amdgpu_pcie_gen2; 70 extern int amdgpu_msi; 71 extern int amdgpu_lockup_timeout; 72 extern int amdgpu_dpm; 73 extern int amdgpu_smc_load_fw; 74 extern int amdgpu_aspm; 75 extern int amdgpu_runtime_pm; 76 extern int amdgpu_hard_reset; 77 extern unsigned amdgpu_ip_block_mask; 78 extern int amdgpu_bapm; 79 extern int amdgpu_deep_color; 80 extern int amdgpu_vm_size; 81 extern int amdgpu_vm_block_size; 82 extern int amdgpu_vm_fault_stop; 83 extern int amdgpu_vm_debug; 84 extern int amdgpu_enable_scheduler; 85 extern int amdgpu_sched_jobs; 86 extern int amdgpu_sched_hw_submission; 87 extern int amdgpu_enable_semaphores; 88 89 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 90 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 91 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 92 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 93 #define AMDGPU_IB_POOL_SIZE 16 94 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 95 #define AMDGPUFB_CONN_LIMIT 4 96 #define AMDGPU_BIOS_NUM_SCRATCH 8 97 98 /* max number of rings */ 99 #define AMDGPU_MAX_RINGS 16 100 #define AMDGPU_MAX_GFX_RINGS 1 101 #define AMDGPU_MAX_COMPUTE_RINGS 8 102 #define AMDGPU_MAX_VCE_RINGS 2 103 104 /* max number of IP instances */ 105 #define AMDGPU_MAX_SDMA_INSTANCES 2 106 107 /* number of hw syncs before falling back on blocking */ 108 #define AMDGPU_NUM_SYNCS 4 109 110 /* hardcode that limit for now */ 111 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 112 113 /* hard reset data */ 114 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 115 116 /* reset flags */ 117 #define AMDGPU_RESET_GFX (1 << 0) 118 #define AMDGPU_RESET_COMPUTE (1 << 1) 119 #define AMDGPU_RESET_DMA (1 << 2) 120 #define AMDGPU_RESET_CP (1 << 3) 121 #define AMDGPU_RESET_GRBM (1 << 4) 122 #define AMDGPU_RESET_DMA1 (1 << 5) 123 #define AMDGPU_RESET_RLC (1 << 6) 124 #define AMDGPU_RESET_SEM (1 << 7) 125 #define AMDGPU_RESET_IH (1 << 8) 126 #define AMDGPU_RESET_VMC (1 << 9) 127 #define AMDGPU_RESET_MC (1 << 10) 128 #define AMDGPU_RESET_DISPLAY (1 << 11) 129 #define AMDGPU_RESET_UVD (1 << 12) 130 #define AMDGPU_RESET_VCE (1 << 13) 131 #define AMDGPU_RESET_VCE1 (1 << 14) 132 133 /* CG block flags */ 134 #define AMDGPU_CG_BLOCK_GFX (1 << 0) 135 #define AMDGPU_CG_BLOCK_MC (1 << 1) 136 #define AMDGPU_CG_BLOCK_SDMA (1 << 2) 137 #define AMDGPU_CG_BLOCK_UVD (1 << 3) 138 #define AMDGPU_CG_BLOCK_VCE (1 << 4) 139 #define AMDGPU_CG_BLOCK_HDP (1 << 5) 140 #define AMDGPU_CG_BLOCK_BIF (1 << 6) 141 142 /* CG flags */ 143 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0) 144 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1) 145 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2) 146 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3) 147 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4) 148 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 149 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6) 150 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7) 151 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8) 152 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9) 153 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10) 154 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11) 155 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12) 156 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13) 157 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14) 158 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15) 159 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16) 160 161 /* PG flags */ 162 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) 163 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) 164 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) 165 #define AMDGPU_PG_SUPPORT_UVD (1 << 3) 166 #define AMDGPU_PG_SUPPORT_VCE (1 << 4) 167 #define AMDGPU_PG_SUPPORT_CP (1 << 5) 168 #define AMDGPU_PG_SUPPORT_GDS (1 << 6) 169 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7) 170 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8) 171 #define AMDGPU_PG_SUPPORT_ACP (1 << 9) 172 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10) 173 174 /* GFX current status */ 175 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 176 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 177 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 178 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 179 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 180 181 /* max cursor sizes (in pixels) */ 182 #define CIK_CURSOR_WIDTH 128 183 #define CIK_CURSOR_HEIGHT 128 184 185 struct amdgpu_device; 186 struct amdgpu_fence; 187 struct amdgpu_ib; 188 struct amdgpu_vm; 189 struct amdgpu_ring; 190 struct amdgpu_semaphore; 191 struct amdgpu_cs_parser; 192 struct amdgpu_job; 193 struct amdgpu_irq_src; 194 struct amdgpu_fpriv; 195 196 enum amdgpu_cp_irq { 197 AMDGPU_CP_IRQ_GFX_EOP = 0, 198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 206 207 AMDGPU_CP_IRQ_LAST 208 }; 209 210 enum amdgpu_sdma_irq { 211 AMDGPU_SDMA_IRQ_TRAP0 = 0, 212 AMDGPU_SDMA_IRQ_TRAP1, 213 214 AMDGPU_SDMA_IRQ_LAST 215 }; 216 217 enum amdgpu_thermal_irq { 218 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 219 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 220 221 AMDGPU_THERMAL_IRQ_LAST 222 }; 223 224 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 225 enum amd_ip_block_type block_type, 226 enum amd_clockgating_state state); 227 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 228 enum amd_ip_block_type block_type, 229 enum amd_powergating_state state); 230 231 struct amdgpu_ip_block_version { 232 enum amd_ip_block_type type; 233 u32 major; 234 u32 minor; 235 u32 rev; 236 const struct amd_ip_funcs *funcs; 237 }; 238 239 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 240 enum amd_ip_block_type type, 241 u32 major, u32 minor); 242 243 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 244 struct amdgpu_device *adev, 245 enum amd_ip_block_type type); 246 247 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 248 struct amdgpu_buffer_funcs { 249 /* maximum bytes in a single operation */ 250 uint32_t copy_max_bytes; 251 252 /* number of dw to reserve per operation */ 253 unsigned copy_num_dw; 254 255 /* used for buffer migration */ 256 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 257 /* src addr in bytes */ 258 uint64_t src_offset, 259 /* dst addr in bytes */ 260 uint64_t dst_offset, 261 /* number of byte to transfer */ 262 uint32_t byte_count); 263 264 /* maximum bytes in a single operation */ 265 uint32_t fill_max_bytes; 266 267 /* number of dw to reserve per operation */ 268 unsigned fill_num_dw; 269 270 /* used for buffer clearing */ 271 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 272 /* value to write to memory */ 273 uint32_t src_data, 274 /* dst addr in bytes */ 275 uint64_t dst_offset, 276 /* number of byte to fill */ 277 uint32_t byte_count); 278 }; 279 280 /* provided by hw blocks that can write ptes, e.g., sdma */ 281 struct amdgpu_vm_pte_funcs { 282 /* copy pte entries from GART */ 283 void (*copy_pte)(struct amdgpu_ib *ib, 284 uint64_t pe, uint64_t src, 285 unsigned count); 286 /* write pte one entry at a time with addr mapping */ 287 void (*write_pte)(struct amdgpu_ib *ib, 288 uint64_t pe, 289 uint64_t addr, unsigned count, 290 uint32_t incr, uint32_t flags); 291 /* for linear pte/pde updates without addr mapping */ 292 void (*set_pte_pde)(struct amdgpu_ib *ib, 293 uint64_t pe, 294 uint64_t addr, unsigned count, 295 uint32_t incr, uint32_t flags); 296 /* pad the indirect buffer to the necessary number of dw */ 297 void (*pad_ib)(struct amdgpu_ib *ib); 298 }; 299 300 /* provided by the gmc block */ 301 struct amdgpu_gart_funcs { 302 /* flush the vm tlb via mmio */ 303 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 304 uint32_t vmid); 305 /* write pte/pde updates using the cpu */ 306 int (*set_pte_pde)(struct amdgpu_device *adev, 307 void *cpu_pt_addr, /* cpu addr of page table */ 308 uint32_t gpu_page_idx, /* pte/pde to update */ 309 uint64_t addr, /* addr to write into pte/pde */ 310 uint32_t flags); /* access flags */ 311 }; 312 313 /* provided by the ih block */ 314 struct amdgpu_ih_funcs { 315 /* ring read/write ptr handling, called from interrupt context */ 316 u32 (*get_wptr)(struct amdgpu_device *adev); 317 void (*decode_iv)(struct amdgpu_device *adev, 318 struct amdgpu_iv_entry *entry); 319 void (*set_rptr)(struct amdgpu_device *adev); 320 }; 321 322 /* provided by hw blocks that expose a ring buffer for commands */ 323 struct amdgpu_ring_funcs { 324 /* ring read/write ptr handling */ 325 u32 (*get_rptr)(struct amdgpu_ring *ring); 326 u32 (*get_wptr)(struct amdgpu_ring *ring); 327 void (*set_wptr)(struct amdgpu_ring *ring); 328 /* validating and patching of IBs */ 329 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 330 /* command emit functions */ 331 void (*emit_ib)(struct amdgpu_ring *ring, 332 struct amdgpu_ib *ib); 333 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 334 uint64_t seq, unsigned flags); 335 bool (*emit_semaphore)(struct amdgpu_ring *ring, 336 struct amdgpu_semaphore *semaphore, 337 bool emit_wait); 338 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 339 uint64_t pd_addr); 340 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 341 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 342 uint32_t gds_base, uint32_t gds_size, 343 uint32_t gws_base, uint32_t gws_size, 344 uint32_t oa_base, uint32_t oa_size); 345 /* testing functions */ 346 int (*test_ring)(struct amdgpu_ring *ring); 347 int (*test_ib)(struct amdgpu_ring *ring); 348 /* insert NOP packets */ 349 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 350 }; 351 352 /* 353 * BIOS. 354 */ 355 bool amdgpu_get_bios(struct amdgpu_device *adev); 356 bool amdgpu_read_bios(struct amdgpu_device *adev); 357 358 /* 359 * Dummy page 360 */ 361 struct amdgpu_dummy_page { 362 struct page *page; 363 dma_addr_t addr; 364 }; 365 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 366 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 367 368 369 /* 370 * Clocks 371 */ 372 373 #define AMDGPU_MAX_PPLL 3 374 375 struct amdgpu_clock { 376 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 377 struct amdgpu_pll spll; 378 struct amdgpu_pll mpll; 379 /* 10 Khz units */ 380 uint32_t default_mclk; 381 uint32_t default_sclk; 382 uint32_t default_dispclk; 383 uint32_t current_dispclk; 384 uint32_t dp_extclk; 385 uint32_t max_pixel_clock; 386 }; 387 388 /* 389 * Fences. 390 */ 391 struct amdgpu_fence_driver { 392 uint64_t gpu_addr; 393 volatile uint32_t *cpu_addr; 394 /* sync_seq is protected by ring emission lock */ 395 uint64_t sync_seq[AMDGPU_MAX_RINGS]; 396 atomic64_t last_seq; 397 bool initialized; 398 struct amdgpu_irq_src *irq_src; 399 unsigned irq_type; 400 struct timer_list fallback_timer; 401 wait_queue_head_t fence_queue; 402 }; 403 404 /* some special values for the owner field */ 405 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 406 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 407 408 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 409 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 410 411 struct amdgpu_fence { 412 struct fence base; 413 414 /* RB, DMA, etc. */ 415 struct amdgpu_ring *ring; 416 uint64_t seq; 417 418 /* filp or special value for fence creator */ 419 void *owner; 420 421 wait_queue_t fence_wake; 422 }; 423 424 struct amdgpu_user_fence { 425 /* write-back bo */ 426 struct amdgpu_bo *bo; 427 /* write-back address offset to bo start */ 428 uint32_t offset; 429 }; 430 431 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 432 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 433 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 434 435 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 436 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 437 struct amdgpu_irq_src *irq_src, 438 unsigned irq_type); 439 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 440 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 441 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, 442 struct amdgpu_fence **fence); 443 void amdgpu_fence_process(struct amdgpu_ring *ring); 444 int amdgpu_fence_wait_next(struct amdgpu_ring *ring); 445 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 446 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 447 448 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, 449 struct amdgpu_ring *ring); 450 void amdgpu_fence_note_sync(struct amdgpu_fence *fence, 451 struct amdgpu_ring *ring); 452 453 /* 454 * TTM. 455 */ 456 struct amdgpu_mman { 457 struct ttm_bo_global_ref bo_global_ref; 458 struct drm_global_reference mem_global_ref; 459 struct ttm_bo_device bdev; 460 bool mem_global_referenced; 461 bool initialized; 462 463 #if defined(CONFIG_DEBUG_FS) 464 struct dentry *vram; 465 struct dentry *gtt; 466 #endif 467 468 /* buffer handling */ 469 const struct amdgpu_buffer_funcs *buffer_funcs; 470 struct amdgpu_ring *buffer_funcs_ring; 471 }; 472 473 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 474 uint64_t src_offset, 475 uint64_t dst_offset, 476 uint32_t byte_count, 477 struct reservation_object *resv, 478 struct fence **fence); 479 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 480 481 struct amdgpu_bo_list_entry { 482 struct amdgpu_bo *robj; 483 struct ttm_validate_buffer tv; 484 struct amdgpu_bo_va *bo_va; 485 unsigned prefered_domains; 486 unsigned allowed_domains; 487 uint32_t priority; 488 }; 489 490 struct amdgpu_bo_va_mapping { 491 struct list_head list; 492 struct interval_tree_node it; 493 uint64_t offset; 494 uint32_t flags; 495 }; 496 497 /* bo virtual addresses in a specific vm */ 498 struct amdgpu_bo_va { 499 /* protected by bo being reserved */ 500 struct list_head bo_list; 501 struct fence *last_pt_update; 502 unsigned ref_count; 503 504 /* protected by vm mutex and spinlock */ 505 struct list_head vm_status; 506 507 /* mappings for this bo_va */ 508 struct list_head invalids; 509 struct list_head valids; 510 511 /* constant after initialization */ 512 struct amdgpu_vm *vm; 513 struct amdgpu_bo *bo; 514 }; 515 516 #define AMDGPU_GEM_DOMAIN_MAX 0x3 517 518 struct amdgpu_bo { 519 /* Protected by gem.mutex */ 520 struct list_head list; 521 /* Protected by tbo.reserved */ 522 u32 initial_domain; 523 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 524 struct ttm_placement placement; 525 struct ttm_buffer_object tbo; 526 struct ttm_bo_kmap_obj kmap; 527 u64 flags; 528 unsigned pin_count; 529 void *kptr; 530 u64 tiling_flags; 531 u64 metadata_flags; 532 void *metadata; 533 u32 metadata_size; 534 /* list of all virtual address to which this bo 535 * is associated to 536 */ 537 struct list_head va; 538 /* Constant after initialization */ 539 struct amdgpu_device *adev; 540 struct drm_gem_object gem_base; 541 542 struct ttm_bo_kmap_obj dma_buf_vmap; 543 pid_t pid; 544 struct amdgpu_mn *mn; 545 struct list_head mn_list; 546 }; 547 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 548 549 void amdgpu_gem_object_free(struct drm_gem_object *obj); 550 int amdgpu_gem_object_open(struct drm_gem_object *obj, 551 struct drm_file *file_priv); 552 void amdgpu_gem_object_close(struct drm_gem_object *obj, 553 struct drm_file *file_priv); 554 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 555 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 556 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 557 struct dma_buf_attachment *attach, 558 struct sg_table *sg); 559 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 560 struct drm_gem_object *gobj, 561 int flags); 562 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 563 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 564 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 565 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 566 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 567 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 568 569 /* sub-allocation manager, it has to be protected by another lock. 570 * By conception this is an helper for other part of the driver 571 * like the indirect buffer or semaphore, which both have their 572 * locking. 573 * 574 * Principe is simple, we keep a list of sub allocation in offset 575 * order (first entry has offset == 0, last entry has the highest 576 * offset). 577 * 578 * When allocating new object we first check if there is room at 579 * the end total_size - (last_object_offset + last_object_size) >= 580 * alloc_size. If so we allocate new object there. 581 * 582 * When there is not enough room at the end, we start waiting for 583 * each sub object until we reach object_offset+object_size >= 584 * alloc_size, this object then become the sub object we return. 585 * 586 * Alignment can't be bigger than page size. 587 * 588 * Hole are not considered for allocation to keep things simple. 589 * Assumption is that there won't be hole (all object on same 590 * alignment). 591 */ 592 struct amdgpu_sa_manager { 593 wait_queue_head_t wq; 594 struct amdgpu_bo *bo; 595 struct list_head *hole; 596 struct list_head flist[AMDGPU_MAX_RINGS]; 597 struct list_head olist; 598 unsigned size; 599 uint64_t gpu_addr; 600 void *cpu_ptr; 601 uint32_t domain; 602 uint32_t align; 603 }; 604 605 struct amdgpu_sa_bo; 606 607 /* sub-allocation buffer */ 608 struct amdgpu_sa_bo { 609 struct list_head olist; 610 struct list_head flist; 611 struct amdgpu_sa_manager *manager; 612 unsigned soffset; 613 unsigned eoffset; 614 struct fence *fence; 615 }; 616 617 /* 618 * GEM objects. 619 */ 620 struct amdgpu_gem { 621 struct mutex mutex; 622 struct list_head objects; 623 }; 624 625 int amdgpu_gem_init(struct amdgpu_device *adev); 626 void amdgpu_gem_fini(struct amdgpu_device *adev); 627 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 628 int alignment, u32 initial_domain, 629 u64 flags, bool kernel, 630 struct drm_gem_object **obj); 631 632 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 633 struct drm_device *dev, 634 struct drm_mode_create_dumb *args); 635 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 636 struct drm_device *dev, 637 uint32_t handle, uint64_t *offset_p); 638 639 /* 640 * Semaphores. 641 */ 642 struct amdgpu_semaphore { 643 struct amdgpu_sa_bo *sa_bo; 644 signed waiters; 645 uint64_t gpu_addr; 646 }; 647 648 int amdgpu_semaphore_create(struct amdgpu_device *adev, 649 struct amdgpu_semaphore **semaphore); 650 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, 651 struct amdgpu_semaphore *semaphore); 652 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, 653 struct amdgpu_semaphore *semaphore); 654 void amdgpu_semaphore_free(struct amdgpu_device *adev, 655 struct amdgpu_semaphore **semaphore, 656 struct fence *fence); 657 658 /* 659 * Synchronization 660 */ 661 struct amdgpu_sync { 662 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS]; 663 struct fence *sync_to[AMDGPU_MAX_RINGS]; 664 DECLARE_HASHTABLE(fences, 4); 665 struct fence *last_vm_update; 666 }; 667 668 void amdgpu_sync_create(struct amdgpu_sync *sync); 669 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 670 struct fence *f); 671 int amdgpu_sync_resv(struct amdgpu_device *adev, 672 struct amdgpu_sync *sync, 673 struct reservation_object *resv, 674 void *owner); 675 int amdgpu_sync_rings(struct amdgpu_sync *sync, 676 struct amdgpu_ring *ring); 677 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 678 int amdgpu_sync_wait(struct amdgpu_sync *sync); 679 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, 680 struct fence *fence); 681 682 /* 683 * GART structures, functions & helpers 684 */ 685 struct amdgpu_mc; 686 687 #define AMDGPU_GPU_PAGE_SIZE 4096 688 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 689 #define AMDGPU_GPU_PAGE_SHIFT 12 690 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 691 692 struct amdgpu_gart { 693 dma_addr_t table_addr; 694 struct amdgpu_bo *robj; 695 void *ptr; 696 unsigned num_gpu_pages; 697 unsigned num_cpu_pages; 698 unsigned table_size; 699 struct page **pages; 700 dma_addr_t *pages_addr; 701 bool ready; 702 const struct amdgpu_gart_funcs *gart_funcs; 703 }; 704 705 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 706 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 707 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 708 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 709 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 710 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 711 int amdgpu_gart_init(struct amdgpu_device *adev); 712 void amdgpu_gart_fini(struct amdgpu_device *adev); 713 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 714 int pages); 715 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 716 int pages, struct page **pagelist, 717 dma_addr_t *dma_addr, uint32_t flags); 718 719 /* 720 * GPU MC structures, functions & helpers 721 */ 722 struct amdgpu_mc { 723 resource_size_t aper_size; 724 resource_size_t aper_base; 725 resource_size_t agp_base; 726 /* for some chips with <= 32MB we need to lie 727 * about vram size near mc fb location */ 728 u64 mc_vram_size; 729 u64 visible_vram_size; 730 u64 gtt_size; 731 u64 gtt_start; 732 u64 gtt_end; 733 u64 vram_start; 734 u64 vram_end; 735 unsigned vram_width; 736 u64 real_vram_size; 737 int vram_mtrr; 738 u64 gtt_base_align; 739 u64 mc_mask; 740 const struct firmware *fw; /* MC firmware */ 741 uint32_t fw_version; 742 struct amdgpu_irq_src vm_fault; 743 uint32_t vram_type; 744 }; 745 746 /* 747 * GPU doorbell structures, functions & helpers 748 */ 749 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 750 { 751 AMDGPU_DOORBELL_KIQ = 0x000, 752 AMDGPU_DOORBELL_HIQ = 0x001, 753 AMDGPU_DOORBELL_DIQ = 0x002, 754 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 755 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 756 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 757 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 758 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 759 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 760 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 761 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 762 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 763 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 764 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 765 AMDGPU_DOORBELL_IH = 0x1E8, 766 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 767 AMDGPU_DOORBELL_INVALID = 0xFFFF 768 } AMDGPU_DOORBELL_ASSIGNMENT; 769 770 struct amdgpu_doorbell { 771 /* doorbell mmio */ 772 resource_size_t base; 773 resource_size_t size; 774 u32 __iomem *ptr; 775 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 776 }; 777 778 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 779 phys_addr_t *aperture_base, 780 size_t *aperture_size, 781 size_t *start_offset); 782 783 /* 784 * IRQS. 785 */ 786 787 struct amdgpu_flip_work { 788 struct work_struct flip_work; 789 struct work_struct unpin_work; 790 struct amdgpu_device *adev; 791 int crtc_id; 792 uint64_t base; 793 struct drm_pending_vblank_event *event; 794 struct amdgpu_bo *old_rbo; 795 struct fence *excl; 796 unsigned shared_count; 797 struct fence **shared; 798 }; 799 800 801 /* 802 * CP & rings. 803 */ 804 805 struct amdgpu_ib { 806 struct amdgpu_sa_bo *sa_bo; 807 uint32_t length_dw; 808 uint64_t gpu_addr; 809 uint32_t *ptr; 810 struct amdgpu_ring *ring; 811 struct amdgpu_fence *fence; 812 struct amdgpu_user_fence *user; 813 struct amdgpu_vm *vm; 814 struct amdgpu_ctx *ctx; 815 struct amdgpu_sync sync; 816 uint32_t gds_base, gds_size; 817 uint32_t gws_base, gws_size; 818 uint32_t oa_base, oa_size; 819 uint32_t flags; 820 /* resulting sequence number */ 821 uint64_t sequence; 822 }; 823 824 enum amdgpu_ring_type { 825 AMDGPU_RING_TYPE_GFX, 826 AMDGPU_RING_TYPE_COMPUTE, 827 AMDGPU_RING_TYPE_SDMA, 828 AMDGPU_RING_TYPE_UVD, 829 AMDGPU_RING_TYPE_VCE 830 }; 831 832 extern struct amd_sched_backend_ops amdgpu_sched_ops; 833 834 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev, 835 struct amdgpu_ring *ring, 836 struct amdgpu_ib *ibs, 837 unsigned num_ibs, 838 int (*free_job)(struct amdgpu_job *), 839 void *owner, 840 struct fence **fence); 841 842 struct amdgpu_ring { 843 struct amdgpu_device *adev; 844 const struct amdgpu_ring_funcs *funcs; 845 struct amdgpu_fence_driver fence_drv; 846 struct amd_gpu_scheduler sched; 847 848 spinlock_t fence_lock; 849 struct mutex *ring_lock; 850 struct amdgpu_bo *ring_obj; 851 volatile uint32_t *ring; 852 unsigned rptr_offs; 853 u64 next_rptr_gpu_addr; 854 volatile u32 *next_rptr_cpu_addr; 855 unsigned wptr; 856 unsigned wptr_old; 857 unsigned ring_size; 858 unsigned ring_free_dw; 859 int count_dw; 860 uint64_t gpu_addr; 861 uint32_t align_mask; 862 uint32_t ptr_mask; 863 bool ready; 864 u32 nop; 865 u32 idx; 866 u64 last_semaphore_signal_addr; 867 u64 last_semaphore_wait_addr; 868 u32 me; 869 u32 pipe; 870 u32 queue; 871 struct amdgpu_bo *mqd_obj; 872 u32 doorbell_index; 873 bool use_doorbell; 874 unsigned wptr_offs; 875 unsigned next_rptr_offs; 876 unsigned fence_offs; 877 struct amdgpu_ctx *current_ctx; 878 enum amdgpu_ring_type type; 879 char name[16]; 880 bool is_pte_ring; 881 }; 882 883 /* 884 * VM 885 */ 886 887 /* maximum number of VMIDs */ 888 #define AMDGPU_NUM_VM 16 889 890 /* number of entries in page table */ 891 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 892 893 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 894 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 895 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 896 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 897 898 #define AMDGPU_PTE_VALID (1 << 0) 899 #define AMDGPU_PTE_SYSTEM (1 << 1) 900 #define AMDGPU_PTE_SNOOPED (1 << 2) 901 902 /* VI only */ 903 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 904 905 #define AMDGPU_PTE_READABLE (1 << 5) 906 #define AMDGPU_PTE_WRITEABLE (1 << 6) 907 908 /* PTE (Page Table Entry) fragment field for different page sizes */ 909 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 910 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 911 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 912 913 /* How to programm VM fault handling */ 914 #define AMDGPU_VM_FAULT_STOP_NEVER 0 915 #define AMDGPU_VM_FAULT_STOP_FIRST 1 916 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 917 918 struct amdgpu_vm_pt { 919 struct amdgpu_bo *bo; 920 uint64_t addr; 921 }; 922 923 struct amdgpu_vm_id { 924 unsigned id; 925 uint64_t pd_gpu_addr; 926 /* last flushed PD/PT update */ 927 struct fence *flushed_updates; 928 }; 929 930 struct amdgpu_vm { 931 struct mutex mutex; 932 933 struct rb_root va; 934 935 /* protecting invalidated */ 936 spinlock_t status_lock; 937 938 /* BOs moved, but not yet updated in the PT */ 939 struct list_head invalidated; 940 941 /* BOs cleared in the PT because of a move */ 942 struct list_head cleared; 943 944 /* BO mappings freed, but not yet updated in the PT */ 945 struct list_head freed; 946 947 /* contains the page directory */ 948 struct amdgpu_bo *page_directory; 949 unsigned max_pde_used; 950 struct fence *page_directory_fence; 951 952 /* array of page tables, one for each page directory entry */ 953 struct amdgpu_vm_pt *page_tables; 954 955 /* for id and flush management per ring */ 956 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; 957 /* for interval tree */ 958 spinlock_t it_lock; 959 }; 960 961 struct amdgpu_vm_manager { 962 struct { 963 struct fence *active; 964 atomic_long_t owner; 965 } ids[AMDGPU_NUM_VM]; 966 967 uint32_t max_pfn; 968 /* number of VMIDs */ 969 unsigned nvm; 970 /* vram base address for page table entry */ 971 u64 vram_base_offset; 972 /* is vm enabled? */ 973 bool enabled; 974 /* vm pte handling */ 975 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 976 struct amdgpu_ring *vm_pte_funcs_ring; 977 }; 978 979 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 980 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 981 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 982 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, 983 struct amdgpu_vm *vm, 984 struct list_head *head); 985 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 986 struct amdgpu_sync *sync); 987 void amdgpu_vm_flush(struct amdgpu_ring *ring, 988 struct amdgpu_vm *vm, 989 struct fence *updates); 990 void amdgpu_vm_fence(struct amdgpu_device *adev, 991 struct amdgpu_vm *vm, 992 struct fence *fence); 993 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); 994 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 995 struct amdgpu_vm *vm); 996 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 997 struct amdgpu_vm *vm); 998 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, 999 struct amdgpu_sync *sync); 1000 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 1001 struct amdgpu_bo_va *bo_va, 1002 struct ttm_mem_reg *mem); 1003 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 1004 struct amdgpu_bo *bo); 1005 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 1006 struct amdgpu_bo *bo); 1007 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 1008 struct amdgpu_vm *vm, 1009 struct amdgpu_bo *bo); 1010 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 1011 struct amdgpu_bo_va *bo_va, 1012 uint64_t addr, uint64_t offset, 1013 uint64_t size, uint32_t flags); 1014 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 1015 struct amdgpu_bo_va *bo_va, 1016 uint64_t addr); 1017 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 1018 struct amdgpu_bo_va *bo_va); 1019 int amdgpu_vm_free_job(struct amdgpu_job *job); 1020 1021 /* 1022 * context related structures 1023 */ 1024 1025 #define AMDGPU_CTX_MAX_CS_PENDING 16 1026 1027 struct amdgpu_ctx_ring { 1028 uint64_t sequence; 1029 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING]; 1030 struct amd_sched_entity entity; 1031 }; 1032 1033 struct amdgpu_ctx { 1034 struct kref refcount; 1035 struct amdgpu_device *adev; 1036 unsigned reset_counter; 1037 spinlock_t ring_lock; 1038 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 1039 }; 1040 1041 struct amdgpu_ctx_mgr { 1042 struct amdgpu_device *adev; 1043 struct mutex lock; 1044 /* protected by lock */ 1045 struct idr ctx_handles; 1046 }; 1047 1048 int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel, 1049 struct amdgpu_ctx *ctx); 1050 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx); 1051 1052 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 1053 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 1054 1055 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 1056 struct fence *fence); 1057 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 1058 struct amdgpu_ring *ring, uint64_t seq); 1059 1060 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 1061 struct drm_file *filp); 1062 1063 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1064 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 1065 1066 /* 1067 * file private structure 1068 */ 1069 1070 struct amdgpu_fpriv { 1071 struct amdgpu_vm vm; 1072 struct mutex bo_list_lock; 1073 struct idr bo_list_handles; 1074 struct amdgpu_ctx_mgr ctx_mgr; 1075 }; 1076 1077 /* 1078 * residency list 1079 */ 1080 1081 struct amdgpu_bo_list { 1082 struct mutex lock; 1083 struct amdgpu_bo *gds_obj; 1084 struct amdgpu_bo *gws_obj; 1085 struct amdgpu_bo *oa_obj; 1086 bool has_userptr; 1087 unsigned num_entries; 1088 struct amdgpu_bo_list_entry *array; 1089 }; 1090 1091 struct amdgpu_bo_list * 1092 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1093 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1094 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1095 1096 /* 1097 * GFX stuff 1098 */ 1099 #include "clearstate_defs.h" 1100 1101 struct amdgpu_rlc { 1102 /* for power gating */ 1103 struct amdgpu_bo *save_restore_obj; 1104 uint64_t save_restore_gpu_addr; 1105 volatile uint32_t *sr_ptr; 1106 const u32 *reg_list; 1107 u32 reg_list_size; 1108 /* for clear state */ 1109 struct amdgpu_bo *clear_state_obj; 1110 uint64_t clear_state_gpu_addr; 1111 volatile uint32_t *cs_ptr; 1112 const struct cs_section_def *cs_data; 1113 u32 clear_state_size; 1114 /* for cp tables */ 1115 struct amdgpu_bo *cp_table_obj; 1116 uint64_t cp_table_gpu_addr; 1117 volatile uint32_t *cp_table_ptr; 1118 u32 cp_table_size; 1119 }; 1120 1121 struct amdgpu_mec { 1122 struct amdgpu_bo *hpd_eop_obj; 1123 u64 hpd_eop_gpu_addr; 1124 u32 num_pipe; 1125 u32 num_mec; 1126 u32 num_queue; 1127 }; 1128 1129 /* 1130 * GPU scratch registers structures, functions & helpers 1131 */ 1132 struct amdgpu_scratch { 1133 unsigned num_reg; 1134 uint32_t reg_base; 1135 bool free[32]; 1136 uint32_t reg[32]; 1137 }; 1138 1139 /* 1140 * GFX configurations 1141 */ 1142 struct amdgpu_gca_config { 1143 unsigned max_shader_engines; 1144 unsigned max_tile_pipes; 1145 unsigned max_cu_per_sh; 1146 unsigned max_sh_per_se; 1147 unsigned max_backends_per_se; 1148 unsigned max_texture_channel_caches; 1149 unsigned max_gprs; 1150 unsigned max_gs_threads; 1151 unsigned max_hw_contexts; 1152 unsigned sc_prim_fifo_size_frontend; 1153 unsigned sc_prim_fifo_size_backend; 1154 unsigned sc_hiz_tile_fifo_size; 1155 unsigned sc_earlyz_tile_fifo_size; 1156 1157 unsigned num_tile_pipes; 1158 unsigned backend_enable_mask; 1159 unsigned mem_max_burst_length_bytes; 1160 unsigned mem_row_size_in_kb; 1161 unsigned shader_engine_tile_size; 1162 unsigned num_gpus; 1163 unsigned multi_gpu_tile_size; 1164 unsigned mc_arb_ramcfg; 1165 unsigned gb_addr_config; 1166 1167 uint32_t tile_mode_array[32]; 1168 uint32_t macrotile_mode_array[16]; 1169 }; 1170 1171 struct amdgpu_gfx { 1172 struct mutex gpu_clock_mutex; 1173 struct amdgpu_gca_config config; 1174 struct amdgpu_rlc rlc; 1175 struct amdgpu_mec mec; 1176 struct amdgpu_scratch scratch; 1177 const struct firmware *me_fw; /* ME firmware */ 1178 uint32_t me_fw_version; 1179 const struct firmware *pfp_fw; /* PFP firmware */ 1180 uint32_t pfp_fw_version; 1181 const struct firmware *ce_fw; /* CE firmware */ 1182 uint32_t ce_fw_version; 1183 const struct firmware *rlc_fw; /* RLC firmware */ 1184 uint32_t rlc_fw_version; 1185 const struct firmware *mec_fw; /* MEC firmware */ 1186 uint32_t mec_fw_version; 1187 const struct firmware *mec2_fw; /* MEC2 firmware */ 1188 uint32_t mec2_fw_version; 1189 uint32_t me_feature_version; 1190 uint32_t ce_feature_version; 1191 uint32_t pfp_feature_version; 1192 uint32_t rlc_feature_version; 1193 uint32_t mec_feature_version; 1194 uint32_t mec2_feature_version; 1195 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1196 unsigned num_gfx_rings; 1197 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1198 unsigned num_compute_rings; 1199 struct amdgpu_irq_src eop_irq; 1200 struct amdgpu_irq_src priv_reg_irq; 1201 struct amdgpu_irq_src priv_inst_irq; 1202 /* gfx status */ 1203 uint32_t gfx_current_status; 1204 /* ce ram size*/ 1205 unsigned ce_ram_size; 1206 }; 1207 1208 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, 1209 unsigned size, struct amdgpu_ib *ib); 1210 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib); 1211 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, 1212 struct amdgpu_ib *ib, void *owner); 1213 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1214 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1215 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1216 /* Ring access between begin & end cannot sleep */ 1217 void amdgpu_ring_free_size(struct amdgpu_ring *ring); 1218 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1219 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw); 1220 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 1221 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1222 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); 1223 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1224 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); 1225 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1226 uint32_t **data); 1227 int amdgpu_ring_restore(struct amdgpu_ring *ring, 1228 unsigned size, uint32_t *data); 1229 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1230 unsigned ring_size, u32 nop, u32 align_mask, 1231 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1232 enum amdgpu_ring_type ring_type); 1233 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1234 struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f); 1235 1236 /* 1237 * CS. 1238 */ 1239 struct amdgpu_cs_chunk { 1240 uint32_t chunk_id; 1241 uint32_t length_dw; 1242 uint32_t *kdata; 1243 void __user *user_ptr; 1244 }; 1245 1246 struct amdgpu_cs_parser { 1247 struct amdgpu_device *adev; 1248 struct drm_file *filp; 1249 struct amdgpu_ctx *ctx; 1250 struct amdgpu_bo_list *bo_list; 1251 /* chunks */ 1252 unsigned nchunks; 1253 struct amdgpu_cs_chunk *chunks; 1254 /* relocations */ 1255 struct amdgpu_bo_list_entry *vm_bos; 1256 struct list_head validated; 1257 struct fence *fence; 1258 1259 struct amdgpu_ib *ibs; 1260 uint32_t num_ibs; 1261 1262 struct ww_acquire_ctx ticket; 1263 1264 /* user fence */ 1265 struct amdgpu_user_fence uf; 1266 }; 1267 1268 struct amdgpu_job { 1269 struct amd_sched_job base; 1270 struct amdgpu_device *adev; 1271 struct amdgpu_ib *ibs; 1272 uint32_t num_ibs; 1273 void *owner; 1274 struct amdgpu_user_fence uf; 1275 int (*free_job)(struct amdgpu_job *job); 1276 }; 1277 #define to_amdgpu_job(sched_job) \ 1278 container_of((sched_job), struct amdgpu_job, base) 1279 1280 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx) 1281 { 1282 return p->ibs[ib_idx].ptr[idx]; 1283 } 1284 1285 /* 1286 * Writeback 1287 */ 1288 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1289 1290 struct amdgpu_wb { 1291 struct amdgpu_bo *wb_obj; 1292 volatile uint32_t *wb; 1293 uint64_t gpu_addr; 1294 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1295 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1296 }; 1297 1298 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1299 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1300 1301 /** 1302 * struct amdgpu_pm - power management datas 1303 * It keeps track of various data needed to take powermanagement decision. 1304 */ 1305 1306 enum amdgpu_pm_state_type { 1307 /* not used for dpm */ 1308 POWER_STATE_TYPE_DEFAULT, 1309 POWER_STATE_TYPE_POWERSAVE, 1310 /* user selectable states */ 1311 POWER_STATE_TYPE_BATTERY, 1312 POWER_STATE_TYPE_BALANCED, 1313 POWER_STATE_TYPE_PERFORMANCE, 1314 /* internal states */ 1315 POWER_STATE_TYPE_INTERNAL_UVD, 1316 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1317 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1318 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1319 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1320 POWER_STATE_TYPE_INTERNAL_BOOT, 1321 POWER_STATE_TYPE_INTERNAL_THERMAL, 1322 POWER_STATE_TYPE_INTERNAL_ACPI, 1323 POWER_STATE_TYPE_INTERNAL_ULV, 1324 POWER_STATE_TYPE_INTERNAL_3DPERF, 1325 }; 1326 1327 enum amdgpu_int_thermal_type { 1328 THERMAL_TYPE_NONE, 1329 THERMAL_TYPE_EXTERNAL, 1330 THERMAL_TYPE_EXTERNAL_GPIO, 1331 THERMAL_TYPE_RV6XX, 1332 THERMAL_TYPE_RV770, 1333 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1334 THERMAL_TYPE_EVERGREEN, 1335 THERMAL_TYPE_SUMO, 1336 THERMAL_TYPE_NI, 1337 THERMAL_TYPE_SI, 1338 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1339 THERMAL_TYPE_CI, 1340 THERMAL_TYPE_KV, 1341 }; 1342 1343 enum amdgpu_dpm_auto_throttle_src { 1344 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1345 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1346 }; 1347 1348 enum amdgpu_dpm_event_src { 1349 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1350 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1351 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1352 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1353 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1354 }; 1355 1356 #define AMDGPU_MAX_VCE_LEVELS 6 1357 1358 enum amdgpu_vce_level { 1359 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1360 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1361 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1362 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1363 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1364 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1365 }; 1366 1367 struct amdgpu_ps { 1368 u32 caps; /* vbios flags */ 1369 u32 class; /* vbios flags */ 1370 u32 class2; /* vbios flags */ 1371 /* UVD clocks */ 1372 u32 vclk; 1373 u32 dclk; 1374 /* VCE clocks */ 1375 u32 evclk; 1376 u32 ecclk; 1377 bool vce_active; 1378 enum amdgpu_vce_level vce_level; 1379 /* asic priv */ 1380 void *ps_priv; 1381 }; 1382 1383 struct amdgpu_dpm_thermal { 1384 /* thermal interrupt work */ 1385 struct work_struct work; 1386 /* low temperature threshold */ 1387 int min_temp; 1388 /* high temperature threshold */ 1389 int max_temp; 1390 /* was last interrupt low to high or high to low */ 1391 bool high_to_low; 1392 /* interrupt source */ 1393 struct amdgpu_irq_src irq; 1394 }; 1395 1396 enum amdgpu_clk_action 1397 { 1398 AMDGPU_SCLK_UP = 1, 1399 AMDGPU_SCLK_DOWN 1400 }; 1401 1402 struct amdgpu_blacklist_clocks 1403 { 1404 u32 sclk; 1405 u32 mclk; 1406 enum amdgpu_clk_action action; 1407 }; 1408 1409 struct amdgpu_clock_and_voltage_limits { 1410 u32 sclk; 1411 u32 mclk; 1412 u16 vddc; 1413 u16 vddci; 1414 }; 1415 1416 struct amdgpu_clock_array { 1417 u32 count; 1418 u32 *values; 1419 }; 1420 1421 struct amdgpu_clock_voltage_dependency_entry { 1422 u32 clk; 1423 u16 v; 1424 }; 1425 1426 struct amdgpu_clock_voltage_dependency_table { 1427 u32 count; 1428 struct amdgpu_clock_voltage_dependency_entry *entries; 1429 }; 1430 1431 union amdgpu_cac_leakage_entry { 1432 struct { 1433 u16 vddc; 1434 u32 leakage; 1435 }; 1436 struct { 1437 u16 vddc1; 1438 u16 vddc2; 1439 u16 vddc3; 1440 }; 1441 }; 1442 1443 struct amdgpu_cac_leakage_table { 1444 u32 count; 1445 union amdgpu_cac_leakage_entry *entries; 1446 }; 1447 1448 struct amdgpu_phase_shedding_limits_entry { 1449 u16 voltage; 1450 u32 sclk; 1451 u32 mclk; 1452 }; 1453 1454 struct amdgpu_phase_shedding_limits_table { 1455 u32 count; 1456 struct amdgpu_phase_shedding_limits_entry *entries; 1457 }; 1458 1459 struct amdgpu_uvd_clock_voltage_dependency_entry { 1460 u32 vclk; 1461 u32 dclk; 1462 u16 v; 1463 }; 1464 1465 struct amdgpu_uvd_clock_voltage_dependency_table { 1466 u8 count; 1467 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1468 }; 1469 1470 struct amdgpu_vce_clock_voltage_dependency_entry { 1471 u32 ecclk; 1472 u32 evclk; 1473 u16 v; 1474 }; 1475 1476 struct amdgpu_vce_clock_voltage_dependency_table { 1477 u8 count; 1478 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1479 }; 1480 1481 struct amdgpu_ppm_table { 1482 u8 ppm_design; 1483 u16 cpu_core_number; 1484 u32 platform_tdp; 1485 u32 small_ac_platform_tdp; 1486 u32 platform_tdc; 1487 u32 small_ac_platform_tdc; 1488 u32 apu_tdp; 1489 u32 dgpu_tdp; 1490 u32 dgpu_ulv_power; 1491 u32 tj_max; 1492 }; 1493 1494 struct amdgpu_cac_tdp_table { 1495 u16 tdp; 1496 u16 configurable_tdp; 1497 u16 tdc; 1498 u16 battery_power_limit; 1499 u16 small_power_limit; 1500 u16 low_cac_leakage; 1501 u16 high_cac_leakage; 1502 u16 maximum_power_delivery_limit; 1503 }; 1504 1505 struct amdgpu_dpm_dynamic_state { 1506 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1507 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1508 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1509 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1510 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1511 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1512 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1513 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1514 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1515 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1516 struct amdgpu_clock_array valid_sclk_values; 1517 struct amdgpu_clock_array valid_mclk_values; 1518 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1519 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1520 u32 mclk_sclk_ratio; 1521 u32 sclk_mclk_delta; 1522 u16 vddc_vddci_delta; 1523 u16 min_vddc_for_pcie_gen2; 1524 struct amdgpu_cac_leakage_table cac_leakage_table; 1525 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1526 struct amdgpu_ppm_table *ppm_table; 1527 struct amdgpu_cac_tdp_table *cac_tdp_table; 1528 }; 1529 1530 struct amdgpu_dpm_fan { 1531 u16 t_min; 1532 u16 t_med; 1533 u16 t_high; 1534 u16 pwm_min; 1535 u16 pwm_med; 1536 u16 pwm_high; 1537 u8 t_hyst; 1538 u32 cycle_delay; 1539 u16 t_max; 1540 u8 control_mode; 1541 u16 default_max_fan_pwm; 1542 u16 default_fan_output_sensitivity; 1543 u16 fan_output_sensitivity; 1544 bool ucode_fan_control; 1545 }; 1546 1547 enum amdgpu_pcie_gen { 1548 AMDGPU_PCIE_GEN1 = 0, 1549 AMDGPU_PCIE_GEN2 = 1, 1550 AMDGPU_PCIE_GEN3 = 2, 1551 AMDGPU_PCIE_GEN_INVALID = 0xffff 1552 }; 1553 1554 enum amdgpu_dpm_forced_level { 1555 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1556 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1557 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1558 }; 1559 1560 struct amdgpu_vce_state { 1561 /* vce clocks */ 1562 u32 evclk; 1563 u32 ecclk; 1564 /* gpu clocks */ 1565 u32 sclk; 1566 u32 mclk; 1567 u8 clk_idx; 1568 u8 pstate; 1569 }; 1570 1571 struct amdgpu_dpm_funcs { 1572 int (*get_temperature)(struct amdgpu_device *adev); 1573 int (*pre_set_power_state)(struct amdgpu_device *adev); 1574 int (*set_power_state)(struct amdgpu_device *adev); 1575 void (*post_set_power_state)(struct amdgpu_device *adev); 1576 void (*display_configuration_changed)(struct amdgpu_device *adev); 1577 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1578 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1579 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1580 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1581 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1582 bool (*vblank_too_short)(struct amdgpu_device *adev); 1583 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1584 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1585 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1586 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1587 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1588 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1589 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1590 }; 1591 1592 struct amdgpu_dpm { 1593 struct amdgpu_ps *ps; 1594 /* number of valid power states */ 1595 int num_ps; 1596 /* current power state that is active */ 1597 struct amdgpu_ps *current_ps; 1598 /* requested power state */ 1599 struct amdgpu_ps *requested_ps; 1600 /* boot up power state */ 1601 struct amdgpu_ps *boot_ps; 1602 /* default uvd power state */ 1603 struct amdgpu_ps *uvd_ps; 1604 /* vce requirements */ 1605 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1606 enum amdgpu_vce_level vce_level; 1607 enum amdgpu_pm_state_type state; 1608 enum amdgpu_pm_state_type user_state; 1609 u32 platform_caps; 1610 u32 voltage_response_time; 1611 u32 backbias_response_time; 1612 void *priv; 1613 u32 new_active_crtcs; 1614 int new_active_crtc_count; 1615 u32 current_active_crtcs; 1616 int current_active_crtc_count; 1617 struct amdgpu_dpm_dynamic_state dyn_state; 1618 struct amdgpu_dpm_fan fan; 1619 u32 tdp_limit; 1620 u32 near_tdp_limit; 1621 u32 near_tdp_limit_adjusted; 1622 u32 sq_ramping_threshold; 1623 u32 cac_leakage; 1624 u16 tdp_od_limit; 1625 u32 tdp_adjustment; 1626 u16 load_line_slope; 1627 bool power_control; 1628 bool ac_power; 1629 /* special states active */ 1630 bool thermal_active; 1631 bool uvd_active; 1632 bool vce_active; 1633 /* thermal handling */ 1634 struct amdgpu_dpm_thermal thermal; 1635 /* forced levels */ 1636 enum amdgpu_dpm_forced_level forced_level; 1637 }; 1638 1639 struct amdgpu_pm { 1640 struct mutex mutex; 1641 u32 current_sclk; 1642 u32 current_mclk; 1643 u32 default_sclk; 1644 u32 default_mclk; 1645 struct amdgpu_i2c_chan *i2c_bus; 1646 /* internal thermal controller on rv6xx+ */ 1647 enum amdgpu_int_thermal_type int_thermal_type; 1648 struct device *int_hwmon_dev; 1649 /* fan control parameters */ 1650 bool no_fan; 1651 u8 fan_pulses_per_revolution; 1652 u8 fan_min_rpm; 1653 u8 fan_max_rpm; 1654 /* dpm */ 1655 bool dpm_enabled; 1656 bool sysfs_initialized; 1657 struct amdgpu_dpm dpm; 1658 const struct firmware *fw; /* SMC firmware */ 1659 uint32_t fw_version; 1660 const struct amdgpu_dpm_funcs *funcs; 1661 }; 1662 1663 /* 1664 * UVD 1665 */ 1666 #define AMDGPU_MAX_UVD_HANDLES 10 1667 #define AMDGPU_UVD_STACK_SIZE (1024*1024) 1668 #define AMDGPU_UVD_HEAP_SIZE (1024*1024) 1669 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1670 1671 struct amdgpu_uvd { 1672 struct amdgpu_bo *vcpu_bo; 1673 void *cpu_addr; 1674 uint64_t gpu_addr; 1675 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1676 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1677 struct delayed_work idle_work; 1678 const struct firmware *fw; /* UVD firmware */ 1679 struct amdgpu_ring ring; 1680 struct amdgpu_irq_src irq; 1681 bool address_64_bit; 1682 }; 1683 1684 /* 1685 * VCE 1686 */ 1687 #define AMDGPU_MAX_VCE_HANDLES 16 1688 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1689 1690 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1691 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1692 1693 struct amdgpu_vce { 1694 struct amdgpu_bo *vcpu_bo; 1695 uint64_t gpu_addr; 1696 unsigned fw_version; 1697 unsigned fb_version; 1698 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1699 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1700 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1701 struct delayed_work idle_work; 1702 const struct firmware *fw; /* VCE firmware */ 1703 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1704 struct amdgpu_irq_src irq; 1705 unsigned harvest_config; 1706 }; 1707 1708 /* 1709 * SDMA 1710 */ 1711 struct amdgpu_sdma_instance { 1712 /* SDMA firmware */ 1713 const struct firmware *fw; 1714 uint32_t fw_version; 1715 uint32_t feature_version; 1716 1717 struct amdgpu_ring ring; 1718 bool burst_nop; 1719 }; 1720 1721 struct amdgpu_sdma { 1722 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1723 struct amdgpu_irq_src trap_irq; 1724 struct amdgpu_irq_src illegal_inst_irq; 1725 int num_instances; 1726 }; 1727 1728 /* 1729 * Firmware 1730 */ 1731 struct amdgpu_firmware { 1732 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1733 bool smu_load; 1734 struct amdgpu_bo *fw_buf; 1735 unsigned int fw_size; 1736 }; 1737 1738 /* 1739 * Benchmarking 1740 */ 1741 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1742 1743 1744 /* 1745 * Testing 1746 */ 1747 void amdgpu_test_moves(struct amdgpu_device *adev); 1748 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1749 struct amdgpu_ring *cpA, 1750 struct amdgpu_ring *cpB); 1751 void amdgpu_test_syncing(struct amdgpu_device *adev); 1752 1753 /* 1754 * MMU Notifier 1755 */ 1756 #if defined(CONFIG_MMU_NOTIFIER) 1757 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1758 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1759 #else 1760 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1761 { 1762 return -ENODEV; 1763 } 1764 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1765 #endif 1766 1767 /* 1768 * Debugfs 1769 */ 1770 struct amdgpu_debugfs { 1771 struct drm_info_list *files; 1772 unsigned num_files; 1773 }; 1774 1775 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1776 struct drm_info_list *files, 1777 unsigned nfiles); 1778 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1779 1780 #if defined(CONFIG_DEBUG_FS) 1781 int amdgpu_debugfs_init(struct drm_minor *minor); 1782 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1783 #endif 1784 1785 /* 1786 * amdgpu smumgr functions 1787 */ 1788 struct amdgpu_smumgr_funcs { 1789 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1790 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1791 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1792 }; 1793 1794 /* 1795 * amdgpu smumgr 1796 */ 1797 struct amdgpu_smumgr { 1798 struct amdgpu_bo *toc_buf; 1799 struct amdgpu_bo *smu_buf; 1800 /* asic priv smu data */ 1801 void *priv; 1802 spinlock_t smu_lock; 1803 /* smumgr functions */ 1804 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1805 /* ucode loading complete flag */ 1806 uint32_t fw_flags; 1807 }; 1808 1809 /* 1810 * ASIC specific register table accessible by UMD 1811 */ 1812 struct amdgpu_allowed_register_entry { 1813 uint32_t reg_offset; 1814 bool untouched; 1815 bool grbm_indexed; 1816 }; 1817 1818 struct amdgpu_cu_info { 1819 uint32_t number; /* total active CU number */ 1820 uint32_t ao_cu_mask; 1821 uint32_t bitmap[4][4]; 1822 }; 1823 1824 1825 /* 1826 * ASIC specific functions. 1827 */ 1828 struct amdgpu_asic_funcs { 1829 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1830 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1831 u32 sh_num, u32 reg_offset, u32 *value); 1832 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1833 int (*reset)(struct amdgpu_device *adev); 1834 /* wait for mc_idle */ 1835 int (*wait_for_mc_idle)(struct amdgpu_device *adev); 1836 /* get the reference clock */ 1837 u32 (*get_xclk)(struct amdgpu_device *adev); 1838 /* get the gpu clock counter */ 1839 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1840 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); 1841 /* MM block clocks */ 1842 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1843 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1844 }; 1845 1846 /* 1847 * IOCTL. 1848 */ 1849 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1850 struct drm_file *filp); 1851 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1852 struct drm_file *filp); 1853 1854 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1855 struct drm_file *filp); 1856 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1857 struct drm_file *filp); 1858 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1859 struct drm_file *filp); 1860 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1861 struct drm_file *filp); 1862 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1863 struct drm_file *filp); 1864 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1865 struct drm_file *filp); 1866 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1867 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1868 1869 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1870 struct drm_file *filp); 1871 1872 /* VRAM scratch page for HDP bug, default vram page */ 1873 struct amdgpu_vram_scratch { 1874 struct amdgpu_bo *robj; 1875 volatile uint32_t *ptr; 1876 u64 gpu_addr; 1877 }; 1878 1879 /* 1880 * ACPI 1881 */ 1882 struct amdgpu_atif_notification_cfg { 1883 bool enabled; 1884 int command_code; 1885 }; 1886 1887 struct amdgpu_atif_notifications { 1888 bool display_switch; 1889 bool expansion_mode_change; 1890 bool thermal_state; 1891 bool forced_power_state; 1892 bool system_power_state; 1893 bool display_conf_change; 1894 bool px_gfx_switch; 1895 bool brightness_change; 1896 bool dgpu_display_event; 1897 }; 1898 1899 struct amdgpu_atif_functions { 1900 bool system_params; 1901 bool sbios_requests; 1902 bool select_active_disp; 1903 bool lid_state; 1904 bool get_tv_standard; 1905 bool set_tv_standard; 1906 bool get_panel_expansion_mode; 1907 bool set_panel_expansion_mode; 1908 bool temperature_change; 1909 bool graphics_device_types; 1910 }; 1911 1912 struct amdgpu_atif { 1913 struct amdgpu_atif_notifications notifications; 1914 struct amdgpu_atif_functions functions; 1915 struct amdgpu_atif_notification_cfg notification_cfg; 1916 struct amdgpu_encoder *encoder_for_bl; 1917 }; 1918 1919 struct amdgpu_atcs_functions { 1920 bool get_ext_state; 1921 bool pcie_perf_req; 1922 bool pcie_dev_rdy; 1923 bool pcie_bus_width; 1924 }; 1925 1926 struct amdgpu_atcs { 1927 struct amdgpu_atcs_functions functions; 1928 }; 1929 1930 /* 1931 * CGS 1932 */ 1933 void *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1934 void amdgpu_cgs_destroy_device(void *cgs_device); 1935 1936 1937 /* 1938 * Core structure, functions and helpers. 1939 */ 1940 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1941 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1942 1943 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1944 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1945 1946 struct amdgpu_ip_block_status { 1947 bool valid; 1948 bool sw; 1949 bool hw; 1950 }; 1951 1952 struct amdgpu_device { 1953 struct device *dev; 1954 struct drm_device *ddev; 1955 struct pci_dev *pdev; 1956 1957 /* ASIC */ 1958 enum amd_asic_type asic_type; 1959 uint32_t family; 1960 uint32_t rev_id; 1961 uint32_t external_rev_id; 1962 unsigned long flags; 1963 int usec_timeout; 1964 const struct amdgpu_asic_funcs *asic_funcs; 1965 bool shutdown; 1966 bool suspend; 1967 bool need_dma32; 1968 bool accel_working; 1969 struct work_struct reset_work; 1970 struct notifier_block acpi_nb; 1971 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1972 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1973 unsigned debugfs_count; 1974 #if defined(CONFIG_DEBUG_FS) 1975 struct dentry *debugfs_regs; 1976 #endif 1977 struct amdgpu_atif atif; 1978 struct amdgpu_atcs atcs; 1979 struct mutex srbm_mutex; 1980 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1981 struct mutex grbm_idx_mutex; 1982 struct dev_pm_domain vga_pm_domain; 1983 bool have_disp_power_ref; 1984 1985 /* BIOS */ 1986 uint8_t *bios; 1987 bool is_atom_bios; 1988 uint16_t bios_header_start; 1989 struct amdgpu_bo *stollen_vga_memory; 1990 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1991 1992 /* Register/doorbell mmio */ 1993 resource_size_t rmmio_base; 1994 resource_size_t rmmio_size; 1995 void __iomem *rmmio; 1996 /* protects concurrent MM_INDEX/DATA based register access */ 1997 spinlock_t mmio_idx_lock; 1998 /* protects concurrent SMC based register access */ 1999 spinlock_t smc_idx_lock; 2000 amdgpu_rreg_t smc_rreg; 2001 amdgpu_wreg_t smc_wreg; 2002 /* protects concurrent PCIE register access */ 2003 spinlock_t pcie_idx_lock; 2004 amdgpu_rreg_t pcie_rreg; 2005 amdgpu_wreg_t pcie_wreg; 2006 /* protects concurrent UVD register access */ 2007 spinlock_t uvd_ctx_idx_lock; 2008 amdgpu_rreg_t uvd_ctx_rreg; 2009 amdgpu_wreg_t uvd_ctx_wreg; 2010 /* protects concurrent DIDT register access */ 2011 spinlock_t didt_idx_lock; 2012 amdgpu_rreg_t didt_rreg; 2013 amdgpu_wreg_t didt_wreg; 2014 /* protects concurrent ENDPOINT (audio) register access */ 2015 spinlock_t audio_endpt_idx_lock; 2016 amdgpu_block_rreg_t audio_endpt_rreg; 2017 amdgpu_block_wreg_t audio_endpt_wreg; 2018 void __iomem *rio_mem; 2019 resource_size_t rio_mem_size; 2020 struct amdgpu_doorbell doorbell; 2021 2022 /* clock/pll info */ 2023 struct amdgpu_clock clock; 2024 2025 /* MC */ 2026 struct amdgpu_mc mc; 2027 struct amdgpu_gart gart; 2028 struct amdgpu_dummy_page dummy_page; 2029 struct amdgpu_vm_manager vm_manager; 2030 2031 /* memory management */ 2032 struct amdgpu_mman mman; 2033 struct amdgpu_gem gem; 2034 struct amdgpu_vram_scratch vram_scratch; 2035 struct amdgpu_wb wb; 2036 atomic64_t vram_usage; 2037 atomic64_t vram_vis_usage; 2038 atomic64_t gtt_usage; 2039 atomic64_t num_bytes_moved; 2040 atomic_t gpu_reset_counter; 2041 2042 /* display */ 2043 struct amdgpu_mode_info mode_info; 2044 struct work_struct hotplug_work; 2045 struct amdgpu_irq_src crtc_irq; 2046 struct amdgpu_irq_src pageflip_irq; 2047 struct amdgpu_irq_src hpd_irq; 2048 2049 /* rings */ 2050 unsigned fence_context; 2051 struct mutex ring_lock; 2052 unsigned num_rings; 2053 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 2054 bool ib_pool_ready; 2055 struct amdgpu_sa_manager ring_tmp_bo; 2056 2057 /* interrupts */ 2058 struct amdgpu_irq irq; 2059 2060 /* dpm */ 2061 struct amdgpu_pm pm; 2062 u32 cg_flags; 2063 u32 pg_flags; 2064 2065 /* amdgpu smumgr */ 2066 struct amdgpu_smumgr smu; 2067 2068 /* gfx */ 2069 struct amdgpu_gfx gfx; 2070 2071 /* sdma */ 2072 struct amdgpu_sdma sdma; 2073 2074 /* uvd */ 2075 bool has_uvd; 2076 struct amdgpu_uvd uvd; 2077 2078 /* vce */ 2079 struct amdgpu_vce vce; 2080 2081 /* firmwares */ 2082 struct amdgpu_firmware firmware; 2083 2084 /* GDS */ 2085 struct amdgpu_gds gds; 2086 2087 const struct amdgpu_ip_block_version *ip_blocks; 2088 int num_ip_blocks; 2089 struct amdgpu_ip_block_status *ip_block_status; 2090 struct mutex mn_lock; 2091 DECLARE_HASHTABLE(mn_hash, 7); 2092 2093 /* tracking pinned memory */ 2094 u64 vram_pin_size; 2095 u64 gart_pin_size; 2096 2097 /* amdkfd interface */ 2098 struct kfd_dev *kfd; 2099 2100 /* kernel conext for IB submission */ 2101 struct amdgpu_ctx kernel_ctx; 2102 }; 2103 2104 bool amdgpu_device_is_px(struct drm_device *dev); 2105 int amdgpu_device_init(struct amdgpu_device *adev, 2106 struct drm_device *ddev, 2107 struct pci_dev *pdev, 2108 uint32_t flags); 2109 void amdgpu_device_fini(struct amdgpu_device *adev); 2110 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2111 2112 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2113 bool always_indirect); 2114 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2115 bool always_indirect); 2116 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2117 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2118 2119 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2120 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2121 2122 /* 2123 * Cast helper 2124 */ 2125 extern const struct fence_ops amdgpu_fence_ops; 2126 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) 2127 { 2128 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 2129 2130 if (__f->base.ops == &amdgpu_fence_ops) 2131 return __f; 2132 2133 return NULL; 2134 } 2135 2136 /* 2137 * Registers read & write functions. 2138 */ 2139 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2140 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2141 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2142 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2143 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2144 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2145 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2146 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2147 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2148 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2149 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2150 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2151 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2152 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2153 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2154 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2155 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2156 #define WREG32_P(reg, val, mask) \ 2157 do { \ 2158 uint32_t tmp_ = RREG32(reg); \ 2159 tmp_ &= (mask); \ 2160 tmp_ |= ((val) & ~(mask)); \ 2161 WREG32(reg, tmp_); \ 2162 } while (0) 2163 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2164 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2165 #define WREG32_PLL_P(reg, val, mask) \ 2166 do { \ 2167 uint32_t tmp_ = RREG32_PLL(reg); \ 2168 tmp_ &= (mask); \ 2169 tmp_ |= ((val) & ~(mask)); \ 2170 WREG32_PLL(reg, tmp_); \ 2171 } while (0) 2172 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2173 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2174 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2175 2176 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2177 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2178 2179 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2180 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2181 2182 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2183 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2184 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2185 2186 #define REG_GET_FIELD(value, reg, field) \ 2187 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2188 2189 /* 2190 * BIOS helpers. 2191 */ 2192 #define RBIOS8(i) (adev->bios[i]) 2193 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2194 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2195 2196 /* 2197 * RING helpers. 2198 */ 2199 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2200 { 2201 if (ring->count_dw <= 0) 2202 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2203 ring->ring[ring->wptr++] = v; 2204 ring->wptr &= ring->ptr_mask; 2205 ring->count_dw--; 2206 ring->ring_free_dw--; 2207 } 2208 2209 static inline struct amdgpu_sdma_instance * 2210 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 2211 { 2212 struct amdgpu_device *adev = ring->adev; 2213 int i; 2214 2215 for (i = 0; i < adev->sdma.num_instances; i++) 2216 if (&adev->sdma.instance[i].ring == ring) 2217 break; 2218 2219 if (i < AMDGPU_MAX_SDMA_INSTANCES) 2220 return &adev->sdma.instance[i]; 2221 else 2222 return NULL; 2223 } 2224 2225 /* 2226 * ASICs macro. 2227 */ 2228 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2229 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2230 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) 2231 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2232 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2233 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2234 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2235 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2236 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2237 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) 2238 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2239 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2240 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2241 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags))) 2242 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2243 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib))) 2244 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2245 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2246 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2247 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2248 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2249 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2250 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) 2251 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2252 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2253 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) 2254 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2255 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2256 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2257 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2258 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2259 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2260 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2261 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2262 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2263 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2264 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2265 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2266 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2267 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2268 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2269 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) 2270 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2271 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2272 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2273 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2274 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2275 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 2276 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 2277 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev)) 2278 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2279 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2280 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2281 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2282 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l)) 2283 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l)) 2284 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2285 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)) 2286 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l)) 2287 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2288 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g)) 2289 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g)) 2290 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2291 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m)) 2292 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev)) 2293 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s)) 2294 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s)) 2295 2296 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2297 2298 /* Common functions */ 2299 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2300 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2301 bool amdgpu_card_posted(struct amdgpu_device *adev); 2302 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2303 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev); 2304 2305 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2306 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2307 u32 ip_instance, u32 ring, 2308 struct amdgpu_ring **out_ring); 2309 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2310 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2311 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2312 uint32_t flags); 2313 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2314 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2315 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2316 struct ttm_mem_reg *mem); 2317 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2318 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2319 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2320 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2321 const u32 *registers, 2322 const u32 array_size); 2323 2324 bool amdgpu_device_is_px(struct drm_device *dev); 2325 /* atpx handler */ 2326 #if defined(CONFIG_VGA_SWITCHEROO) 2327 void amdgpu_register_atpx_handler(void); 2328 void amdgpu_unregister_atpx_handler(void); 2329 #else 2330 static inline void amdgpu_register_atpx_handler(void) {} 2331 static inline void amdgpu_unregister_atpx_handler(void) {} 2332 #endif 2333 2334 /* 2335 * KMS 2336 */ 2337 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2338 extern int amdgpu_max_kms_ioctl; 2339 2340 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2341 int amdgpu_driver_unload_kms(struct drm_device *dev); 2342 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2343 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2344 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2345 struct drm_file *file_priv); 2346 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2347 struct drm_file *file_priv); 2348 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2349 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2350 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 2351 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2352 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2353 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 2354 int *max_error, 2355 struct timeval *vblank_time, 2356 unsigned flags); 2357 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2358 unsigned long arg); 2359 2360 /* 2361 * functions used by amdgpu_encoder.c 2362 */ 2363 struct amdgpu_afmt_acr { 2364 u32 clock; 2365 2366 int n_32khz; 2367 int cts_32khz; 2368 2369 int n_44_1khz; 2370 int cts_44_1khz; 2371 2372 int n_48khz; 2373 int cts_48khz; 2374 2375 }; 2376 2377 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2378 2379 /* amdgpu_acpi.c */ 2380 #if defined(CONFIG_ACPI) 2381 int amdgpu_acpi_init(struct amdgpu_device *adev); 2382 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2383 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2384 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2385 u8 perf_req, bool advertise); 2386 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2387 #else 2388 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2389 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2390 #endif 2391 2392 struct amdgpu_bo_va_mapping * 2393 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2394 uint64_t addr, struct amdgpu_bo **bo); 2395 2396 #include "amdgpu_object.h" 2397 2398 #endif 2399