1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/rbtree.h> 36 #include <linux/hashtable.h> 37 #include <linux/dma-fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_ttm.h" 55 #include "amdgpu_psp.h" 56 #include "amdgpu_gds.h" 57 #include "amdgpu_sync.h" 58 #include "amdgpu_ring.h" 59 #include "amdgpu_vm.h" 60 #include "amd_powerplay.h" 61 #include "amdgpu_dpm.h" 62 #include "amdgpu_acp.h" 63 #include "amdgpu_uvd.h" 64 #include "amdgpu_vce.h" 65 #include "amdgpu_vcn.h" 66 67 #include "gpu_scheduler.h" 68 #include "amdgpu_virt.h" 69 70 /* 71 * Modules parameters. 72 */ 73 extern int amdgpu_modeset; 74 extern int amdgpu_vram_limit; 75 extern int amdgpu_gart_size; 76 extern int amdgpu_moverate; 77 extern int amdgpu_benchmarking; 78 extern int amdgpu_testing; 79 extern int amdgpu_audio; 80 extern int amdgpu_disp_priority; 81 extern int amdgpu_hw_i2c; 82 extern int amdgpu_pcie_gen2; 83 extern int amdgpu_msi; 84 extern int amdgpu_lockup_timeout; 85 extern int amdgpu_dpm; 86 extern int amdgpu_fw_load_type; 87 extern int amdgpu_aspm; 88 extern int amdgpu_runtime_pm; 89 extern unsigned amdgpu_ip_block_mask; 90 extern int amdgpu_bapm; 91 extern int amdgpu_deep_color; 92 extern int amdgpu_vm_size; 93 extern int amdgpu_vm_block_size; 94 extern int amdgpu_vm_fault_stop; 95 extern int amdgpu_vm_debug; 96 extern int amdgpu_sched_jobs; 97 extern int amdgpu_sched_hw_submission; 98 extern int amdgpu_no_evict; 99 extern int amdgpu_direct_gma_size; 100 extern unsigned amdgpu_pcie_gen_cap; 101 extern unsigned amdgpu_pcie_lane_cap; 102 extern unsigned amdgpu_cg_mask; 103 extern unsigned amdgpu_pg_mask; 104 extern char *amdgpu_disable_cu; 105 extern char *amdgpu_virtual_display; 106 extern unsigned amdgpu_pp_feature_mask; 107 extern int amdgpu_vram_page_split; 108 extern int amdgpu_ngg; 109 extern int amdgpu_prim_buf_per_se; 110 extern int amdgpu_pos_buf_per_se; 111 extern int amdgpu_cntl_sb_buf_per_se; 112 extern int amdgpu_param_buf_per_se; 113 extern int amdgpu_job_hang_limit; 114 115 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 116 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 117 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 118 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 119 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 120 #define AMDGPU_IB_POOL_SIZE 16 121 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 122 #define AMDGPUFB_CONN_LIMIT 4 123 #define AMDGPU_BIOS_NUM_SCRATCH 16 124 125 /* max number of IP instances */ 126 #define AMDGPU_MAX_SDMA_INSTANCES 2 127 128 /* hard reset data */ 129 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 130 131 /* reset flags */ 132 #define AMDGPU_RESET_GFX (1 << 0) 133 #define AMDGPU_RESET_COMPUTE (1 << 1) 134 #define AMDGPU_RESET_DMA (1 << 2) 135 #define AMDGPU_RESET_CP (1 << 3) 136 #define AMDGPU_RESET_GRBM (1 << 4) 137 #define AMDGPU_RESET_DMA1 (1 << 5) 138 #define AMDGPU_RESET_RLC (1 << 6) 139 #define AMDGPU_RESET_SEM (1 << 7) 140 #define AMDGPU_RESET_IH (1 << 8) 141 #define AMDGPU_RESET_VMC (1 << 9) 142 #define AMDGPU_RESET_MC (1 << 10) 143 #define AMDGPU_RESET_DISPLAY (1 << 11) 144 #define AMDGPU_RESET_UVD (1 << 12) 145 #define AMDGPU_RESET_VCE (1 << 13) 146 #define AMDGPU_RESET_VCE1 (1 << 14) 147 148 /* GFX current status */ 149 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 150 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 151 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 152 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 153 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 154 155 /* max cursor sizes (in pixels) */ 156 #define CIK_CURSOR_WIDTH 128 157 #define CIK_CURSOR_HEIGHT 128 158 159 struct amdgpu_device; 160 struct amdgpu_ib; 161 struct amdgpu_cs_parser; 162 struct amdgpu_job; 163 struct amdgpu_irq_src; 164 struct amdgpu_fpriv; 165 166 enum amdgpu_cp_irq { 167 AMDGPU_CP_IRQ_GFX_EOP = 0, 168 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 169 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 170 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 171 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 172 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 173 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 174 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 175 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 176 177 AMDGPU_CP_IRQ_LAST 178 }; 179 180 enum amdgpu_sdma_irq { 181 AMDGPU_SDMA_IRQ_TRAP0 = 0, 182 AMDGPU_SDMA_IRQ_TRAP1, 183 184 AMDGPU_SDMA_IRQ_LAST 185 }; 186 187 enum amdgpu_thermal_irq { 188 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 189 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 190 191 AMDGPU_THERMAL_IRQ_LAST 192 }; 193 194 enum amdgpu_kiq_irq { 195 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 196 AMDGPU_CP_KIQ_IRQ_LAST 197 }; 198 199 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 200 enum amd_ip_block_type block_type, 201 enum amd_clockgating_state state); 202 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 203 enum amd_ip_block_type block_type, 204 enum amd_powergating_state state); 205 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); 206 int amdgpu_wait_for_idle(struct amdgpu_device *adev, 207 enum amd_ip_block_type block_type); 208 bool amdgpu_is_idle(struct amdgpu_device *adev, 209 enum amd_ip_block_type block_type); 210 211 #define AMDGPU_MAX_IP_NUM 16 212 213 struct amdgpu_ip_block_status { 214 bool valid; 215 bool sw; 216 bool hw; 217 bool late_initialized; 218 bool hang; 219 }; 220 221 struct amdgpu_ip_block_version { 222 const enum amd_ip_block_type type; 223 const u32 major; 224 const u32 minor; 225 const u32 rev; 226 const struct amd_ip_funcs *funcs; 227 }; 228 229 struct amdgpu_ip_block { 230 struct amdgpu_ip_block_status status; 231 const struct amdgpu_ip_block_version *version; 232 }; 233 234 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 235 enum amd_ip_block_type type, 236 u32 major, u32 minor); 237 238 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 239 enum amd_ip_block_type type); 240 241 int amdgpu_ip_block_add(struct amdgpu_device *adev, 242 const struct amdgpu_ip_block_version *ip_block_version); 243 244 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 245 struct amdgpu_buffer_funcs { 246 /* maximum bytes in a single operation */ 247 uint32_t copy_max_bytes; 248 249 /* number of dw to reserve per operation */ 250 unsigned copy_num_dw; 251 252 /* used for buffer migration */ 253 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 254 /* src addr in bytes */ 255 uint64_t src_offset, 256 /* dst addr in bytes */ 257 uint64_t dst_offset, 258 /* number of byte to transfer */ 259 uint32_t byte_count); 260 261 /* maximum bytes in a single operation */ 262 uint32_t fill_max_bytes; 263 264 /* number of dw to reserve per operation */ 265 unsigned fill_num_dw; 266 267 /* used for buffer clearing */ 268 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 269 /* value to write to memory */ 270 uint32_t src_data, 271 /* dst addr in bytes */ 272 uint64_t dst_offset, 273 /* number of byte to fill */ 274 uint32_t byte_count); 275 }; 276 277 /* provided by hw blocks that can write ptes, e.g., sdma */ 278 struct amdgpu_vm_pte_funcs { 279 /* copy pte entries from GART */ 280 void (*copy_pte)(struct amdgpu_ib *ib, 281 uint64_t pe, uint64_t src, 282 unsigned count); 283 /* write pte one entry at a time with addr mapping */ 284 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 285 uint64_t value, unsigned count, 286 uint32_t incr); 287 /* for linear pte/pde updates without addr mapping */ 288 void (*set_pte_pde)(struct amdgpu_ib *ib, 289 uint64_t pe, 290 uint64_t addr, unsigned count, 291 uint32_t incr, uint64_t flags); 292 }; 293 294 /* provided by the gmc block */ 295 struct amdgpu_gart_funcs { 296 /* flush the vm tlb via mmio */ 297 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 298 uint32_t vmid); 299 /* write pte/pde updates using the cpu */ 300 int (*set_pte_pde)(struct amdgpu_device *adev, 301 void *cpu_pt_addr, /* cpu addr of page table */ 302 uint32_t gpu_page_idx, /* pte/pde to update */ 303 uint64_t addr, /* addr to write into pte/pde */ 304 uint64_t flags); /* access flags */ 305 /* enable/disable PRT support */ 306 void (*set_prt)(struct amdgpu_device *adev, bool enable); 307 /* set pte flags based per asic */ 308 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, 309 uint32_t flags); 310 /* adjust mc addr in fb for APU case */ 311 u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr); 312 uint32_t (*get_invalidate_req)(unsigned int vm_id); 313 }; 314 315 /* provided by the ih block */ 316 struct amdgpu_ih_funcs { 317 /* ring read/write ptr handling, called from interrupt context */ 318 u32 (*get_wptr)(struct amdgpu_device *adev); 319 void (*decode_iv)(struct amdgpu_device *adev, 320 struct amdgpu_iv_entry *entry); 321 void (*set_rptr)(struct amdgpu_device *adev); 322 }; 323 324 /* 325 * BIOS. 326 */ 327 bool amdgpu_get_bios(struct amdgpu_device *adev); 328 bool amdgpu_read_bios(struct amdgpu_device *adev); 329 330 /* 331 * Dummy page 332 */ 333 struct amdgpu_dummy_page { 334 struct page *page; 335 dma_addr_t addr; 336 }; 337 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 338 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 339 340 341 /* 342 * Clocks 343 */ 344 345 #define AMDGPU_MAX_PPLL 3 346 347 struct amdgpu_clock { 348 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 349 struct amdgpu_pll spll; 350 struct amdgpu_pll mpll; 351 /* 10 Khz units */ 352 uint32_t default_mclk; 353 uint32_t default_sclk; 354 uint32_t default_dispclk; 355 uint32_t current_dispclk; 356 uint32_t dp_extclk; 357 uint32_t max_pixel_clock; 358 }; 359 360 /* 361 * BO. 362 */ 363 struct amdgpu_bo_list_entry { 364 struct amdgpu_bo *robj; 365 struct ttm_validate_buffer tv; 366 struct amdgpu_bo_va *bo_va; 367 uint32_t priority; 368 struct page **user_pages; 369 int user_invalidated; 370 }; 371 372 struct amdgpu_bo_va_mapping { 373 struct list_head list; 374 struct rb_node rb; 375 uint64_t start; 376 uint64_t last; 377 uint64_t __subtree_last; 378 uint64_t offset; 379 uint64_t flags; 380 }; 381 382 /* bo virtual addresses in a specific vm */ 383 struct amdgpu_bo_va { 384 /* protected by bo being reserved */ 385 struct list_head bo_list; 386 struct dma_fence *last_pt_update; 387 unsigned ref_count; 388 389 /* protected by vm mutex and spinlock */ 390 struct list_head vm_status; 391 392 /* mappings for this bo_va */ 393 struct list_head invalids; 394 struct list_head valids; 395 396 /* constant after initialization */ 397 struct amdgpu_vm *vm; 398 struct amdgpu_bo *bo; 399 }; 400 401 #define AMDGPU_GEM_DOMAIN_MAX 0x3 402 403 struct amdgpu_bo { 404 /* Protected by tbo.reserved */ 405 u32 prefered_domains; 406 u32 allowed_domains; 407 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 408 struct ttm_placement placement; 409 struct ttm_buffer_object tbo; 410 struct ttm_bo_kmap_obj kmap; 411 u64 flags; 412 unsigned pin_count; 413 void *kptr; 414 u64 tiling_flags; 415 u64 metadata_flags; 416 void *metadata; 417 u32 metadata_size; 418 unsigned prime_shared_count; 419 /* list of all virtual address to which this bo 420 * is associated to 421 */ 422 struct list_head va; 423 /* Constant after initialization */ 424 struct drm_gem_object gem_base; 425 struct amdgpu_bo *parent; 426 struct amdgpu_bo *shadow; 427 428 struct ttm_bo_kmap_obj dma_buf_vmap; 429 struct amdgpu_mn *mn; 430 struct list_head mn_list; 431 struct list_head shadow_list; 432 }; 433 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 434 435 void amdgpu_gem_object_free(struct drm_gem_object *obj); 436 int amdgpu_gem_object_open(struct drm_gem_object *obj, 437 struct drm_file *file_priv); 438 void amdgpu_gem_object_close(struct drm_gem_object *obj, 439 struct drm_file *file_priv); 440 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 441 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 442 struct drm_gem_object * 443 amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 444 struct dma_buf_attachment *attach, 445 struct sg_table *sg); 446 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 447 struct drm_gem_object *gobj, 448 int flags); 449 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 450 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 451 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 452 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 453 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 454 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 455 456 /* sub-allocation manager, it has to be protected by another lock. 457 * By conception this is an helper for other part of the driver 458 * like the indirect buffer or semaphore, which both have their 459 * locking. 460 * 461 * Principe is simple, we keep a list of sub allocation in offset 462 * order (first entry has offset == 0, last entry has the highest 463 * offset). 464 * 465 * When allocating new object we first check if there is room at 466 * the end total_size - (last_object_offset + last_object_size) >= 467 * alloc_size. If so we allocate new object there. 468 * 469 * When there is not enough room at the end, we start waiting for 470 * each sub object until we reach object_offset+object_size >= 471 * alloc_size, this object then become the sub object we return. 472 * 473 * Alignment can't be bigger than page size. 474 * 475 * Hole are not considered for allocation to keep things simple. 476 * Assumption is that there won't be hole (all object on same 477 * alignment). 478 */ 479 480 #define AMDGPU_SA_NUM_FENCE_LISTS 32 481 482 struct amdgpu_sa_manager { 483 wait_queue_head_t wq; 484 struct amdgpu_bo *bo; 485 struct list_head *hole; 486 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 487 struct list_head olist; 488 unsigned size; 489 uint64_t gpu_addr; 490 void *cpu_ptr; 491 uint32_t domain; 492 uint32_t align; 493 }; 494 495 /* sub-allocation buffer */ 496 struct amdgpu_sa_bo { 497 struct list_head olist; 498 struct list_head flist; 499 struct amdgpu_sa_manager *manager; 500 unsigned soffset; 501 unsigned eoffset; 502 struct dma_fence *fence; 503 }; 504 505 /* 506 * GEM objects. 507 */ 508 void amdgpu_gem_force_release(struct amdgpu_device *adev); 509 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 510 int alignment, u32 initial_domain, 511 u64 flags, bool kernel, 512 struct drm_gem_object **obj); 513 514 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 515 struct drm_device *dev, 516 struct drm_mode_create_dumb *args); 517 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 518 struct drm_device *dev, 519 uint32_t handle, uint64_t *offset_p); 520 int amdgpu_fence_slab_init(void); 521 void amdgpu_fence_slab_fini(void); 522 523 /* 524 * GART structures, functions & helpers 525 */ 526 struct amdgpu_mc; 527 528 #define AMDGPU_GPU_PAGE_SIZE 4096 529 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 530 #define AMDGPU_GPU_PAGE_SHIFT 12 531 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 532 533 struct amdgpu_gart { 534 dma_addr_t table_addr; 535 struct amdgpu_bo *robj; 536 void *ptr; 537 unsigned num_gpu_pages; 538 unsigned num_cpu_pages; 539 unsigned table_size; 540 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 541 struct page **pages; 542 #endif 543 bool ready; 544 545 /* Asic default pte flags */ 546 uint64_t gart_pte_flags; 547 548 const struct amdgpu_gart_funcs *gart_funcs; 549 }; 550 551 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 552 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 553 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 554 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 555 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 556 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 557 int amdgpu_gart_init(struct amdgpu_device *adev); 558 void amdgpu_gart_fini(struct amdgpu_device *adev); 559 int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 560 int pages); 561 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 562 int pages, struct page **pagelist, 563 dma_addr_t *dma_addr, uint64_t flags); 564 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev); 565 566 /* 567 * VMHUB structures, functions & helpers 568 */ 569 struct amdgpu_vmhub { 570 uint32_t ctx0_ptb_addr_lo32; 571 uint32_t ctx0_ptb_addr_hi32; 572 uint32_t vm_inv_eng0_req; 573 uint32_t vm_inv_eng0_ack; 574 uint32_t vm_context0_cntl; 575 uint32_t vm_l2_pro_fault_status; 576 uint32_t vm_l2_pro_fault_cntl; 577 }; 578 579 /* 580 * GPU MC structures, functions & helpers 581 */ 582 struct amdgpu_mc { 583 resource_size_t aper_size; 584 resource_size_t aper_base; 585 resource_size_t agp_base; 586 /* for some chips with <= 32MB we need to lie 587 * about vram size near mc fb location */ 588 u64 mc_vram_size; 589 u64 visible_vram_size; 590 u64 gtt_size; 591 u64 gtt_start; 592 u64 gtt_end; 593 u64 vram_start; 594 u64 vram_end; 595 unsigned vram_width; 596 u64 real_vram_size; 597 int vram_mtrr; 598 u64 gtt_base_align; 599 u64 mc_mask; 600 const struct firmware *fw; /* MC firmware */ 601 uint32_t fw_version; 602 struct amdgpu_irq_src vm_fault; 603 uint32_t vram_type; 604 uint32_t srbm_soft_reset; 605 struct amdgpu_mode_mc_save save; 606 bool prt_warning; 607 /* apertures */ 608 u64 shared_aperture_start; 609 u64 shared_aperture_end; 610 u64 private_aperture_start; 611 u64 private_aperture_end; 612 /* protects concurrent invalidation */ 613 spinlock_t invalidate_lock; 614 }; 615 616 /* 617 * GPU doorbell structures, functions & helpers 618 */ 619 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 620 { 621 AMDGPU_DOORBELL_KIQ = 0x000, 622 AMDGPU_DOORBELL_HIQ = 0x001, 623 AMDGPU_DOORBELL_DIQ = 0x002, 624 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 625 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 626 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 627 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 628 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 629 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 630 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 631 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 632 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 633 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 634 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 635 AMDGPU_DOORBELL_IH = 0x1E8, 636 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 637 AMDGPU_DOORBELL_INVALID = 0xFFFF 638 } AMDGPU_DOORBELL_ASSIGNMENT; 639 640 struct amdgpu_doorbell { 641 /* doorbell mmio */ 642 resource_size_t base; 643 resource_size_t size; 644 u32 __iomem *ptr; 645 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 646 }; 647 648 /* 649 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 650 */ 651 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 652 { 653 /* 654 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 655 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 656 * Compute related doorbells are allocated from 0x00 to 0x8a 657 */ 658 659 660 /* kernel scheduling */ 661 AMDGPU_DOORBELL64_KIQ = 0x00, 662 663 /* HSA interface queue and debug queue */ 664 AMDGPU_DOORBELL64_HIQ = 0x01, 665 AMDGPU_DOORBELL64_DIQ = 0x02, 666 667 /* Compute engines */ 668 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 669 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 670 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 671 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 672 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 673 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 674 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 675 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 676 677 /* User queue doorbell range (128 doorbells) */ 678 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 679 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 680 681 /* Graphics engine */ 682 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 683 684 /* 685 * Other graphics doorbells can be allocated here: from 0x8c to 0xef 686 * Graphics voltage island aperture 1 687 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive 688 */ 689 690 /* sDMA engines */ 691 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 692 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 693 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 694 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 695 696 /* Interrupt handler */ 697 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 698 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 699 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 700 701 /* VCN engine use 32 bits doorbell */ 702 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 703 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 704 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 705 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 706 707 /* overlap the doorbell assignment with VCN as they are mutually exclusive 708 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 709 */ 710 AMDGPU_DOORBELL64_RING0_1 = 0xF8, 711 AMDGPU_DOORBELL64_RING2_3 = 0xF9, 712 AMDGPU_DOORBELL64_RING4_5 = 0xFA, 713 AMDGPU_DOORBELL64_RING6_7 = 0xFB, 714 715 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC, 716 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD, 717 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE, 718 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF, 719 720 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 721 AMDGPU_DOORBELL64_INVALID = 0xFFFF 722 } AMDGPU_DOORBELL64_ASSIGNMENT; 723 724 725 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 726 phys_addr_t *aperture_base, 727 size_t *aperture_size, 728 size_t *start_offset); 729 730 /* 731 * IRQS. 732 */ 733 734 struct amdgpu_flip_work { 735 struct delayed_work flip_work; 736 struct work_struct unpin_work; 737 struct amdgpu_device *adev; 738 int crtc_id; 739 u32 target_vblank; 740 uint64_t base; 741 struct drm_pending_vblank_event *event; 742 struct amdgpu_bo *old_abo; 743 struct dma_fence *excl; 744 unsigned shared_count; 745 struct dma_fence **shared; 746 struct dma_fence_cb cb; 747 bool async; 748 }; 749 750 751 /* 752 * CP & rings. 753 */ 754 755 struct amdgpu_ib { 756 struct amdgpu_sa_bo *sa_bo; 757 uint32_t length_dw; 758 uint64_t gpu_addr; 759 uint32_t *ptr; 760 uint32_t flags; 761 }; 762 763 extern const struct amd_sched_backend_ops amdgpu_sched_ops; 764 765 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 766 struct amdgpu_job **job, struct amdgpu_vm *vm); 767 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 768 struct amdgpu_job **job); 769 770 void amdgpu_job_free_resources(struct amdgpu_job *job); 771 void amdgpu_job_free(struct amdgpu_job *job); 772 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 773 struct amd_sched_entity *entity, void *owner, 774 struct dma_fence **f); 775 776 /* 777 * context related structures 778 */ 779 780 struct amdgpu_ctx_ring { 781 uint64_t sequence; 782 struct dma_fence **fences; 783 struct amd_sched_entity entity; 784 }; 785 786 struct amdgpu_ctx { 787 struct kref refcount; 788 struct amdgpu_device *adev; 789 unsigned reset_counter; 790 spinlock_t ring_lock; 791 struct dma_fence **fences; 792 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 793 bool preamble_presented; 794 }; 795 796 struct amdgpu_ctx_mgr { 797 struct amdgpu_device *adev; 798 struct mutex lock; 799 /* protected by lock */ 800 struct idr ctx_handles; 801 }; 802 803 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 804 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 805 806 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 807 struct dma_fence *fence); 808 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 809 struct amdgpu_ring *ring, uint64_t seq); 810 811 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 812 struct drm_file *filp); 813 814 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 815 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 816 817 /* 818 * file private structure 819 */ 820 821 struct amdgpu_fpriv { 822 struct amdgpu_vm vm; 823 struct amdgpu_bo_va *prt_va; 824 struct mutex bo_list_lock; 825 struct idr bo_list_handles; 826 struct amdgpu_ctx_mgr ctx_mgr; 827 }; 828 829 /* 830 * residency list 831 */ 832 833 struct amdgpu_bo_list { 834 struct mutex lock; 835 struct amdgpu_bo *gds_obj; 836 struct amdgpu_bo *gws_obj; 837 struct amdgpu_bo *oa_obj; 838 unsigned first_userptr; 839 unsigned num_entries; 840 struct amdgpu_bo_list_entry *array; 841 }; 842 843 struct amdgpu_bo_list * 844 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 845 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 846 struct list_head *validated); 847 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 848 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 849 850 /* 851 * GFX stuff 852 */ 853 #include "clearstate_defs.h" 854 855 struct amdgpu_rlc_funcs { 856 void (*enter_safe_mode)(struct amdgpu_device *adev); 857 void (*exit_safe_mode)(struct amdgpu_device *adev); 858 }; 859 860 struct amdgpu_rlc { 861 /* for power gating */ 862 struct amdgpu_bo *save_restore_obj; 863 uint64_t save_restore_gpu_addr; 864 volatile uint32_t *sr_ptr; 865 const u32 *reg_list; 866 u32 reg_list_size; 867 /* for clear state */ 868 struct amdgpu_bo *clear_state_obj; 869 uint64_t clear_state_gpu_addr; 870 volatile uint32_t *cs_ptr; 871 const struct cs_section_def *cs_data; 872 u32 clear_state_size; 873 /* for cp tables */ 874 struct amdgpu_bo *cp_table_obj; 875 uint64_t cp_table_gpu_addr; 876 volatile uint32_t *cp_table_ptr; 877 u32 cp_table_size; 878 879 /* safe mode for updating CG/PG state */ 880 bool in_safe_mode; 881 const struct amdgpu_rlc_funcs *funcs; 882 883 /* for firmware data */ 884 u32 save_and_restore_offset; 885 u32 clear_state_descriptor_offset; 886 u32 avail_scratch_ram_locations; 887 u32 reg_restore_list_size; 888 u32 reg_list_format_start; 889 u32 reg_list_format_separate_start; 890 u32 starting_offsets_start; 891 u32 reg_list_format_size_bytes; 892 u32 reg_list_size_bytes; 893 894 u32 *register_list_format; 895 u32 *register_restore; 896 }; 897 898 struct amdgpu_mec { 899 struct amdgpu_bo *hpd_eop_obj; 900 u64 hpd_eop_gpu_addr; 901 struct amdgpu_bo *mec_fw_obj; 902 u64 mec_fw_gpu_addr; 903 u32 num_pipe; 904 u32 num_mec; 905 u32 num_queue; 906 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 907 }; 908 909 struct amdgpu_kiq { 910 u64 eop_gpu_addr; 911 struct amdgpu_bo *eop_obj; 912 struct mutex ring_mutex; 913 struct amdgpu_ring ring; 914 struct amdgpu_irq_src irq; 915 }; 916 917 /* 918 * GPU scratch registers structures, functions & helpers 919 */ 920 struct amdgpu_scratch { 921 unsigned num_reg; 922 uint32_t reg_base; 923 uint32_t free_mask; 924 }; 925 926 /* 927 * GFX configurations 928 */ 929 #define AMDGPU_GFX_MAX_SE 4 930 #define AMDGPU_GFX_MAX_SH_PER_SE 2 931 932 struct amdgpu_rb_config { 933 uint32_t rb_backend_disable; 934 uint32_t user_rb_backend_disable; 935 uint32_t raster_config; 936 uint32_t raster_config_1; 937 }; 938 939 struct gb_addr_config { 940 uint16_t pipe_interleave_size; 941 uint8_t num_pipes; 942 uint8_t max_compress_frags; 943 uint8_t num_banks; 944 uint8_t num_se; 945 uint8_t num_rb_per_se; 946 }; 947 948 struct amdgpu_gfx_config { 949 unsigned max_shader_engines; 950 unsigned max_tile_pipes; 951 unsigned max_cu_per_sh; 952 unsigned max_sh_per_se; 953 unsigned max_backends_per_se; 954 unsigned max_texture_channel_caches; 955 unsigned max_gprs; 956 unsigned max_gs_threads; 957 unsigned max_hw_contexts; 958 unsigned sc_prim_fifo_size_frontend; 959 unsigned sc_prim_fifo_size_backend; 960 unsigned sc_hiz_tile_fifo_size; 961 unsigned sc_earlyz_tile_fifo_size; 962 963 unsigned num_tile_pipes; 964 unsigned backend_enable_mask; 965 unsigned mem_max_burst_length_bytes; 966 unsigned mem_row_size_in_kb; 967 unsigned shader_engine_tile_size; 968 unsigned num_gpus; 969 unsigned multi_gpu_tile_size; 970 unsigned mc_arb_ramcfg; 971 unsigned gb_addr_config; 972 unsigned num_rbs; 973 unsigned gs_vgt_table_depth; 974 unsigned gs_prim_buffer_depth; 975 976 uint32_t tile_mode_array[32]; 977 uint32_t macrotile_mode_array[16]; 978 979 struct gb_addr_config gb_addr_config_fields; 980 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 981 982 /* gfx configure feature */ 983 uint32_t double_offchip_lds_buf; 984 }; 985 986 struct amdgpu_cu_info { 987 uint32_t number; /* total active CU number */ 988 uint32_t ao_cu_mask; 989 uint32_t wave_front_size; 990 uint32_t bitmap[4][4]; 991 }; 992 993 struct amdgpu_gfx_funcs { 994 /* get the gpu clock counter */ 995 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 996 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 997 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); 998 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); 999 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); 1000 }; 1001 1002 struct amdgpu_ngg_buf { 1003 struct amdgpu_bo *bo; 1004 uint64_t gpu_addr; 1005 uint32_t size; 1006 uint32_t bo_size; 1007 }; 1008 1009 enum { 1010 NGG_PRIM = 0, 1011 NGG_POS, 1012 NGG_CNTL, 1013 NGG_PARAM, 1014 NGG_BUF_MAX 1015 }; 1016 1017 struct amdgpu_ngg { 1018 struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; 1019 uint32_t gds_reserve_addr; 1020 uint32_t gds_reserve_size; 1021 bool init; 1022 }; 1023 1024 struct amdgpu_gfx { 1025 struct mutex gpu_clock_mutex; 1026 struct amdgpu_gfx_config config; 1027 struct amdgpu_rlc rlc; 1028 struct amdgpu_mec mec; 1029 struct amdgpu_kiq kiq; 1030 struct amdgpu_scratch scratch; 1031 const struct firmware *me_fw; /* ME firmware */ 1032 uint32_t me_fw_version; 1033 const struct firmware *pfp_fw; /* PFP firmware */ 1034 uint32_t pfp_fw_version; 1035 const struct firmware *ce_fw; /* CE firmware */ 1036 uint32_t ce_fw_version; 1037 const struct firmware *rlc_fw; /* RLC firmware */ 1038 uint32_t rlc_fw_version; 1039 const struct firmware *mec_fw; /* MEC firmware */ 1040 uint32_t mec_fw_version; 1041 const struct firmware *mec2_fw; /* MEC2 firmware */ 1042 uint32_t mec2_fw_version; 1043 uint32_t me_feature_version; 1044 uint32_t ce_feature_version; 1045 uint32_t pfp_feature_version; 1046 uint32_t rlc_feature_version; 1047 uint32_t mec_feature_version; 1048 uint32_t mec2_feature_version; 1049 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1050 unsigned num_gfx_rings; 1051 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1052 unsigned num_compute_rings; 1053 struct amdgpu_irq_src eop_irq; 1054 struct amdgpu_irq_src priv_reg_irq; 1055 struct amdgpu_irq_src priv_inst_irq; 1056 /* gfx status */ 1057 uint32_t gfx_current_status; 1058 /* ce ram size*/ 1059 unsigned ce_ram_size; 1060 struct amdgpu_cu_info cu_info; 1061 const struct amdgpu_gfx_funcs *funcs; 1062 1063 /* reset mask */ 1064 uint32_t grbm_soft_reset; 1065 uint32_t srbm_soft_reset; 1066 bool in_reset; 1067 /* s3/s4 mask */ 1068 bool in_suspend; 1069 /* NGG */ 1070 struct amdgpu_ngg ngg; 1071 }; 1072 1073 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 1074 unsigned size, struct amdgpu_ib *ib); 1075 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 1076 struct dma_fence *f); 1077 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 1078 struct amdgpu_ib *ibs, struct amdgpu_job *job, 1079 struct dma_fence **f); 1080 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1081 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1082 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1083 1084 /* 1085 * CS. 1086 */ 1087 struct amdgpu_cs_chunk { 1088 uint32_t chunk_id; 1089 uint32_t length_dw; 1090 void *kdata; 1091 }; 1092 1093 struct amdgpu_cs_parser { 1094 struct amdgpu_device *adev; 1095 struct drm_file *filp; 1096 struct amdgpu_ctx *ctx; 1097 1098 /* chunks */ 1099 unsigned nchunks; 1100 struct amdgpu_cs_chunk *chunks; 1101 1102 /* scheduler job object */ 1103 struct amdgpu_job *job; 1104 1105 /* buffer objects */ 1106 struct ww_acquire_ctx ticket; 1107 struct amdgpu_bo_list *bo_list; 1108 struct amdgpu_bo_list_entry vm_pd; 1109 struct list_head validated; 1110 struct dma_fence *fence; 1111 uint64_t bytes_moved_threshold; 1112 uint64_t bytes_moved; 1113 struct amdgpu_bo_list_entry *evictable; 1114 1115 /* user fence */ 1116 struct amdgpu_bo_list_entry uf_entry; 1117 }; 1118 1119 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ 1120 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ 1121 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ 1122 1123 struct amdgpu_job { 1124 struct amd_sched_job base; 1125 struct amdgpu_device *adev; 1126 struct amdgpu_vm *vm; 1127 struct amdgpu_ring *ring; 1128 struct amdgpu_sync sync; 1129 struct amdgpu_sync sched_sync; 1130 struct amdgpu_ib *ibs; 1131 struct dma_fence *fence; /* the hw fence */ 1132 uint32_t preamble_status; 1133 uint32_t num_ibs; 1134 void *owner; 1135 uint64_t fence_ctx; /* the fence_context this job uses */ 1136 bool vm_needs_flush; 1137 unsigned vm_id; 1138 uint64_t vm_pd_addr; 1139 uint32_t gds_base, gds_size; 1140 uint32_t gws_base, gws_size; 1141 uint32_t oa_base, oa_size; 1142 1143 /* user fence handling */ 1144 uint64_t uf_addr; 1145 uint64_t uf_sequence; 1146 1147 }; 1148 #define to_amdgpu_job(sched_job) \ 1149 container_of((sched_job), struct amdgpu_job, base) 1150 1151 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 1152 uint32_t ib_idx, int idx) 1153 { 1154 return p->job->ibs[ib_idx].ptr[idx]; 1155 } 1156 1157 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 1158 uint32_t ib_idx, int idx, 1159 uint32_t value) 1160 { 1161 p->job->ibs[ib_idx].ptr[idx] = value; 1162 } 1163 1164 /* 1165 * Writeback 1166 */ 1167 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1168 1169 struct amdgpu_wb { 1170 struct amdgpu_bo *wb_obj; 1171 volatile uint32_t *wb; 1172 uint64_t gpu_addr; 1173 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1174 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1175 }; 1176 1177 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1178 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1179 int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb); 1180 void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb); 1181 1182 void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1183 1184 /* 1185 * SDMA 1186 */ 1187 struct amdgpu_sdma_instance { 1188 /* SDMA firmware */ 1189 const struct firmware *fw; 1190 uint32_t fw_version; 1191 uint32_t feature_version; 1192 1193 struct amdgpu_ring ring; 1194 bool burst_nop; 1195 }; 1196 1197 struct amdgpu_sdma { 1198 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1199 #ifdef CONFIG_DRM_AMDGPU_SI 1200 //SI DMA has a difference trap irq number for the second engine 1201 struct amdgpu_irq_src trap_irq_1; 1202 #endif 1203 struct amdgpu_irq_src trap_irq; 1204 struct amdgpu_irq_src illegal_inst_irq; 1205 int num_instances; 1206 uint32_t srbm_soft_reset; 1207 }; 1208 1209 /* 1210 * Firmware 1211 */ 1212 enum amdgpu_firmware_load_type { 1213 AMDGPU_FW_LOAD_DIRECT = 0, 1214 AMDGPU_FW_LOAD_SMU, 1215 AMDGPU_FW_LOAD_PSP, 1216 }; 1217 1218 struct amdgpu_firmware { 1219 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1220 enum amdgpu_firmware_load_type load_type; 1221 struct amdgpu_bo *fw_buf; 1222 unsigned int fw_size; 1223 unsigned int max_ucodes; 1224 /* firmwares are loaded by psp instead of smu from vega10 */ 1225 const struct amdgpu_psp_funcs *funcs; 1226 struct amdgpu_bo *rbuf; 1227 struct mutex mutex; 1228 }; 1229 1230 /* 1231 * Benchmarking 1232 */ 1233 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1234 1235 1236 /* 1237 * Testing 1238 */ 1239 void amdgpu_test_moves(struct amdgpu_device *adev); 1240 1241 /* 1242 * MMU Notifier 1243 */ 1244 #if defined(CONFIG_MMU_NOTIFIER) 1245 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1246 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1247 #else 1248 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1249 { 1250 return -ENODEV; 1251 } 1252 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1253 #endif 1254 1255 /* 1256 * Debugfs 1257 */ 1258 struct amdgpu_debugfs { 1259 const struct drm_info_list *files; 1260 unsigned num_files; 1261 }; 1262 1263 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1264 const struct drm_info_list *files, 1265 unsigned nfiles); 1266 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1267 1268 #if defined(CONFIG_DEBUG_FS) 1269 int amdgpu_debugfs_init(struct drm_minor *minor); 1270 #endif 1271 1272 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); 1273 1274 /* 1275 * amdgpu smumgr functions 1276 */ 1277 struct amdgpu_smumgr_funcs { 1278 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1279 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1280 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1281 }; 1282 1283 /* 1284 * amdgpu smumgr 1285 */ 1286 struct amdgpu_smumgr { 1287 struct amdgpu_bo *toc_buf; 1288 struct amdgpu_bo *smu_buf; 1289 /* asic priv smu data */ 1290 void *priv; 1291 spinlock_t smu_lock; 1292 /* smumgr functions */ 1293 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1294 /* ucode loading complete flag */ 1295 uint32_t fw_flags; 1296 }; 1297 1298 /* 1299 * ASIC specific register table accessible by UMD 1300 */ 1301 struct amdgpu_allowed_register_entry { 1302 uint32_t reg_offset; 1303 bool grbm_indexed; 1304 }; 1305 1306 /* 1307 * ASIC specific functions. 1308 */ 1309 struct amdgpu_asic_funcs { 1310 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1311 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1312 u8 *bios, u32 length_bytes); 1313 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1314 u32 sh_num, u32 reg_offset, u32 *value); 1315 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1316 int (*reset)(struct amdgpu_device *adev); 1317 /* get the reference clock */ 1318 u32 (*get_xclk)(struct amdgpu_device *adev); 1319 /* MM block clocks */ 1320 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1321 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1322 /* static power management */ 1323 int (*get_pcie_lanes)(struct amdgpu_device *adev); 1324 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 1325 /* get config memsize register */ 1326 u32 (*get_config_memsize)(struct amdgpu_device *adev); 1327 }; 1328 1329 /* 1330 * IOCTL. 1331 */ 1332 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1333 struct drm_file *filp); 1334 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1335 struct drm_file *filp); 1336 1337 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1338 struct drm_file *filp); 1339 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1340 struct drm_file *filp); 1341 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1342 struct drm_file *filp); 1343 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1344 struct drm_file *filp); 1345 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1346 struct drm_file *filp); 1347 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1348 struct drm_file *filp); 1349 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1350 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1351 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 1352 struct drm_file *filp); 1353 1354 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1355 struct drm_file *filp); 1356 1357 /* VRAM scratch page for HDP bug, default vram page */ 1358 struct amdgpu_vram_scratch { 1359 struct amdgpu_bo *robj; 1360 volatile uint32_t *ptr; 1361 u64 gpu_addr; 1362 }; 1363 1364 /* 1365 * ACPI 1366 */ 1367 struct amdgpu_atif_notification_cfg { 1368 bool enabled; 1369 int command_code; 1370 }; 1371 1372 struct amdgpu_atif_notifications { 1373 bool display_switch; 1374 bool expansion_mode_change; 1375 bool thermal_state; 1376 bool forced_power_state; 1377 bool system_power_state; 1378 bool display_conf_change; 1379 bool px_gfx_switch; 1380 bool brightness_change; 1381 bool dgpu_display_event; 1382 }; 1383 1384 struct amdgpu_atif_functions { 1385 bool system_params; 1386 bool sbios_requests; 1387 bool select_active_disp; 1388 bool lid_state; 1389 bool get_tv_standard; 1390 bool set_tv_standard; 1391 bool get_panel_expansion_mode; 1392 bool set_panel_expansion_mode; 1393 bool temperature_change; 1394 bool graphics_device_types; 1395 }; 1396 1397 struct amdgpu_atif { 1398 struct amdgpu_atif_notifications notifications; 1399 struct amdgpu_atif_functions functions; 1400 struct amdgpu_atif_notification_cfg notification_cfg; 1401 struct amdgpu_encoder *encoder_for_bl; 1402 }; 1403 1404 struct amdgpu_atcs_functions { 1405 bool get_ext_state; 1406 bool pcie_perf_req; 1407 bool pcie_dev_rdy; 1408 bool pcie_bus_width; 1409 }; 1410 1411 struct amdgpu_atcs { 1412 struct amdgpu_atcs_functions functions; 1413 }; 1414 1415 /* 1416 * CGS 1417 */ 1418 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1419 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1420 1421 /* 1422 * Core structure, functions and helpers. 1423 */ 1424 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1425 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1426 1427 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1428 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1429 1430 struct amdgpu_device { 1431 struct device *dev; 1432 struct drm_device *ddev; 1433 struct pci_dev *pdev; 1434 1435 #ifdef CONFIG_DRM_AMD_ACP 1436 struct amdgpu_acp acp; 1437 #endif 1438 1439 /* ASIC */ 1440 enum amd_asic_type asic_type; 1441 uint32_t family; 1442 uint32_t rev_id; 1443 uint32_t external_rev_id; 1444 unsigned long flags; 1445 int usec_timeout; 1446 const struct amdgpu_asic_funcs *asic_funcs; 1447 bool shutdown; 1448 bool need_dma32; 1449 bool accel_working; 1450 struct work_struct reset_work; 1451 struct notifier_block acpi_nb; 1452 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1453 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1454 unsigned debugfs_count; 1455 #if defined(CONFIG_DEBUG_FS) 1456 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1457 #endif 1458 struct amdgpu_atif atif; 1459 struct amdgpu_atcs atcs; 1460 struct mutex srbm_mutex; 1461 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1462 struct mutex grbm_idx_mutex; 1463 struct dev_pm_domain vga_pm_domain; 1464 bool have_disp_power_ref; 1465 1466 /* BIOS */ 1467 bool is_atom_fw; 1468 uint8_t *bios; 1469 uint32_t bios_size; 1470 struct amdgpu_bo *stollen_vga_memory; 1471 uint32_t bios_scratch_reg_offset; 1472 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1473 1474 /* Register/doorbell mmio */ 1475 resource_size_t rmmio_base; 1476 resource_size_t rmmio_size; 1477 void __iomem *rmmio; 1478 /* protects concurrent MM_INDEX/DATA based register access */ 1479 spinlock_t mmio_idx_lock; 1480 /* protects concurrent SMC based register access */ 1481 spinlock_t smc_idx_lock; 1482 amdgpu_rreg_t smc_rreg; 1483 amdgpu_wreg_t smc_wreg; 1484 /* protects concurrent PCIE register access */ 1485 spinlock_t pcie_idx_lock; 1486 amdgpu_rreg_t pcie_rreg; 1487 amdgpu_wreg_t pcie_wreg; 1488 amdgpu_rreg_t pciep_rreg; 1489 amdgpu_wreg_t pciep_wreg; 1490 /* protects concurrent UVD register access */ 1491 spinlock_t uvd_ctx_idx_lock; 1492 amdgpu_rreg_t uvd_ctx_rreg; 1493 amdgpu_wreg_t uvd_ctx_wreg; 1494 /* protects concurrent DIDT register access */ 1495 spinlock_t didt_idx_lock; 1496 amdgpu_rreg_t didt_rreg; 1497 amdgpu_wreg_t didt_wreg; 1498 /* protects concurrent gc_cac register access */ 1499 spinlock_t gc_cac_idx_lock; 1500 amdgpu_rreg_t gc_cac_rreg; 1501 amdgpu_wreg_t gc_cac_wreg; 1502 /* protects concurrent ENDPOINT (audio) register access */ 1503 spinlock_t audio_endpt_idx_lock; 1504 amdgpu_block_rreg_t audio_endpt_rreg; 1505 amdgpu_block_wreg_t audio_endpt_wreg; 1506 void __iomem *rio_mem; 1507 resource_size_t rio_mem_size; 1508 struct amdgpu_doorbell doorbell; 1509 1510 /* clock/pll info */ 1511 struct amdgpu_clock clock; 1512 1513 /* MC */ 1514 struct amdgpu_mc mc; 1515 struct amdgpu_gart gart; 1516 struct amdgpu_dummy_page dummy_page; 1517 struct amdgpu_vm_manager vm_manager; 1518 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 1519 1520 /* memory management */ 1521 struct amdgpu_mman mman; 1522 struct amdgpu_vram_scratch vram_scratch; 1523 struct amdgpu_wb wb; 1524 atomic64_t vram_usage; 1525 atomic64_t vram_vis_usage; 1526 atomic64_t gtt_usage; 1527 atomic64_t num_bytes_moved; 1528 atomic64_t num_evictions; 1529 atomic_t gpu_reset_counter; 1530 1531 /* data for buffer migration throttling */ 1532 struct { 1533 spinlock_t lock; 1534 s64 last_update_us; 1535 s64 accum_us; /* accumulated microseconds */ 1536 u32 log2_max_MBps; 1537 } mm_stats; 1538 1539 /* display */ 1540 bool enable_virtual_display; 1541 struct amdgpu_mode_info mode_info; 1542 struct work_struct hotplug_work; 1543 struct amdgpu_irq_src crtc_irq; 1544 struct amdgpu_irq_src pageflip_irq; 1545 struct amdgpu_irq_src hpd_irq; 1546 1547 /* rings */ 1548 u64 fence_context; 1549 unsigned num_rings; 1550 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1551 bool ib_pool_ready; 1552 struct amdgpu_sa_manager ring_tmp_bo; 1553 1554 /* interrupts */ 1555 struct amdgpu_irq irq; 1556 1557 /* powerplay */ 1558 struct amd_powerplay powerplay; 1559 bool pp_enabled; 1560 bool pp_force_state_enabled; 1561 1562 /* dpm */ 1563 struct amdgpu_pm pm; 1564 u32 cg_flags; 1565 u32 pg_flags; 1566 1567 /* amdgpu smumgr */ 1568 struct amdgpu_smumgr smu; 1569 1570 /* gfx */ 1571 struct amdgpu_gfx gfx; 1572 1573 /* sdma */ 1574 struct amdgpu_sdma sdma; 1575 1576 union { 1577 struct { 1578 /* uvd */ 1579 struct amdgpu_uvd uvd; 1580 1581 /* vce */ 1582 struct amdgpu_vce vce; 1583 }; 1584 1585 /* vcn */ 1586 struct amdgpu_vcn vcn; 1587 }; 1588 1589 /* firmwares */ 1590 struct amdgpu_firmware firmware; 1591 1592 /* PSP */ 1593 struct psp_context psp; 1594 1595 /* GDS */ 1596 struct amdgpu_gds gds; 1597 1598 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1599 int num_ip_blocks; 1600 struct mutex mn_lock; 1601 DECLARE_HASHTABLE(mn_hash, 7); 1602 1603 /* tracking pinned memory */ 1604 u64 vram_pin_size; 1605 u64 invisible_pin_size; 1606 u64 gart_pin_size; 1607 1608 /* amdkfd interface */ 1609 struct kfd_dev *kfd; 1610 1611 struct amdgpu_virt virt; 1612 1613 /* link all shadow bo */ 1614 struct list_head shadow_list; 1615 struct mutex shadow_list_lock; 1616 /* link all gtt */ 1617 spinlock_t gtt_list_lock; 1618 struct list_head gtt_list; 1619 1620 /* record hw reset is performed */ 1621 bool has_hw_reset; 1622 1623 }; 1624 1625 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1626 { 1627 return container_of(bdev, struct amdgpu_device, mman.bdev); 1628 } 1629 1630 bool amdgpu_device_is_px(struct drm_device *dev); 1631 int amdgpu_device_init(struct amdgpu_device *adev, 1632 struct drm_device *ddev, 1633 struct pci_dev *pdev, 1634 uint32_t flags); 1635 void amdgpu_device_fini(struct amdgpu_device *adev); 1636 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1637 1638 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1639 uint32_t acc_flags); 1640 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1641 uint32_t acc_flags); 1642 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1643 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1644 1645 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 1646 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1647 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 1648 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 1649 1650 /* 1651 * Registers read & write functions. 1652 */ 1653 1654 #define AMDGPU_REGS_IDX (1<<0) 1655 #define AMDGPU_REGS_NO_KIQ (1<<1) 1656 1657 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1658 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1659 1660 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1661 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1662 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1663 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1664 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1665 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1666 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1667 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1668 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1669 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1670 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1671 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1672 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1673 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1674 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1675 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1676 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1677 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1678 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1679 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1680 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1681 #define WREG32_P(reg, val, mask) \ 1682 do { \ 1683 uint32_t tmp_ = RREG32(reg); \ 1684 tmp_ &= (mask); \ 1685 tmp_ |= ((val) & ~(mask)); \ 1686 WREG32(reg, tmp_); \ 1687 } while (0) 1688 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1689 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1690 #define WREG32_PLL_P(reg, val, mask) \ 1691 do { \ 1692 uint32_t tmp_ = RREG32_PLL(reg); \ 1693 tmp_ &= (mask); \ 1694 tmp_ |= ((val) & ~(mask)); \ 1695 WREG32_PLL(reg, tmp_); \ 1696 } while (0) 1697 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1698 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1699 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1700 1701 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 1702 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1703 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 1704 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 1705 1706 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1707 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1708 1709 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1710 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1711 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1712 1713 #define REG_GET_FIELD(value, reg, field) \ 1714 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1715 1716 #define WREG32_FIELD(reg, field, val) \ 1717 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1718 1719 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1720 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1721 1722 /* 1723 * BIOS helpers. 1724 */ 1725 #define RBIOS8(i) (adev->bios[i]) 1726 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1727 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1728 1729 /* 1730 * RING helpers. 1731 */ 1732 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 1733 { 1734 if (ring->count_dw <= 0) 1735 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 1736 ring->ring[ring->wptr++ & ring->buf_mask] = v; 1737 ring->wptr &= ring->ptr_mask; 1738 ring->count_dw--; 1739 } 1740 1741 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw) 1742 { 1743 unsigned occupied, chunk1, chunk2; 1744 void *dst; 1745 1746 if (unlikely(ring->count_dw < count_dw)) { 1747 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 1748 return; 1749 } 1750 1751 occupied = ring->wptr & ring->buf_mask; 1752 dst = (void *)&ring->ring[occupied]; 1753 chunk1 = ring->buf_mask + 1 - occupied; 1754 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; 1755 chunk2 = count_dw - chunk1; 1756 chunk1 <<= 2; 1757 chunk2 <<= 2; 1758 1759 if (chunk1) 1760 memcpy(dst, src, chunk1); 1761 1762 if (chunk2) { 1763 src += chunk1; 1764 dst = (void *)ring->ring; 1765 memcpy(dst, src, chunk2); 1766 } 1767 1768 ring->wptr += count_dw; 1769 ring->wptr &= ring->ptr_mask; 1770 ring->count_dw -= count_dw; 1771 } 1772 1773 static inline struct amdgpu_sdma_instance * 1774 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 1775 { 1776 struct amdgpu_device *adev = ring->adev; 1777 int i; 1778 1779 for (i = 0; i < adev->sdma.num_instances; i++) 1780 if (&adev->sdma.instance[i].ring == ring) 1781 break; 1782 1783 if (i < AMDGPU_MAX_SDMA_INSTANCES) 1784 return &adev->sdma.instance[i]; 1785 else 1786 return NULL; 1787 } 1788 1789 /* 1790 * ASICs macro. 1791 */ 1792 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1793 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1794 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1795 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1796 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1797 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1798 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1799 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1800 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1801 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1802 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1803 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1804 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 1805 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 1806 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 1807 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 1808 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 1809 #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags)) 1810 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 1811 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 1812 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 1813 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 1814 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 1815 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 1816 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 1817 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 1818 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 1819 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 1820 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 1821 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 1822 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 1823 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 1824 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 1825 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) 1826 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 1827 #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b)) 1828 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 1829 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 1830 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 1831 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 1832 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 1833 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 1834 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 1835 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 1836 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 1837 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 1838 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 1839 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 1840 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 1841 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 1842 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 1843 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 1844 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 1845 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 1846 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 1847 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 1848 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 1849 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 1850 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 1851 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 1852 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 1853 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 1854 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) 1855 1856 /* Common functions */ 1857 int amdgpu_gpu_reset(struct amdgpu_device *adev); 1858 bool amdgpu_need_backup(struct amdgpu_device *adev); 1859 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 1860 bool amdgpu_need_post(struct amdgpu_device *adev); 1861 void amdgpu_update_display_priority(struct amdgpu_device *adev); 1862 1863 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 1864 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 1865 u32 ip_instance, u32 ring, 1866 struct amdgpu_ring **out_ring); 1867 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes); 1868 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 1869 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 1870 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 1871 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 1872 uint32_t flags); 1873 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 1874 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 1875 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1876 unsigned long end); 1877 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 1878 int *last_invalidated); 1879 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 1880 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1881 struct ttm_mem_reg *mem); 1882 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 1883 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 1884 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 1885 int amdgpu_ttm_init(struct amdgpu_device *adev); 1886 void amdgpu_ttm_fini(struct amdgpu_device *adev); 1887 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 1888 const u32 *registers, 1889 const u32 array_size); 1890 1891 bool amdgpu_device_is_px(struct drm_device *dev); 1892 /* atpx handler */ 1893 #if defined(CONFIG_VGA_SWITCHEROO) 1894 void amdgpu_register_atpx_handler(void); 1895 void amdgpu_unregister_atpx_handler(void); 1896 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1897 bool amdgpu_is_atpx_hybrid(void); 1898 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1899 bool amdgpu_has_atpx(void); 1900 #else 1901 static inline void amdgpu_register_atpx_handler(void) {} 1902 static inline void amdgpu_unregister_atpx_handler(void) {} 1903 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1904 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1905 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1906 static inline bool amdgpu_has_atpx(void) { return false; } 1907 #endif 1908 1909 /* 1910 * KMS 1911 */ 1912 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1913 extern const int amdgpu_max_kms_ioctl; 1914 1915 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1916 void amdgpu_driver_unload_kms(struct drm_device *dev); 1917 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1918 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1919 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1920 struct drm_file *file_priv); 1921 int amdgpu_suspend(struct amdgpu_device *adev); 1922 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1923 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1924 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1925 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1926 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1927 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1928 unsigned long arg); 1929 1930 /* 1931 * functions used by amdgpu_encoder.c 1932 */ 1933 struct amdgpu_afmt_acr { 1934 u32 clock; 1935 1936 int n_32khz; 1937 int cts_32khz; 1938 1939 int n_44_1khz; 1940 int cts_44_1khz; 1941 1942 int n_48khz; 1943 int cts_48khz; 1944 1945 }; 1946 1947 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1948 1949 /* amdgpu_acpi.c */ 1950 #if defined(CONFIG_ACPI) 1951 int amdgpu_acpi_init(struct amdgpu_device *adev); 1952 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1953 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1954 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1955 u8 perf_req, bool advertise); 1956 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1957 #else 1958 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1959 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1960 #endif 1961 1962 struct amdgpu_bo_va_mapping * 1963 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1964 uint64_t addr, struct amdgpu_bo **bo); 1965 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser); 1966 1967 #include "amdgpu_object.h" 1968 #endif 1969