1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 #include <drm/ttm/ttm_execbuf_util.h> 57 58 #include <drm/amdgpu_drm.h> 59 #include <drm/drm_gem.h> 60 #include <drm/drm_ioctl.h> 61 62 #include <kgd_kfd_interface.h> 63 #include "dm_pp_interface.h" 64 #include "kgd_pp_interface.h" 65 66 #include "amd_shared.h" 67 #include "amdgpu_mode.h" 68 #include "amdgpu_ih.h" 69 #include "amdgpu_irq.h" 70 #include "amdgpu_ucode.h" 71 #include "amdgpu_ttm.h" 72 #include "amdgpu_psp.h" 73 #include "amdgpu_gds.h" 74 #include "amdgpu_sync.h" 75 #include "amdgpu_ring.h" 76 #include "amdgpu_vm.h" 77 #include "amdgpu_dpm.h" 78 #include "amdgpu_acp.h" 79 #include "amdgpu_uvd.h" 80 #include "amdgpu_vce.h" 81 #include "amdgpu_vcn.h" 82 #include "amdgpu_jpeg.h" 83 #include "amdgpu_gmc.h" 84 #include "amdgpu_gfx.h" 85 #include "amdgpu_sdma.h" 86 #include "amdgpu_lsdma.h" 87 #include "amdgpu_nbio.h" 88 #include "amdgpu_hdp.h" 89 #include "amdgpu_dm.h" 90 #include "amdgpu_virt.h" 91 #include "amdgpu_csa.h" 92 #include "amdgpu_mes_ctx.h" 93 #include "amdgpu_gart.h" 94 #include "amdgpu_debugfs.h" 95 #include "amdgpu_job.h" 96 #include "amdgpu_bo_list.h" 97 #include "amdgpu_gem.h" 98 #include "amdgpu_doorbell.h" 99 #include "amdgpu_amdkfd.h" 100 #include "amdgpu_discovery.h" 101 #include "amdgpu_mes.h" 102 #include "amdgpu_umc.h" 103 #include "amdgpu_mmhub.h" 104 #include "amdgpu_gfxhub.h" 105 #include "amdgpu_df.h" 106 #include "amdgpu_smuio.h" 107 #include "amdgpu_fdinfo.h" 108 #include "amdgpu_mca.h" 109 #include "amdgpu_ras.h" 110 111 #define MAX_GPU_INSTANCE 16 112 113 struct amdgpu_gpu_instance 114 { 115 struct amdgpu_device *adev; 116 int mgpu_fan_enabled; 117 }; 118 119 struct amdgpu_mgpu_info 120 { 121 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 122 struct mutex mutex; 123 uint32_t num_gpu; 124 uint32_t num_dgpu; 125 uint32_t num_apu; 126 127 /* delayed reset_func for XGMI configuration if necessary */ 128 struct delayed_work delayed_reset_work; 129 bool pending_reset; 130 }; 131 132 enum amdgpu_ss { 133 AMDGPU_SS_DRV_LOAD, 134 AMDGPU_SS_DEV_D0, 135 AMDGPU_SS_DEV_D3, 136 AMDGPU_SS_DRV_UNLOAD 137 }; 138 139 struct amdgpu_watchdog_timer 140 { 141 bool timeout_fatal_disable; 142 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 143 }; 144 145 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 146 147 /* 148 * Modules parameters. 149 */ 150 extern int amdgpu_modeset; 151 extern unsigned int amdgpu_vram_limit; 152 extern int amdgpu_vis_vram_limit; 153 extern int amdgpu_gart_size; 154 extern int amdgpu_gtt_size; 155 extern int amdgpu_moverate; 156 extern int amdgpu_audio; 157 extern int amdgpu_disp_priority; 158 extern int amdgpu_hw_i2c; 159 extern int amdgpu_pcie_gen2; 160 extern int amdgpu_msi; 161 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 162 extern int amdgpu_dpm; 163 extern int amdgpu_fw_load_type; 164 extern int amdgpu_aspm; 165 extern int amdgpu_runtime_pm; 166 extern uint amdgpu_ip_block_mask; 167 extern int amdgpu_bapm; 168 extern int amdgpu_deep_color; 169 extern int amdgpu_vm_size; 170 extern int amdgpu_vm_block_size; 171 extern int amdgpu_vm_fragment_size; 172 extern int amdgpu_vm_fault_stop; 173 extern int amdgpu_vm_debug; 174 extern int amdgpu_vm_update_mode; 175 extern int amdgpu_exp_hw_support; 176 extern int amdgpu_dc; 177 extern int amdgpu_sched_jobs; 178 extern int amdgpu_sched_hw_submission; 179 extern uint amdgpu_pcie_gen_cap; 180 extern uint amdgpu_pcie_lane_cap; 181 extern u64 amdgpu_cg_mask; 182 extern uint amdgpu_pg_mask; 183 extern uint amdgpu_sdma_phase_quantum; 184 extern char *amdgpu_disable_cu; 185 extern char *amdgpu_virtual_display; 186 extern uint amdgpu_pp_feature_mask; 187 extern uint amdgpu_force_long_training; 188 extern int amdgpu_job_hang_limit; 189 extern int amdgpu_lbpw; 190 extern int amdgpu_compute_multipipe; 191 extern int amdgpu_gpu_recovery; 192 extern int amdgpu_emu_mode; 193 extern uint amdgpu_smu_memory_pool_size; 194 extern int amdgpu_smu_pptable_id; 195 extern uint amdgpu_dc_feature_mask; 196 extern uint amdgpu_freesync_vid_mode; 197 extern uint amdgpu_dc_debug_mask; 198 extern uint amdgpu_dc_visual_confirm; 199 extern uint amdgpu_dm_abm_level; 200 extern int amdgpu_backlight; 201 extern struct amdgpu_mgpu_info mgpu_info; 202 extern int amdgpu_ras_enable; 203 extern uint amdgpu_ras_mask; 204 extern int amdgpu_bad_page_threshold; 205 extern bool amdgpu_ignore_bad_page_threshold; 206 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 207 extern int amdgpu_async_gfx_ring; 208 extern int amdgpu_mcbp; 209 extern int amdgpu_discovery; 210 extern int amdgpu_mes; 211 extern int amdgpu_mes_kiq; 212 extern int amdgpu_noretry; 213 extern int amdgpu_force_asic_type; 214 extern int amdgpu_smartshift_bias; 215 extern int amdgpu_use_xgmi_p2p; 216 #ifdef CONFIG_HSA_AMD 217 extern int sched_policy; 218 extern bool debug_evictions; 219 extern bool no_system_mem_limit; 220 extern int halt_if_hws_hang; 221 #else 222 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 223 static const bool __maybe_unused debug_evictions; /* = false */ 224 static const bool __maybe_unused no_system_mem_limit; 225 static const int __maybe_unused halt_if_hws_hang; 226 #endif 227 #ifdef CONFIG_HSA_AMD_P2P 228 extern bool pcie_p2p; 229 #endif 230 231 extern int amdgpu_tmz; 232 extern int amdgpu_reset_method; 233 234 #ifdef CONFIG_DRM_AMDGPU_SI 235 extern int amdgpu_si_support; 236 #endif 237 #ifdef CONFIG_DRM_AMDGPU_CIK 238 extern int amdgpu_cik_support; 239 #endif 240 extern int amdgpu_num_kcq; 241 242 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 243 extern int amdgpu_vcnfw_log; 244 extern int amdgpu_sg_display; 245 246 #define AMDGPU_VM_MAX_NUM_CTX 4096 247 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 248 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 249 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 250 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 251 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 252 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 253 #define AMDGPUFB_CONN_LIMIT 4 254 #define AMDGPU_BIOS_NUM_SCRATCH 16 255 256 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 257 258 /* hard reset data */ 259 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 260 261 /* reset flags */ 262 #define AMDGPU_RESET_GFX (1 << 0) 263 #define AMDGPU_RESET_COMPUTE (1 << 1) 264 #define AMDGPU_RESET_DMA (1 << 2) 265 #define AMDGPU_RESET_CP (1 << 3) 266 #define AMDGPU_RESET_GRBM (1 << 4) 267 #define AMDGPU_RESET_DMA1 (1 << 5) 268 #define AMDGPU_RESET_RLC (1 << 6) 269 #define AMDGPU_RESET_SEM (1 << 7) 270 #define AMDGPU_RESET_IH (1 << 8) 271 #define AMDGPU_RESET_VMC (1 << 9) 272 #define AMDGPU_RESET_MC (1 << 10) 273 #define AMDGPU_RESET_DISPLAY (1 << 11) 274 #define AMDGPU_RESET_UVD (1 << 12) 275 #define AMDGPU_RESET_VCE (1 << 13) 276 #define AMDGPU_RESET_VCE1 (1 << 14) 277 278 /* max cursor sizes (in pixels) */ 279 #define CIK_CURSOR_WIDTH 128 280 #define CIK_CURSOR_HEIGHT 128 281 282 /* smart shift bias level limits */ 283 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 284 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 285 286 struct amdgpu_device; 287 struct amdgpu_irq_src; 288 struct amdgpu_fpriv; 289 struct amdgpu_bo_va_mapping; 290 struct kfd_vm_fault_info; 291 struct amdgpu_hive_info; 292 struct amdgpu_reset_context; 293 struct amdgpu_reset_control; 294 295 enum amdgpu_cp_irq { 296 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 297 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 298 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 299 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 300 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 301 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 302 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 303 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 304 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 305 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 306 307 AMDGPU_CP_IRQ_LAST 308 }; 309 310 enum amdgpu_thermal_irq { 311 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 312 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 313 314 AMDGPU_THERMAL_IRQ_LAST 315 }; 316 317 enum amdgpu_kiq_irq { 318 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 319 AMDGPU_CP_KIQ_IRQ_LAST 320 }; 321 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 322 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 323 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 324 #define MAX_KIQ_REG_TRY 1000 325 326 int amdgpu_device_ip_set_clockgating_state(void *dev, 327 enum amd_ip_block_type block_type, 328 enum amd_clockgating_state state); 329 int amdgpu_device_ip_set_powergating_state(void *dev, 330 enum amd_ip_block_type block_type, 331 enum amd_powergating_state state); 332 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 333 u64 *flags); 334 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 335 enum amd_ip_block_type block_type); 336 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 337 enum amd_ip_block_type block_type); 338 339 #define AMDGPU_MAX_IP_NUM 16 340 341 struct amdgpu_ip_block_status { 342 bool valid; 343 bool sw; 344 bool hw; 345 bool late_initialized; 346 bool hang; 347 }; 348 349 struct amdgpu_ip_block_version { 350 const enum amd_ip_block_type type; 351 const u32 major; 352 const u32 minor; 353 const u32 rev; 354 const struct amd_ip_funcs *funcs; 355 }; 356 357 #define HW_REV(_Major, _Minor, _Rev) \ 358 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 359 360 struct amdgpu_ip_block { 361 struct amdgpu_ip_block_status status; 362 const struct amdgpu_ip_block_version *version; 363 }; 364 365 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 366 enum amd_ip_block_type type, 367 u32 major, u32 minor); 368 369 struct amdgpu_ip_block * 370 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 371 enum amd_ip_block_type type); 372 373 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 374 const struct amdgpu_ip_block_version *ip_block_version); 375 376 /* 377 * BIOS. 378 */ 379 bool amdgpu_get_bios(struct amdgpu_device *adev); 380 bool amdgpu_read_bios(struct amdgpu_device *adev); 381 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 382 u8 *bios, u32 length_bytes); 383 /* 384 * Clocks 385 */ 386 387 #define AMDGPU_MAX_PPLL 3 388 389 struct amdgpu_clock { 390 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 391 struct amdgpu_pll spll; 392 struct amdgpu_pll mpll; 393 /* 10 Khz units */ 394 uint32_t default_mclk; 395 uint32_t default_sclk; 396 uint32_t default_dispclk; 397 uint32_t current_dispclk; 398 uint32_t dp_extclk; 399 uint32_t max_pixel_clock; 400 }; 401 402 /* sub-allocation manager, it has to be protected by another lock. 403 * By conception this is an helper for other part of the driver 404 * like the indirect buffer or semaphore, which both have their 405 * locking. 406 * 407 * Principe is simple, we keep a list of sub allocation in offset 408 * order (first entry has offset == 0, last entry has the highest 409 * offset). 410 * 411 * When allocating new object we first check if there is room at 412 * the end total_size - (last_object_offset + last_object_size) >= 413 * alloc_size. If so we allocate new object there. 414 * 415 * When there is not enough room at the end, we start waiting for 416 * each sub object until we reach object_offset+object_size >= 417 * alloc_size, this object then become the sub object we return. 418 * 419 * Alignment can't be bigger than page size. 420 * 421 * Hole are not considered for allocation to keep things simple. 422 * Assumption is that there won't be hole (all object on same 423 * alignment). 424 */ 425 426 struct amdgpu_sa_manager { 427 struct drm_suballoc_manager base; 428 struct amdgpu_bo *bo; 429 uint64_t gpu_addr; 430 void *cpu_ptr; 431 }; 432 433 int amdgpu_fence_slab_init(void); 434 void amdgpu_fence_slab_fini(void); 435 436 /* 437 * IRQS. 438 */ 439 440 struct amdgpu_flip_work { 441 struct delayed_work flip_work; 442 struct work_struct unpin_work; 443 struct amdgpu_device *adev; 444 int crtc_id; 445 u32 target_vblank; 446 uint64_t base; 447 struct drm_pending_vblank_event *event; 448 struct amdgpu_bo *old_abo; 449 unsigned shared_count; 450 struct dma_fence **shared; 451 struct dma_fence_cb cb; 452 bool async; 453 }; 454 455 456 /* 457 * file private structure 458 */ 459 460 struct amdgpu_fpriv { 461 struct amdgpu_vm vm; 462 struct amdgpu_bo_va *prt_va; 463 struct amdgpu_bo_va *csa_va; 464 struct mutex bo_list_lock; 465 struct idr bo_list_handles; 466 struct amdgpu_ctx_mgr ctx_mgr; 467 }; 468 469 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 470 471 /* 472 * Writeback 473 */ 474 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 475 476 struct amdgpu_wb { 477 struct amdgpu_bo *wb_obj; 478 volatile uint32_t *wb; 479 uint64_t gpu_addr; 480 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 481 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 482 }; 483 484 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 485 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 486 487 /* 488 * Benchmarking 489 */ 490 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 491 492 /* 493 * ASIC specific register table accessible by UMD 494 */ 495 struct amdgpu_allowed_register_entry { 496 uint32_t reg_offset; 497 bool grbm_indexed; 498 }; 499 500 enum amd_reset_method { 501 AMD_RESET_METHOD_NONE = -1, 502 AMD_RESET_METHOD_LEGACY = 0, 503 AMD_RESET_METHOD_MODE0, 504 AMD_RESET_METHOD_MODE1, 505 AMD_RESET_METHOD_MODE2, 506 AMD_RESET_METHOD_BACO, 507 AMD_RESET_METHOD_PCI, 508 }; 509 510 struct amdgpu_video_codec_info { 511 u32 codec_type; 512 u32 max_width; 513 u32 max_height; 514 u32 max_pixels_per_frame; 515 u32 max_level; 516 }; 517 518 #define codec_info_build(type, width, height, level) \ 519 .codec_type = type,\ 520 .max_width = width,\ 521 .max_height = height,\ 522 .max_pixels_per_frame = height * width,\ 523 .max_level = level, 524 525 struct amdgpu_video_codecs { 526 const u32 codec_count; 527 const struct amdgpu_video_codec_info *codec_array; 528 }; 529 530 /* 531 * ASIC specific functions. 532 */ 533 struct amdgpu_asic_funcs { 534 bool (*read_disabled_bios)(struct amdgpu_device *adev); 535 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 536 u8 *bios, u32 length_bytes); 537 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 538 u32 sh_num, u32 reg_offset, u32 *value); 539 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 540 int (*reset)(struct amdgpu_device *adev); 541 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 542 /* get the reference clock */ 543 u32 (*get_xclk)(struct amdgpu_device *adev); 544 /* MM block clocks */ 545 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 546 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 547 /* static power management */ 548 int (*get_pcie_lanes)(struct amdgpu_device *adev); 549 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 550 /* get config memsize register */ 551 u32 (*get_config_memsize)(struct amdgpu_device *adev); 552 /* flush hdp write queue */ 553 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 554 /* invalidate hdp read cache */ 555 void (*invalidate_hdp)(struct amdgpu_device *adev, 556 struct amdgpu_ring *ring); 557 /* check if the asic needs a full reset of if soft reset will work */ 558 bool (*need_full_reset)(struct amdgpu_device *adev); 559 /* initialize doorbell layout for specific asic*/ 560 void (*init_doorbell_index)(struct amdgpu_device *adev); 561 /* PCIe bandwidth usage */ 562 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 563 uint64_t *count1); 564 /* do we need to reset the asic at init time (e.g., kexec) */ 565 bool (*need_reset_on_init)(struct amdgpu_device *adev); 566 /* PCIe replay counter */ 567 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 568 /* device supports BACO */ 569 bool (*supports_baco)(struct amdgpu_device *adev); 570 /* pre asic_init quirks */ 571 void (*pre_asic_init)(struct amdgpu_device *adev); 572 /* enter/exit umd stable pstate */ 573 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 574 /* query video codecs */ 575 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 576 const struct amdgpu_video_codecs **codecs); 577 }; 578 579 /* 580 * IOCTL. 581 */ 582 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 583 struct drm_file *filp); 584 585 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 586 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 587 struct drm_file *filp); 588 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 589 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 590 struct drm_file *filp); 591 592 /* VRAM scratch page for HDP bug, default vram page */ 593 struct amdgpu_mem_scratch { 594 struct amdgpu_bo *robj; 595 volatile uint32_t *ptr; 596 u64 gpu_addr; 597 }; 598 599 /* 600 * CGS 601 */ 602 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 603 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 604 605 /* 606 * Core structure, functions and helpers. 607 */ 608 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 609 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 610 611 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 612 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 613 614 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 615 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 616 617 struct amdgpu_mmio_remap { 618 u32 reg_offset; 619 resource_size_t bus_addr; 620 }; 621 622 /* Define the HW IP blocks will be used in driver , add more if necessary */ 623 enum amd_hw_ip_block_type { 624 GC_HWIP = 1, 625 HDP_HWIP, 626 SDMA0_HWIP, 627 SDMA1_HWIP, 628 SDMA2_HWIP, 629 SDMA3_HWIP, 630 SDMA4_HWIP, 631 SDMA5_HWIP, 632 SDMA6_HWIP, 633 SDMA7_HWIP, 634 LSDMA_HWIP, 635 MMHUB_HWIP, 636 ATHUB_HWIP, 637 NBIO_HWIP, 638 MP0_HWIP, 639 MP1_HWIP, 640 UVD_HWIP, 641 VCN_HWIP = UVD_HWIP, 642 JPEG_HWIP = VCN_HWIP, 643 VCN1_HWIP, 644 VCE_HWIP, 645 DF_HWIP, 646 DCE_HWIP, 647 OSSSYS_HWIP, 648 SMUIO_HWIP, 649 PWR_HWIP, 650 NBIF_HWIP, 651 THM_HWIP, 652 CLK_HWIP, 653 UMC_HWIP, 654 RSMU_HWIP, 655 XGMI_HWIP, 656 DCI_HWIP, 657 PCIE_HWIP, 658 MAX_HWIP 659 }; 660 661 #define HWIP_MAX_INSTANCE 28 662 663 #define HW_ID_MAX 300 664 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 665 #define IP_VERSION_MAJ(ver) ((ver) >> 16) 666 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF) 667 #define IP_VERSION_REV(ver) ((ver) & 0xFF) 668 669 struct amd_powerplay { 670 void *pp_handle; 671 const struct amd_pm_funcs *pp_funcs; 672 }; 673 674 struct ip_discovery_top; 675 676 /* polaris10 kickers */ 677 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 678 ((rid == 0xE3) || \ 679 (rid == 0xE4) || \ 680 (rid == 0xE5) || \ 681 (rid == 0xE7) || \ 682 (rid == 0xEF))) || \ 683 ((did == 0x6FDF) && \ 684 ((rid == 0xE7) || \ 685 (rid == 0xEF) || \ 686 (rid == 0xFF)))) 687 688 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 689 ((rid == 0xE1) || \ 690 (rid == 0xF7))) 691 692 /* polaris11 kickers */ 693 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 694 ((rid == 0xE0) || \ 695 (rid == 0xE5))) || \ 696 ((did == 0x67FF) && \ 697 ((rid == 0xCF) || \ 698 (rid == 0xEF) || \ 699 (rid == 0xFF)))) 700 701 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 702 ((rid == 0xE2))) 703 704 /* polaris12 kickers */ 705 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 706 ((rid == 0xC0) || \ 707 (rid == 0xC1) || \ 708 (rid == 0xC3) || \ 709 (rid == 0xC7))) || \ 710 ((did == 0x6981) && \ 711 ((rid == 0x00) || \ 712 (rid == 0x01) || \ 713 (rid == 0x10)))) 714 715 struct amdgpu_mqd_prop { 716 uint64_t mqd_gpu_addr; 717 uint64_t hqd_base_gpu_addr; 718 uint64_t rptr_gpu_addr; 719 uint64_t wptr_gpu_addr; 720 uint32_t queue_size; 721 bool use_doorbell; 722 uint32_t doorbell_index; 723 uint64_t eop_gpu_addr; 724 uint32_t hqd_pipe_priority; 725 uint32_t hqd_queue_priority; 726 bool hqd_active; 727 }; 728 729 struct amdgpu_mqd { 730 unsigned mqd_size; 731 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 732 struct amdgpu_mqd_prop *p); 733 }; 734 735 #define AMDGPU_RESET_MAGIC_NUM 64 736 #define AMDGPU_MAX_DF_PERFMONS 4 737 #define AMDGPU_PRODUCT_NAME_LEN 64 738 struct amdgpu_reset_domain; 739 740 /* 741 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 742 */ 743 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 744 745 struct amdgpu_device { 746 struct device *dev; 747 struct pci_dev *pdev; 748 struct drm_device ddev; 749 750 #ifdef CONFIG_DRM_AMD_ACP 751 struct amdgpu_acp acp; 752 #endif 753 struct amdgpu_hive_info *hive; 754 /* ASIC */ 755 enum amd_asic_type asic_type; 756 uint32_t family; 757 uint32_t rev_id; 758 uint32_t external_rev_id; 759 unsigned long flags; 760 unsigned long apu_flags; 761 int usec_timeout; 762 const struct amdgpu_asic_funcs *asic_funcs; 763 bool shutdown; 764 bool need_swiotlb; 765 bool accel_working; 766 struct notifier_block acpi_nb; 767 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 768 struct debugfs_blob_wrapper debugfs_vbios_blob; 769 struct debugfs_blob_wrapper debugfs_discovery_blob; 770 struct mutex srbm_mutex; 771 /* GRBM index mutex. Protects concurrent access to GRBM index */ 772 struct mutex grbm_idx_mutex; 773 struct dev_pm_domain vga_pm_domain; 774 bool have_disp_power_ref; 775 bool have_atomics_support; 776 777 /* BIOS */ 778 bool is_atom_fw; 779 uint8_t *bios; 780 uint32_t bios_size; 781 uint32_t bios_scratch_reg_offset; 782 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 783 784 /* Register/doorbell mmio */ 785 resource_size_t rmmio_base; 786 resource_size_t rmmio_size; 787 void __iomem *rmmio; 788 /* protects concurrent MM_INDEX/DATA based register access */ 789 spinlock_t mmio_idx_lock; 790 struct amdgpu_mmio_remap rmmio_remap; 791 /* protects concurrent SMC based register access */ 792 spinlock_t smc_idx_lock; 793 amdgpu_rreg_t smc_rreg; 794 amdgpu_wreg_t smc_wreg; 795 /* protects concurrent PCIE register access */ 796 spinlock_t pcie_idx_lock; 797 amdgpu_rreg_t pcie_rreg; 798 amdgpu_wreg_t pcie_wreg; 799 amdgpu_rreg_t pciep_rreg; 800 amdgpu_wreg_t pciep_wreg; 801 amdgpu_rreg64_t pcie_rreg64; 802 amdgpu_wreg64_t pcie_wreg64; 803 /* protects concurrent UVD register access */ 804 spinlock_t uvd_ctx_idx_lock; 805 amdgpu_rreg_t uvd_ctx_rreg; 806 amdgpu_wreg_t uvd_ctx_wreg; 807 /* protects concurrent DIDT register access */ 808 spinlock_t didt_idx_lock; 809 amdgpu_rreg_t didt_rreg; 810 amdgpu_wreg_t didt_wreg; 811 /* protects concurrent gc_cac register access */ 812 spinlock_t gc_cac_idx_lock; 813 amdgpu_rreg_t gc_cac_rreg; 814 amdgpu_wreg_t gc_cac_wreg; 815 /* protects concurrent se_cac register access */ 816 spinlock_t se_cac_idx_lock; 817 amdgpu_rreg_t se_cac_rreg; 818 amdgpu_wreg_t se_cac_wreg; 819 /* protects concurrent ENDPOINT (audio) register access */ 820 spinlock_t audio_endpt_idx_lock; 821 amdgpu_block_rreg_t audio_endpt_rreg; 822 amdgpu_block_wreg_t audio_endpt_wreg; 823 struct amdgpu_doorbell doorbell; 824 825 /* clock/pll info */ 826 struct amdgpu_clock clock; 827 828 /* MC */ 829 struct amdgpu_gmc gmc; 830 struct amdgpu_gart gart; 831 dma_addr_t dummy_page_addr; 832 struct amdgpu_vm_manager vm_manager; 833 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 834 unsigned num_vmhubs; 835 836 /* memory management */ 837 struct amdgpu_mman mman; 838 struct amdgpu_mem_scratch mem_scratch; 839 struct amdgpu_wb wb; 840 atomic64_t num_bytes_moved; 841 atomic64_t num_evictions; 842 atomic64_t num_vram_cpu_page_faults; 843 atomic_t gpu_reset_counter; 844 atomic_t vram_lost_counter; 845 846 /* data for buffer migration throttling */ 847 struct { 848 spinlock_t lock; 849 s64 last_update_us; 850 s64 accum_us; /* accumulated microseconds */ 851 s64 accum_us_vis; /* for visible VRAM */ 852 u32 log2_max_MBps; 853 } mm_stats; 854 855 /* display */ 856 bool enable_virtual_display; 857 struct amdgpu_vkms_output *amdgpu_vkms_output; 858 struct amdgpu_mode_info mode_info; 859 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 860 struct delayed_work hotplug_work; 861 struct amdgpu_irq_src crtc_irq; 862 struct amdgpu_irq_src vline0_irq; 863 struct amdgpu_irq_src vupdate_irq; 864 struct amdgpu_irq_src pageflip_irq; 865 struct amdgpu_irq_src hpd_irq; 866 struct amdgpu_irq_src dmub_trace_irq; 867 struct amdgpu_irq_src dmub_outbox_irq; 868 869 /* rings */ 870 u64 fence_context; 871 unsigned num_rings; 872 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 873 struct dma_fence __rcu *gang_submit; 874 bool ib_pool_ready; 875 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 876 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 877 878 /* interrupts */ 879 struct amdgpu_irq irq; 880 881 /* powerplay */ 882 struct amd_powerplay powerplay; 883 struct amdgpu_pm pm; 884 u64 cg_flags; 885 u32 pg_flags; 886 887 /* nbio */ 888 struct amdgpu_nbio nbio; 889 890 /* hdp */ 891 struct amdgpu_hdp hdp; 892 893 /* smuio */ 894 struct amdgpu_smuio smuio; 895 896 /* mmhub */ 897 struct amdgpu_mmhub mmhub; 898 899 /* gfxhub */ 900 struct amdgpu_gfxhub gfxhub; 901 902 /* gfx */ 903 struct amdgpu_gfx gfx; 904 905 /* sdma */ 906 struct amdgpu_sdma sdma; 907 908 /* lsdma */ 909 struct amdgpu_lsdma lsdma; 910 911 /* uvd */ 912 struct amdgpu_uvd uvd; 913 914 /* vce */ 915 struct amdgpu_vce vce; 916 917 /* vcn */ 918 struct amdgpu_vcn vcn; 919 920 /* jpeg */ 921 struct amdgpu_jpeg jpeg; 922 923 /* firmwares */ 924 struct amdgpu_firmware firmware; 925 926 /* PSP */ 927 struct psp_context psp; 928 929 /* GDS */ 930 struct amdgpu_gds gds; 931 932 /* KFD */ 933 struct amdgpu_kfd_dev kfd; 934 935 /* UMC */ 936 struct amdgpu_umc umc; 937 938 /* display related functionality */ 939 struct amdgpu_display_manager dm; 940 941 /* mes */ 942 bool enable_mes; 943 bool enable_mes_kiq; 944 struct amdgpu_mes mes; 945 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 946 947 /* df */ 948 struct amdgpu_df df; 949 950 /* MCA */ 951 struct amdgpu_mca mca; 952 953 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 954 uint32_t harvest_ip_mask; 955 int num_ip_blocks; 956 struct mutex mn_lock; 957 DECLARE_HASHTABLE(mn_hash, 7); 958 959 /* tracking pinned memory */ 960 atomic64_t vram_pin_size; 961 atomic64_t visible_pin_size; 962 atomic64_t gart_pin_size; 963 964 /* soc15 register offset based on ip, instance and segment */ 965 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 966 967 /* delayed work_func for deferring clockgating during resume */ 968 struct delayed_work delayed_init_work; 969 970 struct amdgpu_virt virt; 971 972 /* link all shadow bo */ 973 struct list_head shadow_list; 974 struct mutex shadow_list_lock; 975 976 /* record hw reset is performed */ 977 bool has_hw_reset; 978 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 979 980 /* s3/s4 mask */ 981 bool in_suspend; 982 bool in_s3; 983 bool in_s4; 984 bool in_s0ix; 985 986 enum pp_mp1_state mp1_state; 987 struct amdgpu_doorbell_index doorbell_index; 988 989 struct mutex notifier_lock; 990 991 int asic_reset_res; 992 struct work_struct xgmi_reset_work; 993 struct list_head reset_list; 994 995 long gfx_timeout; 996 long sdma_timeout; 997 long video_timeout; 998 long compute_timeout; 999 1000 uint64_t unique_id; 1001 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1002 1003 /* enable runtime pm on the device */ 1004 bool in_runpm; 1005 bool has_pr3; 1006 1007 bool ucode_sysfs_en; 1008 bool psp_sysfs_en; 1009 1010 /* Chip product information */ 1011 char product_number[20]; 1012 char product_name[AMDGPU_PRODUCT_NAME_LEN]; 1013 char serial[20]; 1014 1015 atomic_t throttling_logging_enabled; 1016 struct ratelimit_state throttling_logging_rs; 1017 uint32_t ras_hw_enabled; 1018 uint32_t ras_enabled; 1019 1020 bool no_hw_access; 1021 struct pci_saved_state *pci_state; 1022 pci_channel_state_t pci_channel_state; 1023 1024 struct amdgpu_reset_control *reset_cntl; 1025 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1026 1027 bool ram_is_direct_mapped; 1028 1029 struct list_head ras_list; 1030 1031 struct ip_discovery_top *ip_top; 1032 1033 struct amdgpu_reset_domain *reset_domain; 1034 1035 struct mutex benchmark_mutex; 1036 1037 /* reset dump register */ 1038 uint32_t *reset_dump_reg_list; 1039 uint32_t *reset_dump_reg_value; 1040 int num_regs; 1041 #ifdef CONFIG_DEV_COREDUMP 1042 struct amdgpu_task_info reset_task_info; 1043 bool reset_vram_lost; 1044 struct timespec64 reset_time; 1045 #endif 1046 1047 bool scpm_enabled; 1048 uint32_t scpm_status; 1049 1050 struct work_struct reset_work; 1051 1052 bool job_hang; 1053 bool dc_enabled; 1054 }; 1055 1056 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1057 { 1058 return container_of(ddev, struct amdgpu_device, ddev); 1059 } 1060 1061 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1062 { 1063 return &adev->ddev; 1064 } 1065 1066 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1067 { 1068 return container_of(bdev, struct amdgpu_device, mman.bdev); 1069 } 1070 1071 int amdgpu_device_init(struct amdgpu_device *adev, 1072 uint32_t flags); 1073 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1074 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1075 1076 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1077 1078 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1079 void *buf, size_t size, bool write); 1080 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1081 void *buf, size_t size, bool write); 1082 1083 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1084 void *buf, size_t size, bool write); 1085 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1086 uint32_t reg, uint32_t acc_flags); 1087 void amdgpu_device_wreg(struct amdgpu_device *adev, 1088 uint32_t reg, uint32_t v, 1089 uint32_t acc_flags); 1090 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1091 uint32_t reg, uint32_t v); 1092 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1093 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1094 1095 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1096 u32 reg_addr); 1097 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1098 u32 reg_addr); 1099 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1100 u32 reg_addr, u32 reg_data); 1101 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1102 u32 reg_addr, u64 reg_data); 1103 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1104 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1105 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1106 1107 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1108 1109 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1110 struct amdgpu_reset_context *reset_context); 1111 1112 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1113 struct amdgpu_reset_context *reset_context); 1114 1115 int emu_soc_asic_init(struct amdgpu_device *adev); 1116 1117 /* 1118 * Registers read & write functions. 1119 */ 1120 #define AMDGPU_REGS_NO_KIQ (1<<1) 1121 #define AMDGPU_REGS_RLC (1<<2) 1122 1123 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1124 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1125 1126 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1127 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1128 1129 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1130 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1131 1132 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1133 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1134 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1135 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1136 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1137 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1138 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1139 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1140 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1141 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1142 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1143 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1144 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1145 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1146 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1147 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1148 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1149 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1150 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1151 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1152 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1153 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1154 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1155 #define WREG32_P(reg, val, mask) \ 1156 do { \ 1157 uint32_t tmp_ = RREG32(reg); \ 1158 tmp_ &= (mask); \ 1159 tmp_ |= ((val) & ~(mask)); \ 1160 WREG32(reg, tmp_); \ 1161 } while (0) 1162 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1163 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1164 #define WREG32_PLL_P(reg, val, mask) \ 1165 do { \ 1166 uint32_t tmp_ = RREG32_PLL(reg); \ 1167 tmp_ &= (mask); \ 1168 tmp_ |= ((val) & ~(mask)); \ 1169 WREG32_PLL(reg, tmp_); \ 1170 } while (0) 1171 1172 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1173 do { \ 1174 u32 tmp = RREG32_SMC(_Reg); \ 1175 tmp &= (_Mask); \ 1176 tmp |= ((_Val) & ~(_Mask)); \ 1177 WREG32_SMC(_Reg, tmp); \ 1178 } while (0) 1179 1180 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1181 1182 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1183 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1184 1185 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1186 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1187 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1188 1189 #define REG_GET_FIELD(value, reg, field) \ 1190 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1191 1192 #define WREG32_FIELD(reg, field, val) \ 1193 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1194 1195 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1196 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1197 1198 /* 1199 * BIOS helpers. 1200 */ 1201 #define RBIOS8(i) (adev->bios[i]) 1202 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1203 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1204 1205 /* 1206 * ASICs macro. 1207 */ 1208 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1209 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1210 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1211 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1212 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1213 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1214 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1215 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1216 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1217 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1218 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1219 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1220 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1221 #define amdgpu_asic_flush_hdp(adev, r) \ 1222 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1223 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1224 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1225 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0)) 1226 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1227 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1228 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1229 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1230 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1231 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1232 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1233 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1234 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1235 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1236 1237 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1238 1239 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 1240 1241 /* Common functions */ 1242 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1243 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1244 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1245 struct amdgpu_job *job, 1246 struct amdgpu_reset_context *reset_context); 1247 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1248 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1249 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1250 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1251 bool amdgpu_device_aspm_support_quirk(void); 1252 1253 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1254 u64 num_vis_bytes); 1255 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1256 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1257 const u32 *registers, 1258 const u32 array_size); 1259 1260 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1261 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1262 bool amdgpu_device_supports_px(struct drm_device *dev); 1263 bool amdgpu_device_supports_boco(struct drm_device *dev); 1264 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1265 bool amdgpu_device_supports_baco(struct drm_device *dev); 1266 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1267 struct amdgpu_device *peer_adev); 1268 int amdgpu_device_baco_enter(struct drm_device *dev); 1269 int amdgpu_device_baco_exit(struct drm_device *dev); 1270 1271 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1272 struct amdgpu_ring *ring); 1273 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1274 struct amdgpu_ring *ring); 1275 1276 void amdgpu_device_halt(struct amdgpu_device *adev); 1277 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1278 u32 reg); 1279 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1280 u32 reg, u32 v); 1281 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1282 struct dma_fence *gang); 1283 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1284 1285 /* atpx handler */ 1286 #if defined(CONFIG_VGA_SWITCHEROO) 1287 void amdgpu_register_atpx_handler(void); 1288 void amdgpu_unregister_atpx_handler(void); 1289 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1290 bool amdgpu_is_atpx_hybrid(void); 1291 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1292 bool amdgpu_has_atpx(void); 1293 #else 1294 static inline void amdgpu_register_atpx_handler(void) {} 1295 static inline void amdgpu_unregister_atpx_handler(void) {} 1296 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1297 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1298 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1299 static inline bool amdgpu_has_atpx(void) { return false; } 1300 #endif 1301 1302 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1303 void *amdgpu_atpx_get_dhandle(void); 1304 #else 1305 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1306 #endif 1307 1308 /* 1309 * KMS 1310 */ 1311 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1312 extern const int amdgpu_max_kms_ioctl; 1313 1314 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1315 void amdgpu_driver_unload_kms(struct drm_device *dev); 1316 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1317 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1318 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1319 struct drm_file *file_priv); 1320 void amdgpu_driver_release_kms(struct drm_device *dev); 1321 1322 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1323 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1324 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1325 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1326 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1327 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1328 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1329 struct drm_file *filp); 1330 1331 /* 1332 * functions used by amdgpu_encoder.c 1333 */ 1334 struct amdgpu_afmt_acr { 1335 u32 clock; 1336 1337 int n_32khz; 1338 int cts_32khz; 1339 1340 int n_44_1khz; 1341 int cts_44_1khz; 1342 1343 int n_48khz; 1344 int cts_48khz; 1345 1346 }; 1347 1348 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1349 1350 /* amdgpu_acpi.c */ 1351 1352 /* ATCS Device/Driver State */ 1353 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1354 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1355 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1356 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1357 1358 #if defined(CONFIG_ACPI) 1359 int amdgpu_acpi_init(struct amdgpu_device *adev); 1360 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1361 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1362 bool amdgpu_acpi_is_power_shift_control_supported(void); 1363 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1364 u8 perf_req, bool advertise); 1365 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1366 u8 dev_state, bool drv_state); 1367 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1368 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1369 1370 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1371 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1372 void amdgpu_acpi_detect(void); 1373 #else 1374 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1375 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1376 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1377 static inline void amdgpu_acpi_detect(void) { } 1378 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1379 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1380 u8 dev_state, bool drv_state) { return 0; } 1381 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1382 enum amdgpu_ss ss_state) { return 0; } 1383 #endif 1384 1385 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1386 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1387 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1388 #else 1389 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1390 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1391 #endif 1392 1393 #if defined(CONFIG_DRM_AMD_DC) 1394 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1395 #else 1396 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1397 #endif 1398 1399 1400 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1401 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1402 1403 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1404 pci_channel_state_t state); 1405 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1406 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1407 void amdgpu_pci_resume(struct pci_dev *pdev); 1408 1409 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1410 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1411 1412 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1413 1414 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1415 enum amd_clockgating_state state); 1416 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1417 enum amd_powergating_state state); 1418 1419 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1420 { 1421 return amdgpu_gpu_recovery != 0 && 1422 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1423 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1424 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1425 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1426 } 1427 1428 #include "amdgpu_object.h" 1429 1430 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1431 { 1432 return adev->gmc.tmz_enabled; 1433 } 1434 1435 int amdgpu_in_reset(struct amdgpu_device *adev); 1436 1437 #endif 1438