1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_gds.h" 55 #include "amd_powerplay.h" 56 57 #include "gpu_scheduler.h" 58 59 /* 60 * Modules parameters. 61 */ 62 extern int amdgpu_modeset; 63 extern int amdgpu_vram_limit; 64 extern int amdgpu_gart_size; 65 extern int amdgpu_benchmarking; 66 extern int amdgpu_testing; 67 extern int amdgpu_audio; 68 extern int amdgpu_disp_priority; 69 extern int amdgpu_hw_i2c; 70 extern int amdgpu_pcie_gen2; 71 extern int amdgpu_msi; 72 extern int amdgpu_lockup_timeout; 73 extern int amdgpu_dpm; 74 extern int amdgpu_smc_load_fw; 75 extern int amdgpu_aspm; 76 extern int amdgpu_runtime_pm; 77 extern int amdgpu_hard_reset; 78 extern unsigned amdgpu_ip_block_mask; 79 extern int amdgpu_bapm; 80 extern int amdgpu_deep_color; 81 extern int amdgpu_vm_size; 82 extern int amdgpu_vm_block_size; 83 extern int amdgpu_vm_fault_stop; 84 extern int amdgpu_vm_debug; 85 extern int amdgpu_enable_scheduler; 86 extern int amdgpu_sched_jobs; 87 extern int amdgpu_sched_hw_submission; 88 extern int amdgpu_enable_semaphores; 89 extern int amdgpu_powerplay; 90 91 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 92 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 93 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 94 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 95 #define AMDGPU_IB_POOL_SIZE 16 96 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 97 #define AMDGPUFB_CONN_LIMIT 4 98 #define AMDGPU_BIOS_NUM_SCRATCH 8 99 100 /* max number of rings */ 101 #define AMDGPU_MAX_RINGS 16 102 #define AMDGPU_MAX_GFX_RINGS 1 103 #define AMDGPU_MAX_COMPUTE_RINGS 8 104 #define AMDGPU_MAX_VCE_RINGS 2 105 106 /* max number of IP instances */ 107 #define AMDGPU_MAX_SDMA_INSTANCES 2 108 109 /* number of hw syncs before falling back on blocking */ 110 #define AMDGPU_NUM_SYNCS 4 111 112 /* hardcode that limit for now */ 113 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 114 115 /* hard reset data */ 116 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 117 118 /* reset flags */ 119 #define AMDGPU_RESET_GFX (1 << 0) 120 #define AMDGPU_RESET_COMPUTE (1 << 1) 121 #define AMDGPU_RESET_DMA (1 << 2) 122 #define AMDGPU_RESET_CP (1 << 3) 123 #define AMDGPU_RESET_GRBM (1 << 4) 124 #define AMDGPU_RESET_DMA1 (1 << 5) 125 #define AMDGPU_RESET_RLC (1 << 6) 126 #define AMDGPU_RESET_SEM (1 << 7) 127 #define AMDGPU_RESET_IH (1 << 8) 128 #define AMDGPU_RESET_VMC (1 << 9) 129 #define AMDGPU_RESET_MC (1 << 10) 130 #define AMDGPU_RESET_DISPLAY (1 << 11) 131 #define AMDGPU_RESET_UVD (1 << 12) 132 #define AMDGPU_RESET_VCE (1 << 13) 133 #define AMDGPU_RESET_VCE1 (1 << 14) 134 135 /* CG block flags */ 136 #define AMDGPU_CG_BLOCK_GFX (1 << 0) 137 #define AMDGPU_CG_BLOCK_MC (1 << 1) 138 #define AMDGPU_CG_BLOCK_SDMA (1 << 2) 139 #define AMDGPU_CG_BLOCK_UVD (1 << 3) 140 #define AMDGPU_CG_BLOCK_VCE (1 << 4) 141 #define AMDGPU_CG_BLOCK_HDP (1 << 5) 142 #define AMDGPU_CG_BLOCK_BIF (1 << 6) 143 144 /* CG flags */ 145 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0) 146 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1) 147 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2) 148 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3) 149 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4) 150 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 151 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6) 152 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7) 153 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8) 154 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9) 155 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10) 156 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11) 157 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12) 158 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13) 159 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14) 160 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15) 161 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16) 162 163 /* PG flags */ 164 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) 165 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) 166 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) 167 #define AMDGPU_PG_SUPPORT_UVD (1 << 3) 168 #define AMDGPU_PG_SUPPORT_VCE (1 << 4) 169 #define AMDGPU_PG_SUPPORT_CP (1 << 5) 170 #define AMDGPU_PG_SUPPORT_GDS (1 << 6) 171 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7) 172 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8) 173 #define AMDGPU_PG_SUPPORT_ACP (1 << 9) 174 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10) 175 176 /* GFX current status */ 177 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 178 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 179 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 180 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 181 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 182 183 /* max cursor sizes (in pixels) */ 184 #define CIK_CURSOR_WIDTH 128 185 #define CIK_CURSOR_HEIGHT 128 186 187 struct amdgpu_device; 188 struct amdgpu_fence; 189 struct amdgpu_ib; 190 struct amdgpu_vm; 191 struct amdgpu_ring; 192 struct amdgpu_semaphore; 193 struct amdgpu_cs_parser; 194 struct amdgpu_job; 195 struct amdgpu_irq_src; 196 struct amdgpu_fpriv; 197 198 enum amdgpu_cp_irq { 199 AMDGPU_CP_IRQ_GFX_EOP = 0, 200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 202 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 203 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 206 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 207 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 208 209 AMDGPU_CP_IRQ_LAST 210 }; 211 212 enum amdgpu_sdma_irq { 213 AMDGPU_SDMA_IRQ_TRAP0 = 0, 214 AMDGPU_SDMA_IRQ_TRAP1, 215 216 AMDGPU_SDMA_IRQ_LAST 217 }; 218 219 enum amdgpu_thermal_irq { 220 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 221 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 222 223 AMDGPU_THERMAL_IRQ_LAST 224 }; 225 226 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 227 enum amd_ip_block_type block_type, 228 enum amd_clockgating_state state); 229 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 230 enum amd_ip_block_type block_type, 231 enum amd_powergating_state state); 232 233 struct amdgpu_ip_block_version { 234 enum amd_ip_block_type type; 235 u32 major; 236 u32 minor; 237 u32 rev; 238 const struct amd_ip_funcs *funcs; 239 }; 240 241 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 242 enum amd_ip_block_type type, 243 u32 major, u32 minor); 244 245 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 246 struct amdgpu_device *adev, 247 enum amd_ip_block_type type); 248 249 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 250 struct amdgpu_buffer_funcs { 251 /* maximum bytes in a single operation */ 252 uint32_t copy_max_bytes; 253 254 /* number of dw to reserve per operation */ 255 unsigned copy_num_dw; 256 257 /* used for buffer migration */ 258 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 259 /* src addr in bytes */ 260 uint64_t src_offset, 261 /* dst addr in bytes */ 262 uint64_t dst_offset, 263 /* number of byte to transfer */ 264 uint32_t byte_count); 265 266 /* maximum bytes in a single operation */ 267 uint32_t fill_max_bytes; 268 269 /* number of dw to reserve per operation */ 270 unsigned fill_num_dw; 271 272 /* used for buffer clearing */ 273 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 274 /* value to write to memory */ 275 uint32_t src_data, 276 /* dst addr in bytes */ 277 uint64_t dst_offset, 278 /* number of byte to fill */ 279 uint32_t byte_count); 280 }; 281 282 /* provided by hw blocks that can write ptes, e.g., sdma */ 283 struct amdgpu_vm_pte_funcs { 284 /* copy pte entries from GART */ 285 void (*copy_pte)(struct amdgpu_ib *ib, 286 uint64_t pe, uint64_t src, 287 unsigned count); 288 /* write pte one entry at a time with addr mapping */ 289 void (*write_pte)(struct amdgpu_ib *ib, 290 uint64_t pe, 291 uint64_t addr, unsigned count, 292 uint32_t incr, uint32_t flags); 293 /* for linear pte/pde updates without addr mapping */ 294 void (*set_pte_pde)(struct amdgpu_ib *ib, 295 uint64_t pe, 296 uint64_t addr, unsigned count, 297 uint32_t incr, uint32_t flags); 298 /* pad the indirect buffer to the necessary number of dw */ 299 void (*pad_ib)(struct amdgpu_ib *ib); 300 }; 301 302 /* provided by the gmc block */ 303 struct amdgpu_gart_funcs { 304 /* flush the vm tlb via mmio */ 305 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 306 uint32_t vmid); 307 /* write pte/pde updates using the cpu */ 308 int (*set_pte_pde)(struct amdgpu_device *adev, 309 void *cpu_pt_addr, /* cpu addr of page table */ 310 uint32_t gpu_page_idx, /* pte/pde to update */ 311 uint64_t addr, /* addr to write into pte/pde */ 312 uint32_t flags); /* access flags */ 313 }; 314 315 /* provided by the ih block */ 316 struct amdgpu_ih_funcs { 317 /* ring read/write ptr handling, called from interrupt context */ 318 u32 (*get_wptr)(struct amdgpu_device *adev); 319 void (*decode_iv)(struct amdgpu_device *adev, 320 struct amdgpu_iv_entry *entry); 321 void (*set_rptr)(struct amdgpu_device *adev); 322 }; 323 324 /* provided by hw blocks that expose a ring buffer for commands */ 325 struct amdgpu_ring_funcs { 326 /* ring read/write ptr handling */ 327 u32 (*get_rptr)(struct amdgpu_ring *ring); 328 u32 (*get_wptr)(struct amdgpu_ring *ring); 329 void (*set_wptr)(struct amdgpu_ring *ring); 330 /* validating and patching of IBs */ 331 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 332 /* command emit functions */ 333 void (*emit_ib)(struct amdgpu_ring *ring, 334 struct amdgpu_ib *ib); 335 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 336 uint64_t seq, unsigned flags); 337 bool (*emit_semaphore)(struct amdgpu_ring *ring, 338 struct amdgpu_semaphore *semaphore, 339 bool emit_wait); 340 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 341 uint64_t pd_addr); 342 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 343 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 344 uint32_t gds_base, uint32_t gds_size, 345 uint32_t gws_base, uint32_t gws_size, 346 uint32_t oa_base, uint32_t oa_size); 347 /* testing functions */ 348 int (*test_ring)(struct amdgpu_ring *ring); 349 int (*test_ib)(struct amdgpu_ring *ring); 350 /* insert NOP packets */ 351 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 352 }; 353 354 /* 355 * BIOS. 356 */ 357 bool amdgpu_get_bios(struct amdgpu_device *adev); 358 bool amdgpu_read_bios(struct amdgpu_device *adev); 359 360 /* 361 * Dummy page 362 */ 363 struct amdgpu_dummy_page { 364 struct page *page; 365 dma_addr_t addr; 366 }; 367 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 368 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 369 370 371 /* 372 * Clocks 373 */ 374 375 #define AMDGPU_MAX_PPLL 3 376 377 struct amdgpu_clock { 378 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 379 struct amdgpu_pll spll; 380 struct amdgpu_pll mpll; 381 /* 10 Khz units */ 382 uint32_t default_mclk; 383 uint32_t default_sclk; 384 uint32_t default_dispclk; 385 uint32_t current_dispclk; 386 uint32_t dp_extclk; 387 uint32_t max_pixel_clock; 388 }; 389 390 /* 391 * Fences. 392 */ 393 struct amdgpu_fence_driver { 394 uint64_t gpu_addr; 395 volatile uint32_t *cpu_addr; 396 /* sync_seq is protected by ring emission lock */ 397 uint64_t sync_seq[AMDGPU_MAX_RINGS]; 398 atomic64_t last_seq; 399 bool initialized; 400 struct amdgpu_irq_src *irq_src; 401 unsigned irq_type; 402 struct timer_list fallback_timer; 403 wait_queue_head_t fence_queue; 404 }; 405 406 /* some special values for the owner field */ 407 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 408 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 409 410 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 411 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 412 413 struct amdgpu_fence { 414 struct fence base; 415 416 /* RB, DMA, etc. */ 417 struct amdgpu_ring *ring; 418 uint64_t seq; 419 420 /* filp or special value for fence creator */ 421 void *owner; 422 423 wait_queue_t fence_wake; 424 }; 425 426 struct amdgpu_user_fence { 427 /* write-back bo */ 428 struct amdgpu_bo *bo; 429 /* write-back address offset to bo start */ 430 uint32_t offset; 431 }; 432 433 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 434 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 435 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 436 437 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 438 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 439 struct amdgpu_irq_src *irq_src, 440 unsigned irq_type); 441 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 442 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 443 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, 444 struct amdgpu_fence **fence); 445 void amdgpu_fence_process(struct amdgpu_ring *ring); 446 int amdgpu_fence_wait_next(struct amdgpu_ring *ring); 447 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 448 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 449 450 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, 451 struct amdgpu_ring *ring); 452 void amdgpu_fence_note_sync(struct amdgpu_fence *fence, 453 struct amdgpu_ring *ring); 454 455 /* 456 * TTM. 457 */ 458 struct amdgpu_mman { 459 struct ttm_bo_global_ref bo_global_ref; 460 struct drm_global_reference mem_global_ref; 461 struct ttm_bo_device bdev; 462 bool mem_global_referenced; 463 bool initialized; 464 465 #if defined(CONFIG_DEBUG_FS) 466 struct dentry *vram; 467 struct dentry *gtt; 468 #endif 469 470 /* buffer handling */ 471 const struct amdgpu_buffer_funcs *buffer_funcs; 472 struct amdgpu_ring *buffer_funcs_ring; 473 }; 474 475 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 476 uint64_t src_offset, 477 uint64_t dst_offset, 478 uint32_t byte_count, 479 struct reservation_object *resv, 480 struct fence **fence); 481 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 482 483 struct amdgpu_bo_list_entry { 484 struct amdgpu_bo *robj; 485 struct ttm_validate_buffer tv; 486 struct amdgpu_bo_va *bo_va; 487 unsigned prefered_domains; 488 unsigned allowed_domains; 489 uint32_t priority; 490 }; 491 492 struct amdgpu_bo_va_mapping { 493 struct list_head list; 494 struct interval_tree_node it; 495 uint64_t offset; 496 uint32_t flags; 497 }; 498 499 /* bo virtual addresses in a specific vm */ 500 struct amdgpu_bo_va { 501 struct mutex mutex; 502 /* protected by bo being reserved */ 503 struct list_head bo_list; 504 struct fence *last_pt_update; 505 unsigned ref_count; 506 507 /* protected by vm mutex and spinlock */ 508 struct list_head vm_status; 509 510 /* mappings for this bo_va */ 511 struct list_head invalids; 512 struct list_head valids; 513 514 /* constant after initialization */ 515 struct amdgpu_vm *vm; 516 struct amdgpu_bo *bo; 517 }; 518 519 #define AMDGPU_GEM_DOMAIN_MAX 0x3 520 521 struct amdgpu_bo { 522 /* Protected by gem.mutex */ 523 struct list_head list; 524 /* Protected by tbo.reserved */ 525 u32 initial_domain; 526 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 527 struct ttm_placement placement; 528 struct ttm_buffer_object tbo; 529 struct ttm_bo_kmap_obj kmap; 530 u64 flags; 531 unsigned pin_count; 532 void *kptr; 533 u64 tiling_flags; 534 u64 metadata_flags; 535 void *metadata; 536 u32 metadata_size; 537 /* list of all virtual address to which this bo 538 * is associated to 539 */ 540 struct list_head va; 541 /* Constant after initialization */ 542 struct amdgpu_device *adev; 543 struct drm_gem_object gem_base; 544 struct amdgpu_bo *parent; 545 546 struct ttm_bo_kmap_obj dma_buf_vmap; 547 pid_t pid; 548 struct amdgpu_mn *mn; 549 struct list_head mn_list; 550 }; 551 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 552 553 void amdgpu_gem_object_free(struct drm_gem_object *obj); 554 int amdgpu_gem_object_open(struct drm_gem_object *obj, 555 struct drm_file *file_priv); 556 void amdgpu_gem_object_close(struct drm_gem_object *obj, 557 struct drm_file *file_priv); 558 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 559 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 560 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 561 struct dma_buf_attachment *attach, 562 struct sg_table *sg); 563 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 564 struct drm_gem_object *gobj, 565 int flags); 566 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 567 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 568 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 569 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 570 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 571 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 572 573 /* sub-allocation manager, it has to be protected by another lock. 574 * By conception this is an helper for other part of the driver 575 * like the indirect buffer or semaphore, which both have their 576 * locking. 577 * 578 * Principe is simple, we keep a list of sub allocation in offset 579 * order (first entry has offset == 0, last entry has the highest 580 * offset). 581 * 582 * When allocating new object we first check if there is room at 583 * the end total_size - (last_object_offset + last_object_size) >= 584 * alloc_size. If so we allocate new object there. 585 * 586 * When there is not enough room at the end, we start waiting for 587 * each sub object until we reach object_offset+object_size >= 588 * alloc_size, this object then become the sub object we return. 589 * 590 * Alignment can't be bigger than page size. 591 * 592 * Hole are not considered for allocation to keep things simple. 593 * Assumption is that there won't be hole (all object on same 594 * alignment). 595 */ 596 struct amdgpu_sa_manager { 597 wait_queue_head_t wq; 598 struct amdgpu_bo *bo; 599 struct list_head *hole; 600 struct list_head flist[AMDGPU_MAX_RINGS]; 601 struct list_head olist; 602 unsigned size; 603 uint64_t gpu_addr; 604 void *cpu_ptr; 605 uint32_t domain; 606 uint32_t align; 607 }; 608 609 struct amdgpu_sa_bo; 610 611 /* sub-allocation buffer */ 612 struct amdgpu_sa_bo { 613 struct list_head olist; 614 struct list_head flist; 615 struct amdgpu_sa_manager *manager; 616 unsigned soffset; 617 unsigned eoffset; 618 struct fence *fence; 619 }; 620 621 /* 622 * GEM objects. 623 */ 624 struct amdgpu_gem { 625 struct mutex mutex; 626 struct list_head objects; 627 }; 628 629 int amdgpu_gem_init(struct amdgpu_device *adev); 630 void amdgpu_gem_fini(struct amdgpu_device *adev); 631 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 632 int alignment, u32 initial_domain, 633 u64 flags, bool kernel, 634 struct drm_gem_object **obj); 635 636 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 637 struct drm_device *dev, 638 struct drm_mode_create_dumb *args); 639 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 640 struct drm_device *dev, 641 uint32_t handle, uint64_t *offset_p); 642 643 /* 644 * Semaphores. 645 */ 646 struct amdgpu_semaphore { 647 struct amdgpu_sa_bo *sa_bo; 648 signed waiters; 649 uint64_t gpu_addr; 650 }; 651 652 int amdgpu_semaphore_create(struct amdgpu_device *adev, 653 struct amdgpu_semaphore **semaphore); 654 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, 655 struct amdgpu_semaphore *semaphore); 656 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, 657 struct amdgpu_semaphore *semaphore); 658 void amdgpu_semaphore_free(struct amdgpu_device *adev, 659 struct amdgpu_semaphore **semaphore, 660 struct fence *fence); 661 662 /* 663 * Synchronization 664 */ 665 struct amdgpu_sync { 666 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS]; 667 struct fence *sync_to[AMDGPU_MAX_RINGS]; 668 DECLARE_HASHTABLE(fences, 4); 669 struct fence *last_vm_update; 670 }; 671 672 void amdgpu_sync_create(struct amdgpu_sync *sync); 673 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 674 struct fence *f); 675 int amdgpu_sync_resv(struct amdgpu_device *adev, 676 struct amdgpu_sync *sync, 677 struct reservation_object *resv, 678 void *owner); 679 int amdgpu_sync_rings(struct amdgpu_sync *sync, 680 struct amdgpu_ring *ring); 681 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 682 int amdgpu_sync_wait(struct amdgpu_sync *sync); 683 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, 684 struct fence *fence); 685 686 /* 687 * GART structures, functions & helpers 688 */ 689 struct amdgpu_mc; 690 691 #define AMDGPU_GPU_PAGE_SIZE 4096 692 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 693 #define AMDGPU_GPU_PAGE_SHIFT 12 694 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 695 696 struct amdgpu_gart { 697 dma_addr_t table_addr; 698 struct amdgpu_bo *robj; 699 void *ptr; 700 unsigned num_gpu_pages; 701 unsigned num_cpu_pages; 702 unsigned table_size; 703 struct page **pages; 704 dma_addr_t *pages_addr; 705 bool ready; 706 const struct amdgpu_gart_funcs *gart_funcs; 707 }; 708 709 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 710 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 711 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 712 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 713 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 714 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 715 int amdgpu_gart_init(struct amdgpu_device *adev); 716 void amdgpu_gart_fini(struct amdgpu_device *adev); 717 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 718 int pages); 719 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 720 int pages, struct page **pagelist, 721 dma_addr_t *dma_addr, uint32_t flags); 722 723 /* 724 * GPU MC structures, functions & helpers 725 */ 726 struct amdgpu_mc { 727 resource_size_t aper_size; 728 resource_size_t aper_base; 729 resource_size_t agp_base; 730 /* for some chips with <= 32MB we need to lie 731 * about vram size near mc fb location */ 732 u64 mc_vram_size; 733 u64 visible_vram_size; 734 u64 gtt_size; 735 u64 gtt_start; 736 u64 gtt_end; 737 u64 vram_start; 738 u64 vram_end; 739 unsigned vram_width; 740 u64 real_vram_size; 741 int vram_mtrr; 742 u64 gtt_base_align; 743 u64 mc_mask; 744 const struct firmware *fw; /* MC firmware */ 745 uint32_t fw_version; 746 struct amdgpu_irq_src vm_fault; 747 uint32_t vram_type; 748 }; 749 750 /* 751 * GPU doorbell structures, functions & helpers 752 */ 753 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 754 { 755 AMDGPU_DOORBELL_KIQ = 0x000, 756 AMDGPU_DOORBELL_HIQ = 0x001, 757 AMDGPU_DOORBELL_DIQ = 0x002, 758 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 759 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 760 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 761 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 762 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 763 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 764 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 765 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 766 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 767 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 768 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 769 AMDGPU_DOORBELL_IH = 0x1E8, 770 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 771 AMDGPU_DOORBELL_INVALID = 0xFFFF 772 } AMDGPU_DOORBELL_ASSIGNMENT; 773 774 struct amdgpu_doorbell { 775 /* doorbell mmio */ 776 resource_size_t base; 777 resource_size_t size; 778 u32 __iomem *ptr; 779 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 780 }; 781 782 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 783 phys_addr_t *aperture_base, 784 size_t *aperture_size, 785 size_t *start_offset); 786 787 /* 788 * IRQS. 789 */ 790 791 struct amdgpu_flip_work { 792 struct work_struct flip_work; 793 struct work_struct unpin_work; 794 struct amdgpu_device *adev; 795 int crtc_id; 796 uint64_t base; 797 struct drm_pending_vblank_event *event; 798 struct amdgpu_bo *old_rbo; 799 struct fence *excl; 800 unsigned shared_count; 801 struct fence **shared; 802 }; 803 804 805 /* 806 * CP & rings. 807 */ 808 809 struct amdgpu_ib { 810 struct amdgpu_sa_bo *sa_bo; 811 uint32_t length_dw; 812 uint64_t gpu_addr; 813 uint32_t *ptr; 814 struct amdgpu_ring *ring; 815 struct amdgpu_fence *fence; 816 struct amdgpu_user_fence *user; 817 struct amdgpu_vm *vm; 818 struct amdgpu_ctx *ctx; 819 struct amdgpu_sync sync; 820 uint32_t gds_base, gds_size; 821 uint32_t gws_base, gws_size; 822 uint32_t oa_base, oa_size; 823 uint32_t flags; 824 /* resulting sequence number */ 825 uint64_t sequence; 826 }; 827 828 enum amdgpu_ring_type { 829 AMDGPU_RING_TYPE_GFX, 830 AMDGPU_RING_TYPE_COMPUTE, 831 AMDGPU_RING_TYPE_SDMA, 832 AMDGPU_RING_TYPE_UVD, 833 AMDGPU_RING_TYPE_VCE 834 }; 835 836 extern struct amd_sched_backend_ops amdgpu_sched_ops; 837 838 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev, 839 struct amdgpu_ring *ring, 840 struct amdgpu_ib *ibs, 841 unsigned num_ibs, 842 int (*free_job)(struct amdgpu_job *), 843 void *owner, 844 struct fence **fence); 845 846 struct amdgpu_ring { 847 struct amdgpu_device *adev; 848 const struct amdgpu_ring_funcs *funcs; 849 struct amdgpu_fence_driver fence_drv; 850 struct amd_gpu_scheduler sched; 851 852 spinlock_t fence_lock; 853 struct mutex *ring_lock; 854 struct amdgpu_bo *ring_obj; 855 volatile uint32_t *ring; 856 unsigned rptr_offs; 857 u64 next_rptr_gpu_addr; 858 volatile u32 *next_rptr_cpu_addr; 859 unsigned wptr; 860 unsigned wptr_old; 861 unsigned ring_size; 862 unsigned ring_free_dw; 863 int count_dw; 864 uint64_t gpu_addr; 865 uint32_t align_mask; 866 uint32_t ptr_mask; 867 bool ready; 868 u32 nop; 869 u32 idx; 870 u64 last_semaphore_signal_addr; 871 u64 last_semaphore_wait_addr; 872 u32 me; 873 u32 pipe; 874 u32 queue; 875 struct amdgpu_bo *mqd_obj; 876 u32 doorbell_index; 877 bool use_doorbell; 878 unsigned wptr_offs; 879 unsigned next_rptr_offs; 880 unsigned fence_offs; 881 struct amdgpu_ctx *current_ctx; 882 enum amdgpu_ring_type type; 883 char name[16]; 884 bool is_pte_ring; 885 }; 886 887 /* 888 * VM 889 */ 890 891 /* maximum number of VMIDs */ 892 #define AMDGPU_NUM_VM 16 893 894 /* number of entries in page table */ 895 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 896 897 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 898 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 899 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 900 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 901 902 #define AMDGPU_PTE_VALID (1 << 0) 903 #define AMDGPU_PTE_SYSTEM (1 << 1) 904 #define AMDGPU_PTE_SNOOPED (1 << 2) 905 906 /* VI only */ 907 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 908 909 #define AMDGPU_PTE_READABLE (1 << 5) 910 #define AMDGPU_PTE_WRITEABLE (1 << 6) 911 912 /* PTE (Page Table Entry) fragment field for different page sizes */ 913 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 914 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 915 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 916 917 /* How to programm VM fault handling */ 918 #define AMDGPU_VM_FAULT_STOP_NEVER 0 919 #define AMDGPU_VM_FAULT_STOP_FIRST 1 920 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 921 922 struct amdgpu_vm_pt { 923 struct amdgpu_bo_list_entry entry; 924 uint64_t addr; 925 }; 926 927 struct amdgpu_vm_id { 928 unsigned id; 929 uint64_t pd_gpu_addr; 930 /* last flushed PD/PT update */ 931 struct fence *flushed_updates; 932 }; 933 934 struct amdgpu_vm { 935 struct rb_root va; 936 937 /* protecting invalidated */ 938 spinlock_t status_lock; 939 940 /* BOs moved, but not yet updated in the PT */ 941 struct list_head invalidated; 942 943 /* BOs cleared in the PT because of a move */ 944 struct list_head cleared; 945 946 /* BO mappings freed, but not yet updated in the PT */ 947 struct list_head freed; 948 949 /* contains the page directory */ 950 struct amdgpu_bo *page_directory; 951 unsigned max_pde_used; 952 struct fence *page_directory_fence; 953 954 /* array of page tables, one for each page directory entry */ 955 struct amdgpu_vm_pt *page_tables; 956 957 /* for id and flush management per ring */ 958 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; 959 /* for interval tree */ 960 spinlock_t it_lock; 961 /* protecting freed */ 962 spinlock_t freed_lock; 963 }; 964 965 struct amdgpu_vm_manager { 966 struct { 967 struct fence *active; 968 atomic_long_t owner; 969 } ids[AMDGPU_NUM_VM]; 970 971 uint32_t max_pfn; 972 /* number of VMIDs */ 973 unsigned nvm; 974 /* vram base address for page table entry */ 975 u64 vram_base_offset; 976 /* is vm enabled? */ 977 bool enabled; 978 /* vm pte handling */ 979 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 980 struct amdgpu_ring *vm_pte_funcs_ring; 981 }; 982 983 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 984 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 985 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 986 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 987 struct list_head *validated, 988 struct amdgpu_bo_list_entry *entry); 989 void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates); 990 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, 991 struct amdgpu_vm *vm); 992 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 993 struct amdgpu_sync *sync); 994 void amdgpu_vm_flush(struct amdgpu_ring *ring, 995 struct amdgpu_vm *vm, 996 struct fence *updates); 997 void amdgpu_vm_fence(struct amdgpu_device *adev, 998 struct amdgpu_vm *vm, 999 struct fence *fence); 1000 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); 1001 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 1002 struct amdgpu_vm *vm); 1003 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 1004 struct amdgpu_vm *vm); 1005 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, 1006 struct amdgpu_sync *sync); 1007 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 1008 struct amdgpu_bo_va *bo_va, 1009 struct ttm_mem_reg *mem); 1010 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 1011 struct amdgpu_bo *bo); 1012 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 1013 struct amdgpu_bo *bo); 1014 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 1015 struct amdgpu_vm *vm, 1016 struct amdgpu_bo *bo); 1017 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 1018 struct amdgpu_bo_va *bo_va, 1019 uint64_t addr, uint64_t offset, 1020 uint64_t size, uint32_t flags); 1021 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 1022 struct amdgpu_bo_va *bo_va, 1023 uint64_t addr); 1024 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 1025 struct amdgpu_bo_va *bo_va); 1026 int amdgpu_vm_free_job(struct amdgpu_job *job); 1027 1028 /* 1029 * context related structures 1030 */ 1031 1032 struct amdgpu_ctx_ring { 1033 uint64_t sequence; 1034 struct fence **fences; 1035 struct amd_sched_entity entity; 1036 }; 1037 1038 struct amdgpu_ctx { 1039 struct kref refcount; 1040 struct amdgpu_device *adev; 1041 unsigned reset_counter; 1042 spinlock_t ring_lock; 1043 struct fence **fences; 1044 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 1045 }; 1046 1047 struct amdgpu_ctx_mgr { 1048 struct amdgpu_device *adev; 1049 struct mutex lock; 1050 /* protected by lock */ 1051 struct idr ctx_handles; 1052 }; 1053 1054 int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri, 1055 struct amdgpu_ctx *ctx); 1056 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx); 1057 1058 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 1059 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 1060 1061 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 1062 struct fence *fence); 1063 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 1064 struct amdgpu_ring *ring, uint64_t seq); 1065 1066 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 1067 struct drm_file *filp); 1068 1069 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1070 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 1071 1072 /* 1073 * file private structure 1074 */ 1075 1076 struct amdgpu_fpriv { 1077 struct amdgpu_vm vm; 1078 struct mutex bo_list_lock; 1079 struct idr bo_list_handles; 1080 struct amdgpu_ctx_mgr ctx_mgr; 1081 }; 1082 1083 /* 1084 * residency list 1085 */ 1086 1087 struct amdgpu_bo_list { 1088 struct mutex lock; 1089 struct amdgpu_bo *gds_obj; 1090 struct amdgpu_bo *gws_obj; 1091 struct amdgpu_bo *oa_obj; 1092 bool has_userptr; 1093 unsigned num_entries; 1094 struct amdgpu_bo_list_entry *array; 1095 }; 1096 1097 struct amdgpu_bo_list * 1098 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1099 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1100 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1101 1102 /* 1103 * GFX stuff 1104 */ 1105 #include "clearstate_defs.h" 1106 1107 struct amdgpu_rlc { 1108 /* for power gating */ 1109 struct amdgpu_bo *save_restore_obj; 1110 uint64_t save_restore_gpu_addr; 1111 volatile uint32_t *sr_ptr; 1112 const u32 *reg_list; 1113 u32 reg_list_size; 1114 /* for clear state */ 1115 struct amdgpu_bo *clear_state_obj; 1116 uint64_t clear_state_gpu_addr; 1117 volatile uint32_t *cs_ptr; 1118 const struct cs_section_def *cs_data; 1119 u32 clear_state_size; 1120 /* for cp tables */ 1121 struct amdgpu_bo *cp_table_obj; 1122 uint64_t cp_table_gpu_addr; 1123 volatile uint32_t *cp_table_ptr; 1124 u32 cp_table_size; 1125 }; 1126 1127 struct amdgpu_mec { 1128 struct amdgpu_bo *hpd_eop_obj; 1129 u64 hpd_eop_gpu_addr; 1130 u32 num_pipe; 1131 u32 num_mec; 1132 u32 num_queue; 1133 }; 1134 1135 /* 1136 * GPU scratch registers structures, functions & helpers 1137 */ 1138 struct amdgpu_scratch { 1139 unsigned num_reg; 1140 uint32_t reg_base; 1141 bool free[32]; 1142 uint32_t reg[32]; 1143 }; 1144 1145 /* 1146 * GFX configurations 1147 */ 1148 struct amdgpu_gca_config { 1149 unsigned max_shader_engines; 1150 unsigned max_tile_pipes; 1151 unsigned max_cu_per_sh; 1152 unsigned max_sh_per_se; 1153 unsigned max_backends_per_se; 1154 unsigned max_texture_channel_caches; 1155 unsigned max_gprs; 1156 unsigned max_gs_threads; 1157 unsigned max_hw_contexts; 1158 unsigned sc_prim_fifo_size_frontend; 1159 unsigned sc_prim_fifo_size_backend; 1160 unsigned sc_hiz_tile_fifo_size; 1161 unsigned sc_earlyz_tile_fifo_size; 1162 1163 unsigned num_tile_pipes; 1164 unsigned backend_enable_mask; 1165 unsigned mem_max_burst_length_bytes; 1166 unsigned mem_row_size_in_kb; 1167 unsigned shader_engine_tile_size; 1168 unsigned num_gpus; 1169 unsigned multi_gpu_tile_size; 1170 unsigned mc_arb_ramcfg; 1171 unsigned gb_addr_config; 1172 1173 uint32_t tile_mode_array[32]; 1174 uint32_t macrotile_mode_array[16]; 1175 }; 1176 1177 struct amdgpu_gfx { 1178 struct mutex gpu_clock_mutex; 1179 struct amdgpu_gca_config config; 1180 struct amdgpu_rlc rlc; 1181 struct amdgpu_mec mec; 1182 struct amdgpu_scratch scratch; 1183 const struct firmware *me_fw; /* ME firmware */ 1184 uint32_t me_fw_version; 1185 const struct firmware *pfp_fw; /* PFP firmware */ 1186 uint32_t pfp_fw_version; 1187 const struct firmware *ce_fw; /* CE firmware */ 1188 uint32_t ce_fw_version; 1189 const struct firmware *rlc_fw; /* RLC firmware */ 1190 uint32_t rlc_fw_version; 1191 const struct firmware *mec_fw; /* MEC firmware */ 1192 uint32_t mec_fw_version; 1193 const struct firmware *mec2_fw; /* MEC2 firmware */ 1194 uint32_t mec2_fw_version; 1195 uint32_t me_feature_version; 1196 uint32_t ce_feature_version; 1197 uint32_t pfp_feature_version; 1198 uint32_t rlc_feature_version; 1199 uint32_t mec_feature_version; 1200 uint32_t mec2_feature_version; 1201 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1202 unsigned num_gfx_rings; 1203 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1204 unsigned num_compute_rings; 1205 struct amdgpu_irq_src eop_irq; 1206 struct amdgpu_irq_src priv_reg_irq; 1207 struct amdgpu_irq_src priv_inst_irq; 1208 /* gfx status */ 1209 uint32_t gfx_current_status; 1210 /* ce ram size*/ 1211 unsigned ce_ram_size; 1212 }; 1213 1214 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, 1215 unsigned size, struct amdgpu_ib *ib); 1216 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib); 1217 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, 1218 struct amdgpu_ib *ib, void *owner); 1219 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1220 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1221 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1222 /* Ring access between begin & end cannot sleep */ 1223 void amdgpu_ring_free_size(struct amdgpu_ring *ring); 1224 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1225 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw); 1226 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 1227 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1228 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); 1229 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1230 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); 1231 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1232 uint32_t **data); 1233 int amdgpu_ring_restore(struct amdgpu_ring *ring, 1234 unsigned size, uint32_t *data); 1235 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1236 unsigned ring_size, u32 nop, u32 align_mask, 1237 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1238 enum amdgpu_ring_type ring_type); 1239 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1240 struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f); 1241 1242 /* 1243 * CS. 1244 */ 1245 struct amdgpu_cs_chunk { 1246 uint32_t chunk_id; 1247 uint32_t length_dw; 1248 uint32_t *kdata; 1249 void __user *user_ptr; 1250 }; 1251 1252 struct amdgpu_cs_parser { 1253 struct amdgpu_device *adev; 1254 struct drm_file *filp; 1255 struct amdgpu_ctx *ctx; 1256 struct amdgpu_bo_list *bo_list; 1257 /* chunks */ 1258 unsigned nchunks; 1259 struct amdgpu_cs_chunk *chunks; 1260 /* relocations */ 1261 struct amdgpu_bo_list_entry vm_pd; 1262 struct list_head validated; 1263 struct fence *fence; 1264 1265 struct amdgpu_ib *ibs; 1266 uint32_t num_ibs; 1267 1268 struct ww_acquire_ctx ticket; 1269 1270 /* user fence */ 1271 struct amdgpu_user_fence uf; 1272 struct amdgpu_bo_list_entry uf_entry; 1273 }; 1274 1275 struct amdgpu_job { 1276 struct amd_sched_job base; 1277 struct amdgpu_device *adev; 1278 struct amdgpu_ib *ibs; 1279 uint32_t num_ibs; 1280 void *owner; 1281 struct amdgpu_user_fence uf; 1282 int (*free_job)(struct amdgpu_job *job); 1283 }; 1284 #define to_amdgpu_job(sched_job) \ 1285 container_of((sched_job), struct amdgpu_job, base) 1286 1287 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx) 1288 { 1289 return p->ibs[ib_idx].ptr[idx]; 1290 } 1291 1292 /* 1293 * Writeback 1294 */ 1295 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1296 1297 struct amdgpu_wb { 1298 struct amdgpu_bo *wb_obj; 1299 volatile uint32_t *wb; 1300 uint64_t gpu_addr; 1301 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1302 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1303 }; 1304 1305 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1306 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1307 1308 1309 1310 enum amdgpu_int_thermal_type { 1311 THERMAL_TYPE_NONE, 1312 THERMAL_TYPE_EXTERNAL, 1313 THERMAL_TYPE_EXTERNAL_GPIO, 1314 THERMAL_TYPE_RV6XX, 1315 THERMAL_TYPE_RV770, 1316 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1317 THERMAL_TYPE_EVERGREEN, 1318 THERMAL_TYPE_SUMO, 1319 THERMAL_TYPE_NI, 1320 THERMAL_TYPE_SI, 1321 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1322 THERMAL_TYPE_CI, 1323 THERMAL_TYPE_KV, 1324 }; 1325 1326 enum amdgpu_dpm_auto_throttle_src { 1327 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1328 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1329 }; 1330 1331 enum amdgpu_dpm_event_src { 1332 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1333 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1334 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1335 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1336 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1337 }; 1338 1339 #define AMDGPU_MAX_VCE_LEVELS 6 1340 1341 enum amdgpu_vce_level { 1342 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1343 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1344 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1345 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1346 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1347 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1348 }; 1349 1350 struct amdgpu_ps { 1351 u32 caps; /* vbios flags */ 1352 u32 class; /* vbios flags */ 1353 u32 class2; /* vbios flags */ 1354 /* UVD clocks */ 1355 u32 vclk; 1356 u32 dclk; 1357 /* VCE clocks */ 1358 u32 evclk; 1359 u32 ecclk; 1360 bool vce_active; 1361 enum amdgpu_vce_level vce_level; 1362 /* asic priv */ 1363 void *ps_priv; 1364 }; 1365 1366 struct amdgpu_dpm_thermal { 1367 /* thermal interrupt work */ 1368 struct work_struct work; 1369 /* low temperature threshold */ 1370 int min_temp; 1371 /* high temperature threshold */ 1372 int max_temp; 1373 /* was last interrupt low to high or high to low */ 1374 bool high_to_low; 1375 /* interrupt source */ 1376 struct amdgpu_irq_src irq; 1377 }; 1378 1379 enum amdgpu_clk_action 1380 { 1381 AMDGPU_SCLK_UP = 1, 1382 AMDGPU_SCLK_DOWN 1383 }; 1384 1385 struct amdgpu_blacklist_clocks 1386 { 1387 u32 sclk; 1388 u32 mclk; 1389 enum amdgpu_clk_action action; 1390 }; 1391 1392 struct amdgpu_clock_and_voltage_limits { 1393 u32 sclk; 1394 u32 mclk; 1395 u16 vddc; 1396 u16 vddci; 1397 }; 1398 1399 struct amdgpu_clock_array { 1400 u32 count; 1401 u32 *values; 1402 }; 1403 1404 struct amdgpu_clock_voltage_dependency_entry { 1405 u32 clk; 1406 u16 v; 1407 }; 1408 1409 struct amdgpu_clock_voltage_dependency_table { 1410 u32 count; 1411 struct amdgpu_clock_voltage_dependency_entry *entries; 1412 }; 1413 1414 union amdgpu_cac_leakage_entry { 1415 struct { 1416 u16 vddc; 1417 u32 leakage; 1418 }; 1419 struct { 1420 u16 vddc1; 1421 u16 vddc2; 1422 u16 vddc3; 1423 }; 1424 }; 1425 1426 struct amdgpu_cac_leakage_table { 1427 u32 count; 1428 union amdgpu_cac_leakage_entry *entries; 1429 }; 1430 1431 struct amdgpu_phase_shedding_limits_entry { 1432 u16 voltage; 1433 u32 sclk; 1434 u32 mclk; 1435 }; 1436 1437 struct amdgpu_phase_shedding_limits_table { 1438 u32 count; 1439 struct amdgpu_phase_shedding_limits_entry *entries; 1440 }; 1441 1442 struct amdgpu_uvd_clock_voltage_dependency_entry { 1443 u32 vclk; 1444 u32 dclk; 1445 u16 v; 1446 }; 1447 1448 struct amdgpu_uvd_clock_voltage_dependency_table { 1449 u8 count; 1450 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1451 }; 1452 1453 struct amdgpu_vce_clock_voltage_dependency_entry { 1454 u32 ecclk; 1455 u32 evclk; 1456 u16 v; 1457 }; 1458 1459 struct amdgpu_vce_clock_voltage_dependency_table { 1460 u8 count; 1461 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1462 }; 1463 1464 struct amdgpu_ppm_table { 1465 u8 ppm_design; 1466 u16 cpu_core_number; 1467 u32 platform_tdp; 1468 u32 small_ac_platform_tdp; 1469 u32 platform_tdc; 1470 u32 small_ac_platform_tdc; 1471 u32 apu_tdp; 1472 u32 dgpu_tdp; 1473 u32 dgpu_ulv_power; 1474 u32 tj_max; 1475 }; 1476 1477 struct amdgpu_cac_tdp_table { 1478 u16 tdp; 1479 u16 configurable_tdp; 1480 u16 tdc; 1481 u16 battery_power_limit; 1482 u16 small_power_limit; 1483 u16 low_cac_leakage; 1484 u16 high_cac_leakage; 1485 u16 maximum_power_delivery_limit; 1486 }; 1487 1488 struct amdgpu_dpm_dynamic_state { 1489 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1490 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1491 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1492 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1493 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1494 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1495 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1496 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1497 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1498 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1499 struct amdgpu_clock_array valid_sclk_values; 1500 struct amdgpu_clock_array valid_mclk_values; 1501 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1502 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1503 u32 mclk_sclk_ratio; 1504 u32 sclk_mclk_delta; 1505 u16 vddc_vddci_delta; 1506 u16 min_vddc_for_pcie_gen2; 1507 struct amdgpu_cac_leakage_table cac_leakage_table; 1508 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1509 struct amdgpu_ppm_table *ppm_table; 1510 struct amdgpu_cac_tdp_table *cac_tdp_table; 1511 }; 1512 1513 struct amdgpu_dpm_fan { 1514 u16 t_min; 1515 u16 t_med; 1516 u16 t_high; 1517 u16 pwm_min; 1518 u16 pwm_med; 1519 u16 pwm_high; 1520 u8 t_hyst; 1521 u32 cycle_delay; 1522 u16 t_max; 1523 u8 control_mode; 1524 u16 default_max_fan_pwm; 1525 u16 default_fan_output_sensitivity; 1526 u16 fan_output_sensitivity; 1527 bool ucode_fan_control; 1528 }; 1529 1530 enum amdgpu_pcie_gen { 1531 AMDGPU_PCIE_GEN1 = 0, 1532 AMDGPU_PCIE_GEN2 = 1, 1533 AMDGPU_PCIE_GEN3 = 2, 1534 AMDGPU_PCIE_GEN_INVALID = 0xffff 1535 }; 1536 1537 enum amdgpu_dpm_forced_level { 1538 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1539 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1540 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1541 }; 1542 1543 struct amdgpu_vce_state { 1544 /* vce clocks */ 1545 u32 evclk; 1546 u32 ecclk; 1547 /* gpu clocks */ 1548 u32 sclk; 1549 u32 mclk; 1550 u8 clk_idx; 1551 u8 pstate; 1552 }; 1553 1554 struct amdgpu_dpm_funcs { 1555 int (*get_temperature)(struct amdgpu_device *adev); 1556 int (*pre_set_power_state)(struct amdgpu_device *adev); 1557 int (*set_power_state)(struct amdgpu_device *adev); 1558 void (*post_set_power_state)(struct amdgpu_device *adev); 1559 void (*display_configuration_changed)(struct amdgpu_device *adev); 1560 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1561 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1562 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1563 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1564 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1565 bool (*vblank_too_short)(struct amdgpu_device *adev); 1566 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1567 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1568 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1569 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1570 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1571 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1572 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1573 }; 1574 1575 struct amdgpu_dpm { 1576 struct amdgpu_ps *ps; 1577 /* number of valid power states */ 1578 int num_ps; 1579 /* current power state that is active */ 1580 struct amdgpu_ps *current_ps; 1581 /* requested power state */ 1582 struct amdgpu_ps *requested_ps; 1583 /* boot up power state */ 1584 struct amdgpu_ps *boot_ps; 1585 /* default uvd power state */ 1586 struct amdgpu_ps *uvd_ps; 1587 /* vce requirements */ 1588 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1589 enum amdgpu_vce_level vce_level; 1590 enum amd_pm_state_type state; 1591 enum amd_pm_state_type user_state; 1592 u32 platform_caps; 1593 u32 voltage_response_time; 1594 u32 backbias_response_time; 1595 void *priv; 1596 u32 new_active_crtcs; 1597 int new_active_crtc_count; 1598 u32 current_active_crtcs; 1599 int current_active_crtc_count; 1600 struct amdgpu_dpm_dynamic_state dyn_state; 1601 struct amdgpu_dpm_fan fan; 1602 u32 tdp_limit; 1603 u32 near_tdp_limit; 1604 u32 near_tdp_limit_adjusted; 1605 u32 sq_ramping_threshold; 1606 u32 cac_leakage; 1607 u16 tdp_od_limit; 1608 u32 tdp_adjustment; 1609 u16 load_line_slope; 1610 bool power_control; 1611 bool ac_power; 1612 /* special states active */ 1613 bool thermal_active; 1614 bool uvd_active; 1615 bool vce_active; 1616 /* thermal handling */ 1617 struct amdgpu_dpm_thermal thermal; 1618 /* forced levels */ 1619 enum amdgpu_dpm_forced_level forced_level; 1620 }; 1621 1622 struct amdgpu_pm { 1623 struct mutex mutex; 1624 u32 current_sclk; 1625 u32 current_mclk; 1626 u32 default_sclk; 1627 u32 default_mclk; 1628 struct amdgpu_i2c_chan *i2c_bus; 1629 /* internal thermal controller on rv6xx+ */ 1630 enum amdgpu_int_thermal_type int_thermal_type; 1631 struct device *int_hwmon_dev; 1632 /* fan control parameters */ 1633 bool no_fan; 1634 u8 fan_pulses_per_revolution; 1635 u8 fan_min_rpm; 1636 u8 fan_max_rpm; 1637 /* dpm */ 1638 bool dpm_enabled; 1639 bool sysfs_initialized; 1640 struct amdgpu_dpm dpm; 1641 const struct firmware *fw; /* SMC firmware */ 1642 uint32_t fw_version; 1643 const struct amdgpu_dpm_funcs *funcs; 1644 uint32_t pcie_gen_mask; 1645 uint32_t pcie_mlw_mask; 1646 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ 1647 }; 1648 1649 void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1650 1651 /* 1652 * UVD 1653 */ 1654 #define AMDGPU_MAX_UVD_HANDLES 10 1655 #define AMDGPU_UVD_STACK_SIZE (1024*1024) 1656 #define AMDGPU_UVD_HEAP_SIZE (1024*1024) 1657 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1658 1659 struct amdgpu_uvd { 1660 struct amdgpu_bo *vcpu_bo; 1661 void *cpu_addr; 1662 uint64_t gpu_addr; 1663 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1664 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1665 struct delayed_work idle_work; 1666 const struct firmware *fw; /* UVD firmware */ 1667 struct amdgpu_ring ring; 1668 struct amdgpu_irq_src irq; 1669 bool address_64_bit; 1670 }; 1671 1672 /* 1673 * VCE 1674 */ 1675 #define AMDGPU_MAX_VCE_HANDLES 16 1676 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1677 1678 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1679 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1680 1681 struct amdgpu_vce { 1682 struct amdgpu_bo *vcpu_bo; 1683 uint64_t gpu_addr; 1684 unsigned fw_version; 1685 unsigned fb_version; 1686 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1687 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1688 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1689 struct delayed_work idle_work; 1690 const struct firmware *fw; /* VCE firmware */ 1691 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1692 struct amdgpu_irq_src irq; 1693 unsigned harvest_config; 1694 }; 1695 1696 /* 1697 * SDMA 1698 */ 1699 struct amdgpu_sdma_instance { 1700 /* SDMA firmware */ 1701 const struct firmware *fw; 1702 uint32_t fw_version; 1703 uint32_t feature_version; 1704 1705 struct amdgpu_ring ring; 1706 bool burst_nop; 1707 }; 1708 1709 struct amdgpu_sdma { 1710 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1711 struct amdgpu_irq_src trap_irq; 1712 struct amdgpu_irq_src illegal_inst_irq; 1713 int num_instances; 1714 }; 1715 1716 /* 1717 * Firmware 1718 */ 1719 struct amdgpu_firmware { 1720 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1721 bool smu_load; 1722 struct amdgpu_bo *fw_buf; 1723 unsigned int fw_size; 1724 }; 1725 1726 /* 1727 * Benchmarking 1728 */ 1729 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1730 1731 1732 /* 1733 * Testing 1734 */ 1735 void amdgpu_test_moves(struct amdgpu_device *adev); 1736 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1737 struct amdgpu_ring *cpA, 1738 struct amdgpu_ring *cpB); 1739 void amdgpu_test_syncing(struct amdgpu_device *adev); 1740 1741 /* 1742 * MMU Notifier 1743 */ 1744 #if defined(CONFIG_MMU_NOTIFIER) 1745 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1746 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1747 #else 1748 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1749 { 1750 return -ENODEV; 1751 } 1752 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1753 #endif 1754 1755 /* 1756 * Debugfs 1757 */ 1758 struct amdgpu_debugfs { 1759 struct drm_info_list *files; 1760 unsigned num_files; 1761 }; 1762 1763 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1764 struct drm_info_list *files, 1765 unsigned nfiles); 1766 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1767 1768 #if defined(CONFIG_DEBUG_FS) 1769 int amdgpu_debugfs_init(struct drm_minor *minor); 1770 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1771 #endif 1772 1773 /* 1774 * amdgpu smumgr functions 1775 */ 1776 struct amdgpu_smumgr_funcs { 1777 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1778 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1779 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1780 }; 1781 1782 /* 1783 * amdgpu smumgr 1784 */ 1785 struct amdgpu_smumgr { 1786 struct amdgpu_bo *toc_buf; 1787 struct amdgpu_bo *smu_buf; 1788 /* asic priv smu data */ 1789 void *priv; 1790 spinlock_t smu_lock; 1791 /* smumgr functions */ 1792 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1793 /* ucode loading complete flag */ 1794 uint32_t fw_flags; 1795 }; 1796 1797 /* 1798 * ASIC specific register table accessible by UMD 1799 */ 1800 struct amdgpu_allowed_register_entry { 1801 uint32_t reg_offset; 1802 bool untouched; 1803 bool grbm_indexed; 1804 }; 1805 1806 struct amdgpu_cu_info { 1807 uint32_t number; /* total active CU number */ 1808 uint32_t ao_cu_mask; 1809 uint32_t bitmap[4][4]; 1810 }; 1811 1812 1813 /* 1814 * ASIC specific functions. 1815 */ 1816 struct amdgpu_asic_funcs { 1817 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1818 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1819 u8 *bios, u32 length_bytes); 1820 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1821 u32 sh_num, u32 reg_offset, u32 *value); 1822 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1823 int (*reset)(struct amdgpu_device *adev); 1824 /* wait for mc_idle */ 1825 int (*wait_for_mc_idle)(struct amdgpu_device *adev); 1826 /* get the reference clock */ 1827 u32 (*get_xclk)(struct amdgpu_device *adev); 1828 /* get the gpu clock counter */ 1829 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1830 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); 1831 /* MM block clocks */ 1832 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1833 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1834 }; 1835 1836 /* 1837 * IOCTL. 1838 */ 1839 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1840 struct drm_file *filp); 1841 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1842 struct drm_file *filp); 1843 1844 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1845 struct drm_file *filp); 1846 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1847 struct drm_file *filp); 1848 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1849 struct drm_file *filp); 1850 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1851 struct drm_file *filp); 1852 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1853 struct drm_file *filp); 1854 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1855 struct drm_file *filp); 1856 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1857 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1858 1859 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1860 struct drm_file *filp); 1861 1862 /* VRAM scratch page for HDP bug, default vram page */ 1863 struct amdgpu_vram_scratch { 1864 struct amdgpu_bo *robj; 1865 volatile uint32_t *ptr; 1866 u64 gpu_addr; 1867 }; 1868 1869 /* 1870 * ACPI 1871 */ 1872 struct amdgpu_atif_notification_cfg { 1873 bool enabled; 1874 int command_code; 1875 }; 1876 1877 struct amdgpu_atif_notifications { 1878 bool display_switch; 1879 bool expansion_mode_change; 1880 bool thermal_state; 1881 bool forced_power_state; 1882 bool system_power_state; 1883 bool display_conf_change; 1884 bool px_gfx_switch; 1885 bool brightness_change; 1886 bool dgpu_display_event; 1887 }; 1888 1889 struct amdgpu_atif_functions { 1890 bool system_params; 1891 bool sbios_requests; 1892 bool select_active_disp; 1893 bool lid_state; 1894 bool get_tv_standard; 1895 bool set_tv_standard; 1896 bool get_panel_expansion_mode; 1897 bool set_panel_expansion_mode; 1898 bool temperature_change; 1899 bool graphics_device_types; 1900 }; 1901 1902 struct amdgpu_atif { 1903 struct amdgpu_atif_notifications notifications; 1904 struct amdgpu_atif_functions functions; 1905 struct amdgpu_atif_notification_cfg notification_cfg; 1906 struct amdgpu_encoder *encoder_for_bl; 1907 }; 1908 1909 struct amdgpu_atcs_functions { 1910 bool get_ext_state; 1911 bool pcie_perf_req; 1912 bool pcie_dev_rdy; 1913 bool pcie_bus_width; 1914 }; 1915 1916 struct amdgpu_atcs { 1917 struct amdgpu_atcs_functions functions; 1918 }; 1919 1920 /* 1921 * CGS 1922 */ 1923 void *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1924 void amdgpu_cgs_destroy_device(void *cgs_device); 1925 1926 1927 /* 1928 * Core structure, functions and helpers. 1929 */ 1930 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1931 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1932 1933 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1934 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1935 1936 struct amdgpu_ip_block_status { 1937 bool valid; 1938 bool sw; 1939 bool hw; 1940 }; 1941 1942 struct amdgpu_device { 1943 struct device *dev; 1944 struct drm_device *ddev; 1945 struct pci_dev *pdev; 1946 1947 /* ASIC */ 1948 enum amd_asic_type asic_type; 1949 uint32_t family; 1950 uint32_t rev_id; 1951 uint32_t external_rev_id; 1952 unsigned long flags; 1953 int usec_timeout; 1954 const struct amdgpu_asic_funcs *asic_funcs; 1955 bool shutdown; 1956 bool suspend; 1957 bool need_dma32; 1958 bool accel_working; 1959 struct work_struct reset_work; 1960 struct notifier_block acpi_nb; 1961 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1962 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1963 unsigned debugfs_count; 1964 #if defined(CONFIG_DEBUG_FS) 1965 struct dentry *debugfs_regs; 1966 #endif 1967 struct amdgpu_atif atif; 1968 struct amdgpu_atcs atcs; 1969 struct mutex srbm_mutex; 1970 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1971 struct mutex grbm_idx_mutex; 1972 struct dev_pm_domain vga_pm_domain; 1973 bool have_disp_power_ref; 1974 1975 /* BIOS */ 1976 uint8_t *bios; 1977 bool is_atom_bios; 1978 uint16_t bios_header_start; 1979 struct amdgpu_bo *stollen_vga_memory; 1980 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1981 1982 /* Register/doorbell mmio */ 1983 resource_size_t rmmio_base; 1984 resource_size_t rmmio_size; 1985 void __iomem *rmmio; 1986 /* protects concurrent MM_INDEX/DATA based register access */ 1987 spinlock_t mmio_idx_lock; 1988 /* protects concurrent SMC based register access */ 1989 spinlock_t smc_idx_lock; 1990 amdgpu_rreg_t smc_rreg; 1991 amdgpu_wreg_t smc_wreg; 1992 /* protects concurrent PCIE register access */ 1993 spinlock_t pcie_idx_lock; 1994 amdgpu_rreg_t pcie_rreg; 1995 amdgpu_wreg_t pcie_wreg; 1996 /* protects concurrent UVD register access */ 1997 spinlock_t uvd_ctx_idx_lock; 1998 amdgpu_rreg_t uvd_ctx_rreg; 1999 amdgpu_wreg_t uvd_ctx_wreg; 2000 /* protects concurrent DIDT register access */ 2001 spinlock_t didt_idx_lock; 2002 amdgpu_rreg_t didt_rreg; 2003 amdgpu_wreg_t didt_wreg; 2004 /* protects concurrent ENDPOINT (audio) register access */ 2005 spinlock_t audio_endpt_idx_lock; 2006 amdgpu_block_rreg_t audio_endpt_rreg; 2007 amdgpu_block_wreg_t audio_endpt_wreg; 2008 void __iomem *rio_mem; 2009 resource_size_t rio_mem_size; 2010 struct amdgpu_doorbell doorbell; 2011 2012 /* clock/pll info */ 2013 struct amdgpu_clock clock; 2014 2015 /* MC */ 2016 struct amdgpu_mc mc; 2017 struct amdgpu_gart gart; 2018 struct amdgpu_dummy_page dummy_page; 2019 struct amdgpu_vm_manager vm_manager; 2020 2021 /* memory management */ 2022 struct amdgpu_mman mman; 2023 struct amdgpu_gem gem; 2024 struct amdgpu_vram_scratch vram_scratch; 2025 struct amdgpu_wb wb; 2026 atomic64_t vram_usage; 2027 atomic64_t vram_vis_usage; 2028 atomic64_t gtt_usage; 2029 atomic64_t num_bytes_moved; 2030 atomic_t gpu_reset_counter; 2031 2032 /* display */ 2033 struct amdgpu_mode_info mode_info; 2034 struct work_struct hotplug_work; 2035 struct amdgpu_irq_src crtc_irq; 2036 struct amdgpu_irq_src pageflip_irq; 2037 struct amdgpu_irq_src hpd_irq; 2038 2039 /* rings */ 2040 unsigned fence_context; 2041 struct mutex ring_lock; 2042 unsigned num_rings; 2043 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 2044 bool ib_pool_ready; 2045 struct amdgpu_sa_manager ring_tmp_bo; 2046 2047 /* interrupts */ 2048 struct amdgpu_irq irq; 2049 2050 /* powerplay */ 2051 struct amd_powerplay powerplay; 2052 bool pp_enabled; 2053 2054 /* dpm */ 2055 struct amdgpu_pm pm; 2056 u32 cg_flags; 2057 u32 pg_flags; 2058 2059 /* amdgpu smumgr */ 2060 struct amdgpu_smumgr smu; 2061 2062 /* gfx */ 2063 struct amdgpu_gfx gfx; 2064 2065 /* sdma */ 2066 struct amdgpu_sdma sdma; 2067 2068 /* uvd */ 2069 bool has_uvd; 2070 struct amdgpu_uvd uvd; 2071 2072 /* vce */ 2073 struct amdgpu_vce vce; 2074 2075 /* firmwares */ 2076 struct amdgpu_firmware firmware; 2077 2078 /* GDS */ 2079 struct amdgpu_gds gds; 2080 2081 const struct amdgpu_ip_block_version *ip_blocks; 2082 int num_ip_blocks; 2083 struct amdgpu_ip_block_status *ip_block_status; 2084 struct mutex mn_lock; 2085 DECLARE_HASHTABLE(mn_hash, 7); 2086 2087 /* tracking pinned memory */ 2088 u64 vram_pin_size; 2089 u64 gart_pin_size; 2090 2091 /* amdkfd interface */ 2092 struct kfd_dev *kfd; 2093 2094 /* kernel conext for IB submission */ 2095 struct amdgpu_ctx kernel_ctx; 2096 }; 2097 2098 bool amdgpu_device_is_px(struct drm_device *dev); 2099 int amdgpu_device_init(struct amdgpu_device *adev, 2100 struct drm_device *ddev, 2101 struct pci_dev *pdev, 2102 uint32_t flags); 2103 void amdgpu_device_fini(struct amdgpu_device *adev); 2104 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2105 2106 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2107 bool always_indirect); 2108 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2109 bool always_indirect); 2110 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2111 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2112 2113 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2114 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2115 2116 /* 2117 * Cast helper 2118 */ 2119 extern const struct fence_ops amdgpu_fence_ops; 2120 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) 2121 { 2122 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 2123 2124 if (__f->base.ops == &amdgpu_fence_ops) 2125 return __f; 2126 2127 return NULL; 2128 } 2129 2130 /* 2131 * Registers read & write functions. 2132 */ 2133 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2134 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2135 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2136 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2137 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2138 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2139 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2140 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2141 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2142 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2143 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2144 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2145 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2146 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2147 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2148 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2149 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2150 #define WREG32_P(reg, val, mask) \ 2151 do { \ 2152 uint32_t tmp_ = RREG32(reg); \ 2153 tmp_ &= (mask); \ 2154 tmp_ |= ((val) & ~(mask)); \ 2155 WREG32(reg, tmp_); \ 2156 } while (0) 2157 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2158 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2159 #define WREG32_PLL_P(reg, val, mask) \ 2160 do { \ 2161 uint32_t tmp_ = RREG32_PLL(reg); \ 2162 tmp_ &= (mask); \ 2163 tmp_ |= ((val) & ~(mask)); \ 2164 WREG32_PLL(reg, tmp_); \ 2165 } while (0) 2166 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2167 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2168 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2169 2170 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2171 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2172 2173 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2174 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2175 2176 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2177 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2178 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2179 2180 #define REG_GET_FIELD(value, reg, field) \ 2181 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2182 2183 /* 2184 * BIOS helpers. 2185 */ 2186 #define RBIOS8(i) (adev->bios[i]) 2187 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2188 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2189 2190 /* 2191 * RING helpers. 2192 */ 2193 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2194 { 2195 if (ring->count_dw <= 0) 2196 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2197 ring->ring[ring->wptr++] = v; 2198 ring->wptr &= ring->ptr_mask; 2199 ring->count_dw--; 2200 ring->ring_free_dw--; 2201 } 2202 2203 static inline struct amdgpu_sdma_instance * 2204 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 2205 { 2206 struct amdgpu_device *adev = ring->adev; 2207 int i; 2208 2209 for (i = 0; i < adev->sdma.num_instances; i++) 2210 if (&adev->sdma.instance[i].ring == ring) 2211 break; 2212 2213 if (i < AMDGPU_MAX_SDMA_INSTANCES) 2214 return &adev->sdma.instance[i]; 2215 else 2216 return NULL; 2217 } 2218 2219 /* 2220 * ASICs macro. 2221 */ 2222 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2223 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2224 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) 2225 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2226 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2227 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2228 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2229 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2230 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 2231 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2232 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) 2233 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2234 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2235 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2236 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags))) 2237 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2238 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib))) 2239 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2240 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2241 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2242 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2243 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2244 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2245 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) 2246 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2247 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2248 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) 2249 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2250 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2251 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2252 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2253 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2254 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2255 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2256 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2257 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2258 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2259 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2260 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2261 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2262 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2263 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2264 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) 2265 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2266 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2267 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2268 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2269 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2270 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 2271 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 2272 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2273 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2274 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2275 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2276 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2277 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2278 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2279 2280 #define amdgpu_dpm_get_temperature(adev) \ 2281 (adev)->pp_enabled ? \ 2282 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ 2283 (adev)->pm.funcs->get_temperature((adev)) 2284 2285 #define amdgpu_dpm_set_fan_control_mode(adev, m) \ 2286 (adev)->pp_enabled ? \ 2287 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ 2288 (adev)->pm.funcs->set_fan_control_mode((adev), (m)) 2289 2290 #define amdgpu_dpm_get_fan_control_mode(adev) \ 2291 (adev)->pp_enabled ? \ 2292 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ 2293 (adev)->pm.funcs->get_fan_control_mode((adev)) 2294 2295 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ 2296 (adev)->pp_enabled ? \ 2297 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 2298 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)) 2299 2300 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ 2301 (adev)->pp_enabled ? \ 2302 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 2303 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)) 2304 2305 #define amdgpu_dpm_get_sclk(adev, l) \ 2306 (adev)->pp_enabled ? \ 2307 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ 2308 (adev)->pm.funcs->get_sclk((adev), (l)) 2309 2310 #define amdgpu_dpm_get_mclk(adev, l) \ 2311 (adev)->pp_enabled ? \ 2312 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ 2313 (adev)->pm.funcs->get_mclk((adev), (l)) 2314 2315 2316 #define amdgpu_dpm_force_performance_level(adev, l) \ 2317 (adev)->pp_enabled ? \ 2318 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ 2319 (adev)->pm.funcs->force_performance_level((adev), (l)) 2320 2321 #define amdgpu_dpm_powergate_uvd(adev, g) \ 2322 (adev)->pp_enabled ? \ 2323 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ 2324 (adev)->pm.funcs->powergate_uvd((adev), (g)) 2325 2326 #define amdgpu_dpm_powergate_vce(adev, g) \ 2327 (adev)->pp_enabled ? \ 2328 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ 2329 (adev)->pm.funcs->powergate_vce((adev), (g)) 2330 2331 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \ 2332 (adev)->pp_enabled ? \ 2333 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \ 2334 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)) 2335 2336 #define amdgpu_dpm_get_current_power_state(adev) \ 2337 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) 2338 2339 #define amdgpu_dpm_get_performance_level(adev) \ 2340 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) 2341 2342 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ 2343 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) 2344 2345 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2346 2347 /* Common functions */ 2348 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2349 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2350 bool amdgpu_card_posted(struct amdgpu_device *adev); 2351 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2352 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev); 2353 2354 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2355 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2356 u32 ip_instance, u32 ring, 2357 struct amdgpu_ring **out_ring); 2358 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2359 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2360 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2361 uint32_t flags); 2362 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2363 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2364 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2365 struct ttm_mem_reg *mem); 2366 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2367 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2368 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2369 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2370 const u32 *registers, 2371 const u32 array_size); 2372 2373 bool amdgpu_device_is_px(struct drm_device *dev); 2374 /* atpx handler */ 2375 #if defined(CONFIG_VGA_SWITCHEROO) 2376 void amdgpu_register_atpx_handler(void); 2377 void amdgpu_unregister_atpx_handler(void); 2378 #else 2379 static inline void amdgpu_register_atpx_handler(void) {} 2380 static inline void amdgpu_unregister_atpx_handler(void) {} 2381 #endif 2382 2383 /* 2384 * KMS 2385 */ 2386 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2387 extern int amdgpu_max_kms_ioctl; 2388 2389 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2390 int amdgpu_driver_unload_kms(struct drm_device *dev); 2391 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2392 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2393 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2394 struct drm_file *file_priv); 2395 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2396 struct drm_file *file_priv); 2397 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2398 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2399 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 2400 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2401 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2402 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 2403 int *max_error, 2404 struct timeval *vblank_time, 2405 unsigned flags); 2406 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2407 unsigned long arg); 2408 2409 /* 2410 * functions used by amdgpu_encoder.c 2411 */ 2412 struct amdgpu_afmt_acr { 2413 u32 clock; 2414 2415 int n_32khz; 2416 int cts_32khz; 2417 2418 int n_44_1khz; 2419 int cts_44_1khz; 2420 2421 int n_48khz; 2422 int cts_48khz; 2423 2424 }; 2425 2426 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2427 2428 /* amdgpu_acpi.c */ 2429 #if defined(CONFIG_ACPI) 2430 int amdgpu_acpi_init(struct amdgpu_device *adev); 2431 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2432 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2433 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2434 u8 perf_req, bool advertise); 2435 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2436 #else 2437 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2438 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2439 #endif 2440 2441 struct amdgpu_bo_va_mapping * 2442 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2443 uint64_t addr, struct amdgpu_bo **bo); 2444 2445 #include "amdgpu_object.h" 2446 2447 #endif 2448