1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include "amdgpu_ctx.h" 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/rbtree.h> 38 #include <linux/hashtable.h> 39 #include <linux/dma-fence.h> 40 41 #include <drm/ttm/ttm_bo_api.h> 42 #include <drm/ttm/ttm_bo_driver.h> 43 #include <drm/ttm/ttm_placement.h> 44 #include <drm/ttm/ttm_module.h> 45 #include <drm/ttm/ttm_execbuf_util.h> 46 47 #include <drm/drmP.h> 48 #include <drm/drm_gem.h> 49 #include <drm/amdgpu_drm.h> 50 #include <drm/gpu_scheduler.h> 51 52 #include <kgd_kfd_interface.h> 53 #include "dm_pp_interface.h" 54 #include "kgd_pp_interface.h" 55 56 #include "amd_shared.h" 57 #include "amdgpu_mode.h" 58 #include "amdgpu_ih.h" 59 #include "amdgpu_irq.h" 60 #include "amdgpu_ucode.h" 61 #include "amdgpu_ttm.h" 62 #include "amdgpu_psp.h" 63 #include "amdgpu_gds.h" 64 #include "amdgpu_sync.h" 65 #include "amdgpu_ring.h" 66 #include "amdgpu_vm.h" 67 #include "amdgpu_dpm.h" 68 #include "amdgpu_acp.h" 69 #include "amdgpu_uvd.h" 70 #include "amdgpu_vce.h" 71 #include "amdgpu_vcn.h" 72 #include "amdgpu_mn.h" 73 #include "amdgpu_gmc.h" 74 #include "amdgpu_gfx.h" 75 #include "amdgpu_sdma.h" 76 #include "amdgpu_dm.h" 77 #include "amdgpu_virt.h" 78 #include "amdgpu_csa.h" 79 #include "amdgpu_gart.h" 80 #include "amdgpu_debugfs.h" 81 #include "amdgpu_job.h" 82 #include "amdgpu_bo_list.h" 83 #include "amdgpu_gem.h" 84 #include "amdgpu_doorbell.h" 85 #include "amdgpu_amdkfd.h" 86 #include "amdgpu_smu.h" 87 88 #define MAX_GPU_INSTANCE 16 89 90 struct amdgpu_gpu_instance 91 { 92 struct amdgpu_device *adev; 93 int mgpu_fan_enabled; 94 }; 95 96 struct amdgpu_mgpu_info 97 { 98 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 99 struct mutex mutex; 100 uint32_t num_gpu; 101 uint32_t num_dgpu; 102 uint32_t num_apu; 103 }; 104 105 /* 106 * Modules parameters. 107 */ 108 extern int amdgpu_modeset; 109 extern int amdgpu_vram_limit; 110 extern int amdgpu_vis_vram_limit; 111 extern int amdgpu_gart_size; 112 extern int amdgpu_gtt_size; 113 extern int amdgpu_moverate; 114 extern int amdgpu_benchmarking; 115 extern int amdgpu_testing; 116 extern int amdgpu_audio; 117 extern int amdgpu_disp_priority; 118 extern int amdgpu_hw_i2c; 119 extern int amdgpu_pcie_gen2; 120 extern int amdgpu_msi; 121 extern int amdgpu_dpm; 122 extern int amdgpu_fw_load_type; 123 extern int amdgpu_aspm; 124 extern int amdgpu_runtime_pm; 125 extern uint amdgpu_ip_block_mask; 126 extern int amdgpu_bapm; 127 extern int amdgpu_deep_color; 128 extern int amdgpu_vm_size; 129 extern int amdgpu_vm_block_size; 130 extern int amdgpu_vm_fragment_size; 131 extern int amdgpu_vm_fault_stop; 132 extern int amdgpu_vm_debug; 133 extern int amdgpu_vm_update_mode; 134 extern int amdgpu_dc; 135 extern int amdgpu_sched_jobs; 136 extern int amdgpu_sched_hw_submission; 137 extern uint amdgpu_pcie_gen_cap; 138 extern uint amdgpu_pcie_lane_cap; 139 extern uint amdgpu_cg_mask; 140 extern uint amdgpu_pg_mask; 141 extern uint amdgpu_sdma_phase_quantum; 142 extern char *amdgpu_disable_cu; 143 extern char *amdgpu_virtual_display; 144 extern uint amdgpu_pp_feature_mask; 145 extern int amdgpu_vram_page_split; 146 extern int amdgpu_ngg; 147 extern int amdgpu_prim_buf_per_se; 148 extern int amdgpu_pos_buf_per_se; 149 extern int amdgpu_cntl_sb_buf_per_se; 150 extern int amdgpu_param_buf_per_se; 151 extern int amdgpu_job_hang_limit; 152 extern int amdgpu_lbpw; 153 extern int amdgpu_compute_multipipe; 154 extern int amdgpu_gpu_recovery; 155 extern int amdgpu_emu_mode; 156 extern uint amdgpu_smu_memory_pool_size; 157 extern uint amdgpu_dc_feature_mask; 158 extern struct amdgpu_mgpu_info mgpu_info; 159 extern int amdgpu_ras_enable; 160 extern uint amdgpu_ras_mask; 161 162 #ifdef CONFIG_DRM_AMDGPU_SI 163 extern int amdgpu_si_support; 164 #endif 165 #ifdef CONFIG_DRM_AMDGPU_CIK 166 extern int amdgpu_cik_support; 167 #endif 168 169 #define AMDGPU_VM_MAX_NUM_CTX 4096 170 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 171 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 172 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 173 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 174 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 175 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 176 #define AMDGPU_IB_POOL_SIZE 16 177 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 178 #define AMDGPUFB_CONN_LIMIT 4 179 #define AMDGPU_BIOS_NUM_SCRATCH 16 180 181 /* hard reset data */ 182 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 183 184 /* reset flags */ 185 #define AMDGPU_RESET_GFX (1 << 0) 186 #define AMDGPU_RESET_COMPUTE (1 << 1) 187 #define AMDGPU_RESET_DMA (1 << 2) 188 #define AMDGPU_RESET_CP (1 << 3) 189 #define AMDGPU_RESET_GRBM (1 << 4) 190 #define AMDGPU_RESET_DMA1 (1 << 5) 191 #define AMDGPU_RESET_RLC (1 << 6) 192 #define AMDGPU_RESET_SEM (1 << 7) 193 #define AMDGPU_RESET_IH (1 << 8) 194 #define AMDGPU_RESET_VMC (1 << 9) 195 #define AMDGPU_RESET_MC (1 << 10) 196 #define AMDGPU_RESET_DISPLAY (1 << 11) 197 #define AMDGPU_RESET_UVD (1 << 12) 198 #define AMDGPU_RESET_VCE (1 << 13) 199 #define AMDGPU_RESET_VCE1 (1 << 14) 200 201 /* max cursor sizes (in pixels) */ 202 #define CIK_CURSOR_WIDTH 128 203 #define CIK_CURSOR_HEIGHT 128 204 205 struct amdgpu_device; 206 struct amdgpu_ib; 207 struct amdgpu_cs_parser; 208 struct amdgpu_job; 209 struct amdgpu_irq_src; 210 struct amdgpu_fpriv; 211 struct amdgpu_bo_va_mapping; 212 struct amdgpu_atif; 213 struct kfd_vm_fault_info; 214 215 enum amdgpu_cp_irq { 216 AMDGPU_CP_IRQ_GFX_EOP = 0, 217 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 218 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 219 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 220 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 221 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 222 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 223 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 224 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 225 226 AMDGPU_CP_IRQ_LAST 227 }; 228 229 enum amdgpu_thermal_irq { 230 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 231 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 232 233 AMDGPU_THERMAL_IRQ_LAST 234 }; 235 236 enum amdgpu_kiq_irq { 237 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 238 AMDGPU_CP_KIQ_IRQ_LAST 239 }; 240 241 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 242 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 243 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 244 245 int amdgpu_device_ip_set_clockgating_state(void *dev, 246 enum amd_ip_block_type block_type, 247 enum amd_clockgating_state state); 248 int amdgpu_device_ip_set_powergating_state(void *dev, 249 enum amd_ip_block_type block_type, 250 enum amd_powergating_state state); 251 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 252 u32 *flags); 253 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 254 enum amd_ip_block_type block_type); 255 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 256 enum amd_ip_block_type block_type); 257 258 #define AMDGPU_MAX_IP_NUM 16 259 260 struct amdgpu_ip_block_status { 261 bool valid; 262 bool sw; 263 bool hw; 264 bool late_initialized; 265 bool hang; 266 }; 267 268 struct amdgpu_ip_block_version { 269 const enum amd_ip_block_type type; 270 const u32 major; 271 const u32 minor; 272 const u32 rev; 273 const struct amd_ip_funcs *funcs; 274 }; 275 276 struct amdgpu_ip_block { 277 struct amdgpu_ip_block_status status; 278 const struct amdgpu_ip_block_version *version; 279 }; 280 281 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 282 enum amd_ip_block_type type, 283 u32 major, u32 minor); 284 285 struct amdgpu_ip_block * 286 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 287 enum amd_ip_block_type type); 288 289 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 290 const struct amdgpu_ip_block_version *ip_block_version); 291 292 /* 293 * BIOS. 294 */ 295 bool amdgpu_get_bios(struct amdgpu_device *adev); 296 bool amdgpu_read_bios(struct amdgpu_device *adev); 297 298 /* 299 * Clocks 300 */ 301 302 #define AMDGPU_MAX_PPLL 3 303 304 struct amdgpu_clock { 305 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 306 struct amdgpu_pll spll; 307 struct amdgpu_pll mpll; 308 /* 10 Khz units */ 309 uint32_t default_mclk; 310 uint32_t default_sclk; 311 uint32_t default_dispclk; 312 uint32_t current_dispclk; 313 uint32_t dp_extclk; 314 uint32_t max_pixel_clock; 315 }; 316 317 /* sub-allocation manager, it has to be protected by another lock. 318 * By conception this is an helper for other part of the driver 319 * like the indirect buffer or semaphore, which both have their 320 * locking. 321 * 322 * Principe is simple, we keep a list of sub allocation in offset 323 * order (first entry has offset == 0, last entry has the highest 324 * offset). 325 * 326 * When allocating new object we first check if there is room at 327 * the end total_size - (last_object_offset + last_object_size) >= 328 * alloc_size. If so we allocate new object there. 329 * 330 * When there is not enough room at the end, we start waiting for 331 * each sub object until we reach object_offset+object_size >= 332 * alloc_size, this object then become the sub object we return. 333 * 334 * Alignment can't be bigger than page size. 335 * 336 * Hole are not considered for allocation to keep things simple. 337 * Assumption is that there won't be hole (all object on same 338 * alignment). 339 */ 340 341 #define AMDGPU_SA_NUM_FENCE_LISTS 32 342 343 struct amdgpu_sa_manager { 344 wait_queue_head_t wq; 345 struct amdgpu_bo *bo; 346 struct list_head *hole; 347 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 348 struct list_head olist; 349 unsigned size; 350 uint64_t gpu_addr; 351 void *cpu_ptr; 352 uint32_t domain; 353 uint32_t align; 354 }; 355 356 /* sub-allocation buffer */ 357 struct amdgpu_sa_bo { 358 struct list_head olist; 359 struct list_head flist; 360 struct amdgpu_sa_manager *manager; 361 unsigned soffset; 362 unsigned eoffset; 363 struct dma_fence *fence; 364 }; 365 366 int amdgpu_fence_slab_init(void); 367 void amdgpu_fence_slab_fini(void); 368 369 /* 370 * IRQS. 371 */ 372 373 struct amdgpu_flip_work { 374 struct delayed_work flip_work; 375 struct work_struct unpin_work; 376 struct amdgpu_device *adev; 377 int crtc_id; 378 u32 target_vblank; 379 uint64_t base; 380 struct drm_pending_vblank_event *event; 381 struct amdgpu_bo *old_abo; 382 struct dma_fence *excl; 383 unsigned shared_count; 384 struct dma_fence **shared; 385 struct dma_fence_cb cb; 386 bool async; 387 }; 388 389 390 /* 391 * CP & rings. 392 */ 393 394 struct amdgpu_ib { 395 struct amdgpu_sa_bo *sa_bo; 396 uint32_t length_dw; 397 uint64_t gpu_addr; 398 uint32_t *ptr; 399 uint32_t flags; 400 }; 401 402 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 403 404 /* 405 * file private structure 406 */ 407 408 struct amdgpu_fpriv { 409 struct amdgpu_vm vm; 410 struct amdgpu_bo_va *prt_va; 411 struct amdgpu_bo_va *csa_va; 412 struct mutex bo_list_lock; 413 struct idr bo_list_handles; 414 struct amdgpu_ctx_mgr ctx_mgr; 415 }; 416 417 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 418 int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev); 419 420 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 421 unsigned size, struct amdgpu_ib *ib); 422 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 423 struct dma_fence *f); 424 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 425 struct amdgpu_ib *ibs, struct amdgpu_job *job, 426 struct dma_fence **f); 427 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 428 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 429 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 430 431 /* 432 * CS. 433 */ 434 struct amdgpu_cs_chunk { 435 uint32_t chunk_id; 436 uint32_t length_dw; 437 void *kdata; 438 }; 439 440 struct amdgpu_cs_post_dep { 441 struct drm_syncobj *syncobj; 442 struct dma_fence_chain *chain; 443 u64 point; 444 }; 445 446 struct amdgpu_cs_parser { 447 struct amdgpu_device *adev; 448 struct drm_file *filp; 449 struct amdgpu_ctx *ctx; 450 451 /* chunks */ 452 unsigned nchunks; 453 struct amdgpu_cs_chunk *chunks; 454 455 /* scheduler job object */ 456 struct amdgpu_job *job; 457 struct drm_sched_entity *entity; 458 459 /* buffer objects */ 460 struct ww_acquire_ctx ticket; 461 struct amdgpu_bo_list *bo_list; 462 struct amdgpu_mn *mn; 463 struct amdgpu_bo_list_entry vm_pd; 464 struct list_head validated; 465 struct dma_fence *fence; 466 uint64_t bytes_moved_threshold; 467 uint64_t bytes_moved_vis_threshold; 468 uint64_t bytes_moved; 469 uint64_t bytes_moved_vis; 470 struct amdgpu_bo_list_entry *evictable; 471 472 /* user fence */ 473 struct amdgpu_bo_list_entry uf_entry; 474 475 unsigned num_post_deps; 476 struct amdgpu_cs_post_dep *post_deps; 477 }; 478 479 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 480 uint32_t ib_idx, int idx) 481 { 482 return p->job->ibs[ib_idx].ptr[idx]; 483 } 484 485 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 486 uint32_t ib_idx, int idx, 487 uint32_t value) 488 { 489 p->job->ibs[ib_idx].ptr[idx] = value; 490 } 491 492 /* 493 * Writeback 494 */ 495 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 496 497 struct amdgpu_wb { 498 struct amdgpu_bo *wb_obj; 499 volatile uint32_t *wb; 500 uint64_t gpu_addr; 501 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 502 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 503 }; 504 505 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 506 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 507 508 /* 509 * Benchmarking 510 */ 511 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 512 513 514 /* 515 * Testing 516 */ 517 void amdgpu_test_moves(struct amdgpu_device *adev); 518 519 /* 520 * ASIC specific register table accessible by UMD 521 */ 522 struct amdgpu_allowed_register_entry { 523 uint32_t reg_offset; 524 bool grbm_indexed; 525 }; 526 527 /* 528 * ASIC specific functions. 529 */ 530 struct amdgpu_asic_funcs { 531 bool (*read_disabled_bios)(struct amdgpu_device *adev); 532 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 533 u8 *bios, u32 length_bytes); 534 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 535 u32 sh_num, u32 reg_offset, u32 *value); 536 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 537 int (*reset)(struct amdgpu_device *adev); 538 /* get the reference clock */ 539 u32 (*get_xclk)(struct amdgpu_device *adev); 540 /* MM block clocks */ 541 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 542 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 543 /* static power management */ 544 int (*get_pcie_lanes)(struct amdgpu_device *adev); 545 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 546 /* get config memsize register */ 547 u32 (*get_config_memsize)(struct amdgpu_device *adev); 548 /* flush hdp write queue */ 549 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 550 /* invalidate hdp read cache */ 551 void (*invalidate_hdp)(struct amdgpu_device *adev, 552 struct amdgpu_ring *ring); 553 /* check if the asic needs a full reset of if soft reset will work */ 554 bool (*need_full_reset)(struct amdgpu_device *adev); 555 /* initialize doorbell layout for specific asic*/ 556 void (*init_doorbell_index)(struct amdgpu_device *adev); 557 /* PCIe bandwidth usage */ 558 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 559 uint64_t *count1); 560 /* do we need to reset the asic at init time (e.g., kexec) */ 561 bool (*need_reset_on_init)(struct amdgpu_device *adev); 562 /* PCIe replay counter */ 563 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 564 }; 565 566 /* 567 * IOCTL. 568 */ 569 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 570 struct drm_file *filp); 571 572 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 573 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 574 struct drm_file *filp); 575 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 576 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 577 struct drm_file *filp); 578 579 /* VRAM scratch page for HDP bug, default vram page */ 580 struct amdgpu_vram_scratch { 581 struct amdgpu_bo *robj; 582 volatile uint32_t *ptr; 583 u64 gpu_addr; 584 }; 585 586 /* 587 * ACPI 588 */ 589 struct amdgpu_atcs_functions { 590 bool get_ext_state; 591 bool pcie_perf_req; 592 bool pcie_dev_rdy; 593 bool pcie_bus_width; 594 }; 595 596 struct amdgpu_atcs { 597 struct amdgpu_atcs_functions functions; 598 }; 599 600 /* 601 * Firmware VRAM reservation 602 */ 603 struct amdgpu_fw_vram_usage { 604 u64 start_offset; 605 u64 size; 606 struct amdgpu_bo *reserved_bo; 607 void *va; 608 }; 609 610 /* 611 * CGS 612 */ 613 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 614 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 615 616 /* 617 * Core structure, functions and helpers. 618 */ 619 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 620 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 621 622 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 623 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 624 625 626 /* 627 * amdgpu nbio functions 628 * 629 */ 630 struct nbio_hdp_flush_reg { 631 u32 ref_and_mask_cp0; 632 u32 ref_and_mask_cp1; 633 u32 ref_and_mask_cp2; 634 u32 ref_and_mask_cp3; 635 u32 ref_and_mask_cp4; 636 u32 ref_and_mask_cp5; 637 u32 ref_and_mask_cp6; 638 u32 ref_and_mask_cp7; 639 u32 ref_and_mask_cp8; 640 u32 ref_and_mask_cp9; 641 u32 ref_and_mask_sdma0; 642 u32 ref_and_mask_sdma1; 643 }; 644 645 struct amdgpu_mmio_remap { 646 u32 reg_offset; 647 resource_size_t bus_addr; 648 }; 649 650 struct amdgpu_nbio_funcs { 651 const struct nbio_hdp_flush_reg *hdp_flush_reg; 652 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 653 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 654 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 655 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 656 u32 (*get_rev_id)(struct amdgpu_device *adev); 657 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 658 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 659 u32 (*get_memsize)(struct amdgpu_device *adev); 660 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 661 bool use_doorbell, int doorbell_index, int doorbell_size); 662 void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 663 bool enable); 664 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 665 bool enable); 666 void (*ih_doorbell_range)(struct amdgpu_device *adev, 667 bool use_doorbell, int doorbell_index); 668 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 669 bool enable); 670 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 671 bool enable); 672 void (*get_clockgating_state)(struct amdgpu_device *adev, 673 u32 *flags); 674 void (*ih_control)(struct amdgpu_device *adev); 675 void (*init_registers)(struct amdgpu_device *adev); 676 void (*detect_hw_virt)(struct amdgpu_device *adev); 677 void (*remap_hdp_registers)(struct amdgpu_device *adev); 678 }; 679 680 struct amdgpu_df_funcs { 681 void (*init)(struct amdgpu_device *adev); 682 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 683 bool enable); 684 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 685 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 686 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 687 bool enable); 688 void (*get_clockgating_state)(struct amdgpu_device *adev, 689 u32 *flags); 690 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 691 bool enable); 692 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config, 693 int is_enable); 694 int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config, 695 int is_disable); 696 void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config, 697 uint64_t *count); 698 }; 699 /* Define the HW IP blocks will be used in driver , add more if necessary */ 700 enum amd_hw_ip_block_type { 701 GC_HWIP = 1, 702 HDP_HWIP, 703 SDMA0_HWIP, 704 SDMA1_HWIP, 705 MMHUB_HWIP, 706 ATHUB_HWIP, 707 NBIO_HWIP, 708 MP0_HWIP, 709 MP1_HWIP, 710 UVD_HWIP, 711 VCN_HWIP = UVD_HWIP, 712 VCE_HWIP, 713 DF_HWIP, 714 DCE_HWIP, 715 OSSSYS_HWIP, 716 SMUIO_HWIP, 717 PWR_HWIP, 718 NBIF_HWIP, 719 THM_HWIP, 720 CLK_HWIP, 721 MAX_HWIP 722 }; 723 724 #define HWIP_MAX_INSTANCE 6 725 726 struct amd_powerplay { 727 void *pp_handle; 728 const struct amd_pm_funcs *pp_funcs; 729 }; 730 731 #define AMDGPU_RESET_MAGIC_NUM 64 732 struct amdgpu_device { 733 struct device *dev; 734 struct drm_device *ddev; 735 struct pci_dev *pdev; 736 737 #ifdef CONFIG_DRM_AMD_ACP 738 struct amdgpu_acp acp; 739 #endif 740 741 /* ASIC */ 742 enum amd_asic_type asic_type; 743 uint32_t family; 744 uint32_t rev_id; 745 uint32_t external_rev_id; 746 unsigned long flags; 747 int usec_timeout; 748 const struct amdgpu_asic_funcs *asic_funcs; 749 bool shutdown; 750 bool need_dma32; 751 bool need_swiotlb; 752 bool accel_working; 753 struct notifier_block acpi_nb; 754 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 755 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 756 unsigned debugfs_count; 757 #if defined(CONFIG_DEBUG_FS) 758 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 759 #endif 760 struct amdgpu_atif *atif; 761 struct amdgpu_atcs atcs; 762 struct mutex srbm_mutex; 763 /* GRBM index mutex. Protects concurrent access to GRBM index */ 764 struct mutex grbm_idx_mutex; 765 struct dev_pm_domain vga_pm_domain; 766 bool have_disp_power_ref; 767 768 /* BIOS */ 769 bool is_atom_fw; 770 uint8_t *bios; 771 uint32_t bios_size; 772 struct amdgpu_bo *stolen_vga_memory; 773 uint32_t bios_scratch_reg_offset; 774 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 775 776 /* Register/doorbell mmio */ 777 resource_size_t rmmio_base; 778 resource_size_t rmmio_size; 779 void __iomem *rmmio; 780 /* protects concurrent MM_INDEX/DATA based register access */ 781 spinlock_t mmio_idx_lock; 782 struct amdgpu_mmio_remap rmmio_remap; 783 /* protects concurrent SMC based register access */ 784 spinlock_t smc_idx_lock; 785 amdgpu_rreg_t smc_rreg; 786 amdgpu_wreg_t smc_wreg; 787 /* protects concurrent PCIE register access */ 788 spinlock_t pcie_idx_lock; 789 amdgpu_rreg_t pcie_rreg; 790 amdgpu_wreg_t pcie_wreg; 791 amdgpu_rreg_t pciep_rreg; 792 amdgpu_wreg_t pciep_wreg; 793 /* protects concurrent UVD register access */ 794 spinlock_t uvd_ctx_idx_lock; 795 amdgpu_rreg_t uvd_ctx_rreg; 796 amdgpu_wreg_t uvd_ctx_wreg; 797 /* protects concurrent DIDT register access */ 798 spinlock_t didt_idx_lock; 799 amdgpu_rreg_t didt_rreg; 800 amdgpu_wreg_t didt_wreg; 801 /* protects concurrent gc_cac register access */ 802 spinlock_t gc_cac_idx_lock; 803 amdgpu_rreg_t gc_cac_rreg; 804 amdgpu_wreg_t gc_cac_wreg; 805 /* protects concurrent se_cac register access */ 806 spinlock_t se_cac_idx_lock; 807 amdgpu_rreg_t se_cac_rreg; 808 amdgpu_wreg_t se_cac_wreg; 809 /* protects concurrent ENDPOINT (audio) register access */ 810 spinlock_t audio_endpt_idx_lock; 811 amdgpu_block_rreg_t audio_endpt_rreg; 812 amdgpu_block_wreg_t audio_endpt_wreg; 813 void __iomem *rio_mem; 814 resource_size_t rio_mem_size; 815 struct amdgpu_doorbell doorbell; 816 817 /* clock/pll info */ 818 struct amdgpu_clock clock; 819 820 /* MC */ 821 struct amdgpu_gmc gmc; 822 struct amdgpu_gart gart; 823 dma_addr_t dummy_page_addr; 824 struct amdgpu_vm_manager vm_manager; 825 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 826 827 /* memory management */ 828 struct amdgpu_mman mman; 829 struct amdgpu_vram_scratch vram_scratch; 830 struct amdgpu_wb wb; 831 atomic64_t num_bytes_moved; 832 atomic64_t num_evictions; 833 atomic64_t num_vram_cpu_page_faults; 834 atomic_t gpu_reset_counter; 835 atomic_t vram_lost_counter; 836 837 /* data for buffer migration throttling */ 838 struct { 839 spinlock_t lock; 840 s64 last_update_us; 841 s64 accum_us; /* accumulated microseconds */ 842 s64 accum_us_vis; /* for visible VRAM */ 843 u32 log2_max_MBps; 844 } mm_stats; 845 846 /* display */ 847 bool enable_virtual_display; 848 struct amdgpu_mode_info mode_info; 849 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 850 struct work_struct hotplug_work; 851 struct amdgpu_irq_src crtc_irq; 852 struct amdgpu_irq_src vupdate_irq; 853 struct amdgpu_irq_src pageflip_irq; 854 struct amdgpu_irq_src hpd_irq; 855 856 /* rings */ 857 u64 fence_context; 858 unsigned num_rings; 859 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 860 bool ib_pool_ready; 861 struct amdgpu_sa_manager ring_tmp_bo; 862 863 /* interrupts */ 864 struct amdgpu_irq irq; 865 866 /* powerplay */ 867 struct amd_powerplay powerplay; 868 bool pp_force_state_enabled; 869 870 /* smu */ 871 struct smu_context smu; 872 873 /* dpm */ 874 struct amdgpu_pm pm; 875 u32 cg_flags; 876 u32 pg_flags; 877 878 /* gfx */ 879 struct amdgpu_gfx gfx; 880 881 /* sdma */ 882 struct amdgpu_sdma sdma; 883 884 /* uvd */ 885 struct amdgpu_uvd uvd; 886 887 /* vce */ 888 struct amdgpu_vce vce; 889 890 /* vcn */ 891 struct amdgpu_vcn vcn; 892 893 /* firmwares */ 894 struct amdgpu_firmware firmware; 895 896 /* PSP */ 897 struct psp_context psp; 898 899 /* GDS */ 900 struct amdgpu_gds gds; 901 902 /* KFD */ 903 struct amdgpu_kfd_dev kfd; 904 905 /* display related functionality */ 906 struct amdgpu_display_manager dm; 907 908 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 909 int num_ip_blocks; 910 struct mutex mn_lock; 911 DECLARE_HASHTABLE(mn_hash, 7); 912 913 /* tracking pinned memory */ 914 atomic64_t vram_pin_size; 915 atomic64_t visible_pin_size; 916 atomic64_t gart_pin_size; 917 918 /* soc15 register offset based on ip, instance and segment */ 919 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 920 921 const struct amdgpu_nbio_funcs *nbio_funcs; 922 const struct amdgpu_df_funcs *df_funcs; 923 924 /* delayed work_func for deferring clockgating during resume */ 925 struct delayed_work late_init_work; 926 927 struct amdgpu_virt virt; 928 /* firmware VRAM reservation */ 929 struct amdgpu_fw_vram_usage fw_vram_usage; 930 931 /* link all shadow bo */ 932 struct list_head shadow_list; 933 struct mutex shadow_list_lock; 934 /* keep an lru list of rings by HW IP */ 935 struct list_head ring_lru_list; 936 spinlock_t ring_lru_list_lock; 937 938 /* record hw reset is performed */ 939 bool has_hw_reset; 940 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 941 942 /* s3/s4 mask */ 943 bool in_suspend; 944 945 /* record last mm index being written through WREG32*/ 946 unsigned long last_mm_index; 947 bool in_gpu_reset; 948 struct mutex lock_reset; 949 struct amdgpu_doorbell_index doorbell_index; 950 951 int asic_reset_res; 952 struct work_struct xgmi_reset_work; 953 954 bool in_baco_reset; 955 956 long gfx_timeout; 957 long sdma_timeout; 958 long video_timeout; 959 long compute_timeout; 960 961 uint64_t unique_id; 962 }; 963 964 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 965 { 966 return container_of(bdev, struct amdgpu_device, mman.bdev); 967 } 968 969 int amdgpu_device_init(struct amdgpu_device *adev, 970 struct drm_device *ddev, 971 struct pci_dev *pdev, 972 uint32_t flags); 973 void amdgpu_device_fini(struct amdgpu_device *adev); 974 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 975 976 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 977 uint32_t acc_flags); 978 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 979 uint32_t acc_flags); 980 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 981 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 982 983 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 984 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 985 986 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 987 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 988 989 int emu_soc_asic_init(struct amdgpu_device *adev); 990 991 /* 992 * Registers read & write functions. 993 */ 994 995 #define AMDGPU_REGS_IDX (1<<0) 996 #define AMDGPU_REGS_NO_KIQ (1<<1) 997 998 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 999 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1000 1001 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1002 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1003 1004 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1005 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1006 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1007 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1008 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1009 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1010 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1011 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1012 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1013 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1014 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1015 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1016 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1017 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1018 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1019 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1020 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1021 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1022 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1023 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1024 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1025 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1026 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1027 #define WREG32_P(reg, val, mask) \ 1028 do { \ 1029 uint32_t tmp_ = RREG32(reg); \ 1030 tmp_ &= (mask); \ 1031 tmp_ |= ((val) & ~(mask)); \ 1032 WREG32(reg, tmp_); \ 1033 } while (0) 1034 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1035 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1036 #define WREG32_PLL_P(reg, val, mask) \ 1037 do { \ 1038 uint32_t tmp_ = RREG32_PLL(reg); \ 1039 tmp_ &= (mask); \ 1040 tmp_ |= ((val) & ~(mask)); \ 1041 WREG32_PLL(reg, tmp_); \ 1042 } while (0) 1043 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1044 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1045 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1046 1047 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1048 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1049 1050 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1051 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1052 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1053 1054 #define REG_GET_FIELD(value, reg, field) \ 1055 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1056 1057 #define WREG32_FIELD(reg, field, val) \ 1058 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1059 1060 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1061 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1062 1063 /* 1064 * BIOS helpers. 1065 */ 1066 #define RBIOS8(i) (adev->bios[i]) 1067 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1068 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1069 1070 /* 1071 * ASICs macro. 1072 */ 1073 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1074 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1075 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1076 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1077 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1078 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1079 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1080 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1081 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1082 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1083 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1084 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1085 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1086 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1087 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1088 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1089 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1090 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1091 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1092 1093 /* Common functions */ 1094 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1095 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1096 struct amdgpu_job* job); 1097 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1098 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1099 1100 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1101 u64 num_vis_bytes); 1102 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1103 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1104 const u32 *registers, 1105 const u32 array_size); 1106 1107 bool amdgpu_device_is_px(struct drm_device *dev); 1108 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1109 struct amdgpu_device *peer_adev); 1110 1111 /* atpx handler */ 1112 #if defined(CONFIG_VGA_SWITCHEROO) 1113 void amdgpu_register_atpx_handler(void); 1114 void amdgpu_unregister_atpx_handler(void); 1115 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1116 bool amdgpu_is_atpx_hybrid(void); 1117 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1118 bool amdgpu_has_atpx(void); 1119 #else 1120 static inline void amdgpu_register_atpx_handler(void) {} 1121 static inline void amdgpu_unregister_atpx_handler(void) {} 1122 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1123 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1124 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1125 static inline bool amdgpu_has_atpx(void) { return false; } 1126 #endif 1127 1128 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1129 void *amdgpu_atpx_get_dhandle(void); 1130 #else 1131 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1132 #endif 1133 1134 /* 1135 * KMS 1136 */ 1137 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1138 extern const int amdgpu_max_kms_ioctl; 1139 1140 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1141 void amdgpu_driver_unload_kms(struct drm_device *dev); 1142 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1143 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1144 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1145 struct drm_file *file_priv); 1146 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1147 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1148 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1149 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1150 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1151 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1152 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1153 unsigned long arg); 1154 1155 /* 1156 * functions used by amdgpu_encoder.c 1157 */ 1158 struct amdgpu_afmt_acr { 1159 u32 clock; 1160 1161 int n_32khz; 1162 int cts_32khz; 1163 1164 int n_44_1khz; 1165 int cts_44_1khz; 1166 1167 int n_48khz; 1168 int cts_48khz; 1169 1170 }; 1171 1172 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1173 1174 /* amdgpu_acpi.c */ 1175 #if defined(CONFIG_ACPI) 1176 int amdgpu_acpi_init(struct amdgpu_device *adev); 1177 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1178 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1179 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1180 u8 perf_req, bool advertise); 1181 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1182 1183 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1184 struct amdgpu_dm_backlight_caps *caps); 1185 #else 1186 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1187 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1188 #endif 1189 1190 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1191 uint64_t addr, struct amdgpu_bo **bo, 1192 struct amdgpu_bo_va_mapping **mapping); 1193 1194 #if defined(CONFIG_DRM_AMD_DC) 1195 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1196 #else 1197 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1198 #endif 1199 1200 #include "amdgpu_object.h" 1201 #endif 1202