1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_execbuf_util.h> 59 60 #include <drm/amdgpu_drm.h> 61 #include <drm/drm_gem.h> 62 #include <drm/drm_ioctl.h> 63 64 #include <kgd_kfd_interface.h> 65 #include "dm_pp_interface.h" 66 #include "kgd_pp_interface.h" 67 68 #include "amd_shared.h" 69 #include "amdgpu_mode.h" 70 #include "amdgpu_ih.h" 71 #include "amdgpu_irq.h" 72 #include "amdgpu_ucode.h" 73 #include "amdgpu_ttm.h" 74 #include "amdgpu_psp.h" 75 #include "amdgpu_gds.h" 76 #include "amdgpu_sync.h" 77 #include "amdgpu_ring.h" 78 #include "amdgpu_vm.h" 79 #include "amdgpu_dpm.h" 80 #include "amdgpu_acp.h" 81 #include "amdgpu_uvd.h" 82 #include "amdgpu_vce.h" 83 #include "amdgpu_vcn.h" 84 #include "amdgpu_jpeg.h" 85 #include "amdgpu_mn.h" 86 #include "amdgpu_gmc.h" 87 #include "amdgpu_gfx.h" 88 #include "amdgpu_sdma.h" 89 #include "amdgpu_lsdma.h" 90 #include "amdgpu_nbio.h" 91 #include "amdgpu_hdp.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_mes_ctx.h" 96 #include "amdgpu_gart.h" 97 #include "amdgpu_debugfs.h" 98 #include "amdgpu_job.h" 99 #include "amdgpu_bo_list.h" 100 #include "amdgpu_gem.h" 101 #include "amdgpu_doorbell.h" 102 #include "amdgpu_amdkfd.h" 103 #include "amdgpu_discovery.h" 104 #include "amdgpu_mes.h" 105 #include "amdgpu_umc.h" 106 #include "amdgpu_mmhub.h" 107 #include "amdgpu_gfxhub.h" 108 #include "amdgpu_df.h" 109 #include "amdgpu_smuio.h" 110 #include "amdgpu_fdinfo.h" 111 #include "amdgpu_mca.h" 112 #include "amdgpu_ras.h" 113 114 #define MAX_GPU_INSTANCE 16 115 116 struct amdgpu_gpu_instance 117 { 118 struct amdgpu_device *adev; 119 int mgpu_fan_enabled; 120 }; 121 122 struct amdgpu_mgpu_info 123 { 124 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 125 struct mutex mutex; 126 uint32_t num_gpu; 127 uint32_t num_dgpu; 128 uint32_t num_apu; 129 130 /* delayed reset_func for XGMI configuration if necessary */ 131 struct delayed_work delayed_reset_work; 132 bool pending_reset; 133 }; 134 135 enum amdgpu_ss { 136 AMDGPU_SS_DRV_LOAD, 137 AMDGPU_SS_DEV_D0, 138 AMDGPU_SS_DEV_D3, 139 AMDGPU_SS_DRV_UNLOAD 140 }; 141 142 struct amdgpu_watchdog_timer 143 { 144 bool timeout_fatal_disable; 145 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 146 }; 147 148 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 149 150 /* 151 * Modules parameters. 152 */ 153 extern int amdgpu_modeset; 154 extern int amdgpu_vram_limit; 155 extern int amdgpu_vis_vram_limit; 156 extern int amdgpu_gart_size; 157 extern int amdgpu_gtt_size; 158 extern int amdgpu_moverate; 159 extern int amdgpu_audio; 160 extern int amdgpu_disp_priority; 161 extern int amdgpu_hw_i2c; 162 extern int amdgpu_pcie_gen2; 163 extern int amdgpu_msi; 164 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 165 extern int amdgpu_dpm; 166 extern int amdgpu_fw_load_type; 167 extern int amdgpu_aspm; 168 extern int amdgpu_runtime_pm; 169 extern uint amdgpu_ip_block_mask; 170 extern int amdgpu_bapm; 171 extern int amdgpu_deep_color; 172 extern int amdgpu_vm_size; 173 extern int amdgpu_vm_block_size; 174 extern int amdgpu_vm_fragment_size; 175 extern int amdgpu_vm_fault_stop; 176 extern int amdgpu_vm_debug; 177 extern int amdgpu_vm_update_mode; 178 extern int amdgpu_exp_hw_support; 179 extern int amdgpu_dc; 180 extern int amdgpu_sched_jobs; 181 extern int amdgpu_sched_hw_submission; 182 extern uint amdgpu_pcie_gen_cap; 183 extern uint amdgpu_pcie_lane_cap; 184 extern u64 amdgpu_cg_mask; 185 extern uint amdgpu_pg_mask; 186 extern uint amdgpu_sdma_phase_quantum; 187 extern char *amdgpu_disable_cu; 188 extern char *amdgpu_virtual_display; 189 extern uint amdgpu_pp_feature_mask; 190 extern uint amdgpu_force_long_training; 191 extern int amdgpu_job_hang_limit; 192 extern int amdgpu_lbpw; 193 extern int amdgpu_compute_multipipe; 194 extern int amdgpu_gpu_recovery; 195 extern int amdgpu_emu_mode; 196 extern uint amdgpu_smu_memory_pool_size; 197 extern int amdgpu_smu_pptable_id; 198 extern uint amdgpu_dc_feature_mask; 199 extern uint amdgpu_dc_debug_mask; 200 extern uint amdgpu_dc_visual_confirm; 201 extern uint amdgpu_dm_abm_level; 202 extern int amdgpu_backlight; 203 extern struct amdgpu_mgpu_info mgpu_info; 204 extern int amdgpu_ras_enable; 205 extern uint amdgpu_ras_mask; 206 extern int amdgpu_bad_page_threshold; 207 extern bool amdgpu_ignore_bad_page_threshold; 208 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 209 extern int amdgpu_async_gfx_ring; 210 extern int amdgpu_mcbp; 211 extern int amdgpu_discovery; 212 extern int amdgpu_mes; 213 extern int amdgpu_mes_kiq; 214 extern int amdgpu_noretry; 215 extern int amdgpu_force_asic_type; 216 extern int amdgpu_smartshift_bias; 217 extern int amdgpu_use_xgmi_p2p; 218 #ifdef CONFIG_HSA_AMD 219 extern int sched_policy; 220 extern bool debug_evictions; 221 extern bool no_system_mem_limit; 222 #else 223 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 224 static const bool __maybe_unused debug_evictions; /* = false */ 225 static const bool __maybe_unused no_system_mem_limit; 226 #endif 227 #ifdef CONFIG_HSA_AMD_P2P 228 extern bool pcie_p2p; 229 #endif 230 231 extern int amdgpu_tmz; 232 extern int amdgpu_reset_method; 233 234 #ifdef CONFIG_DRM_AMDGPU_SI 235 extern int amdgpu_si_support; 236 #endif 237 #ifdef CONFIG_DRM_AMDGPU_CIK 238 extern int amdgpu_cik_support; 239 #endif 240 extern int amdgpu_num_kcq; 241 242 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 243 extern int amdgpu_vcnfw_log; 244 245 #define AMDGPU_VM_MAX_NUM_CTX 4096 246 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 247 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 248 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 249 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 250 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 251 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 252 #define AMDGPUFB_CONN_LIMIT 4 253 #define AMDGPU_BIOS_NUM_SCRATCH 16 254 255 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 256 257 /* hard reset data */ 258 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 259 260 /* reset flags */ 261 #define AMDGPU_RESET_GFX (1 << 0) 262 #define AMDGPU_RESET_COMPUTE (1 << 1) 263 #define AMDGPU_RESET_DMA (1 << 2) 264 #define AMDGPU_RESET_CP (1 << 3) 265 #define AMDGPU_RESET_GRBM (1 << 4) 266 #define AMDGPU_RESET_DMA1 (1 << 5) 267 #define AMDGPU_RESET_RLC (1 << 6) 268 #define AMDGPU_RESET_SEM (1 << 7) 269 #define AMDGPU_RESET_IH (1 << 8) 270 #define AMDGPU_RESET_VMC (1 << 9) 271 #define AMDGPU_RESET_MC (1 << 10) 272 #define AMDGPU_RESET_DISPLAY (1 << 11) 273 #define AMDGPU_RESET_UVD (1 << 12) 274 #define AMDGPU_RESET_VCE (1 << 13) 275 #define AMDGPU_RESET_VCE1 (1 << 14) 276 277 /* max cursor sizes (in pixels) */ 278 #define CIK_CURSOR_WIDTH 128 279 #define CIK_CURSOR_HEIGHT 128 280 281 /* smart shift bias level limits */ 282 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 283 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 284 285 struct amdgpu_device; 286 struct amdgpu_irq_src; 287 struct amdgpu_fpriv; 288 struct amdgpu_bo_va_mapping; 289 struct kfd_vm_fault_info; 290 struct amdgpu_hive_info; 291 struct amdgpu_reset_context; 292 struct amdgpu_reset_control; 293 294 enum amdgpu_cp_irq { 295 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 296 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 297 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 298 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 299 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 300 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 301 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 302 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 303 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 304 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 305 306 AMDGPU_CP_IRQ_LAST 307 }; 308 309 enum amdgpu_thermal_irq { 310 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 311 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 312 313 AMDGPU_THERMAL_IRQ_LAST 314 }; 315 316 enum amdgpu_kiq_irq { 317 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 318 AMDGPU_CP_KIQ_IRQ_LAST 319 }; 320 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 321 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 322 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 323 #define MAX_KIQ_REG_TRY 1000 324 325 int amdgpu_device_ip_set_clockgating_state(void *dev, 326 enum amd_ip_block_type block_type, 327 enum amd_clockgating_state state); 328 int amdgpu_device_ip_set_powergating_state(void *dev, 329 enum amd_ip_block_type block_type, 330 enum amd_powergating_state state); 331 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 332 u64 *flags); 333 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 334 enum amd_ip_block_type block_type); 335 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 336 enum amd_ip_block_type block_type); 337 338 #define AMDGPU_MAX_IP_NUM 16 339 340 struct amdgpu_ip_block_status { 341 bool valid; 342 bool sw; 343 bool hw; 344 bool late_initialized; 345 bool hang; 346 }; 347 348 struct amdgpu_ip_block_version { 349 const enum amd_ip_block_type type; 350 const u32 major; 351 const u32 minor; 352 const u32 rev; 353 const struct amd_ip_funcs *funcs; 354 }; 355 356 #define HW_REV(_Major, _Minor, _Rev) \ 357 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 358 359 struct amdgpu_ip_block { 360 struct amdgpu_ip_block_status status; 361 const struct amdgpu_ip_block_version *version; 362 }; 363 364 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 365 enum amd_ip_block_type type, 366 u32 major, u32 minor); 367 368 struct amdgpu_ip_block * 369 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 370 enum amd_ip_block_type type); 371 372 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 373 const struct amdgpu_ip_block_version *ip_block_version); 374 375 /* 376 * BIOS. 377 */ 378 bool amdgpu_get_bios(struct amdgpu_device *adev); 379 bool amdgpu_read_bios(struct amdgpu_device *adev); 380 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 381 u8 *bios, u32 length_bytes); 382 /* 383 * Clocks 384 */ 385 386 #define AMDGPU_MAX_PPLL 3 387 388 struct amdgpu_clock { 389 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 390 struct amdgpu_pll spll; 391 struct amdgpu_pll mpll; 392 /* 10 Khz units */ 393 uint32_t default_mclk; 394 uint32_t default_sclk; 395 uint32_t default_dispclk; 396 uint32_t current_dispclk; 397 uint32_t dp_extclk; 398 uint32_t max_pixel_clock; 399 }; 400 401 /* sub-allocation manager, it has to be protected by another lock. 402 * By conception this is an helper for other part of the driver 403 * like the indirect buffer or semaphore, which both have their 404 * locking. 405 * 406 * Principe is simple, we keep a list of sub allocation in offset 407 * order (first entry has offset == 0, last entry has the highest 408 * offset). 409 * 410 * When allocating new object we first check if there is room at 411 * the end total_size - (last_object_offset + last_object_size) >= 412 * alloc_size. If so we allocate new object there. 413 * 414 * When there is not enough room at the end, we start waiting for 415 * each sub object until we reach object_offset+object_size >= 416 * alloc_size, this object then become the sub object we return. 417 * 418 * Alignment can't be bigger than page size. 419 * 420 * Hole are not considered for allocation to keep things simple. 421 * Assumption is that there won't be hole (all object on same 422 * alignment). 423 */ 424 425 #define AMDGPU_SA_NUM_FENCE_LISTS 32 426 427 struct amdgpu_sa_manager { 428 wait_queue_head_t wq; 429 struct amdgpu_bo *bo; 430 struct list_head *hole; 431 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 432 struct list_head olist; 433 unsigned size; 434 uint64_t gpu_addr; 435 void *cpu_ptr; 436 uint32_t domain; 437 uint32_t align; 438 }; 439 440 /* sub-allocation buffer */ 441 struct amdgpu_sa_bo { 442 struct list_head olist; 443 struct list_head flist; 444 struct amdgpu_sa_manager *manager; 445 unsigned soffset; 446 unsigned eoffset; 447 struct dma_fence *fence; 448 }; 449 450 int amdgpu_fence_slab_init(void); 451 void amdgpu_fence_slab_fini(void); 452 453 /* 454 * IRQS. 455 */ 456 457 struct amdgpu_flip_work { 458 struct delayed_work flip_work; 459 struct work_struct unpin_work; 460 struct amdgpu_device *adev; 461 int crtc_id; 462 u32 target_vblank; 463 uint64_t base; 464 struct drm_pending_vblank_event *event; 465 struct amdgpu_bo *old_abo; 466 unsigned shared_count; 467 struct dma_fence **shared; 468 struct dma_fence_cb cb; 469 bool async; 470 }; 471 472 473 /* 474 * file private structure 475 */ 476 477 struct amdgpu_fpriv { 478 struct amdgpu_vm vm; 479 struct amdgpu_bo_va *prt_va; 480 struct amdgpu_bo_va *csa_va; 481 struct mutex bo_list_lock; 482 struct idr bo_list_handles; 483 struct amdgpu_ctx_mgr ctx_mgr; 484 }; 485 486 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 487 488 /* 489 * Writeback 490 */ 491 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 492 493 struct amdgpu_wb { 494 struct amdgpu_bo *wb_obj; 495 volatile uint32_t *wb; 496 uint64_t gpu_addr; 497 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 498 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 499 }; 500 501 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 502 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 503 504 /* 505 * Benchmarking 506 */ 507 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 508 509 /* 510 * ASIC specific register table accessible by UMD 511 */ 512 struct amdgpu_allowed_register_entry { 513 uint32_t reg_offset; 514 bool grbm_indexed; 515 }; 516 517 enum amd_reset_method { 518 AMD_RESET_METHOD_NONE = -1, 519 AMD_RESET_METHOD_LEGACY = 0, 520 AMD_RESET_METHOD_MODE0, 521 AMD_RESET_METHOD_MODE1, 522 AMD_RESET_METHOD_MODE2, 523 AMD_RESET_METHOD_BACO, 524 AMD_RESET_METHOD_PCI, 525 }; 526 527 struct amdgpu_video_codec_info { 528 u32 codec_type; 529 u32 max_width; 530 u32 max_height; 531 u32 max_pixels_per_frame; 532 u32 max_level; 533 }; 534 535 #define codec_info_build(type, width, height, level) \ 536 .codec_type = type,\ 537 .max_width = width,\ 538 .max_height = height,\ 539 .max_pixels_per_frame = height * width,\ 540 .max_level = level, 541 542 struct amdgpu_video_codecs { 543 const u32 codec_count; 544 const struct amdgpu_video_codec_info *codec_array; 545 }; 546 547 /* 548 * ASIC specific functions. 549 */ 550 struct amdgpu_asic_funcs { 551 bool (*read_disabled_bios)(struct amdgpu_device *adev); 552 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 553 u8 *bios, u32 length_bytes); 554 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 555 u32 sh_num, u32 reg_offset, u32 *value); 556 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 557 int (*reset)(struct amdgpu_device *adev); 558 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 559 /* get the reference clock */ 560 u32 (*get_xclk)(struct amdgpu_device *adev); 561 /* MM block clocks */ 562 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 563 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 564 /* static power management */ 565 int (*get_pcie_lanes)(struct amdgpu_device *adev); 566 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 567 /* get config memsize register */ 568 u32 (*get_config_memsize)(struct amdgpu_device *adev); 569 /* flush hdp write queue */ 570 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 571 /* invalidate hdp read cache */ 572 void (*invalidate_hdp)(struct amdgpu_device *adev, 573 struct amdgpu_ring *ring); 574 /* check if the asic needs a full reset of if soft reset will work */ 575 bool (*need_full_reset)(struct amdgpu_device *adev); 576 /* initialize doorbell layout for specific asic*/ 577 void (*init_doorbell_index)(struct amdgpu_device *adev); 578 /* PCIe bandwidth usage */ 579 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 580 uint64_t *count1); 581 /* do we need to reset the asic at init time (e.g., kexec) */ 582 bool (*need_reset_on_init)(struct amdgpu_device *adev); 583 /* PCIe replay counter */ 584 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 585 /* device supports BACO */ 586 bool (*supports_baco)(struct amdgpu_device *adev); 587 /* pre asic_init quirks */ 588 void (*pre_asic_init)(struct amdgpu_device *adev); 589 /* enter/exit umd stable pstate */ 590 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 591 /* query video codecs */ 592 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 593 const struct amdgpu_video_codecs **codecs); 594 }; 595 596 /* 597 * IOCTL. 598 */ 599 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 600 struct drm_file *filp); 601 602 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 603 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 604 struct drm_file *filp); 605 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 606 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 607 struct drm_file *filp); 608 609 /* VRAM scratch page for HDP bug, default vram page */ 610 struct amdgpu_vram_scratch { 611 struct amdgpu_bo *robj; 612 volatile uint32_t *ptr; 613 u64 gpu_addr; 614 }; 615 616 /* 617 * CGS 618 */ 619 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 620 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 621 622 /* 623 * Core structure, functions and helpers. 624 */ 625 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 626 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 627 628 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 629 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 630 631 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 632 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 633 634 struct amdgpu_mmio_remap { 635 u32 reg_offset; 636 resource_size_t bus_addr; 637 }; 638 639 /* Define the HW IP blocks will be used in driver , add more if necessary */ 640 enum amd_hw_ip_block_type { 641 GC_HWIP = 1, 642 HDP_HWIP, 643 SDMA0_HWIP, 644 SDMA1_HWIP, 645 SDMA2_HWIP, 646 SDMA3_HWIP, 647 SDMA4_HWIP, 648 SDMA5_HWIP, 649 SDMA6_HWIP, 650 SDMA7_HWIP, 651 LSDMA_HWIP, 652 MMHUB_HWIP, 653 ATHUB_HWIP, 654 NBIO_HWIP, 655 MP0_HWIP, 656 MP1_HWIP, 657 UVD_HWIP, 658 VCN_HWIP = UVD_HWIP, 659 JPEG_HWIP = VCN_HWIP, 660 VCN1_HWIP, 661 VCE_HWIP, 662 DF_HWIP, 663 DCE_HWIP, 664 OSSSYS_HWIP, 665 SMUIO_HWIP, 666 PWR_HWIP, 667 NBIF_HWIP, 668 THM_HWIP, 669 CLK_HWIP, 670 UMC_HWIP, 671 RSMU_HWIP, 672 XGMI_HWIP, 673 DCI_HWIP, 674 PCIE_HWIP, 675 MAX_HWIP 676 }; 677 678 #define HWIP_MAX_INSTANCE 11 679 680 #define HW_ID_MAX 300 681 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 682 #define IP_VERSION_MAJ(ver) ((ver) >> 16) 683 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF) 684 #define IP_VERSION_REV(ver) ((ver) & 0xFF) 685 686 struct amd_powerplay { 687 void *pp_handle; 688 const struct amd_pm_funcs *pp_funcs; 689 }; 690 691 struct ip_discovery_top; 692 693 /* polaris10 kickers */ 694 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 695 ((rid == 0xE3) || \ 696 (rid == 0xE4) || \ 697 (rid == 0xE5) || \ 698 (rid == 0xE7) || \ 699 (rid == 0xEF))) || \ 700 ((did == 0x6FDF) && \ 701 ((rid == 0xE7) || \ 702 (rid == 0xEF) || \ 703 (rid == 0xFF)))) 704 705 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 706 ((rid == 0xE1) || \ 707 (rid == 0xF7))) 708 709 /* polaris11 kickers */ 710 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 711 ((rid == 0xE0) || \ 712 (rid == 0xE5))) || \ 713 ((did == 0x67FF) && \ 714 ((rid == 0xCF) || \ 715 (rid == 0xEF) || \ 716 (rid == 0xFF)))) 717 718 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 719 ((rid == 0xE2))) 720 721 /* polaris12 kickers */ 722 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 723 ((rid == 0xC0) || \ 724 (rid == 0xC1) || \ 725 (rid == 0xC3) || \ 726 (rid == 0xC7))) || \ 727 ((did == 0x6981) && \ 728 ((rid == 0x00) || \ 729 (rid == 0x01) || \ 730 (rid == 0x10)))) 731 732 struct amdgpu_mqd_prop { 733 uint64_t mqd_gpu_addr; 734 uint64_t hqd_base_gpu_addr; 735 uint64_t rptr_gpu_addr; 736 uint64_t wptr_gpu_addr; 737 uint32_t queue_size; 738 bool use_doorbell; 739 uint32_t doorbell_index; 740 uint64_t eop_gpu_addr; 741 uint32_t hqd_pipe_priority; 742 uint32_t hqd_queue_priority; 743 bool hqd_active; 744 }; 745 746 struct amdgpu_mqd { 747 unsigned mqd_size; 748 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 749 struct amdgpu_mqd_prop *p); 750 }; 751 752 #define AMDGPU_RESET_MAGIC_NUM 64 753 #define AMDGPU_MAX_DF_PERFMONS 4 754 #define AMDGPU_PRODUCT_NAME_LEN 64 755 struct amdgpu_reset_domain; 756 757 struct amdgpu_device { 758 struct device *dev; 759 struct pci_dev *pdev; 760 struct drm_device ddev; 761 762 #ifdef CONFIG_DRM_AMD_ACP 763 struct amdgpu_acp acp; 764 #endif 765 struct amdgpu_hive_info *hive; 766 /* ASIC */ 767 enum amd_asic_type asic_type; 768 uint32_t family; 769 uint32_t rev_id; 770 uint32_t external_rev_id; 771 unsigned long flags; 772 unsigned long apu_flags; 773 int usec_timeout; 774 const struct amdgpu_asic_funcs *asic_funcs; 775 bool shutdown; 776 bool need_swiotlb; 777 bool accel_working; 778 struct notifier_block acpi_nb; 779 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 780 struct debugfs_blob_wrapper debugfs_vbios_blob; 781 struct debugfs_blob_wrapper debugfs_discovery_blob; 782 struct mutex srbm_mutex; 783 /* GRBM index mutex. Protects concurrent access to GRBM index */ 784 struct mutex grbm_idx_mutex; 785 struct dev_pm_domain vga_pm_domain; 786 bool have_disp_power_ref; 787 bool have_atomics_support; 788 789 /* BIOS */ 790 bool is_atom_fw; 791 uint8_t *bios; 792 uint32_t bios_size; 793 uint32_t bios_scratch_reg_offset; 794 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 795 796 /* Register/doorbell mmio */ 797 resource_size_t rmmio_base; 798 resource_size_t rmmio_size; 799 void __iomem *rmmio; 800 /* protects concurrent MM_INDEX/DATA based register access */ 801 spinlock_t mmio_idx_lock; 802 struct amdgpu_mmio_remap rmmio_remap; 803 /* protects concurrent SMC based register access */ 804 spinlock_t smc_idx_lock; 805 amdgpu_rreg_t smc_rreg; 806 amdgpu_wreg_t smc_wreg; 807 /* protects concurrent PCIE register access */ 808 spinlock_t pcie_idx_lock; 809 amdgpu_rreg_t pcie_rreg; 810 amdgpu_wreg_t pcie_wreg; 811 amdgpu_rreg_t pciep_rreg; 812 amdgpu_wreg_t pciep_wreg; 813 amdgpu_rreg64_t pcie_rreg64; 814 amdgpu_wreg64_t pcie_wreg64; 815 /* protects concurrent UVD register access */ 816 spinlock_t uvd_ctx_idx_lock; 817 amdgpu_rreg_t uvd_ctx_rreg; 818 amdgpu_wreg_t uvd_ctx_wreg; 819 /* protects concurrent DIDT register access */ 820 spinlock_t didt_idx_lock; 821 amdgpu_rreg_t didt_rreg; 822 amdgpu_wreg_t didt_wreg; 823 /* protects concurrent gc_cac register access */ 824 spinlock_t gc_cac_idx_lock; 825 amdgpu_rreg_t gc_cac_rreg; 826 amdgpu_wreg_t gc_cac_wreg; 827 /* protects concurrent se_cac register access */ 828 spinlock_t se_cac_idx_lock; 829 amdgpu_rreg_t se_cac_rreg; 830 amdgpu_wreg_t se_cac_wreg; 831 /* protects concurrent ENDPOINT (audio) register access */ 832 spinlock_t audio_endpt_idx_lock; 833 amdgpu_block_rreg_t audio_endpt_rreg; 834 amdgpu_block_wreg_t audio_endpt_wreg; 835 struct amdgpu_doorbell doorbell; 836 837 /* clock/pll info */ 838 struct amdgpu_clock clock; 839 840 /* MC */ 841 struct amdgpu_gmc gmc; 842 struct amdgpu_gart gart; 843 dma_addr_t dummy_page_addr; 844 struct amdgpu_vm_manager vm_manager; 845 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 846 unsigned num_vmhubs; 847 848 /* memory management */ 849 struct amdgpu_mman mman; 850 struct amdgpu_vram_scratch vram_scratch; 851 struct amdgpu_wb wb; 852 atomic64_t num_bytes_moved; 853 atomic64_t num_evictions; 854 atomic64_t num_vram_cpu_page_faults; 855 atomic_t gpu_reset_counter; 856 atomic_t vram_lost_counter; 857 858 /* data for buffer migration throttling */ 859 struct { 860 spinlock_t lock; 861 s64 last_update_us; 862 s64 accum_us; /* accumulated microseconds */ 863 s64 accum_us_vis; /* for visible VRAM */ 864 u32 log2_max_MBps; 865 } mm_stats; 866 867 /* display */ 868 bool enable_virtual_display; 869 struct amdgpu_vkms_output *amdgpu_vkms_output; 870 struct amdgpu_mode_info mode_info; 871 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 872 struct work_struct hotplug_work; 873 struct amdgpu_irq_src crtc_irq; 874 struct amdgpu_irq_src vline0_irq; 875 struct amdgpu_irq_src vupdate_irq; 876 struct amdgpu_irq_src pageflip_irq; 877 struct amdgpu_irq_src hpd_irq; 878 struct amdgpu_irq_src dmub_trace_irq; 879 struct amdgpu_irq_src dmub_outbox_irq; 880 881 /* rings */ 882 u64 fence_context; 883 unsigned num_rings; 884 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 885 struct dma_fence __rcu *gang_submit; 886 bool ib_pool_ready; 887 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 888 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 889 890 /* interrupts */ 891 struct amdgpu_irq irq; 892 893 /* powerplay */ 894 struct amd_powerplay powerplay; 895 struct amdgpu_pm pm; 896 u64 cg_flags; 897 u32 pg_flags; 898 899 /* nbio */ 900 struct amdgpu_nbio nbio; 901 902 /* hdp */ 903 struct amdgpu_hdp hdp; 904 905 /* smuio */ 906 struct amdgpu_smuio smuio; 907 908 /* mmhub */ 909 struct amdgpu_mmhub mmhub; 910 911 /* gfxhub */ 912 struct amdgpu_gfxhub gfxhub; 913 914 /* gfx */ 915 struct amdgpu_gfx gfx; 916 917 /* sdma */ 918 struct amdgpu_sdma sdma; 919 920 /* lsdma */ 921 struct amdgpu_lsdma lsdma; 922 923 /* uvd */ 924 struct amdgpu_uvd uvd; 925 926 /* vce */ 927 struct amdgpu_vce vce; 928 929 /* vcn */ 930 struct amdgpu_vcn vcn; 931 932 /* jpeg */ 933 struct amdgpu_jpeg jpeg; 934 935 /* firmwares */ 936 struct amdgpu_firmware firmware; 937 938 /* PSP */ 939 struct psp_context psp; 940 941 /* GDS */ 942 struct amdgpu_gds gds; 943 944 /* KFD */ 945 struct amdgpu_kfd_dev kfd; 946 947 /* UMC */ 948 struct amdgpu_umc umc; 949 950 /* display related functionality */ 951 struct amdgpu_display_manager dm; 952 953 /* mes */ 954 bool enable_mes; 955 bool enable_mes_kiq; 956 struct amdgpu_mes mes; 957 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 958 959 /* df */ 960 struct amdgpu_df df; 961 962 /* MCA */ 963 struct amdgpu_mca mca; 964 965 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 966 uint32_t harvest_ip_mask; 967 int num_ip_blocks; 968 struct mutex mn_lock; 969 DECLARE_HASHTABLE(mn_hash, 7); 970 971 /* tracking pinned memory */ 972 atomic64_t vram_pin_size; 973 atomic64_t visible_pin_size; 974 atomic64_t gart_pin_size; 975 976 /* soc15 register offset based on ip, instance and segment */ 977 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 978 979 /* delayed work_func for deferring clockgating during resume */ 980 struct delayed_work delayed_init_work; 981 982 struct amdgpu_virt virt; 983 984 /* link all shadow bo */ 985 struct list_head shadow_list; 986 struct mutex shadow_list_lock; 987 988 /* record hw reset is performed */ 989 bool has_hw_reset; 990 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 991 992 /* s3/s4 mask */ 993 bool in_suspend; 994 bool in_s3; 995 bool in_s4; 996 bool in_s0ix; 997 998 enum pp_mp1_state mp1_state; 999 struct amdgpu_doorbell_index doorbell_index; 1000 1001 struct mutex notifier_lock; 1002 1003 int asic_reset_res; 1004 struct work_struct xgmi_reset_work; 1005 struct list_head reset_list; 1006 1007 long gfx_timeout; 1008 long sdma_timeout; 1009 long video_timeout; 1010 long compute_timeout; 1011 1012 uint64_t unique_id; 1013 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1014 1015 /* enable runtime pm on the device */ 1016 bool in_runpm; 1017 bool has_pr3; 1018 1019 bool pm_sysfs_en; 1020 bool ucode_sysfs_en; 1021 bool psp_sysfs_en; 1022 1023 /* Chip product information */ 1024 char product_number[20]; 1025 char product_name[AMDGPU_PRODUCT_NAME_LEN]; 1026 char serial[20]; 1027 1028 atomic_t throttling_logging_enabled; 1029 struct ratelimit_state throttling_logging_rs; 1030 uint32_t ras_hw_enabled; 1031 uint32_t ras_enabled; 1032 1033 bool no_hw_access; 1034 struct pci_saved_state *pci_state; 1035 pci_channel_state_t pci_channel_state; 1036 1037 struct amdgpu_reset_control *reset_cntl; 1038 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1039 1040 bool ram_is_direct_mapped; 1041 1042 struct list_head ras_list; 1043 1044 struct ip_discovery_top *ip_top; 1045 1046 struct amdgpu_reset_domain *reset_domain; 1047 1048 struct mutex benchmark_mutex; 1049 1050 /* reset dump register */ 1051 uint32_t *reset_dump_reg_list; 1052 uint32_t *reset_dump_reg_value; 1053 int num_regs; 1054 #ifdef CONFIG_DEV_COREDUMP 1055 struct amdgpu_task_info reset_task_info; 1056 bool reset_vram_lost; 1057 struct timespec64 reset_time; 1058 #endif 1059 1060 bool scpm_enabled; 1061 uint32_t scpm_status; 1062 1063 struct work_struct reset_work; 1064 1065 bool job_hang; 1066 }; 1067 1068 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1069 { 1070 return container_of(ddev, struct amdgpu_device, ddev); 1071 } 1072 1073 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1074 { 1075 return &adev->ddev; 1076 } 1077 1078 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1079 { 1080 return container_of(bdev, struct amdgpu_device, mman.bdev); 1081 } 1082 1083 int amdgpu_device_init(struct amdgpu_device *adev, 1084 uint32_t flags); 1085 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1086 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1087 1088 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1089 1090 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1091 void *buf, size_t size, bool write); 1092 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1093 void *buf, size_t size, bool write); 1094 1095 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1096 void *buf, size_t size, bool write); 1097 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1098 uint32_t reg, uint32_t acc_flags); 1099 void amdgpu_device_wreg(struct amdgpu_device *adev, 1100 uint32_t reg, uint32_t v, 1101 uint32_t acc_flags); 1102 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1103 uint32_t reg, uint32_t v); 1104 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1105 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1106 1107 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1108 u32 pcie_index, u32 pcie_data, 1109 u32 reg_addr); 1110 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1111 u32 pcie_index, u32 pcie_data, 1112 u32 reg_addr); 1113 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1114 u32 pcie_index, u32 pcie_data, 1115 u32 reg_addr, u32 reg_data); 1116 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1117 u32 pcie_index, u32 pcie_data, 1118 u32 reg_addr, u64 reg_data); 1119 1120 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1121 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1122 1123 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1124 struct amdgpu_reset_context *reset_context); 1125 1126 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1127 struct amdgpu_reset_context *reset_context); 1128 1129 int emu_soc_asic_init(struct amdgpu_device *adev); 1130 1131 /* 1132 * Registers read & write functions. 1133 */ 1134 #define AMDGPU_REGS_NO_KIQ (1<<1) 1135 #define AMDGPU_REGS_RLC (1<<2) 1136 1137 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1138 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1139 1140 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1141 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1142 1143 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1144 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1145 1146 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1147 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1148 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1149 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1150 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1151 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1152 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1153 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1154 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1155 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1156 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1157 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1158 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1159 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1160 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1161 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1162 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1163 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1164 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1165 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1166 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1167 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1168 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1169 #define WREG32_P(reg, val, mask) \ 1170 do { \ 1171 uint32_t tmp_ = RREG32(reg); \ 1172 tmp_ &= (mask); \ 1173 tmp_ |= ((val) & ~(mask)); \ 1174 WREG32(reg, tmp_); \ 1175 } while (0) 1176 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1177 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1178 #define WREG32_PLL_P(reg, val, mask) \ 1179 do { \ 1180 uint32_t tmp_ = RREG32_PLL(reg); \ 1181 tmp_ &= (mask); \ 1182 tmp_ |= ((val) & ~(mask)); \ 1183 WREG32_PLL(reg, tmp_); \ 1184 } while (0) 1185 1186 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1187 do { \ 1188 u32 tmp = RREG32_SMC(_Reg); \ 1189 tmp &= (_Mask); \ 1190 tmp |= ((_Val) & ~(_Mask)); \ 1191 WREG32_SMC(_Reg, tmp); \ 1192 } while (0) 1193 1194 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1195 1196 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1197 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1198 1199 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1200 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1201 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1202 1203 #define REG_GET_FIELD(value, reg, field) \ 1204 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1205 1206 #define WREG32_FIELD(reg, field, val) \ 1207 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1208 1209 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1210 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1211 1212 /* 1213 * BIOS helpers. 1214 */ 1215 #define RBIOS8(i) (adev->bios[i]) 1216 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1217 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1218 1219 /* 1220 * ASICs macro. 1221 */ 1222 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1223 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1224 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1225 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1226 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1227 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1228 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1229 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1230 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1231 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1232 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1233 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1234 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1235 #define amdgpu_asic_flush_hdp(adev, r) \ 1236 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1237 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1238 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1239 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0)) 1240 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1241 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1242 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1243 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1244 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1245 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1246 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1247 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1248 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1249 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1250 1251 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1252 1253 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 1254 1255 /* Common functions */ 1256 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1257 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1258 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1259 struct amdgpu_job *job, 1260 struct amdgpu_reset_context *reset_context); 1261 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1262 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1263 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1264 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1265 1266 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1267 u64 num_vis_bytes); 1268 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1269 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1270 const u32 *registers, 1271 const u32 array_size); 1272 1273 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1274 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1275 bool amdgpu_device_supports_px(struct drm_device *dev); 1276 bool amdgpu_device_supports_boco(struct drm_device *dev); 1277 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1278 bool amdgpu_device_supports_baco(struct drm_device *dev); 1279 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1280 struct amdgpu_device *peer_adev); 1281 int amdgpu_device_baco_enter(struct drm_device *dev); 1282 int amdgpu_device_baco_exit(struct drm_device *dev); 1283 1284 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1285 struct amdgpu_ring *ring); 1286 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1287 struct amdgpu_ring *ring); 1288 1289 void amdgpu_device_halt(struct amdgpu_device *adev); 1290 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1291 u32 reg); 1292 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1293 u32 reg, u32 v); 1294 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1295 struct dma_fence *gang); 1296 1297 /* atpx handler */ 1298 #if defined(CONFIG_VGA_SWITCHEROO) 1299 void amdgpu_register_atpx_handler(void); 1300 void amdgpu_unregister_atpx_handler(void); 1301 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1302 bool amdgpu_is_atpx_hybrid(void); 1303 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1304 bool amdgpu_has_atpx(void); 1305 #else 1306 static inline void amdgpu_register_atpx_handler(void) {} 1307 static inline void amdgpu_unregister_atpx_handler(void) {} 1308 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1309 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1310 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1311 static inline bool amdgpu_has_atpx(void) { return false; } 1312 #endif 1313 1314 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1315 void *amdgpu_atpx_get_dhandle(void); 1316 #else 1317 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1318 #endif 1319 1320 /* 1321 * KMS 1322 */ 1323 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1324 extern const int amdgpu_max_kms_ioctl; 1325 1326 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1327 void amdgpu_driver_unload_kms(struct drm_device *dev); 1328 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1329 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1330 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1331 struct drm_file *file_priv); 1332 void amdgpu_driver_release_kms(struct drm_device *dev); 1333 1334 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1335 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1336 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1337 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1338 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1339 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1340 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1341 struct drm_file *filp); 1342 1343 /* 1344 * functions used by amdgpu_encoder.c 1345 */ 1346 struct amdgpu_afmt_acr { 1347 u32 clock; 1348 1349 int n_32khz; 1350 int cts_32khz; 1351 1352 int n_44_1khz; 1353 int cts_44_1khz; 1354 1355 int n_48khz; 1356 int cts_48khz; 1357 1358 }; 1359 1360 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1361 1362 /* amdgpu_acpi.c */ 1363 1364 /* ATCS Device/Driver State */ 1365 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1366 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1367 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1368 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1369 1370 #if defined(CONFIG_ACPI) 1371 int amdgpu_acpi_init(struct amdgpu_device *adev); 1372 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1373 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1374 bool amdgpu_acpi_is_power_shift_control_supported(void); 1375 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1376 u8 perf_req, bool advertise); 1377 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1378 u8 dev_state, bool drv_state); 1379 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1380 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1381 1382 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1383 void amdgpu_acpi_detect(void); 1384 #else 1385 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1386 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1387 static inline void amdgpu_acpi_detect(void) { } 1388 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1389 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1390 u8 dev_state, bool drv_state) { return 0; } 1391 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1392 enum amdgpu_ss ss_state) { return 0; } 1393 #endif 1394 1395 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1396 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1397 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1398 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1399 #else 1400 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1401 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1402 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1403 #endif 1404 1405 #if defined(CONFIG_DRM_AMD_DC) 1406 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1407 #else 1408 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1409 #endif 1410 1411 1412 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1413 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1414 1415 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1416 pci_channel_state_t state); 1417 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1418 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1419 void amdgpu_pci_resume(struct pci_dev *pdev); 1420 1421 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1422 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1423 1424 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1425 1426 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1427 enum amd_clockgating_state state); 1428 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1429 enum amd_powergating_state state); 1430 1431 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1432 { 1433 return amdgpu_gpu_recovery != 0 && 1434 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1435 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1436 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1437 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1438 } 1439 1440 #include "amdgpu_object.h" 1441 1442 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1443 { 1444 return adev->gmc.tmz_enabled; 1445 } 1446 1447 int amdgpu_in_reset(struct amdgpu_device *adev); 1448 1449 #endif 1450