1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_execbuf_util.h> 59 60 #include <drm/amdgpu_drm.h> 61 #include <drm/drm_gem.h> 62 #include <drm/drm_ioctl.h> 63 #include <drm/gpu_scheduler.h> 64 65 #include <kgd_kfd_interface.h> 66 #include "dm_pp_interface.h" 67 #include "kgd_pp_interface.h" 68 69 #include "amd_shared.h" 70 #include "amdgpu_mode.h" 71 #include "amdgpu_ih.h" 72 #include "amdgpu_irq.h" 73 #include "amdgpu_ucode.h" 74 #include "amdgpu_ttm.h" 75 #include "amdgpu_psp.h" 76 #include "amdgpu_gds.h" 77 #include "amdgpu_sync.h" 78 #include "amdgpu_ring.h" 79 #include "amdgpu_vm.h" 80 #include "amdgpu_dpm.h" 81 #include "amdgpu_acp.h" 82 #include "amdgpu_uvd.h" 83 #include "amdgpu_vce.h" 84 #include "amdgpu_vcn.h" 85 #include "amdgpu_jpeg.h" 86 #include "amdgpu_mn.h" 87 #include "amdgpu_gmc.h" 88 #include "amdgpu_gfx.h" 89 #include "amdgpu_sdma.h" 90 #include "amdgpu_nbio.h" 91 #include "amdgpu_hdp.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_smu.h" 103 #include "amdgpu_discovery.h" 104 #include "amdgpu_mes.h" 105 #include "amdgpu_umc.h" 106 #include "amdgpu_mmhub.h" 107 #include "amdgpu_gfxhub.h" 108 #include "amdgpu_df.h" 109 #include "amdgpu_smuio.h" 110 #include "amdgpu_fdinfo.h" 111 112 #define MAX_GPU_INSTANCE 16 113 114 struct amdgpu_gpu_instance 115 { 116 struct amdgpu_device *adev; 117 int mgpu_fan_enabled; 118 }; 119 120 struct amdgpu_mgpu_info 121 { 122 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 123 struct mutex mutex; 124 uint32_t num_gpu; 125 uint32_t num_dgpu; 126 uint32_t num_apu; 127 128 /* delayed reset_func for XGMI configuration if necessary */ 129 struct delayed_work delayed_reset_work; 130 bool pending_reset; 131 }; 132 133 enum amdgpu_ss { 134 AMDGPU_SS_DRV_LOAD, 135 AMDGPU_SS_DEV_D0, 136 AMDGPU_SS_DEV_D3, 137 AMDGPU_SS_DRV_UNLOAD 138 }; 139 140 struct amdgpu_watchdog_timer 141 { 142 bool timeout_fatal_disable; 143 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 144 }; 145 146 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 147 148 /* 149 * Modules parameters. 150 */ 151 extern int amdgpu_modeset; 152 extern int amdgpu_vram_limit; 153 extern int amdgpu_vis_vram_limit; 154 extern int amdgpu_gart_size; 155 extern int amdgpu_gtt_size; 156 extern int amdgpu_moverate; 157 extern int amdgpu_benchmarking; 158 extern int amdgpu_testing; 159 extern int amdgpu_audio; 160 extern int amdgpu_disp_priority; 161 extern int amdgpu_hw_i2c; 162 extern int amdgpu_pcie_gen2; 163 extern int amdgpu_msi; 164 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 165 extern int amdgpu_dpm; 166 extern int amdgpu_fw_load_type; 167 extern int amdgpu_aspm; 168 extern int amdgpu_runtime_pm; 169 extern uint amdgpu_ip_block_mask; 170 extern int amdgpu_bapm; 171 extern int amdgpu_deep_color; 172 extern int amdgpu_vm_size; 173 extern int amdgpu_vm_block_size; 174 extern int amdgpu_vm_fragment_size; 175 extern int amdgpu_vm_fault_stop; 176 extern int amdgpu_vm_debug; 177 extern int amdgpu_vm_update_mode; 178 extern int amdgpu_exp_hw_support; 179 extern int amdgpu_dc; 180 extern int amdgpu_sched_jobs; 181 extern int amdgpu_sched_hw_submission; 182 extern uint amdgpu_pcie_gen_cap; 183 extern uint amdgpu_pcie_lane_cap; 184 extern uint amdgpu_cg_mask; 185 extern uint amdgpu_pg_mask; 186 extern uint amdgpu_sdma_phase_quantum; 187 extern char *amdgpu_disable_cu; 188 extern char *amdgpu_virtual_display; 189 extern uint amdgpu_pp_feature_mask; 190 extern uint amdgpu_force_long_training; 191 extern int amdgpu_job_hang_limit; 192 extern int amdgpu_lbpw; 193 extern int amdgpu_compute_multipipe; 194 extern int amdgpu_gpu_recovery; 195 extern int amdgpu_emu_mode; 196 extern uint amdgpu_smu_memory_pool_size; 197 extern int amdgpu_smu_pptable_id; 198 extern uint amdgpu_dc_feature_mask; 199 extern uint amdgpu_freesync_vid_mode; 200 extern uint amdgpu_dc_debug_mask; 201 extern uint amdgpu_dm_abm_level; 202 extern int amdgpu_backlight; 203 extern struct amdgpu_mgpu_info mgpu_info; 204 extern int amdgpu_ras_enable; 205 extern uint amdgpu_ras_mask; 206 extern int amdgpu_bad_page_threshold; 207 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 208 extern int amdgpu_async_gfx_ring; 209 extern int amdgpu_mcbp; 210 extern int amdgpu_discovery; 211 extern int amdgpu_mes; 212 extern int amdgpu_noretry; 213 extern int amdgpu_force_asic_type; 214 extern int amdgpu_smartshift_bias; 215 #ifdef CONFIG_HSA_AMD 216 extern int sched_policy; 217 extern bool debug_evictions; 218 extern bool no_system_mem_limit; 219 #else 220 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 221 static const bool __maybe_unused debug_evictions; /* = false */ 222 static const bool __maybe_unused no_system_mem_limit; 223 #endif 224 225 extern int amdgpu_tmz; 226 extern int amdgpu_reset_method; 227 228 #ifdef CONFIG_DRM_AMDGPU_SI 229 extern int amdgpu_si_support; 230 #endif 231 #ifdef CONFIG_DRM_AMDGPU_CIK 232 extern int amdgpu_cik_support; 233 #endif 234 extern int amdgpu_num_kcq; 235 236 #define AMDGPU_VM_MAX_NUM_CTX 4096 237 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 238 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 239 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 240 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 241 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 242 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 243 #define AMDGPUFB_CONN_LIMIT 4 244 #define AMDGPU_BIOS_NUM_SCRATCH 16 245 246 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 247 248 /* hard reset data */ 249 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 250 251 /* reset flags */ 252 #define AMDGPU_RESET_GFX (1 << 0) 253 #define AMDGPU_RESET_COMPUTE (1 << 1) 254 #define AMDGPU_RESET_DMA (1 << 2) 255 #define AMDGPU_RESET_CP (1 << 3) 256 #define AMDGPU_RESET_GRBM (1 << 4) 257 #define AMDGPU_RESET_DMA1 (1 << 5) 258 #define AMDGPU_RESET_RLC (1 << 6) 259 #define AMDGPU_RESET_SEM (1 << 7) 260 #define AMDGPU_RESET_IH (1 << 8) 261 #define AMDGPU_RESET_VMC (1 << 9) 262 #define AMDGPU_RESET_MC (1 << 10) 263 #define AMDGPU_RESET_DISPLAY (1 << 11) 264 #define AMDGPU_RESET_UVD (1 << 12) 265 #define AMDGPU_RESET_VCE (1 << 13) 266 #define AMDGPU_RESET_VCE1 (1 << 14) 267 268 /* max cursor sizes (in pixels) */ 269 #define CIK_CURSOR_WIDTH 128 270 #define CIK_CURSOR_HEIGHT 128 271 272 /* smasrt shift bias level limits */ 273 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 274 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 275 276 struct amdgpu_device; 277 struct amdgpu_ib; 278 struct amdgpu_cs_parser; 279 struct amdgpu_job; 280 struct amdgpu_irq_src; 281 struct amdgpu_fpriv; 282 struct amdgpu_bo_va_mapping; 283 struct kfd_vm_fault_info; 284 struct amdgpu_hive_info; 285 struct amdgpu_reset_context; 286 struct amdgpu_reset_control; 287 288 enum amdgpu_cp_irq { 289 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 290 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 291 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 292 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 293 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 294 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 295 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 296 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 297 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 298 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 299 300 AMDGPU_CP_IRQ_LAST 301 }; 302 303 enum amdgpu_thermal_irq { 304 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 305 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 306 307 AMDGPU_THERMAL_IRQ_LAST 308 }; 309 310 enum amdgpu_kiq_irq { 311 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 312 AMDGPU_CP_KIQ_IRQ_LAST 313 }; 314 315 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 316 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 317 #define MAX_KIQ_REG_TRY 1000 318 319 int amdgpu_device_ip_set_clockgating_state(void *dev, 320 enum amd_ip_block_type block_type, 321 enum amd_clockgating_state state); 322 int amdgpu_device_ip_set_powergating_state(void *dev, 323 enum amd_ip_block_type block_type, 324 enum amd_powergating_state state); 325 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 326 u32 *flags); 327 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 328 enum amd_ip_block_type block_type); 329 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 330 enum amd_ip_block_type block_type); 331 332 #define AMDGPU_MAX_IP_NUM 16 333 334 struct amdgpu_ip_block_status { 335 bool valid; 336 bool sw; 337 bool hw; 338 bool late_initialized; 339 bool hang; 340 }; 341 342 struct amdgpu_ip_block_version { 343 const enum amd_ip_block_type type; 344 const u32 major; 345 const u32 minor; 346 const u32 rev; 347 const struct amd_ip_funcs *funcs; 348 }; 349 350 #define HW_REV(_Major, _Minor, _Rev) \ 351 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 352 353 struct amdgpu_ip_block { 354 struct amdgpu_ip_block_status status; 355 const struct amdgpu_ip_block_version *version; 356 }; 357 358 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 359 enum amd_ip_block_type type, 360 u32 major, u32 minor); 361 362 struct amdgpu_ip_block * 363 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 364 enum amd_ip_block_type type); 365 366 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 367 const struct amdgpu_ip_block_version *ip_block_version); 368 369 /* 370 * BIOS. 371 */ 372 bool amdgpu_get_bios(struct amdgpu_device *adev); 373 bool amdgpu_read_bios(struct amdgpu_device *adev); 374 375 /* 376 * Clocks 377 */ 378 379 #define AMDGPU_MAX_PPLL 3 380 381 struct amdgpu_clock { 382 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 383 struct amdgpu_pll spll; 384 struct amdgpu_pll mpll; 385 /* 10 Khz units */ 386 uint32_t default_mclk; 387 uint32_t default_sclk; 388 uint32_t default_dispclk; 389 uint32_t current_dispclk; 390 uint32_t dp_extclk; 391 uint32_t max_pixel_clock; 392 }; 393 394 /* sub-allocation manager, it has to be protected by another lock. 395 * By conception this is an helper for other part of the driver 396 * like the indirect buffer or semaphore, which both have their 397 * locking. 398 * 399 * Principe is simple, we keep a list of sub allocation in offset 400 * order (first entry has offset == 0, last entry has the highest 401 * offset). 402 * 403 * When allocating new object we first check if there is room at 404 * the end total_size - (last_object_offset + last_object_size) >= 405 * alloc_size. If so we allocate new object there. 406 * 407 * When there is not enough room at the end, we start waiting for 408 * each sub object until we reach object_offset+object_size >= 409 * alloc_size, this object then become the sub object we return. 410 * 411 * Alignment can't be bigger than page size. 412 * 413 * Hole are not considered for allocation to keep things simple. 414 * Assumption is that there won't be hole (all object on same 415 * alignment). 416 */ 417 418 #define AMDGPU_SA_NUM_FENCE_LISTS 32 419 420 struct amdgpu_sa_manager { 421 wait_queue_head_t wq; 422 struct amdgpu_bo *bo; 423 struct list_head *hole; 424 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 425 struct list_head olist; 426 unsigned size; 427 uint64_t gpu_addr; 428 void *cpu_ptr; 429 uint32_t domain; 430 uint32_t align; 431 }; 432 433 /* sub-allocation buffer */ 434 struct amdgpu_sa_bo { 435 struct list_head olist; 436 struct list_head flist; 437 struct amdgpu_sa_manager *manager; 438 unsigned soffset; 439 unsigned eoffset; 440 struct dma_fence *fence; 441 }; 442 443 int amdgpu_fence_slab_init(void); 444 void amdgpu_fence_slab_fini(void); 445 446 /* 447 * IRQS. 448 */ 449 450 struct amdgpu_flip_work { 451 struct delayed_work flip_work; 452 struct work_struct unpin_work; 453 struct amdgpu_device *adev; 454 int crtc_id; 455 u32 target_vblank; 456 uint64_t base; 457 struct drm_pending_vblank_event *event; 458 struct amdgpu_bo *old_abo; 459 struct dma_fence *excl; 460 unsigned shared_count; 461 struct dma_fence **shared; 462 struct dma_fence_cb cb; 463 bool async; 464 }; 465 466 467 /* 468 * CP & rings. 469 */ 470 471 struct amdgpu_ib { 472 struct amdgpu_sa_bo *sa_bo; 473 uint32_t length_dw; 474 uint64_t gpu_addr; 475 uint32_t *ptr; 476 uint32_t flags; 477 }; 478 479 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 480 481 /* 482 * file private structure 483 */ 484 485 struct amdgpu_fpriv { 486 struct amdgpu_vm vm; 487 struct amdgpu_bo_va *prt_va; 488 struct amdgpu_bo_va *csa_va; 489 struct mutex bo_list_lock; 490 struct idr bo_list_handles; 491 struct amdgpu_ctx_mgr ctx_mgr; 492 }; 493 494 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 495 496 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 497 unsigned size, 498 enum amdgpu_ib_pool_type pool, 499 struct amdgpu_ib *ib); 500 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 501 struct dma_fence *f); 502 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 503 struct amdgpu_ib *ibs, struct amdgpu_job *job, 504 struct dma_fence **f); 505 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 506 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 507 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 508 509 /* 510 * CS. 511 */ 512 struct amdgpu_cs_chunk { 513 uint32_t chunk_id; 514 uint32_t length_dw; 515 void *kdata; 516 }; 517 518 struct amdgpu_cs_post_dep { 519 struct drm_syncobj *syncobj; 520 struct dma_fence_chain *chain; 521 u64 point; 522 }; 523 524 struct amdgpu_cs_parser { 525 struct amdgpu_device *adev; 526 struct drm_file *filp; 527 struct amdgpu_ctx *ctx; 528 529 /* chunks */ 530 unsigned nchunks; 531 struct amdgpu_cs_chunk *chunks; 532 533 /* scheduler job object */ 534 struct amdgpu_job *job; 535 struct drm_sched_entity *entity; 536 537 /* buffer objects */ 538 struct ww_acquire_ctx ticket; 539 struct amdgpu_bo_list *bo_list; 540 struct amdgpu_mn *mn; 541 struct amdgpu_bo_list_entry vm_pd; 542 struct list_head validated; 543 struct dma_fence *fence; 544 uint64_t bytes_moved_threshold; 545 uint64_t bytes_moved_vis_threshold; 546 uint64_t bytes_moved; 547 uint64_t bytes_moved_vis; 548 549 /* user fence */ 550 struct amdgpu_bo_list_entry uf_entry; 551 552 unsigned num_post_deps; 553 struct amdgpu_cs_post_dep *post_deps; 554 }; 555 556 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 557 uint32_t ib_idx, int idx) 558 { 559 return p->job->ibs[ib_idx].ptr[idx]; 560 } 561 562 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 563 uint32_t ib_idx, int idx, 564 uint32_t value) 565 { 566 p->job->ibs[ib_idx].ptr[idx] = value; 567 } 568 569 /* 570 * Writeback 571 */ 572 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 573 574 struct amdgpu_wb { 575 struct amdgpu_bo *wb_obj; 576 volatile uint32_t *wb; 577 uint64_t gpu_addr; 578 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 579 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 580 }; 581 582 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 583 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 584 585 /* 586 * Benchmarking 587 */ 588 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 589 590 591 /* 592 * Testing 593 */ 594 void amdgpu_test_moves(struct amdgpu_device *adev); 595 596 /* 597 * ASIC specific register table accessible by UMD 598 */ 599 struct amdgpu_allowed_register_entry { 600 uint32_t reg_offset; 601 bool grbm_indexed; 602 }; 603 604 enum amd_reset_method { 605 AMD_RESET_METHOD_NONE = -1, 606 AMD_RESET_METHOD_LEGACY = 0, 607 AMD_RESET_METHOD_MODE0, 608 AMD_RESET_METHOD_MODE1, 609 AMD_RESET_METHOD_MODE2, 610 AMD_RESET_METHOD_BACO, 611 AMD_RESET_METHOD_PCI, 612 }; 613 614 struct amdgpu_video_codec_info { 615 u32 codec_type; 616 u32 max_width; 617 u32 max_height; 618 u32 max_pixels_per_frame; 619 u32 max_level; 620 }; 621 622 #define codec_info_build(type, width, height, level) \ 623 .codec_type = type,\ 624 .max_width = width,\ 625 .max_height = height,\ 626 .max_pixels_per_frame = height * width,\ 627 .max_level = level, 628 629 struct amdgpu_video_codecs { 630 const u32 codec_count; 631 const struct amdgpu_video_codec_info *codec_array; 632 }; 633 634 /* 635 * ASIC specific functions. 636 */ 637 struct amdgpu_asic_funcs { 638 bool (*read_disabled_bios)(struct amdgpu_device *adev); 639 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 640 u8 *bios, u32 length_bytes); 641 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 642 u32 sh_num, u32 reg_offset, u32 *value); 643 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 644 int (*reset)(struct amdgpu_device *adev); 645 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 646 /* get the reference clock */ 647 u32 (*get_xclk)(struct amdgpu_device *adev); 648 /* MM block clocks */ 649 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 650 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 651 /* static power management */ 652 int (*get_pcie_lanes)(struct amdgpu_device *adev); 653 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 654 /* get config memsize register */ 655 u32 (*get_config_memsize)(struct amdgpu_device *adev); 656 /* flush hdp write queue */ 657 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 658 /* invalidate hdp read cache */ 659 void (*invalidate_hdp)(struct amdgpu_device *adev, 660 struct amdgpu_ring *ring); 661 /* check if the asic needs a full reset of if soft reset will work */ 662 bool (*need_full_reset)(struct amdgpu_device *adev); 663 /* initialize doorbell layout for specific asic*/ 664 void (*init_doorbell_index)(struct amdgpu_device *adev); 665 /* PCIe bandwidth usage */ 666 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 667 uint64_t *count1); 668 /* do we need to reset the asic at init time (e.g., kexec) */ 669 bool (*need_reset_on_init)(struct amdgpu_device *adev); 670 /* PCIe replay counter */ 671 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 672 /* device supports BACO */ 673 bool (*supports_baco)(struct amdgpu_device *adev); 674 /* pre asic_init quirks */ 675 void (*pre_asic_init)(struct amdgpu_device *adev); 676 /* enter/exit umd stable pstate */ 677 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 678 /* query video codecs */ 679 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 680 const struct amdgpu_video_codecs **codecs); 681 }; 682 683 /* 684 * IOCTL. 685 */ 686 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 687 struct drm_file *filp); 688 689 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 690 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 691 struct drm_file *filp); 692 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 693 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 694 struct drm_file *filp); 695 696 /* VRAM scratch page for HDP bug, default vram page */ 697 struct amdgpu_vram_scratch { 698 struct amdgpu_bo *robj; 699 volatile uint32_t *ptr; 700 u64 gpu_addr; 701 }; 702 703 /* 704 * CGS 705 */ 706 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 707 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 708 709 /* 710 * Core structure, functions and helpers. 711 */ 712 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 713 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 714 715 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 716 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 717 718 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 719 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 720 721 struct amdgpu_mmio_remap { 722 u32 reg_offset; 723 resource_size_t bus_addr; 724 }; 725 726 /* Define the HW IP blocks will be used in driver , add more if necessary */ 727 enum amd_hw_ip_block_type { 728 GC_HWIP = 1, 729 HDP_HWIP, 730 SDMA0_HWIP, 731 SDMA1_HWIP, 732 SDMA2_HWIP, 733 SDMA3_HWIP, 734 SDMA4_HWIP, 735 SDMA5_HWIP, 736 SDMA6_HWIP, 737 SDMA7_HWIP, 738 MMHUB_HWIP, 739 ATHUB_HWIP, 740 NBIO_HWIP, 741 MP0_HWIP, 742 MP1_HWIP, 743 UVD_HWIP, 744 VCN_HWIP = UVD_HWIP, 745 JPEG_HWIP = VCN_HWIP, 746 VCE_HWIP, 747 DF_HWIP, 748 DCE_HWIP, 749 OSSSYS_HWIP, 750 SMUIO_HWIP, 751 PWR_HWIP, 752 NBIF_HWIP, 753 THM_HWIP, 754 CLK_HWIP, 755 UMC_HWIP, 756 RSMU_HWIP, 757 MAX_HWIP 758 }; 759 760 #define HWIP_MAX_INSTANCE 8 761 762 struct amd_powerplay { 763 void *pp_handle; 764 const struct amd_pm_funcs *pp_funcs; 765 }; 766 767 /* polaris10 kickers */ 768 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 769 ((rid == 0xE3) || \ 770 (rid == 0xE4) || \ 771 (rid == 0xE5) || \ 772 (rid == 0xE7) || \ 773 (rid == 0xEF))) || \ 774 ((did == 0x6FDF) && \ 775 ((rid == 0xE7) || \ 776 (rid == 0xEF) || \ 777 (rid == 0xFF)))) 778 779 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 780 ((rid == 0xE1) || \ 781 (rid == 0xF7))) 782 783 /* polaris11 kickers */ 784 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 785 ((rid == 0xE0) || \ 786 (rid == 0xE5))) || \ 787 ((did == 0x67FF) && \ 788 ((rid == 0xCF) || \ 789 (rid == 0xEF) || \ 790 (rid == 0xFF)))) 791 792 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 793 ((rid == 0xE2))) 794 795 /* polaris12 kickers */ 796 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 797 ((rid == 0xC0) || \ 798 (rid == 0xC1) || \ 799 (rid == 0xC3) || \ 800 (rid == 0xC7))) || \ 801 ((did == 0x6981) && \ 802 ((rid == 0x00) || \ 803 (rid == 0x01) || \ 804 (rid == 0x10)))) 805 806 #define AMDGPU_RESET_MAGIC_NUM 64 807 #define AMDGPU_MAX_DF_PERFMONS 4 808 struct amdgpu_device { 809 struct device *dev; 810 struct pci_dev *pdev; 811 struct drm_device ddev; 812 813 #ifdef CONFIG_DRM_AMD_ACP 814 struct amdgpu_acp acp; 815 #endif 816 struct amdgpu_hive_info *hive; 817 /* ASIC */ 818 enum amd_asic_type asic_type; 819 uint32_t family; 820 uint32_t rev_id; 821 uint32_t external_rev_id; 822 unsigned long flags; 823 unsigned long apu_flags; 824 int usec_timeout; 825 const struct amdgpu_asic_funcs *asic_funcs; 826 bool shutdown; 827 bool need_swiotlb; 828 bool accel_working; 829 struct notifier_block acpi_nb; 830 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 831 struct debugfs_blob_wrapper debugfs_vbios_blob; 832 struct mutex srbm_mutex; 833 /* GRBM index mutex. Protects concurrent access to GRBM index */ 834 struct mutex grbm_idx_mutex; 835 struct dev_pm_domain vga_pm_domain; 836 bool have_disp_power_ref; 837 bool have_atomics_support; 838 839 /* BIOS */ 840 bool is_atom_fw; 841 uint8_t *bios; 842 uint32_t bios_size; 843 uint32_t bios_scratch_reg_offset; 844 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 845 846 /* Register/doorbell mmio */ 847 resource_size_t rmmio_base; 848 resource_size_t rmmio_size; 849 void __iomem *rmmio; 850 /* protects concurrent MM_INDEX/DATA based register access */ 851 spinlock_t mmio_idx_lock; 852 struct amdgpu_mmio_remap rmmio_remap; 853 /* protects concurrent SMC based register access */ 854 spinlock_t smc_idx_lock; 855 amdgpu_rreg_t smc_rreg; 856 amdgpu_wreg_t smc_wreg; 857 /* protects concurrent PCIE register access */ 858 spinlock_t pcie_idx_lock; 859 amdgpu_rreg_t pcie_rreg; 860 amdgpu_wreg_t pcie_wreg; 861 amdgpu_rreg_t pciep_rreg; 862 amdgpu_wreg_t pciep_wreg; 863 amdgpu_rreg64_t pcie_rreg64; 864 amdgpu_wreg64_t pcie_wreg64; 865 /* protects concurrent UVD register access */ 866 spinlock_t uvd_ctx_idx_lock; 867 amdgpu_rreg_t uvd_ctx_rreg; 868 amdgpu_wreg_t uvd_ctx_wreg; 869 /* protects concurrent DIDT register access */ 870 spinlock_t didt_idx_lock; 871 amdgpu_rreg_t didt_rreg; 872 amdgpu_wreg_t didt_wreg; 873 /* protects concurrent gc_cac register access */ 874 spinlock_t gc_cac_idx_lock; 875 amdgpu_rreg_t gc_cac_rreg; 876 amdgpu_wreg_t gc_cac_wreg; 877 /* protects concurrent se_cac register access */ 878 spinlock_t se_cac_idx_lock; 879 amdgpu_rreg_t se_cac_rreg; 880 amdgpu_wreg_t se_cac_wreg; 881 /* protects concurrent ENDPOINT (audio) register access */ 882 spinlock_t audio_endpt_idx_lock; 883 amdgpu_block_rreg_t audio_endpt_rreg; 884 amdgpu_block_wreg_t audio_endpt_wreg; 885 struct amdgpu_doorbell doorbell; 886 887 /* clock/pll info */ 888 struct amdgpu_clock clock; 889 890 /* MC */ 891 struct amdgpu_gmc gmc; 892 struct amdgpu_gart gart; 893 dma_addr_t dummy_page_addr; 894 struct amdgpu_vm_manager vm_manager; 895 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 896 unsigned num_vmhubs; 897 898 /* memory management */ 899 struct amdgpu_mman mman; 900 struct amdgpu_vram_scratch vram_scratch; 901 struct amdgpu_wb wb; 902 atomic64_t num_bytes_moved; 903 atomic64_t num_evictions; 904 atomic64_t num_vram_cpu_page_faults; 905 atomic_t gpu_reset_counter; 906 atomic_t vram_lost_counter; 907 908 /* data for buffer migration throttling */ 909 struct { 910 spinlock_t lock; 911 s64 last_update_us; 912 s64 accum_us; /* accumulated microseconds */ 913 s64 accum_us_vis; /* for visible VRAM */ 914 u32 log2_max_MBps; 915 } mm_stats; 916 917 /* display */ 918 bool enable_virtual_display; 919 struct amdgpu_mode_info mode_info; 920 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 921 struct work_struct hotplug_work; 922 struct amdgpu_irq_src crtc_irq; 923 struct amdgpu_irq_src vline0_irq; 924 struct amdgpu_irq_src vupdate_irq; 925 struct amdgpu_irq_src pageflip_irq; 926 struct amdgpu_irq_src hpd_irq; 927 struct amdgpu_irq_src dmub_trace_irq; 928 struct amdgpu_irq_src dmub_outbox_irq; 929 930 /* rings */ 931 u64 fence_context; 932 unsigned num_rings; 933 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 934 bool ib_pool_ready; 935 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 936 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 937 938 /* interrupts */ 939 struct amdgpu_irq irq; 940 941 /* powerplay */ 942 struct amd_powerplay powerplay; 943 bool pp_force_state_enabled; 944 945 /* smu */ 946 struct smu_context smu; 947 948 /* dpm */ 949 struct amdgpu_pm pm; 950 u32 cg_flags; 951 u32 pg_flags; 952 953 /* nbio */ 954 struct amdgpu_nbio nbio; 955 956 /* hdp */ 957 struct amdgpu_hdp hdp; 958 959 /* smuio */ 960 struct amdgpu_smuio smuio; 961 962 /* mmhub */ 963 struct amdgpu_mmhub mmhub; 964 965 /* gfxhub */ 966 struct amdgpu_gfxhub gfxhub; 967 968 /* gfx */ 969 struct amdgpu_gfx gfx; 970 971 /* sdma */ 972 struct amdgpu_sdma sdma; 973 974 /* uvd */ 975 struct amdgpu_uvd uvd; 976 977 /* vce */ 978 struct amdgpu_vce vce; 979 980 /* vcn */ 981 struct amdgpu_vcn vcn; 982 983 /* jpeg */ 984 struct amdgpu_jpeg jpeg; 985 986 /* firmwares */ 987 struct amdgpu_firmware firmware; 988 989 /* PSP */ 990 struct psp_context psp; 991 992 /* GDS */ 993 struct amdgpu_gds gds; 994 995 /* KFD */ 996 struct amdgpu_kfd_dev kfd; 997 998 /* UMC */ 999 struct amdgpu_umc umc; 1000 1001 /* display related functionality */ 1002 struct amdgpu_display_manager dm; 1003 1004 /* mes */ 1005 bool enable_mes; 1006 struct amdgpu_mes mes; 1007 1008 /* df */ 1009 struct amdgpu_df df; 1010 1011 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1012 uint32_t harvest_ip_mask; 1013 int num_ip_blocks; 1014 struct mutex mn_lock; 1015 DECLARE_HASHTABLE(mn_hash, 7); 1016 1017 /* tracking pinned memory */ 1018 atomic64_t vram_pin_size; 1019 atomic64_t visible_pin_size; 1020 atomic64_t gart_pin_size; 1021 1022 /* soc15 register offset based on ip, instance and segment */ 1023 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1024 1025 /* delayed work_func for deferring clockgating during resume */ 1026 struct delayed_work delayed_init_work; 1027 1028 struct amdgpu_virt virt; 1029 1030 /* link all shadow bo */ 1031 struct list_head shadow_list; 1032 struct mutex shadow_list_lock; 1033 1034 /* record hw reset is performed */ 1035 bool has_hw_reset; 1036 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1037 1038 /* s3/s4 mask */ 1039 bool in_suspend; 1040 bool in_s3; 1041 bool in_s4; 1042 bool in_s0ix; 1043 1044 atomic_t in_gpu_reset; 1045 enum pp_mp1_state mp1_state; 1046 struct rw_semaphore reset_sem; 1047 struct amdgpu_doorbell_index doorbell_index; 1048 1049 struct mutex notifier_lock; 1050 1051 int asic_reset_res; 1052 struct work_struct xgmi_reset_work; 1053 struct list_head reset_list; 1054 1055 long gfx_timeout; 1056 long sdma_timeout; 1057 long video_timeout; 1058 long compute_timeout; 1059 1060 uint64_t unique_id; 1061 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1062 1063 /* enable runtime pm on the device */ 1064 bool runpm; 1065 bool in_runpm; 1066 bool has_pr3; 1067 1068 bool pm_sysfs_en; 1069 bool ucode_sysfs_en; 1070 1071 /* Chip product information */ 1072 char product_number[16]; 1073 char product_name[32]; 1074 char serial[20]; 1075 1076 struct amdgpu_autodump autodump; 1077 1078 atomic_t throttling_logging_enabled; 1079 struct ratelimit_state throttling_logging_rs; 1080 uint32_t ras_hw_enabled; 1081 uint32_t ras_enabled; 1082 1083 bool no_hw_access; 1084 struct pci_saved_state *pci_state; 1085 1086 struct amdgpu_reset_control *reset_cntl; 1087 }; 1088 1089 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1090 { 1091 return container_of(ddev, struct amdgpu_device, ddev); 1092 } 1093 1094 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1095 { 1096 return &adev->ddev; 1097 } 1098 1099 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1100 { 1101 return container_of(bdev, struct amdgpu_device, mman.bdev); 1102 } 1103 1104 int amdgpu_device_init(struct amdgpu_device *adev, 1105 uint32_t flags); 1106 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1107 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1108 1109 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1110 1111 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1112 uint32_t *buf, size_t size, bool write); 1113 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1114 uint32_t reg, uint32_t acc_flags); 1115 void amdgpu_device_wreg(struct amdgpu_device *adev, 1116 uint32_t reg, uint32_t v, 1117 uint32_t acc_flags); 1118 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1119 uint32_t reg, uint32_t v); 1120 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1121 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1122 1123 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1124 u32 pcie_index, u32 pcie_data, 1125 u32 reg_addr); 1126 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1127 u32 pcie_index, u32 pcie_data, 1128 u32 reg_addr); 1129 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1130 u32 pcie_index, u32 pcie_data, 1131 u32 reg_addr, u32 reg_data); 1132 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1133 u32 pcie_index, u32 pcie_data, 1134 u32 reg_addr, u64 reg_data); 1135 1136 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1137 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1138 1139 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1140 struct amdgpu_reset_context *reset_context); 1141 1142 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1143 struct amdgpu_reset_context *reset_context); 1144 1145 int emu_soc_asic_init(struct amdgpu_device *adev); 1146 1147 /* 1148 * Registers read & write functions. 1149 */ 1150 #define AMDGPU_REGS_NO_KIQ (1<<1) 1151 #define AMDGPU_REGS_RLC (1<<2) 1152 1153 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1154 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1155 1156 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1157 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1158 1159 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1160 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1161 1162 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1163 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1164 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1165 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1166 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1167 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1168 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1169 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1170 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1171 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1172 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1173 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1174 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1175 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1176 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1177 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1178 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1179 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1180 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1181 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1182 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1183 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1184 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1185 #define WREG32_P(reg, val, mask) \ 1186 do { \ 1187 uint32_t tmp_ = RREG32(reg); \ 1188 tmp_ &= (mask); \ 1189 tmp_ |= ((val) & ~(mask)); \ 1190 WREG32(reg, tmp_); \ 1191 } while (0) 1192 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1193 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1194 #define WREG32_PLL_P(reg, val, mask) \ 1195 do { \ 1196 uint32_t tmp_ = RREG32_PLL(reg); \ 1197 tmp_ &= (mask); \ 1198 tmp_ |= ((val) & ~(mask)); \ 1199 WREG32_PLL(reg, tmp_); \ 1200 } while (0) 1201 1202 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1203 do { \ 1204 u32 tmp = RREG32_SMC(_Reg); \ 1205 tmp &= (_Mask); \ 1206 tmp |= ((_Val) & ~(_Mask)); \ 1207 WREG32_SMC(_Reg, tmp); \ 1208 } while (0) 1209 1210 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1211 1212 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1213 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1214 1215 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1216 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1217 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1218 1219 #define REG_GET_FIELD(value, reg, field) \ 1220 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1221 1222 #define WREG32_FIELD(reg, field, val) \ 1223 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1224 1225 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1226 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1227 1228 /* 1229 * BIOS helpers. 1230 */ 1231 #define RBIOS8(i) (adev->bios[i]) 1232 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1233 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1234 1235 /* 1236 * ASICs macro. 1237 */ 1238 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1239 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1240 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1241 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1242 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1243 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1244 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1245 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1246 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1247 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1248 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1249 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1250 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1251 #define amdgpu_asic_flush_hdp(adev, r) \ 1252 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1253 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1254 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r))) 1255 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1256 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1257 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1258 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1259 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1260 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1261 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1262 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1263 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1264 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1265 1266 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1267 1268 /* Common functions */ 1269 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1270 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1271 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1272 struct amdgpu_job* job); 1273 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1274 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1275 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1276 1277 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1278 u64 num_vis_bytes); 1279 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1280 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1281 const u32 *registers, 1282 const u32 array_size); 1283 1284 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1285 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1286 bool amdgpu_device_supports_px(struct drm_device *dev); 1287 bool amdgpu_device_supports_boco(struct drm_device *dev); 1288 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1289 bool amdgpu_device_supports_baco(struct drm_device *dev); 1290 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1291 struct amdgpu_device *peer_adev); 1292 int amdgpu_device_baco_enter(struct drm_device *dev); 1293 int amdgpu_device_baco_exit(struct drm_device *dev); 1294 1295 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1296 struct amdgpu_ring *ring); 1297 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1298 struct amdgpu_ring *ring); 1299 1300 /* atpx handler */ 1301 #if defined(CONFIG_VGA_SWITCHEROO) 1302 void amdgpu_register_atpx_handler(void); 1303 void amdgpu_unregister_atpx_handler(void); 1304 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1305 bool amdgpu_is_atpx_hybrid(void); 1306 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1307 bool amdgpu_has_atpx(void); 1308 #else 1309 static inline void amdgpu_register_atpx_handler(void) {} 1310 static inline void amdgpu_unregister_atpx_handler(void) {} 1311 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1312 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1313 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1314 static inline bool amdgpu_has_atpx(void) { return false; } 1315 #endif 1316 1317 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1318 void *amdgpu_atpx_get_dhandle(void); 1319 #else 1320 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1321 #endif 1322 1323 /* 1324 * KMS 1325 */ 1326 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1327 extern const int amdgpu_max_kms_ioctl; 1328 1329 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1330 void amdgpu_driver_unload_kms(struct drm_device *dev); 1331 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1332 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1333 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1334 struct drm_file *file_priv); 1335 void amdgpu_driver_release_kms(struct drm_device *dev); 1336 1337 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1338 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1339 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1340 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1341 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1342 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1343 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1344 unsigned long arg); 1345 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1346 struct drm_file *filp); 1347 1348 /* 1349 * functions used by amdgpu_encoder.c 1350 */ 1351 struct amdgpu_afmt_acr { 1352 u32 clock; 1353 1354 int n_32khz; 1355 int cts_32khz; 1356 1357 int n_44_1khz; 1358 int cts_44_1khz; 1359 1360 int n_48khz; 1361 int cts_48khz; 1362 1363 }; 1364 1365 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1366 1367 /* amdgpu_acpi.c */ 1368 1369 /* ATCS Device/Driver State */ 1370 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1371 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1372 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1373 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1374 1375 #if defined(CONFIG_ACPI) 1376 int amdgpu_acpi_init(struct amdgpu_device *adev); 1377 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1378 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1379 bool amdgpu_acpi_is_power_shift_control_supported(void); 1380 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1381 u8 perf_req, bool advertise); 1382 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1383 u8 dev_state, bool drv_state); 1384 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1385 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1386 1387 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1388 bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev); 1389 void amdgpu_acpi_detect(void); 1390 #else 1391 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1392 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1393 static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; } 1394 static inline void amdgpu_acpi_detect(void) { } 1395 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1396 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1397 u8 dev_state, bool drv_state) { return 0; } 1398 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1399 enum amdgpu_ss ss_state) { return 0; } 1400 #endif 1401 1402 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1403 uint64_t addr, struct amdgpu_bo **bo, 1404 struct amdgpu_bo_va_mapping **mapping); 1405 1406 #if defined(CONFIG_DRM_AMD_DC) 1407 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1408 #else 1409 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1410 #endif 1411 1412 1413 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1414 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1415 1416 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1417 pci_channel_state_t state); 1418 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1419 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1420 void amdgpu_pci_resume(struct pci_dev *pdev); 1421 1422 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1423 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1424 1425 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1426 1427 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1428 enum amd_clockgating_state state); 1429 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1430 enum amd_powergating_state state); 1431 1432 #include "amdgpu_object.h" 1433 1434 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1435 { 1436 return adev->gmc.tmz_enabled; 1437 } 1438 1439 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1440 { 1441 return atomic_read(&adev->in_gpu_reset); 1442 } 1443 #endif 1444