1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include "amdgpu_ctx.h" 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/rbtree.h> 38 #include <linux/hashtable.h> 39 #include <linux/dma-fence.h> 40 41 #include <drm/ttm/ttm_bo_api.h> 42 #include <drm/ttm/ttm_bo_driver.h> 43 #include <drm/ttm/ttm_placement.h> 44 #include <drm/ttm/ttm_module.h> 45 #include <drm/ttm/ttm_execbuf_util.h> 46 47 #include <drm/drmP.h> 48 #include <drm/drm_gem.h> 49 #include <drm/amdgpu_drm.h> 50 #include <drm/gpu_scheduler.h> 51 52 #include <kgd_kfd_interface.h> 53 #include "dm_pp_interface.h" 54 #include "kgd_pp_interface.h" 55 56 #include "amd_shared.h" 57 #include "amdgpu_mode.h" 58 #include "amdgpu_ih.h" 59 #include "amdgpu_irq.h" 60 #include "amdgpu_ucode.h" 61 #include "amdgpu_ttm.h" 62 #include "amdgpu_psp.h" 63 #include "amdgpu_gds.h" 64 #include "amdgpu_sync.h" 65 #include "amdgpu_ring.h" 66 #include "amdgpu_vm.h" 67 #include "amdgpu_dpm.h" 68 #include "amdgpu_acp.h" 69 #include "amdgpu_uvd.h" 70 #include "amdgpu_vce.h" 71 #include "amdgpu_vcn.h" 72 #include "amdgpu_mn.h" 73 #include "amdgpu_gmc.h" 74 #include "amdgpu_gfx.h" 75 #include "amdgpu_sdma.h" 76 #include "amdgpu_dm.h" 77 #include "amdgpu_virt.h" 78 #include "amdgpu_gart.h" 79 #include "amdgpu_debugfs.h" 80 #include "amdgpu_job.h" 81 #include "amdgpu_bo_list.h" 82 #include "amdgpu_gem.h" 83 84 #define MAX_GPU_INSTANCE 16 85 86 struct amdgpu_gpu_instance 87 { 88 struct amdgpu_device *adev; 89 int mgpu_fan_enabled; 90 }; 91 92 struct amdgpu_mgpu_info 93 { 94 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 95 struct mutex mutex; 96 uint32_t num_gpu; 97 uint32_t num_dgpu; 98 uint32_t num_apu; 99 }; 100 101 /* 102 * Modules parameters. 103 */ 104 extern int amdgpu_modeset; 105 extern int amdgpu_vram_limit; 106 extern int amdgpu_vis_vram_limit; 107 extern int amdgpu_gart_size; 108 extern int amdgpu_gtt_size; 109 extern int amdgpu_moverate; 110 extern int amdgpu_benchmarking; 111 extern int amdgpu_testing; 112 extern int amdgpu_audio; 113 extern int amdgpu_disp_priority; 114 extern int amdgpu_hw_i2c; 115 extern int amdgpu_pcie_gen2; 116 extern int amdgpu_msi; 117 extern int amdgpu_lockup_timeout; 118 extern int amdgpu_dpm; 119 extern int amdgpu_fw_load_type; 120 extern int amdgpu_aspm; 121 extern int amdgpu_runtime_pm; 122 extern uint amdgpu_ip_block_mask; 123 extern int amdgpu_bapm; 124 extern int amdgpu_deep_color; 125 extern int amdgpu_vm_size; 126 extern int amdgpu_vm_block_size; 127 extern int amdgpu_vm_fragment_size; 128 extern int amdgpu_vm_fault_stop; 129 extern int amdgpu_vm_debug; 130 extern int amdgpu_vm_update_mode; 131 extern int amdgpu_dc; 132 extern int amdgpu_sched_jobs; 133 extern int amdgpu_sched_hw_submission; 134 extern uint amdgpu_pcie_gen_cap; 135 extern uint amdgpu_pcie_lane_cap; 136 extern uint amdgpu_cg_mask; 137 extern uint amdgpu_pg_mask; 138 extern uint amdgpu_sdma_phase_quantum; 139 extern char *amdgpu_disable_cu; 140 extern char *amdgpu_virtual_display; 141 extern uint amdgpu_pp_feature_mask; 142 extern int amdgpu_vram_page_split; 143 extern int amdgpu_ngg; 144 extern int amdgpu_prim_buf_per_se; 145 extern int amdgpu_pos_buf_per_se; 146 extern int amdgpu_cntl_sb_buf_per_se; 147 extern int amdgpu_param_buf_per_se; 148 extern int amdgpu_job_hang_limit; 149 extern int amdgpu_lbpw; 150 extern int amdgpu_compute_multipipe; 151 extern int amdgpu_gpu_recovery; 152 extern int amdgpu_emu_mode; 153 extern uint amdgpu_smu_memory_pool_size; 154 extern struct amdgpu_mgpu_info mgpu_info; 155 156 #ifdef CONFIG_DRM_AMDGPU_SI 157 extern int amdgpu_si_support; 158 #endif 159 #ifdef CONFIG_DRM_AMDGPU_CIK 160 extern int amdgpu_cik_support; 161 #endif 162 163 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 164 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 165 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 166 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 167 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 168 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 169 #define AMDGPU_IB_POOL_SIZE 16 170 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 171 #define AMDGPUFB_CONN_LIMIT 4 172 #define AMDGPU_BIOS_NUM_SCRATCH 16 173 174 /* hard reset data */ 175 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 176 177 /* reset flags */ 178 #define AMDGPU_RESET_GFX (1 << 0) 179 #define AMDGPU_RESET_COMPUTE (1 << 1) 180 #define AMDGPU_RESET_DMA (1 << 2) 181 #define AMDGPU_RESET_CP (1 << 3) 182 #define AMDGPU_RESET_GRBM (1 << 4) 183 #define AMDGPU_RESET_DMA1 (1 << 5) 184 #define AMDGPU_RESET_RLC (1 << 6) 185 #define AMDGPU_RESET_SEM (1 << 7) 186 #define AMDGPU_RESET_IH (1 << 8) 187 #define AMDGPU_RESET_VMC (1 << 9) 188 #define AMDGPU_RESET_MC (1 << 10) 189 #define AMDGPU_RESET_DISPLAY (1 << 11) 190 #define AMDGPU_RESET_UVD (1 << 12) 191 #define AMDGPU_RESET_VCE (1 << 13) 192 #define AMDGPU_RESET_VCE1 (1 << 14) 193 194 /* max cursor sizes (in pixels) */ 195 #define CIK_CURSOR_WIDTH 128 196 #define CIK_CURSOR_HEIGHT 128 197 198 struct amdgpu_device; 199 struct amdgpu_ib; 200 struct amdgpu_cs_parser; 201 struct amdgpu_job; 202 struct amdgpu_irq_src; 203 struct amdgpu_fpriv; 204 struct amdgpu_bo_va_mapping; 205 struct amdgpu_atif; 206 207 enum amdgpu_cp_irq { 208 AMDGPU_CP_IRQ_GFX_EOP = 0, 209 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 210 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 211 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 212 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 213 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 214 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 215 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 216 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 217 218 AMDGPU_CP_IRQ_LAST 219 }; 220 221 enum amdgpu_thermal_irq { 222 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 223 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 224 225 AMDGPU_THERMAL_IRQ_LAST 226 }; 227 228 enum amdgpu_kiq_irq { 229 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 230 AMDGPU_CP_KIQ_IRQ_LAST 231 }; 232 233 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 234 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 235 #define MAX_KIQ_REG_TRY 20 236 237 int amdgpu_device_ip_set_clockgating_state(void *dev, 238 enum amd_ip_block_type block_type, 239 enum amd_clockgating_state state); 240 int amdgpu_device_ip_set_powergating_state(void *dev, 241 enum amd_ip_block_type block_type, 242 enum amd_powergating_state state); 243 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 244 u32 *flags); 245 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 246 enum amd_ip_block_type block_type); 247 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 248 enum amd_ip_block_type block_type); 249 250 #define AMDGPU_MAX_IP_NUM 16 251 252 struct amdgpu_ip_block_status { 253 bool valid; 254 bool sw; 255 bool hw; 256 bool late_initialized; 257 bool hang; 258 }; 259 260 struct amdgpu_ip_block_version { 261 const enum amd_ip_block_type type; 262 const u32 major; 263 const u32 minor; 264 const u32 rev; 265 const struct amd_ip_funcs *funcs; 266 }; 267 268 struct amdgpu_ip_block { 269 struct amdgpu_ip_block_status status; 270 const struct amdgpu_ip_block_version *version; 271 }; 272 273 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 274 enum amd_ip_block_type type, 275 u32 major, u32 minor); 276 277 struct amdgpu_ip_block * 278 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 279 enum amd_ip_block_type type); 280 281 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 282 const struct amdgpu_ip_block_version *ip_block_version); 283 284 /* 285 * BIOS. 286 */ 287 bool amdgpu_get_bios(struct amdgpu_device *adev); 288 bool amdgpu_read_bios(struct amdgpu_device *adev); 289 290 /* 291 * Clocks 292 */ 293 294 #define AMDGPU_MAX_PPLL 3 295 296 struct amdgpu_clock { 297 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 298 struct amdgpu_pll spll; 299 struct amdgpu_pll mpll; 300 /* 10 Khz units */ 301 uint32_t default_mclk; 302 uint32_t default_sclk; 303 uint32_t default_dispclk; 304 uint32_t current_dispclk; 305 uint32_t dp_extclk; 306 uint32_t max_pixel_clock; 307 }; 308 309 /* sub-allocation manager, it has to be protected by another lock. 310 * By conception this is an helper for other part of the driver 311 * like the indirect buffer or semaphore, which both have their 312 * locking. 313 * 314 * Principe is simple, we keep a list of sub allocation in offset 315 * order (first entry has offset == 0, last entry has the highest 316 * offset). 317 * 318 * When allocating new object we first check if there is room at 319 * the end total_size - (last_object_offset + last_object_size) >= 320 * alloc_size. If so we allocate new object there. 321 * 322 * When there is not enough room at the end, we start waiting for 323 * each sub object until we reach object_offset+object_size >= 324 * alloc_size, this object then become the sub object we return. 325 * 326 * Alignment can't be bigger than page size. 327 * 328 * Hole are not considered for allocation to keep things simple. 329 * Assumption is that there won't be hole (all object on same 330 * alignment). 331 */ 332 333 #define AMDGPU_SA_NUM_FENCE_LISTS 32 334 335 struct amdgpu_sa_manager { 336 wait_queue_head_t wq; 337 struct amdgpu_bo *bo; 338 struct list_head *hole; 339 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 340 struct list_head olist; 341 unsigned size; 342 uint64_t gpu_addr; 343 void *cpu_ptr; 344 uint32_t domain; 345 uint32_t align; 346 }; 347 348 /* sub-allocation buffer */ 349 struct amdgpu_sa_bo { 350 struct list_head olist; 351 struct list_head flist; 352 struct amdgpu_sa_manager *manager; 353 unsigned soffset; 354 unsigned eoffset; 355 struct dma_fence *fence; 356 }; 357 358 int amdgpu_fence_slab_init(void); 359 void amdgpu_fence_slab_fini(void); 360 361 /* 362 * GPU doorbell structures, functions & helpers 363 */ 364 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 365 { 366 AMDGPU_DOORBELL_KIQ = 0x000, 367 AMDGPU_DOORBELL_HIQ = 0x001, 368 AMDGPU_DOORBELL_DIQ = 0x002, 369 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 370 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 371 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 372 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 373 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 374 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 375 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 376 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 377 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 378 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 379 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 380 AMDGPU_DOORBELL_IH = 0x1E8, 381 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 382 AMDGPU_DOORBELL_INVALID = 0xFFFF 383 } AMDGPU_DOORBELL_ASSIGNMENT; 384 385 struct amdgpu_doorbell { 386 /* doorbell mmio */ 387 resource_size_t base; 388 resource_size_t size; 389 u32 __iomem *ptr; 390 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 391 }; 392 393 /* 394 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 395 */ 396 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 397 { 398 /* 399 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 400 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 401 * Compute related doorbells are allocated from 0x00 to 0x8a 402 */ 403 404 405 /* kernel scheduling */ 406 AMDGPU_DOORBELL64_KIQ = 0x00, 407 408 /* HSA interface queue and debug queue */ 409 AMDGPU_DOORBELL64_HIQ = 0x01, 410 AMDGPU_DOORBELL64_DIQ = 0x02, 411 412 /* Compute engines */ 413 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 414 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 415 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 416 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 417 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 418 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 419 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 420 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 421 422 /* User queue doorbell range (128 doorbells) */ 423 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 424 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 425 426 /* Graphics engine */ 427 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 428 429 /* 430 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf 431 * Graphics voltage island aperture 1 432 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive 433 */ 434 435 /* sDMA engines reserved from 0xe0 -oxef */ 436 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xE0, 437 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xE1, 438 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xE8, 439 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xE9, 440 441 /* For vega10 sriov, the sdma doorbell must be fixed as follow 442 * to keep the same setting with host driver, or it will 443 * happen conflicts 444 */ 445 AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 = 0xF0, 446 AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 447 AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 = 0xF2, 448 AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 449 450 /* Interrupt handler */ 451 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 452 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 453 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 454 455 /* VCN engine use 32 bits doorbell */ 456 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 457 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 458 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 459 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 460 461 /* overlap the doorbell assignment with VCN as they are mutually exclusive 462 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 463 */ 464 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 465 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 466 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 467 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 468 469 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 470 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 471 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 472 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 473 474 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 475 AMDGPU_DOORBELL64_INVALID = 0xFFFF 476 } AMDGPU_DOORBELL64_ASSIGNMENT; 477 478 /* 479 * IRQS. 480 */ 481 482 struct amdgpu_flip_work { 483 struct delayed_work flip_work; 484 struct work_struct unpin_work; 485 struct amdgpu_device *adev; 486 int crtc_id; 487 u32 target_vblank; 488 uint64_t base; 489 struct drm_pending_vblank_event *event; 490 struct amdgpu_bo *old_abo; 491 struct dma_fence *excl; 492 unsigned shared_count; 493 struct dma_fence **shared; 494 struct dma_fence_cb cb; 495 bool async; 496 }; 497 498 499 /* 500 * CP & rings. 501 */ 502 503 struct amdgpu_ib { 504 struct amdgpu_sa_bo *sa_bo; 505 uint32_t length_dw; 506 uint64_t gpu_addr; 507 uint32_t *ptr; 508 uint32_t flags; 509 }; 510 511 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 512 513 /* 514 * file private structure 515 */ 516 517 struct amdgpu_fpriv { 518 struct amdgpu_vm vm; 519 struct amdgpu_bo_va *prt_va; 520 struct amdgpu_bo_va *csa_va; 521 struct mutex bo_list_lock; 522 struct idr bo_list_handles; 523 struct amdgpu_ctx_mgr ctx_mgr; 524 }; 525 526 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 527 unsigned size, struct amdgpu_ib *ib); 528 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 529 struct dma_fence *f); 530 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 531 struct amdgpu_ib *ibs, struct amdgpu_job *job, 532 struct dma_fence **f); 533 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 534 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 535 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 536 537 /* 538 * CS. 539 */ 540 struct amdgpu_cs_chunk { 541 uint32_t chunk_id; 542 uint32_t length_dw; 543 void *kdata; 544 }; 545 546 struct amdgpu_cs_parser { 547 struct amdgpu_device *adev; 548 struct drm_file *filp; 549 struct amdgpu_ctx *ctx; 550 551 /* chunks */ 552 unsigned nchunks; 553 struct amdgpu_cs_chunk *chunks; 554 555 /* scheduler job object */ 556 struct amdgpu_job *job; 557 struct drm_sched_entity *entity; 558 559 /* buffer objects */ 560 struct ww_acquire_ctx ticket; 561 struct amdgpu_bo_list *bo_list; 562 struct amdgpu_mn *mn; 563 struct amdgpu_bo_list_entry vm_pd; 564 struct list_head validated; 565 struct dma_fence *fence; 566 uint64_t bytes_moved_threshold; 567 uint64_t bytes_moved_vis_threshold; 568 uint64_t bytes_moved; 569 uint64_t bytes_moved_vis; 570 struct amdgpu_bo_list_entry *evictable; 571 572 /* user fence */ 573 struct amdgpu_bo_list_entry uf_entry; 574 575 unsigned num_post_dep_syncobjs; 576 struct drm_syncobj **post_dep_syncobjs; 577 }; 578 579 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 580 uint32_t ib_idx, int idx) 581 { 582 return p->job->ibs[ib_idx].ptr[idx]; 583 } 584 585 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 586 uint32_t ib_idx, int idx, 587 uint32_t value) 588 { 589 p->job->ibs[ib_idx].ptr[idx] = value; 590 } 591 592 /* 593 * Writeback 594 */ 595 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 596 597 struct amdgpu_wb { 598 struct amdgpu_bo *wb_obj; 599 volatile uint32_t *wb; 600 uint64_t gpu_addr; 601 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 602 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 603 }; 604 605 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 606 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 607 608 /* 609 * Benchmarking 610 */ 611 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 612 613 614 /* 615 * Testing 616 */ 617 void amdgpu_test_moves(struct amdgpu_device *adev); 618 619 /* 620 * ASIC specific register table accessible by UMD 621 */ 622 struct amdgpu_allowed_register_entry { 623 uint32_t reg_offset; 624 bool grbm_indexed; 625 }; 626 627 /* 628 * ASIC specific functions. 629 */ 630 struct amdgpu_asic_funcs { 631 bool (*read_disabled_bios)(struct amdgpu_device *adev); 632 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 633 u8 *bios, u32 length_bytes); 634 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 635 u32 sh_num, u32 reg_offset, u32 *value); 636 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 637 int (*reset)(struct amdgpu_device *adev); 638 /* get the reference clock */ 639 u32 (*get_xclk)(struct amdgpu_device *adev); 640 /* MM block clocks */ 641 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 642 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 643 /* static power management */ 644 int (*get_pcie_lanes)(struct amdgpu_device *adev); 645 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 646 /* get config memsize register */ 647 u32 (*get_config_memsize)(struct amdgpu_device *adev); 648 /* flush hdp write queue */ 649 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 650 /* invalidate hdp read cache */ 651 void (*invalidate_hdp)(struct amdgpu_device *adev, 652 struct amdgpu_ring *ring); 653 /* check if the asic needs a full reset of if soft reset will work */ 654 bool (*need_full_reset)(struct amdgpu_device *adev); 655 }; 656 657 /* 658 * IOCTL. 659 */ 660 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 661 struct drm_file *filp); 662 663 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 664 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 665 struct drm_file *filp); 666 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 667 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 668 struct drm_file *filp); 669 670 /* VRAM scratch page for HDP bug, default vram page */ 671 struct amdgpu_vram_scratch { 672 struct amdgpu_bo *robj; 673 volatile uint32_t *ptr; 674 u64 gpu_addr; 675 }; 676 677 /* 678 * ACPI 679 */ 680 struct amdgpu_atcs_functions { 681 bool get_ext_state; 682 bool pcie_perf_req; 683 bool pcie_dev_rdy; 684 bool pcie_bus_width; 685 }; 686 687 struct amdgpu_atcs { 688 struct amdgpu_atcs_functions functions; 689 }; 690 691 /* 692 * Firmware VRAM reservation 693 */ 694 struct amdgpu_fw_vram_usage { 695 u64 start_offset; 696 u64 size; 697 struct amdgpu_bo *reserved_bo; 698 void *va; 699 }; 700 701 /* 702 * CGS 703 */ 704 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 705 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 706 707 /* 708 * Core structure, functions and helpers. 709 */ 710 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 711 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 712 713 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 714 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 715 716 717 /* 718 * amdgpu nbio functions 719 * 720 */ 721 struct nbio_hdp_flush_reg { 722 u32 ref_and_mask_cp0; 723 u32 ref_and_mask_cp1; 724 u32 ref_and_mask_cp2; 725 u32 ref_and_mask_cp3; 726 u32 ref_and_mask_cp4; 727 u32 ref_and_mask_cp5; 728 u32 ref_and_mask_cp6; 729 u32 ref_and_mask_cp7; 730 u32 ref_and_mask_cp8; 731 u32 ref_and_mask_cp9; 732 u32 ref_and_mask_sdma0; 733 u32 ref_and_mask_sdma1; 734 }; 735 736 struct amdgpu_nbio_funcs { 737 const struct nbio_hdp_flush_reg *hdp_flush_reg; 738 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 739 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 740 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 741 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 742 u32 (*get_rev_id)(struct amdgpu_device *adev); 743 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 744 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 745 u32 (*get_memsize)(struct amdgpu_device *adev); 746 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 747 bool use_doorbell, int doorbell_index); 748 void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 749 bool enable); 750 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 751 bool enable); 752 void (*ih_doorbell_range)(struct amdgpu_device *adev, 753 bool use_doorbell, int doorbell_index); 754 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 755 bool enable); 756 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 757 bool enable); 758 void (*get_clockgating_state)(struct amdgpu_device *adev, 759 u32 *flags); 760 void (*ih_control)(struct amdgpu_device *adev); 761 void (*init_registers)(struct amdgpu_device *adev); 762 void (*detect_hw_virt)(struct amdgpu_device *adev); 763 }; 764 765 struct amdgpu_df_funcs { 766 void (*init)(struct amdgpu_device *adev); 767 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 768 bool enable); 769 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 770 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 771 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 772 bool enable); 773 void (*get_clockgating_state)(struct amdgpu_device *adev, 774 u32 *flags); 775 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 776 bool enable); 777 }; 778 /* Define the HW IP blocks will be used in driver , add more if necessary */ 779 enum amd_hw_ip_block_type { 780 GC_HWIP = 1, 781 HDP_HWIP, 782 SDMA0_HWIP, 783 SDMA1_HWIP, 784 MMHUB_HWIP, 785 ATHUB_HWIP, 786 NBIO_HWIP, 787 MP0_HWIP, 788 MP1_HWIP, 789 UVD_HWIP, 790 VCN_HWIP = UVD_HWIP, 791 VCE_HWIP, 792 DF_HWIP, 793 DCE_HWIP, 794 OSSSYS_HWIP, 795 SMUIO_HWIP, 796 PWR_HWIP, 797 NBIF_HWIP, 798 THM_HWIP, 799 CLK_HWIP, 800 MAX_HWIP 801 }; 802 803 #define HWIP_MAX_INSTANCE 6 804 805 struct amd_powerplay { 806 void *pp_handle; 807 const struct amd_pm_funcs *pp_funcs; 808 uint32_t pp_feature; 809 }; 810 811 #define AMDGPU_RESET_MAGIC_NUM 64 812 struct amdgpu_device { 813 struct device *dev; 814 struct drm_device *ddev; 815 struct pci_dev *pdev; 816 817 #ifdef CONFIG_DRM_AMD_ACP 818 struct amdgpu_acp acp; 819 #endif 820 821 /* ASIC */ 822 enum amd_asic_type asic_type; 823 uint32_t family; 824 uint32_t rev_id; 825 uint32_t external_rev_id; 826 unsigned long flags; 827 int usec_timeout; 828 const struct amdgpu_asic_funcs *asic_funcs; 829 bool shutdown; 830 bool need_dma32; 831 bool need_swiotlb; 832 bool accel_working; 833 struct work_struct reset_work; 834 struct notifier_block acpi_nb; 835 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 836 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 837 unsigned debugfs_count; 838 #if defined(CONFIG_DEBUG_FS) 839 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 840 #endif 841 struct amdgpu_atif *atif; 842 struct amdgpu_atcs atcs; 843 struct mutex srbm_mutex; 844 /* GRBM index mutex. Protects concurrent access to GRBM index */ 845 struct mutex grbm_idx_mutex; 846 struct dev_pm_domain vga_pm_domain; 847 bool have_disp_power_ref; 848 849 /* BIOS */ 850 bool is_atom_fw; 851 uint8_t *bios; 852 uint32_t bios_size; 853 struct amdgpu_bo *stolen_vga_memory; 854 uint32_t bios_scratch_reg_offset; 855 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 856 857 /* Register/doorbell mmio */ 858 resource_size_t rmmio_base; 859 resource_size_t rmmio_size; 860 void __iomem *rmmio; 861 /* protects concurrent MM_INDEX/DATA based register access */ 862 spinlock_t mmio_idx_lock; 863 /* protects concurrent SMC based register access */ 864 spinlock_t smc_idx_lock; 865 amdgpu_rreg_t smc_rreg; 866 amdgpu_wreg_t smc_wreg; 867 /* protects concurrent PCIE register access */ 868 spinlock_t pcie_idx_lock; 869 amdgpu_rreg_t pcie_rreg; 870 amdgpu_wreg_t pcie_wreg; 871 amdgpu_rreg_t pciep_rreg; 872 amdgpu_wreg_t pciep_wreg; 873 /* protects concurrent UVD register access */ 874 spinlock_t uvd_ctx_idx_lock; 875 amdgpu_rreg_t uvd_ctx_rreg; 876 amdgpu_wreg_t uvd_ctx_wreg; 877 /* protects concurrent DIDT register access */ 878 spinlock_t didt_idx_lock; 879 amdgpu_rreg_t didt_rreg; 880 amdgpu_wreg_t didt_wreg; 881 /* protects concurrent gc_cac register access */ 882 spinlock_t gc_cac_idx_lock; 883 amdgpu_rreg_t gc_cac_rreg; 884 amdgpu_wreg_t gc_cac_wreg; 885 /* protects concurrent se_cac register access */ 886 spinlock_t se_cac_idx_lock; 887 amdgpu_rreg_t se_cac_rreg; 888 amdgpu_wreg_t se_cac_wreg; 889 /* protects concurrent ENDPOINT (audio) register access */ 890 spinlock_t audio_endpt_idx_lock; 891 amdgpu_block_rreg_t audio_endpt_rreg; 892 amdgpu_block_wreg_t audio_endpt_wreg; 893 void __iomem *rio_mem; 894 resource_size_t rio_mem_size; 895 struct amdgpu_doorbell doorbell; 896 897 /* clock/pll info */ 898 struct amdgpu_clock clock; 899 900 /* MC */ 901 struct amdgpu_gmc gmc; 902 struct amdgpu_gart gart; 903 dma_addr_t dummy_page_addr; 904 struct amdgpu_vm_manager vm_manager; 905 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 906 907 /* memory management */ 908 struct amdgpu_mman mman; 909 struct amdgpu_vram_scratch vram_scratch; 910 struct amdgpu_wb wb; 911 atomic64_t num_bytes_moved; 912 atomic64_t num_evictions; 913 atomic64_t num_vram_cpu_page_faults; 914 atomic_t gpu_reset_counter; 915 atomic_t vram_lost_counter; 916 917 /* data for buffer migration throttling */ 918 struct { 919 spinlock_t lock; 920 s64 last_update_us; 921 s64 accum_us; /* accumulated microseconds */ 922 s64 accum_us_vis; /* for visible VRAM */ 923 u32 log2_max_MBps; 924 } mm_stats; 925 926 /* display */ 927 bool enable_virtual_display; 928 struct amdgpu_mode_info mode_info; 929 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 930 struct work_struct hotplug_work; 931 struct amdgpu_irq_src crtc_irq; 932 struct amdgpu_irq_src pageflip_irq; 933 struct amdgpu_irq_src hpd_irq; 934 935 /* rings */ 936 u64 fence_context; 937 unsigned num_rings; 938 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 939 bool ib_pool_ready; 940 struct amdgpu_sa_manager ring_tmp_bo; 941 942 /* interrupts */ 943 struct amdgpu_irq irq; 944 945 /* powerplay */ 946 struct amd_powerplay powerplay; 947 bool pp_force_state_enabled; 948 949 /* dpm */ 950 struct amdgpu_pm pm; 951 u32 cg_flags; 952 u32 pg_flags; 953 954 /* gfx */ 955 struct amdgpu_gfx gfx; 956 957 /* sdma */ 958 struct amdgpu_sdma sdma; 959 960 /* uvd */ 961 struct amdgpu_uvd uvd; 962 963 /* vce */ 964 struct amdgpu_vce vce; 965 966 /* vcn */ 967 struct amdgpu_vcn vcn; 968 969 /* firmwares */ 970 struct amdgpu_firmware firmware; 971 972 /* PSP */ 973 struct psp_context psp; 974 975 /* GDS */ 976 struct amdgpu_gds gds; 977 978 /* display related functionality */ 979 struct amdgpu_display_manager dm; 980 981 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 982 int num_ip_blocks; 983 struct mutex mn_lock; 984 DECLARE_HASHTABLE(mn_hash, 7); 985 986 /* tracking pinned memory */ 987 atomic64_t vram_pin_size; 988 atomic64_t visible_pin_size; 989 atomic64_t gart_pin_size; 990 991 /* amdkfd interface */ 992 struct kfd_dev *kfd; 993 994 /* soc15 register offset based on ip, instance and segment */ 995 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 996 997 const struct amdgpu_nbio_funcs *nbio_funcs; 998 const struct amdgpu_df_funcs *df_funcs; 999 1000 /* delayed work_func for deferring clockgating during resume */ 1001 struct delayed_work late_init_work; 1002 1003 struct amdgpu_virt virt; 1004 /* firmware VRAM reservation */ 1005 struct amdgpu_fw_vram_usage fw_vram_usage; 1006 1007 /* link all shadow bo */ 1008 struct list_head shadow_list; 1009 struct mutex shadow_list_lock; 1010 /* keep an lru list of rings by HW IP */ 1011 struct list_head ring_lru_list; 1012 spinlock_t ring_lru_list_lock; 1013 1014 /* record hw reset is performed */ 1015 bool has_hw_reset; 1016 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1017 1018 /* s3/s4 mask */ 1019 bool in_suspend; 1020 1021 /* record last mm index being written through WREG32*/ 1022 unsigned long last_mm_index; 1023 bool in_gpu_reset; 1024 struct mutex lock_reset; 1025 }; 1026 1027 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1028 { 1029 return container_of(bdev, struct amdgpu_device, mman.bdev); 1030 } 1031 1032 int amdgpu_device_init(struct amdgpu_device *adev, 1033 struct drm_device *ddev, 1034 struct pci_dev *pdev, 1035 uint32_t flags); 1036 void amdgpu_device_fini(struct amdgpu_device *adev); 1037 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1038 1039 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1040 uint32_t acc_flags); 1041 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1042 uint32_t acc_flags); 1043 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1044 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1045 1046 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1047 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1048 1049 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 1050 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1051 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 1052 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 1053 1054 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1055 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1056 1057 int emu_soc_asic_init(struct amdgpu_device *adev); 1058 1059 /* 1060 * Registers read & write functions. 1061 */ 1062 1063 #define AMDGPU_REGS_IDX (1<<0) 1064 #define AMDGPU_REGS_NO_KIQ (1<<1) 1065 1066 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1067 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1068 1069 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1070 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1071 1072 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1073 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1074 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1075 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1076 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1077 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1078 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1079 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1080 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1081 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1082 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1083 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1084 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1085 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1086 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1087 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1088 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1089 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1090 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1091 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1092 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1093 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1094 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1095 #define WREG32_P(reg, val, mask) \ 1096 do { \ 1097 uint32_t tmp_ = RREG32(reg); \ 1098 tmp_ &= (mask); \ 1099 tmp_ |= ((val) & ~(mask)); \ 1100 WREG32(reg, tmp_); \ 1101 } while (0) 1102 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1103 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1104 #define WREG32_PLL_P(reg, val, mask) \ 1105 do { \ 1106 uint32_t tmp_ = RREG32_PLL(reg); \ 1107 tmp_ &= (mask); \ 1108 tmp_ |= ((val) & ~(mask)); \ 1109 WREG32_PLL(reg, tmp_); \ 1110 } while (0) 1111 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1112 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1113 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1114 1115 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 1116 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1117 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 1118 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 1119 1120 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1121 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1122 1123 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1124 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1125 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1126 1127 #define REG_GET_FIELD(value, reg, field) \ 1128 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1129 1130 #define WREG32_FIELD(reg, field, val) \ 1131 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1132 1133 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1134 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1135 1136 /* 1137 * BIOS helpers. 1138 */ 1139 #define RBIOS8(i) (adev->bios[i]) 1140 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1141 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1142 1143 /* 1144 * ASICs macro. 1145 */ 1146 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1147 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1148 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1149 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1150 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1151 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1152 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1153 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1154 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1155 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1156 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1157 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1158 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1159 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1160 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1161 1162 /* Common functions */ 1163 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1164 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1165 struct amdgpu_job* job); 1166 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1167 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1168 1169 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1170 u64 num_vis_bytes); 1171 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1172 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1173 const u32 *registers, 1174 const u32 array_size); 1175 1176 bool amdgpu_device_is_px(struct drm_device *dev); 1177 /* atpx handler */ 1178 #if defined(CONFIG_VGA_SWITCHEROO) 1179 void amdgpu_register_atpx_handler(void); 1180 void amdgpu_unregister_atpx_handler(void); 1181 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1182 bool amdgpu_is_atpx_hybrid(void); 1183 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1184 bool amdgpu_has_atpx(void); 1185 #else 1186 static inline void amdgpu_register_atpx_handler(void) {} 1187 static inline void amdgpu_unregister_atpx_handler(void) {} 1188 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1189 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1190 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1191 static inline bool amdgpu_has_atpx(void) { return false; } 1192 #endif 1193 1194 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1195 void *amdgpu_atpx_get_dhandle(void); 1196 #else 1197 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1198 #endif 1199 1200 /* 1201 * KMS 1202 */ 1203 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1204 extern const int amdgpu_max_kms_ioctl; 1205 1206 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1207 void amdgpu_driver_unload_kms(struct drm_device *dev); 1208 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1209 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1210 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1211 struct drm_file *file_priv); 1212 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1213 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1214 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1215 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1216 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1217 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1218 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1219 unsigned long arg); 1220 1221 1222 /* 1223 * functions used by amdgpu_xgmi.c 1224 */ 1225 int amdgpu_xgmi_add_device(struct amdgpu_device *adev); 1226 1227 /* 1228 * functions used by amdgpu_encoder.c 1229 */ 1230 struct amdgpu_afmt_acr { 1231 u32 clock; 1232 1233 int n_32khz; 1234 int cts_32khz; 1235 1236 int n_44_1khz; 1237 int cts_44_1khz; 1238 1239 int n_48khz; 1240 int cts_48khz; 1241 1242 }; 1243 1244 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1245 1246 /* amdgpu_acpi.c */ 1247 #if defined(CONFIG_ACPI) 1248 int amdgpu_acpi_init(struct amdgpu_device *adev); 1249 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1250 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1251 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1252 u8 perf_req, bool advertise); 1253 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1254 #else 1255 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1256 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1257 #endif 1258 1259 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1260 uint64_t addr, struct amdgpu_bo **bo, 1261 struct amdgpu_bo_va_mapping **mapping); 1262 1263 #if defined(CONFIG_DRM_AMD_DC) 1264 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1265 #else 1266 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1267 #endif 1268 1269 #include "amdgpu_object.h" 1270 #endif 1271