1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include "amdgpu_ctx.h" 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/rbtree.h> 38 #include <linux/hashtable.h> 39 #include <linux/dma-fence.h> 40 41 #include <drm/ttm/ttm_bo_api.h> 42 #include <drm/ttm/ttm_bo_driver.h> 43 #include <drm/ttm/ttm_placement.h> 44 #include <drm/ttm/ttm_module.h> 45 #include <drm/ttm/ttm_execbuf_util.h> 46 47 #include <drm/amdgpu_drm.h> 48 #include <drm/drm_gem.h> 49 #include <drm/drm_ioctl.h> 50 #include <drm/gpu_scheduler.h> 51 52 #include <kgd_kfd_interface.h> 53 #include "dm_pp_interface.h" 54 #include "kgd_pp_interface.h" 55 56 #include "amd_shared.h" 57 #include "amdgpu_mode.h" 58 #include "amdgpu_ih.h" 59 #include "amdgpu_irq.h" 60 #include "amdgpu_ucode.h" 61 #include "amdgpu_ttm.h" 62 #include "amdgpu_psp.h" 63 #include "amdgpu_gds.h" 64 #include "amdgpu_sync.h" 65 #include "amdgpu_ring.h" 66 #include "amdgpu_vm.h" 67 #include "amdgpu_dpm.h" 68 #include "amdgpu_acp.h" 69 #include "amdgpu_uvd.h" 70 #include "amdgpu_vce.h" 71 #include "amdgpu_vcn.h" 72 #include "amdgpu_mn.h" 73 #include "amdgpu_gmc.h" 74 #include "amdgpu_gfx.h" 75 #include "amdgpu_sdma.h" 76 #include "amdgpu_dm.h" 77 #include "amdgpu_virt.h" 78 #include "amdgpu_csa.h" 79 #include "amdgpu_gart.h" 80 #include "amdgpu_debugfs.h" 81 #include "amdgpu_job.h" 82 #include "amdgpu_bo_list.h" 83 #include "amdgpu_gem.h" 84 #include "amdgpu_doorbell.h" 85 #include "amdgpu_amdkfd.h" 86 #include "amdgpu_smu.h" 87 #include "amdgpu_discovery.h" 88 #include "amdgpu_mes.h" 89 #include "amdgpu_umc.h" 90 #include "amdgpu_mmhub.h" 91 92 #define MAX_GPU_INSTANCE 16 93 94 struct amdgpu_gpu_instance 95 { 96 struct amdgpu_device *adev; 97 int mgpu_fan_enabled; 98 }; 99 100 struct amdgpu_mgpu_info 101 { 102 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 103 struct mutex mutex; 104 uint32_t num_gpu; 105 uint32_t num_dgpu; 106 uint32_t num_apu; 107 }; 108 109 /* 110 * Modules parameters. 111 */ 112 extern int amdgpu_modeset; 113 extern int amdgpu_vram_limit; 114 extern int amdgpu_vis_vram_limit; 115 extern int amdgpu_gart_size; 116 extern int amdgpu_gtt_size; 117 extern int amdgpu_moverate; 118 extern int amdgpu_benchmarking; 119 extern int amdgpu_testing; 120 extern int amdgpu_audio; 121 extern int amdgpu_disp_priority; 122 extern int amdgpu_hw_i2c; 123 extern int amdgpu_pcie_gen2; 124 extern int amdgpu_msi; 125 extern int amdgpu_dpm; 126 extern int amdgpu_fw_load_type; 127 extern int amdgpu_aspm; 128 extern int amdgpu_runtime_pm; 129 extern uint amdgpu_ip_block_mask; 130 extern int amdgpu_bapm; 131 extern int amdgpu_deep_color; 132 extern int amdgpu_vm_size; 133 extern int amdgpu_vm_block_size; 134 extern int amdgpu_vm_fragment_size; 135 extern int amdgpu_vm_fault_stop; 136 extern int amdgpu_vm_debug; 137 extern int amdgpu_vm_update_mode; 138 extern int amdgpu_dc; 139 extern int amdgpu_sched_jobs; 140 extern int amdgpu_sched_hw_submission; 141 extern uint amdgpu_pcie_gen_cap; 142 extern uint amdgpu_pcie_lane_cap; 143 extern uint amdgpu_cg_mask; 144 extern uint amdgpu_pg_mask; 145 extern uint amdgpu_sdma_phase_quantum; 146 extern char *amdgpu_disable_cu; 147 extern char *amdgpu_virtual_display; 148 extern uint amdgpu_pp_feature_mask; 149 extern int amdgpu_ngg; 150 extern int amdgpu_prim_buf_per_se; 151 extern int amdgpu_pos_buf_per_se; 152 extern int amdgpu_cntl_sb_buf_per_se; 153 extern int amdgpu_param_buf_per_se; 154 extern int amdgpu_job_hang_limit; 155 extern int amdgpu_lbpw; 156 extern int amdgpu_compute_multipipe; 157 extern int amdgpu_gpu_recovery; 158 extern int amdgpu_emu_mode; 159 extern uint amdgpu_smu_memory_pool_size; 160 extern uint amdgpu_dc_feature_mask; 161 extern uint amdgpu_dm_abm_level; 162 extern struct amdgpu_mgpu_info mgpu_info; 163 extern int amdgpu_ras_enable; 164 extern uint amdgpu_ras_mask; 165 extern int amdgpu_async_gfx_ring; 166 extern int amdgpu_mcbp; 167 extern int amdgpu_discovery; 168 extern int amdgpu_mes; 169 extern int amdgpu_noretry; 170 171 #ifdef CONFIG_DRM_AMDGPU_SI 172 extern int amdgpu_si_support; 173 #endif 174 #ifdef CONFIG_DRM_AMDGPU_CIK 175 extern int amdgpu_cik_support; 176 #endif 177 178 #define AMDGPU_VM_MAX_NUM_CTX 4096 179 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 180 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 181 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 182 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 183 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 184 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 185 #define AMDGPU_IB_POOL_SIZE 16 186 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 187 #define AMDGPUFB_CONN_LIMIT 4 188 #define AMDGPU_BIOS_NUM_SCRATCH 16 189 190 /* hard reset data */ 191 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 192 193 /* reset flags */ 194 #define AMDGPU_RESET_GFX (1 << 0) 195 #define AMDGPU_RESET_COMPUTE (1 << 1) 196 #define AMDGPU_RESET_DMA (1 << 2) 197 #define AMDGPU_RESET_CP (1 << 3) 198 #define AMDGPU_RESET_GRBM (1 << 4) 199 #define AMDGPU_RESET_DMA1 (1 << 5) 200 #define AMDGPU_RESET_RLC (1 << 6) 201 #define AMDGPU_RESET_SEM (1 << 7) 202 #define AMDGPU_RESET_IH (1 << 8) 203 #define AMDGPU_RESET_VMC (1 << 9) 204 #define AMDGPU_RESET_MC (1 << 10) 205 #define AMDGPU_RESET_DISPLAY (1 << 11) 206 #define AMDGPU_RESET_UVD (1 << 12) 207 #define AMDGPU_RESET_VCE (1 << 13) 208 #define AMDGPU_RESET_VCE1 (1 << 14) 209 210 /* max cursor sizes (in pixels) */ 211 #define CIK_CURSOR_WIDTH 128 212 #define CIK_CURSOR_HEIGHT 128 213 214 struct amdgpu_device; 215 struct amdgpu_ib; 216 struct amdgpu_cs_parser; 217 struct amdgpu_job; 218 struct amdgpu_irq_src; 219 struct amdgpu_fpriv; 220 struct amdgpu_bo_va_mapping; 221 struct amdgpu_atif; 222 struct kfd_vm_fault_info; 223 224 enum amdgpu_cp_irq { 225 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 226 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 227 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 228 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 229 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 230 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 231 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 232 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 233 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 234 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 235 236 AMDGPU_CP_IRQ_LAST 237 }; 238 239 enum amdgpu_thermal_irq { 240 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 241 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 242 243 AMDGPU_THERMAL_IRQ_LAST 244 }; 245 246 enum amdgpu_kiq_irq { 247 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 248 AMDGPU_CP_KIQ_IRQ_LAST 249 }; 250 251 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 252 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 253 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 254 255 int amdgpu_device_ip_set_clockgating_state(void *dev, 256 enum amd_ip_block_type block_type, 257 enum amd_clockgating_state state); 258 int amdgpu_device_ip_set_powergating_state(void *dev, 259 enum amd_ip_block_type block_type, 260 enum amd_powergating_state state); 261 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 262 u32 *flags); 263 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 264 enum amd_ip_block_type block_type); 265 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 266 enum amd_ip_block_type block_type); 267 268 #define AMDGPU_MAX_IP_NUM 16 269 270 struct amdgpu_ip_block_status { 271 bool valid; 272 bool sw; 273 bool hw; 274 bool late_initialized; 275 bool hang; 276 }; 277 278 struct amdgpu_ip_block_version { 279 const enum amd_ip_block_type type; 280 const u32 major; 281 const u32 minor; 282 const u32 rev; 283 const struct amd_ip_funcs *funcs; 284 }; 285 286 struct amdgpu_ip_block { 287 struct amdgpu_ip_block_status status; 288 const struct amdgpu_ip_block_version *version; 289 }; 290 291 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 292 enum amd_ip_block_type type, 293 u32 major, u32 minor); 294 295 struct amdgpu_ip_block * 296 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 297 enum amd_ip_block_type type); 298 299 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 300 const struct amdgpu_ip_block_version *ip_block_version); 301 302 /* 303 * BIOS. 304 */ 305 bool amdgpu_get_bios(struct amdgpu_device *adev); 306 bool amdgpu_read_bios(struct amdgpu_device *adev); 307 308 /* 309 * Clocks 310 */ 311 312 #define AMDGPU_MAX_PPLL 3 313 314 struct amdgpu_clock { 315 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 316 struct amdgpu_pll spll; 317 struct amdgpu_pll mpll; 318 /* 10 Khz units */ 319 uint32_t default_mclk; 320 uint32_t default_sclk; 321 uint32_t default_dispclk; 322 uint32_t current_dispclk; 323 uint32_t dp_extclk; 324 uint32_t max_pixel_clock; 325 }; 326 327 /* sub-allocation manager, it has to be protected by another lock. 328 * By conception this is an helper for other part of the driver 329 * like the indirect buffer or semaphore, which both have their 330 * locking. 331 * 332 * Principe is simple, we keep a list of sub allocation in offset 333 * order (first entry has offset == 0, last entry has the highest 334 * offset). 335 * 336 * When allocating new object we first check if there is room at 337 * the end total_size - (last_object_offset + last_object_size) >= 338 * alloc_size. If so we allocate new object there. 339 * 340 * When there is not enough room at the end, we start waiting for 341 * each sub object until we reach object_offset+object_size >= 342 * alloc_size, this object then become the sub object we return. 343 * 344 * Alignment can't be bigger than page size. 345 * 346 * Hole are not considered for allocation to keep things simple. 347 * Assumption is that there won't be hole (all object on same 348 * alignment). 349 */ 350 351 #define AMDGPU_SA_NUM_FENCE_LISTS 32 352 353 struct amdgpu_sa_manager { 354 wait_queue_head_t wq; 355 struct amdgpu_bo *bo; 356 struct list_head *hole; 357 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 358 struct list_head olist; 359 unsigned size; 360 uint64_t gpu_addr; 361 void *cpu_ptr; 362 uint32_t domain; 363 uint32_t align; 364 }; 365 366 /* sub-allocation buffer */ 367 struct amdgpu_sa_bo { 368 struct list_head olist; 369 struct list_head flist; 370 struct amdgpu_sa_manager *manager; 371 unsigned soffset; 372 unsigned eoffset; 373 struct dma_fence *fence; 374 }; 375 376 int amdgpu_fence_slab_init(void); 377 void amdgpu_fence_slab_fini(void); 378 379 /* 380 * IRQS. 381 */ 382 383 struct amdgpu_flip_work { 384 struct delayed_work flip_work; 385 struct work_struct unpin_work; 386 struct amdgpu_device *adev; 387 int crtc_id; 388 u32 target_vblank; 389 uint64_t base; 390 struct drm_pending_vblank_event *event; 391 struct amdgpu_bo *old_abo; 392 struct dma_fence *excl; 393 unsigned shared_count; 394 struct dma_fence **shared; 395 struct dma_fence_cb cb; 396 bool async; 397 }; 398 399 400 /* 401 * CP & rings. 402 */ 403 404 struct amdgpu_ib { 405 struct amdgpu_sa_bo *sa_bo; 406 uint32_t length_dw; 407 uint64_t gpu_addr; 408 uint32_t *ptr; 409 uint32_t flags; 410 }; 411 412 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 413 414 /* 415 * file private structure 416 */ 417 418 struct amdgpu_fpriv { 419 struct amdgpu_vm vm; 420 struct amdgpu_bo_va *prt_va; 421 struct amdgpu_bo_va *csa_va; 422 struct mutex bo_list_lock; 423 struct idr bo_list_handles; 424 struct amdgpu_ctx_mgr ctx_mgr; 425 }; 426 427 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 428 int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev); 429 430 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 431 unsigned size, struct amdgpu_ib *ib); 432 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 433 struct dma_fence *f); 434 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 435 struct amdgpu_ib *ibs, struct amdgpu_job *job, 436 struct dma_fence **f); 437 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 438 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 439 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 440 441 /* 442 * CS. 443 */ 444 struct amdgpu_cs_chunk { 445 uint32_t chunk_id; 446 uint32_t length_dw; 447 void *kdata; 448 }; 449 450 struct amdgpu_cs_post_dep { 451 struct drm_syncobj *syncobj; 452 struct dma_fence_chain *chain; 453 u64 point; 454 }; 455 456 struct amdgpu_cs_parser { 457 struct amdgpu_device *adev; 458 struct drm_file *filp; 459 struct amdgpu_ctx *ctx; 460 461 /* chunks */ 462 unsigned nchunks; 463 struct amdgpu_cs_chunk *chunks; 464 465 /* scheduler job object */ 466 struct amdgpu_job *job; 467 struct drm_sched_entity *entity; 468 469 /* buffer objects */ 470 struct ww_acquire_ctx ticket; 471 struct amdgpu_bo_list *bo_list; 472 struct amdgpu_mn *mn; 473 struct amdgpu_bo_list_entry vm_pd; 474 struct list_head validated; 475 struct dma_fence *fence; 476 uint64_t bytes_moved_threshold; 477 uint64_t bytes_moved_vis_threshold; 478 uint64_t bytes_moved; 479 uint64_t bytes_moved_vis; 480 struct amdgpu_bo_list_entry *evictable; 481 482 /* user fence */ 483 struct amdgpu_bo_list_entry uf_entry; 484 485 unsigned num_post_deps; 486 struct amdgpu_cs_post_dep *post_deps; 487 }; 488 489 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 490 uint32_t ib_idx, int idx) 491 { 492 return p->job->ibs[ib_idx].ptr[idx]; 493 } 494 495 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 496 uint32_t ib_idx, int idx, 497 uint32_t value) 498 { 499 p->job->ibs[ib_idx].ptr[idx] = value; 500 } 501 502 /* 503 * Writeback 504 */ 505 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 506 507 struct amdgpu_wb { 508 struct amdgpu_bo *wb_obj; 509 volatile uint32_t *wb; 510 uint64_t gpu_addr; 511 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 512 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 513 }; 514 515 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 516 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 517 518 /* 519 * Benchmarking 520 */ 521 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 522 523 524 /* 525 * Testing 526 */ 527 void amdgpu_test_moves(struct amdgpu_device *adev); 528 529 /* 530 * ASIC specific register table accessible by UMD 531 */ 532 struct amdgpu_allowed_register_entry { 533 uint32_t reg_offset; 534 bool grbm_indexed; 535 }; 536 537 enum amd_reset_method { 538 AMD_RESET_METHOD_LEGACY = 0, 539 AMD_RESET_METHOD_MODE0, 540 AMD_RESET_METHOD_MODE1, 541 AMD_RESET_METHOD_MODE2, 542 AMD_RESET_METHOD_BACO 543 }; 544 545 /* 546 * ASIC specific functions. 547 */ 548 struct amdgpu_asic_funcs { 549 bool (*read_disabled_bios)(struct amdgpu_device *adev); 550 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 551 u8 *bios, u32 length_bytes); 552 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 553 u32 sh_num, u32 reg_offset, u32 *value); 554 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 555 int (*reset)(struct amdgpu_device *adev); 556 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 557 /* get the reference clock */ 558 u32 (*get_xclk)(struct amdgpu_device *adev); 559 /* MM block clocks */ 560 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 561 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 562 /* static power management */ 563 int (*get_pcie_lanes)(struct amdgpu_device *adev); 564 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 565 /* get config memsize register */ 566 u32 (*get_config_memsize)(struct amdgpu_device *adev); 567 /* flush hdp write queue */ 568 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 569 /* invalidate hdp read cache */ 570 void (*invalidate_hdp)(struct amdgpu_device *adev, 571 struct amdgpu_ring *ring); 572 /* check if the asic needs a full reset of if soft reset will work */ 573 bool (*need_full_reset)(struct amdgpu_device *adev); 574 /* initialize doorbell layout for specific asic*/ 575 void (*init_doorbell_index)(struct amdgpu_device *adev); 576 /* PCIe bandwidth usage */ 577 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 578 uint64_t *count1); 579 /* do we need to reset the asic at init time (e.g., kexec) */ 580 bool (*need_reset_on_init)(struct amdgpu_device *adev); 581 /* PCIe replay counter */ 582 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 583 }; 584 585 /* 586 * IOCTL. 587 */ 588 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 589 struct drm_file *filp); 590 591 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 592 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 593 struct drm_file *filp); 594 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 595 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 596 struct drm_file *filp); 597 598 /* VRAM scratch page for HDP bug, default vram page */ 599 struct amdgpu_vram_scratch { 600 struct amdgpu_bo *robj; 601 volatile uint32_t *ptr; 602 u64 gpu_addr; 603 }; 604 605 /* 606 * ACPI 607 */ 608 struct amdgpu_atcs_functions { 609 bool get_ext_state; 610 bool pcie_perf_req; 611 bool pcie_dev_rdy; 612 bool pcie_bus_width; 613 }; 614 615 struct amdgpu_atcs { 616 struct amdgpu_atcs_functions functions; 617 }; 618 619 /* 620 * Firmware VRAM reservation 621 */ 622 struct amdgpu_fw_vram_usage { 623 u64 start_offset; 624 u64 size; 625 struct amdgpu_bo *reserved_bo; 626 void *va; 627 }; 628 629 /* 630 * CGS 631 */ 632 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 633 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 634 635 /* 636 * Core structure, functions and helpers. 637 */ 638 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 639 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 640 641 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 642 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 643 644 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 645 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 646 647 648 /* 649 * amdgpu nbio functions 650 * 651 */ 652 struct nbio_hdp_flush_reg { 653 u32 ref_and_mask_cp0; 654 u32 ref_and_mask_cp1; 655 u32 ref_and_mask_cp2; 656 u32 ref_and_mask_cp3; 657 u32 ref_and_mask_cp4; 658 u32 ref_and_mask_cp5; 659 u32 ref_and_mask_cp6; 660 u32 ref_and_mask_cp7; 661 u32 ref_and_mask_cp8; 662 u32 ref_and_mask_cp9; 663 u32 ref_and_mask_sdma0; 664 u32 ref_and_mask_sdma1; 665 u32 ref_and_mask_sdma2; 666 u32 ref_and_mask_sdma3; 667 u32 ref_and_mask_sdma4; 668 u32 ref_and_mask_sdma5; 669 u32 ref_and_mask_sdma6; 670 u32 ref_and_mask_sdma7; 671 }; 672 673 struct amdgpu_mmio_remap { 674 u32 reg_offset; 675 resource_size_t bus_addr; 676 }; 677 678 struct amdgpu_nbio_funcs { 679 const struct nbio_hdp_flush_reg *hdp_flush_reg; 680 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 681 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 682 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 683 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 684 u32 (*get_rev_id)(struct amdgpu_device *adev); 685 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 686 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 687 u32 (*get_memsize)(struct amdgpu_device *adev); 688 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 689 bool use_doorbell, int doorbell_index, int doorbell_size); 690 void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell, 691 int doorbell_index, int instance); 692 void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 693 bool enable); 694 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 695 bool enable); 696 void (*ih_doorbell_range)(struct amdgpu_device *adev, 697 bool use_doorbell, int doorbell_index); 698 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 699 bool enable); 700 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 701 bool enable); 702 void (*get_clockgating_state)(struct amdgpu_device *adev, 703 u32 *flags); 704 void (*ih_control)(struct amdgpu_device *adev); 705 void (*init_registers)(struct amdgpu_device *adev); 706 void (*detect_hw_virt)(struct amdgpu_device *adev); 707 void (*remap_hdp_registers)(struct amdgpu_device *adev); 708 }; 709 710 struct amdgpu_df_funcs { 711 void (*sw_init)(struct amdgpu_device *adev); 712 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 713 bool enable); 714 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 715 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 716 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 717 bool enable); 718 void (*get_clockgating_state)(struct amdgpu_device *adev, 719 u32 *flags); 720 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 721 bool enable); 722 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config, 723 int is_enable); 724 int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config, 725 int is_disable); 726 void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config, 727 uint64_t *count); 728 uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val); 729 void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val, 730 uint32_t ficadl_val, uint32_t ficadh_val); 731 }; 732 /* Define the HW IP blocks will be used in driver , add more if necessary */ 733 enum amd_hw_ip_block_type { 734 GC_HWIP = 1, 735 HDP_HWIP, 736 SDMA0_HWIP, 737 SDMA1_HWIP, 738 SDMA2_HWIP, 739 SDMA3_HWIP, 740 SDMA4_HWIP, 741 SDMA5_HWIP, 742 SDMA6_HWIP, 743 SDMA7_HWIP, 744 MMHUB_HWIP, 745 ATHUB_HWIP, 746 NBIO_HWIP, 747 MP0_HWIP, 748 MP1_HWIP, 749 UVD_HWIP, 750 VCN_HWIP = UVD_HWIP, 751 VCE_HWIP, 752 DF_HWIP, 753 DCE_HWIP, 754 OSSSYS_HWIP, 755 SMUIO_HWIP, 756 PWR_HWIP, 757 NBIF_HWIP, 758 THM_HWIP, 759 CLK_HWIP, 760 UMC_HWIP, 761 RSMU_HWIP, 762 MAX_HWIP 763 }; 764 765 #define HWIP_MAX_INSTANCE 8 766 767 struct amd_powerplay { 768 void *pp_handle; 769 const struct amd_pm_funcs *pp_funcs; 770 }; 771 772 #define AMDGPU_RESET_MAGIC_NUM 64 773 #define AMDGPU_MAX_DF_PERFMONS 4 774 struct amdgpu_device { 775 struct device *dev; 776 struct drm_device *ddev; 777 struct pci_dev *pdev; 778 779 #ifdef CONFIG_DRM_AMD_ACP 780 struct amdgpu_acp acp; 781 #endif 782 783 /* ASIC */ 784 enum amd_asic_type asic_type; 785 uint32_t family; 786 uint32_t rev_id; 787 uint32_t external_rev_id; 788 unsigned long flags; 789 int usec_timeout; 790 const struct amdgpu_asic_funcs *asic_funcs; 791 bool shutdown; 792 bool need_swiotlb; 793 bool accel_working; 794 struct notifier_block acpi_nb; 795 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 796 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 797 unsigned debugfs_count; 798 #if defined(CONFIG_DEBUG_FS) 799 struct dentry *debugfs_preempt; 800 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 801 #endif 802 struct amdgpu_atif *atif; 803 struct amdgpu_atcs atcs; 804 struct mutex srbm_mutex; 805 /* GRBM index mutex. Protects concurrent access to GRBM index */ 806 struct mutex grbm_idx_mutex; 807 struct dev_pm_domain vga_pm_domain; 808 bool have_disp_power_ref; 809 bool have_atomics_support; 810 811 /* BIOS */ 812 bool is_atom_fw; 813 uint8_t *bios; 814 uint32_t bios_size; 815 struct amdgpu_bo *stolen_vga_memory; 816 uint32_t bios_scratch_reg_offset; 817 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 818 819 /* Register/doorbell mmio */ 820 resource_size_t rmmio_base; 821 resource_size_t rmmio_size; 822 void __iomem *rmmio; 823 /* protects concurrent MM_INDEX/DATA based register access */ 824 spinlock_t mmio_idx_lock; 825 struct amdgpu_mmio_remap rmmio_remap; 826 /* protects concurrent SMC based register access */ 827 spinlock_t smc_idx_lock; 828 amdgpu_rreg_t smc_rreg; 829 amdgpu_wreg_t smc_wreg; 830 /* protects concurrent PCIE register access */ 831 spinlock_t pcie_idx_lock; 832 amdgpu_rreg_t pcie_rreg; 833 amdgpu_wreg_t pcie_wreg; 834 amdgpu_rreg_t pciep_rreg; 835 amdgpu_wreg_t pciep_wreg; 836 amdgpu_rreg64_t pcie_rreg64; 837 amdgpu_wreg64_t pcie_wreg64; 838 /* protects concurrent UVD register access */ 839 spinlock_t uvd_ctx_idx_lock; 840 amdgpu_rreg_t uvd_ctx_rreg; 841 amdgpu_wreg_t uvd_ctx_wreg; 842 /* protects concurrent DIDT register access */ 843 spinlock_t didt_idx_lock; 844 amdgpu_rreg_t didt_rreg; 845 amdgpu_wreg_t didt_wreg; 846 /* protects concurrent gc_cac register access */ 847 spinlock_t gc_cac_idx_lock; 848 amdgpu_rreg_t gc_cac_rreg; 849 amdgpu_wreg_t gc_cac_wreg; 850 /* protects concurrent se_cac register access */ 851 spinlock_t se_cac_idx_lock; 852 amdgpu_rreg_t se_cac_rreg; 853 amdgpu_wreg_t se_cac_wreg; 854 /* protects concurrent ENDPOINT (audio) register access */ 855 spinlock_t audio_endpt_idx_lock; 856 amdgpu_block_rreg_t audio_endpt_rreg; 857 amdgpu_block_wreg_t audio_endpt_wreg; 858 void __iomem *rio_mem; 859 resource_size_t rio_mem_size; 860 struct amdgpu_doorbell doorbell; 861 862 /* clock/pll info */ 863 struct amdgpu_clock clock; 864 865 /* MC */ 866 struct amdgpu_gmc gmc; 867 struct amdgpu_gart gart; 868 dma_addr_t dummy_page_addr; 869 struct amdgpu_vm_manager vm_manager; 870 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 871 unsigned num_vmhubs; 872 873 /* memory management */ 874 struct amdgpu_mman mman; 875 struct amdgpu_vram_scratch vram_scratch; 876 struct amdgpu_wb wb; 877 atomic64_t num_bytes_moved; 878 atomic64_t num_evictions; 879 atomic64_t num_vram_cpu_page_faults; 880 atomic_t gpu_reset_counter; 881 atomic_t vram_lost_counter; 882 883 /* data for buffer migration throttling */ 884 struct { 885 spinlock_t lock; 886 s64 last_update_us; 887 s64 accum_us; /* accumulated microseconds */ 888 s64 accum_us_vis; /* for visible VRAM */ 889 u32 log2_max_MBps; 890 } mm_stats; 891 892 /* display */ 893 bool enable_virtual_display; 894 struct amdgpu_mode_info mode_info; 895 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 896 struct work_struct hotplug_work; 897 struct amdgpu_irq_src crtc_irq; 898 struct amdgpu_irq_src vupdate_irq; 899 struct amdgpu_irq_src pageflip_irq; 900 struct amdgpu_irq_src hpd_irq; 901 902 /* rings */ 903 u64 fence_context; 904 unsigned num_rings; 905 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 906 bool ib_pool_ready; 907 struct amdgpu_sa_manager ring_tmp_bo; 908 909 /* interrupts */ 910 struct amdgpu_irq irq; 911 912 /* powerplay */ 913 struct amd_powerplay powerplay; 914 bool pp_force_state_enabled; 915 916 /* smu */ 917 struct smu_context smu; 918 919 /* dpm */ 920 struct amdgpu_pm pm; 921 u32 cg_flags; 922 u32 pg_flags; 923 924 /* gfx */ 925 struct amdgpu_gfx gfx; 926 927 /* sdma */ 928 struct amdgpu_sdma sdma; 929 930 /* uvd */ 931 struct amdgpu_uvd uvd; 932 933 /* vce */ 934 struct amdgpu_vce vce; 935 936 /* vcn */ 937 struct amdgpu_vcn vcn; 938 939 /* firmwares */ 940 struct amdgpu_firmware firmware; 941 942 /* PSP */ 943 struct psp_context psp; 944 945 /* GDS */ 946 struct amdgpu_gds gds; 947 948 /* KFD */ 949 struct amdgpu_kfd_dev kfd; 950 951 /* UMC */ 952 struct amdgpu_umc umc; 953 954 /* display related functionality */ 955 struct amdgpu_display_manager dm; 956 957 /* discovery */ 958 uint8_t *discovery; 959 960 /* mes */ 961 bool enable_mes; 962 struct amdgpu_mes mes; 963 964 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 965 int num_ip_blocks; 966 struct mutex mn_lock; 967 DECLARE_HASHTABLE(mn_hash, 7); 968 969 /* tracking pinned memory */ 970 atomic64_t vram_pin_size; 971 atomic64_t visible_pin_size; 972 atomic64_t gart_pin_size; 973 974 /* soc15 register offset based on ip, instance and segment */ 975 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 976 977 const struct amdgpu_nbio_funcs *nbio_funcs; 978 const struct amdgpu_df_funcs *df_funcs; 979 const struct amdgpu_mmhub_funcs *mmhub_funcs; 980 981 /* delayed work_func for deferring clockgating during resume */ 982 struct delayed_work delayed_init_work; 983 984 struct amdgpu_virt virt; 985 /* firmware VRAM reservation */ 986 struct amdgpu_fw_vram_usage fw_vram_usage; 987 988 /* link all shadow bo */ 989 struct list_head shadow_list; 990 struct mutex shadow_list_lock; 991 /* keep an lru list of rings by HW IP */ 992 struct list_head ring_lru_list; 993 spinlock_t ring_lru_list_lock; 994 995 /* record hw reset is performed */ 996 bool has_hw_reset; 997 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 998 999 /* s3/s4 mask */ 1000 bool in_suspend; 1001 1002 /* record last mm index being written through WREG32*/ 1003 unsigned long last_mm_index; 1004 bool in_gpu_reset; 1005 enum pp_mp1_state mp1_state; 1006 struct mutex lock_reset; 1007 struct amdgpu_doorbell_index doorbell_index; 1008 1009 int asic_reset_res; 1010 struct work_struct xgmi_reset_work; 1011 1012 bool in_baco_reset; 1013 1014 long gfx_timeout; 1015 long sdma_timeout; 1016 long video_timeout; 1017 long compute_timeout; 1018 1019 uint64_t unique_id; 1020 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1021 }; 1022 1023 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1024 { 1025 return container_of(bdev, struct amdgpu_device, mman.bdev); 1026 } 1027 1028 int amdgpu_device_init(struct amdgpu_device *adev, 1029 struct drm_device *ddev, 1030 struct pci_dev *pdev, 1031 uint32_t flags); 1032 void amdgpu_device_fini(struct amdgpu_device *adev); 1033 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1034 1035 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1036 uint32_t acc_flags); 1037 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1038 uint32_t acc_flags); 1039 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1040 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1041 1042 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1043 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1044 1045 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1046 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1047 1048 int emu_soc_asic_init(struct amdgpu_device *adev); 1049 1050 /* 1051 * Registers read & write functions. 1052 */ 1053 1054 #define AMDGPU_REGS_IDX (1<<0) 1055 #define AMDGPU_REGS_NO_KIQ (1<<1) 1056 1057 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1058 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1059 1060 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1061 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1062 1063 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1064 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1065 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1066 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1067 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1068 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1069 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1070 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1071 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1072 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1073 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1074 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1075 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1076 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1077 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1078 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1079 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1080 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1081 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1082 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1083 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1084 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1085 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1086 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1087 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1088 #define WREG32_P(reg, val, mask) \ 1089 do { \ 1090 uint32_t tmp_ = RREG32(reg); \ 1091 tmp_ &= (mask); \ 1092 tmp_ |= ((val) & ~(mask)); \ 1093 WREG32(reg, tmp_); \ 1094 } while (0) 1095 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1096 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1097 #define WREG32_PLL_P(reg, val, mask) \ 1098 do { \ 1099 uint32_t tmp_ = RREG32_PLL(reg); \ 1100 tmp_ &= (mask); \ 1101 tmp_ |= ((val) & ~(mask)); \ 1102 WREG32_PLL(reg, tmp_); \ 1103 } while (0) 1104 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1105 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1106 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1107 1108 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1109 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1110 1111 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1112 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1113 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1114 1115 #define REG_GET_FIELD(value, reg, field) \ 1116 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1117 1118 #define WREG32_FIELD(reg, field, val) \ 1119 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1120 1121 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1122 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1123 1124 /* 1125 * BIOS helpers. 1126 */ 1127 #define RBIOS8(i) (adev->bios[i]) 1128 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1129 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1130 1131 /* 1132 * ASICs macro. 1133 */ 1134 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1135 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1136 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1137 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1138 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1139 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1140 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1141 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1142 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1143 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1144 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1145 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1146 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1147 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1148 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1149 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1150 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1151 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1152 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1153 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1154 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1155 1156 /* Common functions */ 1157 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1158 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1159 struct amdgpu_job* job); 1160 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1161 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1162 1163 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1164 u64 num_vis_bytes); 1165 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1166 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1167 const u32 *registers, 1168 const u32 array_size); 1169 1170 bool amdgpu_device_is_px(struct drm_device *dev); 1171 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1172 struct amdgpu_device *peer_adev); 1173 1174 /* atpx handler */ 1175 #if defined(CONFIG_VGA_SWITCHEROO) 1176 void amdgpu_register_atpx_handler(void); 1177 void amdgpu_unregister_atpx_handler(void); 1178 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1179 bool amdgpu_is_atpx_hybrid(void); 1180 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1181 bool amdgpu_has_atpx(void); 1182 #else 1183 static inline void amdgpu_register_atpx_handler(void) {} 1184 static inline void amdgpu_unregister_atpx_handler(void) {} 1185 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1186 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1187 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1188 static inline bool amdgpu_has_atpx(void) { return false; } 1189 #endif 1190 1191 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1192 void *amdgpu_atpx_get_dhandle(void); 1193 #else 1194 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1195 #endif 1196 1197 /* 1198 * KMS 1199 */ 1200 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1201 extern const int amdgpu_max_kms_ioctl; 1202 1203 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1204 void amdgpu_driver_unload_kms(struct drm_device *dev); 1205 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1206 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1207 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1208 struct drm_file *file_priv); 1209 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1210 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1211 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1212 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1213 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1214 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1215 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1216 unsigned long arg); 1217 1218 /* 1219 * functions used by amdgpu_encoder.c 1220 */ 1221 struct amdgpu_afmt_acr { 1222 u32 clock; 1223 1224 int n_32khz; 1225 int cts_32khz; 1226 1227 int n_44_1khz; 1228 int cts_44_1khz; 1229 1230 int n_48khz; 1231 int cts_48khz; 1232 1233 }; 1234 1235 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1236 1237 /* amdgpu_acpi.c */ 1238 #if defined(CONFIG_ACPI) 1239 int amdgpu_acpi_init(struct amdgpu_device *adev); 1240 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1241 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1242 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1243 u8 perf_req, bool advertise); 1244 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1245 1246 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1247 struct amdgpu_dm_backlight_caps *caps); 1248 #else 1249 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1250 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1251 #endif 1252 1253 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1254 uint64_t addr, struct amdgpu_bo **bo, 1255 struct amdgpu_bo_va_mapping **mapping); 1256 1257 #if defined(CONFIG_DRM_AMD_DC) 1258 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1259 #else 1260 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1261 #endif 1262 1263 1264 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1265 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1266 1267 #include "amdgpu_object.h" 1268 1269 /* used by df_v3_6.c and amdgpu_pmu.c */ 1270 #define AMDGPU_PMU_ATTR(_name, _object) \ 1271 static ssize_t \ 1272 _name##_show(struct device *dev, \ 1273 struct device_attribute *attr, \ 1274 char *page) \ 1275 { \ 1276 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1277 return sprintf(page, _object "\n"); \ 1278 } \ 1279 \ 1280 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1281 1282 #endif 1283 1284