1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 #include <drm/ttm/ttm_execbuf_util.h> 57 58 #include <drm/amdgpu_drm.h> 59 #include <drm/drm_gem.h> 60 #include <drm/drm_ioctl.h> 61 62 #include <kgd_kfd_interface.h> 63 #include "dm_pp_interface.h" 64 #include "kgd_pp_interface.h" 65 66 #include "amd_shared.h" 67 #include "amdgpu_mode.h" 68 #include "amdgpu_ih.h" 69 #include "amdgpu_irq.h" 70 #include "amdgpu_ucode.h" 71 #include "amdgpu_ttm.h" 72 #include "amdgpu_psp.h" 73 #include "amdgpu_gds.h" 74 #include "amdgpu_sync.h" 75 #include "amdgpu_ring.h" 76 #include "amdgpu_vm.h" 77 #include "amdgpu_dpm.h" 78 #include "amdgpu_acp.h" 79 #include "amdgpu_uvd.h" 80 #include "amdgpu_vce.h" 81 #include "amdgpu_vcn.h" 82 #include "amdgpu_jpeg.h" 83 #include "amdgpu_gmc.h" 84 #include "amdgpu_gfx.h" 85 #include "amdgpu_sdma.h" 86 #include "amdgpu_lsdma.h" 87 #include "amdgpu_nbio.h" 88 #include "amdgpu_hdp.h" 89 #include "amdgpu_dm.h" 90 #include "amdgpu_virt.h" 91 #include "amdgpu_csa.h" 92 #include "amdgpu_mes_ctx.h" 93 #include "amdgpu_gart.h" 94 #include "amdgpu_debugfs.h" 95 #include "amdgpu_job.h" 96 #include "amdgpu_bo_list.h" 97 #include "amdgpu_gem.h" 98 #include "amdgpu_doorbell.h" 99 #include "amdgpu_amdkfd.h" 100 #include "amdgpu_discovery.h" 101 #include "amdgpu_mes.h" 102 #include "amdgpu_umc.h" 103 #include "amdgpu_mmhub.h" 104 #include "amdgpu_gfxhub.h" 105 #include "amdgpu_df.h" 106 #include "amdgpu_smuio.h" 107 #include "amdgpu_fdinfo.h" 108 #include "amdgpu_mca.h" 109 #include "amdgpu_ras.h" 110 #include "amdgpu_xcp.h" 111 112 #define MAX_GPU_INSTANCE 64 113 114 struct amdgpu_gpu_instance 115 { 116 struct amdgpu_device *adev; 117 int mgpu_fan_enabled; 118 }; 119 120 struct amdgpu_mgpu_info 121 { 122 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 123 struct mutex mutex; 124 uint32_t num_gpu; 125 uint32_t num_dgpu; 126 uint32_t num_apu; 127 128 /* delayed reset_func for XGMI configuration if necessary */ 129 struct delayed_work delayed_reset_work; 130 bool pending_reset; 131 }; 132 133 enum amdgpu_ss { 134 AMDGPU_SS_DRV_LOAD, 135 AMDGPU_SS_DEV_D0, 136 AMDGPU_SS_DEV_D3, 137 AMDGPU_SS_DRV_UNLOAD 138 }; 139 140 struct amdgpu_watchdog_timer 141 { 142 bool timeout_fatal_disable; 143 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 144 }; 145 146 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 147 148 /* 149 * Modules parameters. 150 */ 151 extern int amdgpu_modeset; 152 extern unsigned int amdgpu_vram_limit; 153 extern int amdgpu_vis_vram_limit; 154 extern int amdgpu_gart_size; 155 extern int amdgpu_gtt_size; 156 extern int amdgpu_moverate; 157 extern int amdgpu_audio; 158 extern int amdgpu_disp_priority; 159 extern int amdgpu_hw_i2c; 160 extern int amdgpu_pcie_gen2; 161 extern int amdgpu_msi; 162 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 163 extern int amdgpu_dpm; 164 extern int amdgpu_fw_load_type; 165 extern int amdgpu_aspm; 166 extern int amdgpu_runtime_pm; 167 extern uint amdgpu_ip_block_mask; 168 extern int amdgpu_bapm; 169 extern int amdgpu_deep_color; 170 extern int amdgpu_vm_size; 171 extern int amdgpu_vm_block_size; 172 extern int amdgpu_vm_fragment_size; 173 extern int amdgpu_vm_fault_stop; 174 extern int amdgpu_vm_debug; 175 extern int amdgpu_vm_update_mode; 176 extern int amdgpu_exp_hw_support; 177 extern int amdgpu_dc; 178 extern int amdgpu_sched_jobs; 179 extern int amdgpu_sched_hw_submission; 180 extern uint amdgpu_pcie_gen_cap; 181 extern uint amdgpu_pcie_lane_cap; 182 extern u64 amdgpu_cg_mask; 183 extern uint amdgpu_pg_mask; 184 extern uint amdgpu_sdma_phase_quantum; 185 extern char *amdgpu_disable_cu; 186 extern char *amdgpu_virtual_display; 187 extern uint amdgpu_pp_feature_mask; 188 extern uint amdgpu_force_long_training; 189 extern int amdgpu_lbpw; 190 extern int amdgpu_compute_multipipe; 191 extern int amdgpu_gpu_recovery; 192 extern int amdgpu_emu_mode; 193 extern uint amdgpu_smu_memory_pool_size; 194 extern int amdgpu_smu_pptable_id; 195 extern uint amdgpu_dc_feature_mask; 196 extern uint amdgpu_freesync_vid_mode; 197 extern uint amdgpu_dc_debug_mask; 198 extern uint amdgpu_dc_visual_confirm; 199 extern uint amdgpu_dm_abm_level; 200 extern int amdgpu_backlight; 201 extern struct amdgpu_mgpu_info mgpu_info; 202 extern int amdgpu_ras_enable; 203 extern uint amdgpu_ras_mask; 204 extern int amdgpu_bad_page_threshold; 205 extern bool amdgpu_ignore_bad_page_threshold; 206 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 207 extern int amdgpu_async_gfx_ring; 208 extern int amdgpu_mcbp; 209 extern int amdgpu_discovery; 210 extern int amdgpu_mes; 211 extern int amdgpu_mes_kiq; 212 extern int amdgpu_noretry; 213 extern int amdgpu_force_asic_type; 214 extern int amdgpu_smartshift_bias; 215 extern int amdgpu_use_xgmi_p2p; 216 extern int amdgpu_mtype_local; 217 extern bool enforce_isolation; 218 #ifdef CONFIG_HSA_AMD 219 extern int sched_policy; 220 extern bool debug_evictions; 221 extern bool no_system_mem_limit; 222 extern int halt_if_hws_hang; 223 #else 224 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 225 static const bool __maybe_unused debug_evictions; /* = false */ 226 static const bool __maybe_unused no_system_mem_limit; 227 static const int __maybe_unused halt_if_hws_hang; 228 #endif 229 #ifdef CONFIG_HSA_AMD_P2P 230 extern bool pcie_p2p; 231 #endif 232 233 extern int amdgpu_tmz; 234 extern int amdgpu_reset_method; 235 236 #ifdef CONFIG_DRM_AMDGPU_SI 237 extern int amdgpu_si_support; 238 #endif 239 #ifdef CONFIG_DRM_AMDGPU_CIK 240 extern int amdgpu_cik_support; 241 #endif 242 extern int amdgpu_num_kcq; 243 244 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 245 extern int amdgpu_vcnfw_log; 246 extern int amdgpu_sg_display; 247 248 extern int amdgpu_user_partt_mode; 249 250 #define AMDGPU_VM_MAX_NUM_CTX 4096 251 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 252 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 253 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 254 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 255 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 256 #define AMDGPUFB_CONN_LIMIT 4 257 #define AMDGPU_BIOS_NUM_SCRATCH 16 258 259 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 260 261 /* hard reset data */ 262 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 263 264 /* reset flags */ 265 #define AMDGPU_RESET_GFX (1 << 0) 266 #define AMDGPU_RESET_COMPUTE (1 << 1) 267 #define AMDGPU_RESET_DMA (1 << 2) 268 #define AMDGPU_RESET_CP (1 << 3) 269 #define AMDGPU_RESET_GRBM (1 << 4) 270 #define AMDGPU_RESET_DMA1 (1 << 5) 271 #define AMDGPU_RESET_RLC (1 << 6) 272 #define AMDGPU_RESET_SEM (1 << 7) 273 #define AMDGPU_RESET_IH (1 << 8) 274 #define AMDGPU_RESET_VMC (1 << 9) 275 #define AMDGPU_RESET_MC (1 << 10) 276 #define AMDGPU_RESET_DISPLAY (1 << 11) 277 #define AMDGPU_RESET_UVD (1 << 12) 278 #define AMDGPU_RESET_VCE (1 << 13) 279 #define AMDGPU_RESET_VCE1 (1 << 14) 280 281 /* max cursor sizes (in pixels) */ 282 #define CIK_CURSOR_WIDTH 128 283 #define CIK_CURSOR_HEIGHT 128 284 285 /* smart shift bias level limits */ 286 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 287 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 288 289 struct amdgpu_xcp_mgr; 290 struct amdgpu_device; 291 struct amdgpu_irq_src; 292 struct amdgpu_fpriv; 293 struct amdgpu_bo_va_mapping; 294 struct kfd_vm_fault_info; 295 struct amdgpu_hive_info; 296 struct amdgpu_reset_context; 297 struct amdgpu_reset_control; 298 299 enum amdgpu_cp_irq { 300 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 301 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 302 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 303 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 304 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 305 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 306 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 307 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 308 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 309 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 310 311 AMDGPU_CP_IRQ_LAST 312 }; 313 314 enum amdgpu_thermal_irq { 315 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 316 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 317 318 AMDGPU_THERMAL_IRQ_LAST 319 }; 320 321 enum amdgpu_kiq_irq { 322 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 323 AMDGPU_CP_KIQ_IRQ_LAST 324 }; 325 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 326 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 327 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 328 #define MAX_KIQ_REG_TRY 1000 329 330 int amdgpu_device_ip_set_clockgating_state(void *dev, 331 enum amd_ip_block_type block_type, 332 enum amd_clockgating_state state); 333 int amdgpu_device_ip_set_powergating_state(void *dev, 334 enum amd_ip_block_type block_type, 335 enum amd_powergating_state state); 336 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 337 u64 *flags); 338 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 339 enum amd_ip_block_type block_type); 340 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 341 enum amd_ip_block_type block_type); 342 343 #define AMDGPU_MAX_IP_NUM 16 344 345 struct amdgpu_ip_block_status { 346 bool valid; 347 bool sw; 348 bool hw; 349 bool late_initialized; 350 bool hang; 351 }; 352 353 struct amdgpu_ip_block_version { 354 const enum amd_ip_block_type type; 355 const u32 major; 356 const u32 minor; 357 const u32 rev; 358 const struct amd_ip_funcs *funcs; 359 }; 360 361 #define HW_REV(_Major, _Minor, _Rev) \ 362 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 363 364 struct amdgpu_ip_block { 365 struct amdgpu_ip_block_status status; 366 const struct amdgpu_ip_block_version *version; 367 }; 368 369 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 370 enum amd_ip_block_type type, 371 u32 major, u32 minor); 372 373 struct amdgpu_ip_block * 374 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 375 enum amd_ip_block_type type); 376 377 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 378 const struct amdgpu_ip_block_version *ip_block_version); 379 380 /* 381 * BIOS. 382 */ 383 bool amdgpu_get_bios(struct amdgpu_device *adev); 384 bool amdgpu_read_bios(struct amdgpu_device *adev); 385 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 386 u8 *bios, u32 length_bytes); 387 /* 388 * Clocks 389 */ 390 391 #define AMDGPU_MAX_PPLL 3 392 393 struct amdgpu_clock { 394 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 395 struct amdgpu_pll spll; 396 struct amdgpu_pll mpll; 397 /* 10 Khz units */ 398 uint32_t default_mclk; 399 uint32_t default_sclk; 400 uint32_t default_dispclk; 401 uint32_t current_dispclk; 402 uint32_t dp_extclk; 403 uint32_t max_pixel_clock; 404 }; 405 406 /* sub-allocation manager, it has to be protected by another lock. 407 * By conception this is an helper for other part of the driver 408 * like the indirect buffer or semaphore, which both have their 409 * locking. 410 * 411 * Principe is simple, we keep a list of sub allocation in offset 412 * order (first entry has offset == 0, last entry has the highest 413 * offset). 414 * 415 * When allocating new object we first check if there is room at 416 * the end total_size - (last_object_offset + last_object_size) >= 417 * alloc_size. If so we allocate new object there. 418 * 419 * When there is not enough room at the end, we start waiting for 420 * each sub object until we reach object_offset+object_size >= 421 * alloc_size, this object then become the sub object we return. 422 * 423 * Alignment can't be bigger than page size. 424 * 425 * Hole are not considered for allocation to keep things simple. 426 * Assumption is that there won't be hole (all object on same 427 * alignment). 428 */ 429 430 struct amdgpu_sa_manager { 431 struct drm_suballoc_manager base; 432 struct amdgpu_bo *bo; 433 uint64_t gpu_addr; 434 void *cpu_ptr; 435 }; 436 437 int amdgpu_fence_slab_init(void); 438 void amdgpu_fence_slab_fini(void); 439 440 /* 441 * IRQS. 442 */ 443 444 struct amdgpu_flip_work { 445 struct delayed_work flip_work; 446 struct work_struct unpin_work; 447 struct amdgpu_device *adev; 448 int crtc_id; 449 u32 target_vblank; 450 uint64_t base; 451 struct drm_pending_vblank_event *event; 452 struct amdgpu_bo *old_abo; 453 unsigned shared_count; 454 struct dma_fence **shared; 455 struct dma_fence_cb cb; 456 bool async; 457 }; 458 459 460 /* 461 * file private structure 462 */ 463 464 struct amdgpu_fpriv { 465 struct amdgpu_vm vm; 466 struct amdgpu_bo_va *prt_va; 467 struct amdgpu_bo_va *csa_va; 468 struct mutex bo_list_lock; 469 struct idr bo_list_handles; 470 struct amdgpu_ctx_mgr ctx_mgr; 471 /** GPU partition selection */ 472 uint32_t xcp_id; 473 }; 474 475 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 476 477 /* 478 * Writeback 479 */ 480 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 481 482 struct amdgpu_wb { 483 struct amdgpu_bo *wb_obj; 484 volatile uint32_t *wb; 485 uint64_t gpu_addr; 486 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 487 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 488 }; 489 490 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 491 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 492 493 /* 494 * Benchmarking 495 */ 496 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 497 498 /* 499 * ASIC specific register table accessible by UMD 500 */ 501 struct amdgpu_allowed_register_entry { 502 uint32_t reg_offset; 503 bool grbm_indexed; 504 }; 505 506 enum amd_reset_method { 507 AMD_RESET_METHOD_NONE = -1, 508 AMD_RESET_METHOD_LEGACY = 0, 509 AMD_RESET_METHOD_MODE0, 510 AMD_RESET_METHOD_MODE1, 511 AMD_RESET_METHOD_MODE2, 512 AMD_RESET_METHOD_BACO, 513 AMD_RESET_METHOD_PCI, 514 }; 515 516 struct amdgpu_video_codec_info { 517 u32 codec_type; 518 u32 max_width; 519 u32 max_height; 520 u32 max_pixels_per_frame; 521 u32 max_level; 522 }; 523 524 #define codec_info_build(type, width, height, level) \ 525 .codec_type = type,\ 526 .max_width = width,\ 527 .max_height = height,\ 528 .max_pixels_per_frame = height * width,\ 529 .max_level = level, 530 531 struct amdgpu_video_codecs { 532 const u32 codec_count; 533 const struct amdgpu_video_codec_info *codec_array; 534 }; 535 536 /* 537 * ASIC specific functions. 538 */ 539 struct amdgpu_asic_funcs { 540 bool (*read_disabled_bios)(struct amdgpu_device *adev); 541 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 542 u8 *bios, u32 length_bytes); 543 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 544 u32 sh_num, u32 reg_offset, u32 *value); 545 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 546 int (*reset)(struct amdgpu_device *adev); 547 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 548 /* get the reference clock */ 549 u32 (*get_xclk)(struct amdgpu_device *adev); 550 /* MM block clocks */ 551 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 552 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 553 /* static power management */ 554 int (*get_pcie_lanes)(struct amdgpu_device *adev); 555 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 556 /* get config memsize register */ 557 u32 (*get_config_memsize)(struct amdgpu_device *adev); 558 /* flush hdp write queue */ 559 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 560 /* invalidate hdp read cache */ 561 void (*invalidate_hdp)(struct amdgpu_device *adev, 562 struct amdgpu_ring *ring); 563 /* check if the asic needs a full reset of if soft reset will work */ 564 bool (*need_full_reset)(struct amdgpu_device *adev); 565 /* initialize doorbell layout for specific asic*/ 566 void (*init_doorbell_index)(struct amdgpu_device *adev); 567 /* PCIe bandwidth usage */ 568 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 569 uint64_t *count1); 570 /* do we need to reset the asic at init time (e.g., kexec) */ 571 bool (*need_reset_on_init)(struct amdgpu_device *adev); 572 /* PCIe replay counter */ 573 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 574 /* device supports BACO */ 575 bool (*supports_baco)(struct amdgpu_device *adev); 576 /* pre asic_init quirks */ 577 void (*pre_asic_init)(struct amdgpu_device *adev); 578 /* enter/exit umd stable pstate */ 579 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 580 /* query video codecs */ 581 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 582 const struct amdgpu_video_codecs **codecs); 583 /* encode "> 32bits" smn addressing */ 584 u64 (*encode_ext_smn_addressing)(int ext_id); 585 }; 586 587 /* 588 * IOCTL. 589 */ 590 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 591 struct drm_file *filp); 592 593 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 594 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 595 struct drm_file *filp); 596 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 597 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 598 struct drm_file *filp); 599 600 /* VRAM scratch page for HDP bug, default vram page */ 601 struct amdgpu_mem_scratch { 602 struct amdgpu_bo *robj; 603 volatile uint32_t *ptr; 604 u64 gpu_addr; 605 }; 606 607 /* 608 * CGS 609 */ 610 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 611 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 612 613 /* 614 * Core structure, functions and helpers. 615 */ 616 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 617 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 618 619 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 620 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 621 622 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 623 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 624 625 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 626 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 627 628 struct amdgpu_mmio_remap { 629 u32 reg_offset; 630 resource_size_t bus_addr; 631 }; 632 633 /* Define the HW IP blocks will be used in driver , add more if necessary */ 634 enum amd_hw_ip_block_type { 635 GC_HWIP = 1, 636 HDP_HWIP, 637 SDMA0_HWIP, 638 SDMA1_HWIP, 639 SDMA2_HWIP, 640 SDMA3_HWIP, 641 SDMA4_HWIP, 642 SDMA5_HWIP, 643 SDMA6_HWIP, 644 SDMA7_HWIP, 645 LSDMA_HWIP, 646 MMHUB_HWIP, 647 ATHUB_HWIP, 648 NBIO_HWIP, 649 MP0_HWIP, 650 MP1_HWIP, 651 UVD_HWIP, 652 VCN_HWIP = UVD_HWIP, 653 JPEG_HWIP = VCN_HWIP, 654 VCN1_HWIP, 655 VCE_HWIP, 656 DF_HWIP, 657 DCE_HWIP, 658 OSSSYS_HWIP, 659 SMUIO_HWIP, 660 PWR_HWIP, 661 NBIF_HWIP, 662 THM_HWIP, 663 CLK_HWIP, 664 UMC_HWIP, 665 RSMU_HWIP, 666 XGMI_HWIP, 667 DCI_HWIP, 668 PCIE_HWIP, 669 MAX_HWIP 670 }; 671 672 #define HWIP_MAX_INSTANCE 44 673 674 #define HW_ID_MAX 300 675 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 676 #define IP_VERSION_MAJ(ver) ((ver) >> 16) 677 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF) 678 #define IP_VERSION_REV(ver) ((ver) & 0xFF) 679 680 struct amdgpu_ip_map_info { 681 /* Map of logical to actual dev instances/mask */ 682 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 683 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 684 enum amd_hw_ip_block_type block, 685 int8_t inst); 686 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 687 enum amd_hw_ip_block_type block, 688 uint32_t mask); 689 }; 690 691 struct amd_powerplay { 692 void *pp_handle; 693 const struct amd_pm_funcs *pp_funcs; 694 }; 695 696 struct ip_discovery_top; 697 698 /* polaris10 kickers */ 699 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 700 ((rid == 0xE3) || \ 701 (rid == 0xE4) || \ 702 (rid == 0xE5) || \ 703 (rid == 0xE7) || \ 704 (rid == 0xEF))) || \ 705 ((did == 0x6FDF) && \ 706 ((rid == 0xE7) || \ 707 (rid == 0xEF) || \ 708 (rid == 0xFF)))) 709 710 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 711 ((rid == 0xE1) || \ 712 (rid == 0xF7))) 713 714 /* polaris11 kickers */ 715 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 716 ((rid == 0xE0) || \ 717 (rid == 0xE5))) || \ 718 ((did == 0x67FF) && \ 719 ((rid == 0xCF) || \ 720 (rid == 0xEF) || \ 721 (rid == 0xFF)))) 722 723 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 724 ((rid == 0xE2))) 725 726 /* polaris12 kickers */ 727 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 728 ((rid == 0xC0) || \ 729 (rid == 0xC1) || \ 730 (rid == 0xC3) || \ 731 (rid == 0xC7))) || \ 732 ((did == 0x6981) && \ 733 ((rid == 0x00) || \ 734 (rid == 0x01) || \ 735 (rid == 0x10)))) 736 737 struct amdgpu_mqd_prop { 738 uint64_t mqd_gpu_addr; 739 uint64_t hqd_base_gpu_addr; 740 uint64_t rptr_gpu_addr; 741 uint64_t wptr_gpu_addr; 742 uint32_t queue_size; 743 bool use_doorbell; 744 uint32_t doorbell_index; 745 uint64_t eop_gpu_addr; 746 uint32_t hqd_pipe_priority; 747 uint32_t hqd_queue_priority; 748 bool hqd_active; 749 }; 750 751 struct amdgpu_mqd { 752 unsigned mqd_size; 753 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 754 struct amdgpu_mqd_prop *p); 755 }; 756 757 #define AMDGPU_RESET_MAGIC_NUM 64 758 #define AMDGPU_MAX_DF_PERFMONS 4 759 #define AMDGPU_PRODUCT_NAME_LEN 64 760 struct amdgpu_reset_domain; 761 762 /* 763 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 764 */ 765 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 766 767 struct amdgpu_device { 768 struct device *dev; 769 struct pci_dev *pdev; 770 struct drm_device ddev; 771 772 #ifdef CONFIG_DRM_AMD_ACP 773 struct amdgpu_acp acp; 774 #endif 775 struct amdgpu_hive_info *hive; 776 struct amdgpu_xcp_mgr *xcp_mgr; 777 /* ASIC */ 778 enum amd_asic_type asic_type; 779 uint32_t family; 780 uint32_t rev_id; 781 uint32_t external_rev_id; 782 unsigned long flags; 783 unsigned long apu_flags; 784 int usec_timeout; 785 const struct amdgpu_asic_funcs *asic_funcs; 786 bool shutdown; 787 bool need_swiotlb; 788 bool accel_working; 789 struct notifier_block acpi_nb; 790 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 791 struct debugfs_blob_wrapper debugfs_vbios_blob; 792 struct debugfs_blob_wrapper debugfs_discovery_blob; 793 struct mutex srbm_mutex; 794 /* GRBM index mutex. Protects concurrent access to GRBM index */ 795 struct mutex grbm_idx_mutex; 796 struct dev_pm_domain vga_pm_domain; 797 bool have_disp_power_ref; 798 bool have_atomics_support; 799 800 /* BIOS */ 801 bool is_atom_fw; 802 uint8_t *bios; 803 uint32_t bios_size; 804 uint32_t bios_scratch_reg_offset; 805 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 806 807 /* Register/doorbell mmio */ 808 resource_size_t rmmio_base; 809 resource_size_t rmmio_size; 810 void __iomem *rmmio; 811 /* protects concurrent MM_INDEX/DATA based register access */ 812 spinlock_t mmio_idx_lock; 813 struct amdgpu_mmio_remap rmmio_remap; 814 /* protects concurrent SMC based register access */ 815 spinlock_t smc_idx_lock; 816 amdgpu_rreg_t smc_rreg; 817 amdgpu_wreg_t smc_wreg; 818 /* protects concurrent PCIE register access */ 819 spinlock_t pcie_idx_lock; 820 amdgpu_rreg_t pcie_rreg; 821 amdgpu_wreg_t pcie_wreg; 822 amdgpu_rreg_t pciep_rreg; 823 amdgpu_wreg_t pciep_wreg; 824 amdgpu_rreg_ext_t pcie_rreg_ext; 825 amdgpu_wreg_ext_t pcie_wreg_ext; 826 amdgpu_rreg64_t pcie_rreg64; 827 amdgpu_wreg64_t pcie_wreg64; 828 /* protects concurrent UVD register access */ 829 spinlock_t uvd_ctx_idx_lock; 830 amdgpu_rreg_t uvd_ctx_rreg; 831 amdgpu_wreg_t uvd_ctx_wreg; 832 /* protects concurrent DIDT register access */ 833 spinlock_t didt_idx_lock; 834 amdgpu_rreg_t didt_rreg; 835 amdgpu_wreg_t didt_wreg; 836 /* protects concurrent gc_cac register access */ 837 spinlock_t gc_cac_idx_lock; 838 amdgpu_rreg_t gc_cac_rreg; 839 amdgpu_wreg_t gc_cac_wreg; 840 /* protects concurrent se_cac register access */ 841 spinlock_t se_cac_idx_lock; 842 amdgpu_rreg_t se_cac_rreg; 843 amdgpu_wreg_t se_cac_wreg; 844 /* protects concurrent ENDPOINT (audio) register access */ 845 spinlock_t audio_endpt_idx_lock; 846 amdgpu_block_rreg_t audio_endpt_rreg; 847 amdgpu_block_wreg_t audio_endpt_wreg; 848 struct amdgpu_doorbell doorbell; 849 850 /* clock/pll info */ 851 struct amdgpu_clock clock; 852 853 /* MC */ 854 struct amdgpu_gmc gmc; 855 struct amdgpu_gart gart; 856 dma_addr_t dummy_page_addr; 857 struct amdgpu_vm_manager vm_manager; 858 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 859 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 860 861 /* memory management */ 862 struct amdgpu_mman mman; 863 struct amdgpu_mem_scratch mem_scratch; 864 struct amdgpu_wb wb; 865 atomic64_t num_bytes_moved; 866 atomic64_t num_evictions; 867 atomic64_t num_vram_cpu_page_faults; 868 atomic_t gpu_reset_counter; 869 atomic_t vram_lost_counter; 870 871 /* data for buffer migration throttling */ 872 struct { 873 spinlock_t lock; 874 s64 last_update_us; 875 s64 accum_us; /* accumulated microseconds */ 876 s64 accum_us_vis; /* for visible VRAM */ 877 u32 log2_max_MBps; 878 } mm_stats; 879 880 /* display */ 881 bool enable_virtual_display; 882 struct amdgpu_vkms_output *amdgpu_vkms_output; 883 struct amdgpu_mode_info mode_info; 884 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 885 struct delayed_work hotplug_work; 886 struct amdgpu_irq_src crtc_irq; 887 struct amdgpu_irq_src vline0_irq; 888 struct amdgpu_irq_src vupdate_irq; 889 struct amdgpu_irq_src pageflip_irq; 890 struct amdgpu_irq_src hpd_irq; 891 struct amdgpu_irq_src dmub_trace_irq; 892 struct amdgpu_irq_src dmub_outbox_irq; 893 894 /* rings */ 895 u64 fence_context; 896 unsigned num_rings; 897 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 898 struct dma_fence __rcu *gang_submit; 899 bool ib_pool_ready; 900 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 901 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 902 903 /* interrupts */ 904 struct amdgpu_irq irq; 905 906 /* powerplay */ 907 struct amd_powerplay powerplay; 908 struct amdgpu_pm pm; 909 u64 cg_flags; 910 u32 pg_flags; 911 912 /* nbio */ 913 struct amdgpu_nbio nbio; 914 915 /* hdp */ 916 struct amdgpu_hdp hdp; 917 918 /* smuio */ 919 struct amdgpu_smuio smuio; 920 921 /* mmhub */ 922 struct amdgpu_mmhub mmhub; 923 924 /* gfxhub */ 925 struct amdgpu_gfxhub gfxhub; 926 927 /* gfx */ 928 struct amdgpu_gfx gfx; 929 930 /* sdma */ 931 struct amdgpu_sdma sdma; 932 933 /* lsdma */ 934 struct amdgpu_lsdma lsdma; 935 936 /* uvd */ 937 struct amdgpu_uvd uvd; 938 939 /* vce */ 940 struct amdgpu_vce vce; 941 942 /* vcn */ 943 struct amdgpu_vcn vcn; 944 945 /* jpeg */ 946 struct amdgpu_jpeg jpeg; 947 948 /* firmwares */ 949 struct amdgpu_firmware firmware; 950 951 /* PSP */ 952 struct psp_context psp; 953 954 /* GDS */ 955 struct amdgpu_gds gds; 956 957 /* KFD */ 958 struct amdgpu_kfd_dev kfd; 959 960 /* UMC */ 961 struct amdgpu_umc umc; 962 963 /* display related functionality */ 964 struct amdgpu_display_manager dm; 965 966 /* mes */ 967 bool enable_mes; 968 bool enable_mes_kiq; 969 struct amdgpu_mes mes; 970 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 971 972 /* df */ 973 struct amdgpu_df df; 974 975 /* MCA */ 976 struct amdgpu_mca mca; 977 978 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 979 uint32_t harvest_ip_mask; 980 int num_ip_blocks; 981 struct mutex mn_lock; 982 DECLARE_HASHTABLE(mn_hash, 7); 983 984 /* tracking pinned memory */ 985 atomic64_t vram_pin_size; 986 atomic64_t visible_pin_size; 987 atomic64_t gart_pin_size; 988 989 /* soc15 register offset based on ip, instance and segment */ 990 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 991 struct amdgpu_ip_map_info ip_map; 992 993 /* delayed work_func for deferring clockgating during resume */ 994 struct delayed_work delayed_init_work; 995 996 struct amdgpu_virt virt; 997 998 /* link all shadow bo */ 999 struct list_head shadow_list; 1000 struct mutex shadow_list_lock; 1001 1002 /* record hw reset is performed */ 1003 bool has_hw_reset; 1004 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1005 1006 /* s3/s4 mask */ 1007 bool in_suspend; 1008 bool in_s3; 1009 bool in_s4; 1010 bool in_s0ix; 1011 1012 enum pp_mp1_state mp1_state; 1013 struct amdgpu_doorbell_index doorbell_index; 1014 1015 struct mutex notifier_lock; 1016 1017 int asic_reset_res; 1018 struct work_struct xgmi_reset_work; 1019 struct list_head reset_list; 1020 1021 long gfx_timeout; 1022 long sdma_timeout; 1023 long video_timeout; 1024 long compute_timeout; 1025 1026 uint64_t unique_id; 1027 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1028 1029 /* enable runtime pm on the device */ 1030 bool in_runpm; 1031 bool has_pr3; 1032 1033 bool ucode_sysfs_en; 1034 bool psp_sysfs_en; 1035 1036 /* Chip product information */ 1037 char product_number[20]; 1038 char product_name[AMDGPU_PRODUCT_NAME_LEN]; 1039 char serial[20]; 1040 1041 atomic_t throttling_logging_enabled; 1042 struct ratelimit_state throttling_logging_rs; 1043 uint32_t ras_hw_enabled; 1044 uint32_t ras_enabled; 1045 1046 bool no_hw_access; 1047 struct pci_saved_state *pci_state; 1048 pci_channel_state_t pci_channel_state; 1049 1050 /* Track auto wait count on s_barrier settings */ 1051 bool barrier_has_auto_waitcnt; 1052 1053 struct amdgpu_reset_control *reset_cntl; 1054 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1055 1056 bool ram_is_direct_mapped; 1057 1058 struct list_head ras_list; 1059 1060 struct ip_discovery_top *ip_top; 1061 1062 struct amdgpu_reset_domain *reset_domain; 1063 1064 struct mutex benchmark_mutex; 1065 1066 /* reset dump register */ 1067 uint32_t *reset_dump_reg_list; 1068 uint32_t *reset_dump_reg_value; 1069 int num_regs; 1070 #ifdef CONFIG_DEV_COREDUMP 1071 struct amdgpu_task_info reset_task_info; 1072 bool reset_vram_lost; 1073 struct timespec64 reset_time; 1074 #endif 1075 1076 bool scpm_enabled; 1077 uint32_t scpm_status; 1078 1079 struct work_struct reset_work; 1080 1081 bool job_hang; 1082 bool dc_enabled; 1083 /* Mask of active clusters */ 1084 uint32_t aid_mask; 1085 }; 1086 1087 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1088 { 1089 return container_of(ddev, struct amdgpu_device, ddev); 1090 } 1091 1092 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1093 { 1094 return &adev->ddev; 1095 } 1096 1097 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1098 { 1099 return container_of(bdev, struct amdgpu_device, mman.bdev); 1100 } 1101 1102 int amdgpu_device_init(struct amdgpu_device *adev, 1103 uint32_t flags); 1104 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1105 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1106 1107 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1108 1109 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1110 void *buf, size_t size, bool write); 1111 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1112 void *buf, size_t size, bool write); 1113 1114 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1115 void *buf, size_t size, bool write); 1116 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1117 uint32_t inst, uint32_t reg_addr, char reg_name[], 1118 uint32_t expected_value, uint32_t mask); 1119 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1120 uint32_t reg, uint32_t acc_flags); 1121 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1122 u64 reg_addr); 1123 void amdgpu_device_wreg(struct amdgpu_device *adev, 1124 uint32_t reg, uint32_t v, 1125 uint32_t acc_flags); 1126 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1127 u64 reg_addr, u32 reg_data); 1128 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1129 uint32_t reg, uint32_t v); 1130 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1131 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1132 1133 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1134 u32 reg_addr); 1135 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1136 u32 reg_addr); 1137 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1138 u32 reg_addr, u32 reg_data); 1139 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1140 u32 reg_addr, u64 reg_data); 1141 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1142 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1143 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1144 1145 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1146 1147 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1148 struct amdgpu_reset_context *reset_context); 1149 1150 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1151 struct amdgpu_reset_context *reset_context); 1152 1153 int emu_soc_asic_init(struct amdgpu_device *adev); 1154 1155 /* 1156 * Registers read & write functions. 1157 */ 1158 #define AMDGPU_REGS_NO_KIQ (1<<1) 1159 #define AMDGPU_REGS_RLC (1<<2) 1160 1161 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1162 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1163 1164 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1165 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1166 1167 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1168 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1169 1170 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1171 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1172 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1173 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1174 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1175 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1176 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1177 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1178 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1179 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1180 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1181 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1182 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1183 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1184 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1185 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1186 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1187 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1188 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1189 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1190 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1191 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1192 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1193 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1194 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1195 #define WREG32_P(reg, val, mask) \ 1196 do { \ 1197 uint32_t tmp_ = RREG32(reg); \ 1198 tmp_ &= (mask); \ 1199 tmp_ |= ((val) & ~(mask)); \ 1200 WREG32(reg, tmp_); \ 1201 } while (0) 1202 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1203 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1204 #define WREG32_PLL_P(reg, val, mask) \ 1205 do { \ 1206 uint32_t tmp_ = RREG32_PLL(reg); \ 1207 tmp_ &= (mask); \ 1208 tmp_ |= ((val) & ~(mask)); \ 1209 WREG32_PLL(reg, tmp_); \ 1210 } while (0) 1211 1212 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1213 do { \ 1214 u32 tmp = RREG32_SMC(_Reg); \ 1215 tmp &= (_Mask); \ 1216 tmp |= ((_Val) & ~(_Mask)); \ 1217 WREG32_SMC(_Reg, tmp); \ 1218 } while (0) 1219 1220 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1221 1222 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1223 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1224 1225 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1226 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1227 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1228 1229 #define REG_GET_FIELD(value, reg, field) \ 1230 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1231 1232 #define WREG32_FIELD(reg, field, val) \ 1233 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1234 1235 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1236 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1237 1238 /* 1239 * BIOS helpers. 1240 */ 1241 #define RBIOS8(i) (adev->bios[i]) 1242 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1243 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1244 1245 /* 1246 * ASICs macro. 1247 */ 1248 #define amdgpu_asic_set_vga_state(adev, state) \ 1249 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1250 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1251 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1252 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1253 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1254 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1255 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1256 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1257 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1258 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1259 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1260 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1261 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1262 #define amdgpu_asic_flush_hdp(adev, r) \ 1263 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1264 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1265 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1266 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1267 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1268 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1269 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1270 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1271 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1272 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1273 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1274 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1275 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1276 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1277 1278 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1279 1280 #define for_each_inst(i, inst_mask) \ 1281 for (i = ffs(inst_mask) - 1; inst_mask; \ 1282 inst_mask &= ~(1U << i), i = ffs(inst_mask) - 1) 1283 1284 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 1285 1286 /* Common functions */ 1287 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1288 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1289 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1290 struct amdgpu_job *job, 1291 struct amdgpu_reset_context *reset_context); 1292 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1293 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1294 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1295 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1296 bool amdgpu_device_aspm_support_quirk(void); 1297 1298 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1299 u64 num_vis_bytes); 1300 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1301 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1302 const u32 *registers, 1303 const u32 array_size); 1304 1305 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1306 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1307 bool amdgpu_device_supports_px(struct drm_device *dev); 1308 bool amdgpu_device_supports_boco(struct drm_device *dev); 1309 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1310 bool amdgpu_device_supports_baco(struct drm_device *dev); 1311 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1312 struct amdgpu_device *peer_adev); 1313 int amdgpu_device_baco_enter(struct drm_device *dev); 1314 int amdgpu_device_baco_exit(struct drm_device *dev); 1315 1316 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1317 struct amdgpu_ring *ring); 1318 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1319 struct amdgpu_ring *ring); 1320 1321 void amdgpu_device_halt(struct amdgpu_device *adev); 1322 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1323 u32 reg); 1324 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1325 u32 reg, u32 v); 1326 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1327 struct dma_fence *gang); 1328 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1329 1330 /* atpx handler */ 1331 #if defined(CONFIG_VGA_SWITCHEROO) 1332 void amdgpu_register_atpx_handler(void); 1333 void amdgpu_unregister_atpx_handler(void); 1334 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1335 bool amdgpu_is_atpx_hybrid(void); 1336 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1337 bool amdgpu_has_atpx(void); 1338 #else 1339 static inline void amdgpu_register_atpx_handler(void) {} 1340 static inline void amdgpu_unregister_atpx_handler(void) {} 1341 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1342 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1343 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1344 static inline bool amdgpu_has_atpx(void) { return false; } 1345 #endif 1346 1347 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1348 void *amdgpu_atpx_get_dhandle(void); 1349 #else 1350 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1351 #endif 1352 1353 /* 1354 * KMS 1355 */ 1356 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1357 extern const int amdgpu_max_kms_ioctl; 1358 1359 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1360 void amdgpu_driver_unload_kms(struct drm_device *dev); 1361 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1362 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1363 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1364 struct drm_file *file_priv); 1365 void amdgpu_driver_release_kms(struct drm_device *dev); 1366 1367 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1368 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1369 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1370 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1371 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1372 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1373 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1374 struct drm_file *filp); 1375 1376 /* 1377 * functions used by amdgpu_encoder.c 1378 */ 1379 struct amdgpu_afmt_acr { 1380 u32 clock; 1381 1382 int n_32khz; 1383 int cts_32khz; 1384 1385 int n_44_1khz; 1386 int cts_44_1khz; 1387 1388 int n_48khz; 1389 int cts_48khz; 1390 1391 }; 1392 1393 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1394 1395 /* amdgpu_acpi.c */ 1396 1397 struct amdgpu_numa_info { 1398 uint64_t size; 1399 int pxm; 1400 int nid; 1401 }; 1402 1403 /* ATCS Device/Driver State */ 1404 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1405 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1406 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1407 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1408 1409 #if defined(CONFIG_ACPI) 1410 int amdgpu_acpi_init(struct amdgpu_device *adev); 1411 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1412 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1413 bool amdgpu_acpi_is_power_shift_control_supported(void); 1414 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1415 u8 perf_req, bool advertise); 1416 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1417 u8 dev_state, bool drv_state); 1418 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1419 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1420 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1421 u64 *tmr_size); 1422 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1423 struct amdgpu_numa_info *numa_info); 1424 1425 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1426 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1427 void amdgpu_acpi_detect(void); 1428 void amdgpu_acpi_release(void); 1429 #else 1430 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1431 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1432 u64 *tmr_offset, u64 *tmr_size) 1433 { 1434 return -EINVAL; 1435 } 1436 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1437 int xcc_id, 1438 struct amdgpu_numa_info *numa_info) 1439 { 1440 return -EINVAL; 1441 } 1442 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1443 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1444 static inline void amdgpu_acpi_detect(void) { } 1445 static inline void amdgpu_acpi_release(void) { } 1446 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1447 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1448 u8 dev_state, bool drv_state) { return 0; } 1449 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1450 enum amdgpu_ss ss_state) { return 0; } 1451 #endif 1452 1453 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1454 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1455 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1456 #else 1457 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1458 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1459 #endif 1460 1461 #if defined(CONFIG_DRM_AMD_DC) 1462 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1463 #else 1464 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1465 #endif 1466 1467 1468 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1469 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1470 1471 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1472 pci_channel_state_t state); 1473 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1474 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1475 void amdgpu_pci_resume(struct pci_dev *pdev); 1476 1477 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1478 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1479 1480 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1481 1482 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1483 enum amd_clockgating_state state); 1484 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1485 enum amd_powergating_state state); 1486 1487 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1488 { 1489 return amdgpu_gpu_recovery != 0 && 1490 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1491 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1492 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1493 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1494 } 1495 1496 #include "amdgpu_object.h" 1497 1498 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1499 { 1500 return adev->gmc.tmz_enabled; 1501 } 1502 1503 int amdgpu_in_reset(struct amdgpu_device *adev); 1504 1505 #endif 1506