1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include "amdgpu_ctx.h" 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/rbtree.h> 38 #include <linux/hashtable.h> 39 #include <linux/dma-fence.h> 40 41 #include <drm/ttm/ttm_bo_api.h> 42 #include <drm/ttm/ttm_bo_driver.h> 43 #include <drm/ttm/ttm_placement.h> 44 #include <drm/ttm/ttm_module.h> 45 #include <drm/ttm/ttm_execbuf_util.h> 46 47 #include <drm/drmP.h> 48 #include <drm/drm_gem.h> 49 #include <drm/amdgpu_drm.h> 50 #include <drm/gpu_scheduler.h> 51 52 #include <kgd_kfd_interface.h> 53 #include "dm_pp_interface.h" 54 #include "kgd_pp_interface.h" 55 56 #include "amd_shared.h" 57 #include "amdgpu_mode.h" 58 #include "amdgpu_ih.h" 59 #include "amdgpu_irq.h" 60 #include "amdgpu_ucode.h" 61 #include "amdgpu_ttm.h" 62 #include "amdgpu_psp.h" 63 #include "amdgpu_gds.h" 64 #include "amdgpu_sync.h" 65 #include "amdgpu_ring.h" 66 #include "amdgpu_vm.h" 67 #include "amdgpu_dpm.h" 68 #include "amdgpu_acp.h" 69 #include "amdgpu_uvd.h" 70 #include "amdgpu_vce.h" 71 #include "amdgpu_vcn.h" 72 #include "amdgpu_mn.h" 73 #include "amdgpu_gmc.h" 74 #include "amdgpu_gfx.h" 75 #include "amdgpu_sdma.h" 76 #include "amdgpu_dm.h" 77 #include "amdgpu_virt.h" 78 #include "amdgpu_csa.h" 79 #include "amdgpu_gart.h" 80 #include "amdgpu_debugfs.h" 81 #include "amdgpu_job.h" 82 #include "amdgpu_bo_list.h" 83 #include "amdgpu_gem.h" 84 85 #define MAX_GPU_INSTANCE 16 86 87 struct amdgpu_gpu_instance 88 { 89 struct amdgpu_device *adev; 90 int mgpu_fan_enabled; 91 }; 92 93 struct amdgpu_mgpu_info 94 { 95 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 96 struct mutex mutex; 97 uint32_t num_gpu; 98 uint32_t num_dgpu; 99 uint32_t num_apu; 100 }; 101 102 /* 103 * Modules parameters. 104 */ 105 extern int amdgpu_modeset; 106 extern int amdgpu_vram_limit; 107 extern int amdgpu_vis_vram_limit; 108 extern int amdgpu_gart_size; 109 extern int amdgpu_gtt_size; 110 extern int amdgpu_moverate; 111 extern int amdgpu_benchmarking; 112 extern int amdgpu_testing; 113 extern int amdgpu_audio; 114 extern int amdgpu_disp_priority; 115 extern int amdgpu_hw_i2c; 116 extern int amdgpu_pcie_gen2; 117 extern int amdgpu_msi; 118 extern int amdgpu_lockup_timeout; 119 extern int amdgpu_dpm; 120 extern int amdgpu_fw_load_type; 121 extern int amdgpu_aspm; 122 extern int amdgpu_runtime_pm; 123 extern uint amdgpu_ip_block_mask; 124 extern int amdgpu_bapm; 125 extern int amdgpu_deep_color; 126 extern int amdgpu_vm_size; 127 extern int amdgpu_vm_block_size; 128 extern int amdgpu_vm_fragment_size; 129 extern int amdgpu_vm_fault_stop; 130 extern int amdgpu_vm_debug; 131 extern int amdgpu_vm_update_mode; 132 extern int amdgpu_dc; 133 extern int amdgpu_sched_jobs; 134 extern int amdgpu_sched_hw_submission; 135 extern uint amdgpu_pcie_gen_cap; 136 extern uint amdgpu_pcie_lane_cap; 137 extern uint amdgpu_cg_mask; 138 extern uint amdgpu_pg_mask; 139 extern uint amdgpu_sdma_phase_quantum; 140 extern char *amdgpu_disable_cu; 141 extern char *amdgpu_virtual_display; 142 extern uint amdgpu_pp_feature_mask; 143 extern int amdgpu_vram_page_split; 144 extern int amdgpu_ngg; 145 extern int amdgpu_prim_buf_per_se; 146 extern int amdgpu_pos_buf_per_se; 147 extern int amdgpu_cntl_sb_buf_per_se; 148 extern int amdgpu_param_buf_per_se; 149 extern int amdgpu_job_hang_limit; 150 extern int amdgpu_lbpw; 151 extern int amdgpu_compute_multipipe; 152 extern int amdgpu_gpu_recovery; 153 extern int amdgpu_emu_mode; 154 extern uint amdgpu_smu_memory_pool_size; 155 extern uint amdgpu_dc_feature_mask; 156 extern struct amdgpu_mgpu_info mgpu_info; 157 158 #ifdef CONFIG_DRM_AMDGPU_SI 159 extern int amdgpu_si_support; 160 #endif 161 #ifdef CONFIG_DRM_AMDGPU_CIK 162 extern int amdgpu_cik_support; 163 #endif 164 165 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 166 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 167 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 168 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 169 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 170 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 171 #define AMDGPU_IB_POOL_SIZE 16 172 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 173 #define AMDGPUFB_CONN_LIMIT 4 174 #define AMDGPU_BIOS_NUM_SCRATCH 16 175 176 /* hard reset data */ 177 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 178 179 /* reset flags */ 180 #define AMDGPU_RESET_GFX (1 << 0) 181 #define AMDGPU_RESET_COMPUTE (1 << 1) 182 #define AMDGPU_RESET_DMA (1 << 2) 183 #define AMDGPU_RESET_CP (1 << 3) 184 #define AMDGPU_RESET_GRBM (1 << 4) 185 #define AMDGPU_RESET_DMA1 (1 << 5) 186 #define AMDGPU_RESET_RLC (1 << 6) 187 #define AMDGPU_RESET_SEM (1 << 7) 188 #define AMDGPU_RESET_IH (1 << 8) 189 #define AMDGPU_RESET_VMC (1 << 9) 190 #define AMDGPU_RESET_MC (1 << 10) 191 #define AMDGPU_RESET_DISPLAY (1 << 11) 192 #define AMDGPU_RESET_UVD (1 << 12) 193 #define AMDGPU_RESET_VCE (1 << 13) 194 #define AMDGPU_RESET_VCE1 (1 << 14) 195 196 /* max cursor sizes (in pixels) */ 197 #define CIK_CURSOR_WIDTH 128 198 #define CIK_CURSOR_HEIGHT 128 199 200 struct amdgpu_device; 201 struct amdgpu_ib; 202 struct amdgpu_cs_parser; 203 struct amdgpu_job; 204 struct amdgpu_irq_src; 205 struct amdgpu_fpriv; 206 struct amdgpu_bo_va_mapping; 207 struct amdgpu_atif; 208 209 enum amdgpu_cp_irq { 210 AMDGPU_CP_IRQ_GFX_EOP = 0, 211 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 212 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 213 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 214 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 215 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 216 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 217 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 218 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 219 220 AMDGPU_CP_IRQ_LAST 221 }; 222 223 enum amdgpu_thermal_irq { 224 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 225 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 226 227 AMDGPU_THERMAL_IRQ_LAST 228 }; 229 230 enum amdgpu_kiq_irq { 231 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 232 AMDGPU_CP_KIQ_IRQ_LAST 233 }; 234 235 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 236 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 237 #define MAX_KIQ_REG_TRY 20 238 239 int amdgpu_device_ip_set_clockgating_state(void *dev, 240 enum amd_ip_block_type block_type, 241 enum amd_clockgating_state state); 242 int amdgpu_device_ip_set_powergating_state(void *dev, 243 enum amd_ip_block_type block_type, 244 enum amd_powergating_state state); 245 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 246 u32 *flags); 247 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 248 enum amd_ip_block_type block_type); 249 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 250 enum amd_ip_block_type block_type); 251 252 #define AMDGPU_MAX_IP_NUM 16 253 254 struct amdgpu_ip_block_status { 255 bool valid; 256 bool sw; 257 bool hw; 258 bool late_initialized; 259 bool hang; 260 }; 261 262 struct amdgpu_ip_block_version { 263 const enum amd_ip_block_type type; 264 const u32 major; 265 const u32 minor; 266 const u32 rev; 267 const struct amd_ip_funcs *funcs; 268 }; 269 270 struct amdgpu_ip_block { 271 struct amdgpu_ip_block_status status; 272 const struct amdgpu_ip_block_version *version; 273 }; 274 275 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 276 enum amd_ip_block_type type, 277 u32 major, u32 minor); 278 279 struct amdgpu_ip_block * 280 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 281 enum amd_ip_block_type type); 282 283 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 284 const struct amdgpu_ip_block_version *ip_block_version); 285 286 /* 287 * BIOS. 288 */ 289 bool amdgpu_get_bios(struct amdgpu_device *adev); 290 bool amdgpu_read_bios(struct amdgpu_device *adev); 291 292 /* 293 * Clocks 294 */ 295 296 #define AMDGPU_MAX_PPLL 3 297 298 struct amdgpu_clock { 299 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 300 struct amdgpu_pll spll; 301 struct amdgpu_pll mpll; 302 /* 10 Khz units */ 303 uint32_t default_mclk; 304 uint32_t default_sclk; 305 uint32_t default_dispclk; 306 uint32_t current_dispclk; 307 uint32_t dp_extclk; 308 uint32_t max_pixel_clock; 309 }; 310 311 /* sub-allocation manager, it has to be protected by another lock. 312 * By conception this is an helper for other part of the driver 313 * like the indirect buffer or semaphore, which both have their 314 * locking. 315 * 316 * Principe is simple, we keep a list of sub allocation in offset 317 * order (first entry has offset == 0, last entry has the highest 318 * offset). 319 * 320 * When allocating new object we first check if there is room at 321 * the end total_size - (last_object_offset + last_object_size) >= 322 * alloc_size. If so we allocate new object there. 323 * 324 * When there is not enough room at the end, we start waiting for 325 * each sub object until we reach object_offset+object_size >= 326 * alloc_size, this object then become the sub object we return. 327 * 328 * Alignment can't be bigger than page size. 329 * 330 * Hole are not considered for allocation to keep things simple. 331 * Assumption is that there won't be hole (all object on same 332 * alignment). 333 */ 334 335 #define AMDGPU_SA_NUM_FENCE_LISTS 32 336 337 struct amdgpu_sa_manager { 338 wait_queue_head_t wq; 339 struct amdgpu_bo *bo; 340 struct list_head *hole; 341 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 342 struct list_head olist; 343 unsigned size; 344 uint64_t gpu_addr; 345 void *cpu_ptr; 346 uint32_t domain; 347 uint32_t align; 348 }; 349 350 /* sub-allocation buffer */ 351 struct amdgpu_sa_bo { 352 struct list_head olist; 353 struct list_head flist; 354 struct amdgpu_sa_manager *manager; 355 unsigned soffset; 356 unsigned eoffset; 357 struct dma_fence *fence; 358 }; 359 360 int amdgpu_fence_slab_init(void); 361 void amdgpu_fence_slab_fini(void); 362 363 /* 364 * GPU doorbell structures, functions & helpers 365 */ 366 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 367 { 368 AMDGPU_DOORBELL_KIQ = 0x000, 369 AMDGPU_DOORBELL_HIQ = 0x001, 370 AMDGPU_DOORBELL_DIQ = 0x002, 371 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 372 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 373 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 374 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 375 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 376 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 377 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 378 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 379 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 380 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 381 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 382 AMDGPU_DOORBELL_IH = 0x1E8, 383 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 384 AMDGPU_DOORBELL_INVALID = 0xFFFF 385 } AMDGPU_DOORBELL_ASSIGNMENT; 386 387 struct amdgpu_doorbell { 388 /* doorbell mmio */ 389 resource_size_t base; 390 resource_size_t size; 391 u32 __iomem *ptr; 392 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 393 }; 394 395 /* 396 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 397 */ 398 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 399 { 400 /* 401 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 402 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 403 * Compute related doorbells are allocated from 0x00 to 0x8a 404 */ 405 406 407 /* kernel scheduling */ 408 AMDGPU_DOORBELL64_KIQ = 0x00, 409 410 /* HSA interface queue and debug queue */ 411 AMDGPU_DOORBELL64_HIQ = 0x01, 412 AMDGPU_DOORBELL64_DIQ = 0x02, 413 414 /* Compute engines */ 415 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 416 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 417 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 418 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 419 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 420 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 421 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 422 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 423 424 /* User queue doorbell range (128 doorbells) */ 425 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 426 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 427 428 /* Graphics engine */ 429 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 430 431 /* 432 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf 433 * Graphics voltage island aperture 1 434 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive 435 */ 436 437 /* sDMA engines reserved from 0xe0 -0xef */ 438 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xE0, 439 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xE1, 440 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xE8, 441 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xE9, 442 443 /* For vega10 sriov, the sdma doorbell must be fixed as follow 444 * to keep the same setting with host driver, or it will 445 * happen conflicts 446 */ 447 AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 = 0xF0, 448 AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 449 AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 = 0xF2, 450 AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 451 452 /* Interrupt handler */ 453 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 454 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 455 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 456 457 /* VCN engine use 32 bits doorbell */ 458 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 459 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 460 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 461 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 462 463 /* overlap the doorbell assignment with VCN as they are mutually exclusive 464 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 465 */ 466 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 467 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 468 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 469 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 470 471 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 472 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 473 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 474 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 475 476 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 477 AMDGPU_DOORBELL64_INVALID = 0xFFFF 478 } AMDGPU_DOORBELL64_ASSIGNMENT; 479 480 /* 481 * IRQS. 482 */ 483 484 struct amdgpu_flip_work { 485 struct delayed_work flip_work; 486 struct work_struct unpin_work; 487 struct amdgpu_device *adev; 488 int crtc_id; 489 u32 target_vblank; 490 uint64_t base; 491 struct drm_pending_vblank_event *event; 492 struct amdgpu_bo *old_abo; 493 struct dma_fence *excl; 494 unsigned shared_count; 495 struct dma_fence **shared; 496 struct dma_fence_cb cb; 497 bool async; 498 }; 499 500 501 /* 502 * CP & rings. 503 */ 504 505 struct amdgpu_ib { 506 struct amdgpu_sa_bo *sa_bo; 507 uint32_t length_dw; 508 uint64_t gpu_addr; 509 uint32_t *ptr; 510 uint32_t flags; 511 }; 512 513 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 514 515 /* 516 * file private structure 517 */ 518 519 struct amdgpu_fpriv { 520 struct amdgpu_vm vm; 521 struct amdgpu_bo_va *prt_va; 522 struct amdgpu_bo_va *csa_va; 523 struct mutex bo_list_lock; 524 struct idr bo_list_handles; 525 struct amdgpu_ctx_mgr ctx_mgr; 526 }; 527 528 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 529 unsigned size, struct amdgpu_ib *ib); 530 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 531 struct dma_fence *f); 532 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 533 struct amdgpu_ib *ibs, struct amdgpu_job *job, 534 struct dma_fence **f); 535 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 536 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 537 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 538 539 /* 540 * CS. 541 */ 542 struct amdgpu_cs_chunk { 543 uint32_t chunk_id; 544 uint32_t length_dw; 545 void *kdata; 546 }; 547 548 struct amdgpu_cs_parser { 549 struct amdgpu_device *adev; 550 struct drm_file *filp; 551 struct amdgpu_ctx *ctx; 552 553 /* chunks */ 554 unsigned nchunks; 555 struct amdgpu_cs_chunk *chunks; 556 557 /* scheduler job object */ 558 struct amdgpu_job *job; 559 struct drm_sched_entity *entity; 560 561 /* buffer objects */ 562 struct ww_acquire_ctx ticket; 563 struct amdgpu_bo_list *bo_list; 564 struct amdgpu_mn *mn; 565 struct amdgpu_bo_list_entry vm_pd; 566 struct list_head validated; 567 struct dma_fence *fence; 568 uint64_t bytes_moved_threshold; 569 uint64_t bytes_moved_vis_threshold; 570 uint64_t bytes_moved; 571 uint64_t bytes_moved_vis; 572 struct amdgpu_bo_list_entry *evictable; 573 574 /* user fence */ 575 struct amdgpu_bo_list_entry uf_entry; 576 577 unsigned num_post_dep_syncobjs; 578 struct drm_syncobj **post_dep_syncobjs; 579 }; 580 581 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 582 uint32_t ib_idx, int idx) 583 { 584 return p->job->ibs[ib_idx].ptr[idx]; 585 } 586 587 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 588 uint32_t ib_idx, int idx, 589 uint32_t value) 590 { 591 p->job->ibs[ib_idx].ptr[idx] = value; 592 } 593 594 /* 595 * Writeback 596 */ 597 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 598 599 struct amdgpu_wb { 600 struct amdgpu_bo *wb_obj; 601 volatile uint32_t *wb; 602 uint64_t gpu_addr; 603 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 604 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 605 }; 606 607 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 608 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 609 610 /* 611 * Benchmarking 612 */ 613 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 614 615 616 /* 617 * Testing 618 */ 619 void amdgpu_test_moves(struct amdgpu_device *adev); 620 621 /* 622 * ASIC specific register table accessible by UMD 623 */ 624 struct amdgpu_allowed_register_entry { 625 uint32_t reg_offset; 626 bool grbm_indexed; 627 }; 628 629 /* 630 * ASIC specific functions. 631 */ 632 struct amdgpu_asic_funcs { 633 bool (*read_disabled_bios)(struct amdgpu_device *adev); 634 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 635 u8 *bios, u32 length_bytes); 636 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 637 u32 sh_num, u32 reg_offset, u32 *value); 638 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 639 int (*reset)(struct amdgpu_device *adev); 640 /* get the reference clock */ 641 u32 (*get_xclk)(struct amdgpu_device *adev); 642 /* MM block clocks */ 643 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 644 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 645 /* static power management */ 646 int (*get_pcie_lanes)(struct amdgpu_device *adev); 647 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 648 /* get config memsize register */ 649 u32 (*get_config_memsize)(struct amdgpu_device *adev); 650 /* flush hdp write queue */ 651 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 652 /* invalidate hdp read cache */ 653 void (*invalidate_hdp)(struct amdgpu_device *adev, 654 struct amdgpu_ring *ring); 655 /* check if the asic needs a full reset of if soft reset will work */ 656 bool (*need_full_reset)(struct amdgpu_device *adev); 657 }; 658 659 /* 660 * IOCTL. 661 */ 662 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 663 struct drm_file *filp); 664 665 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 666 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 667 struct drm_file *filp); 668 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 669 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 670 struct drm_file *filp); 671 672 /* VRAM scratch page for HDP bug, default vram page */ 673 struct amdgpu_vram_scratch { 674 struct amdgpu_bo *robj; 675 volatile uint32_t *ptr; 676 u64 gpu_addr; 677 }; 678 679 /* 680 * ACPI 681 */ 682 struct amdgpu_atcs_functions { 683 bool get_ext_state; 684 bool pcie_perf_req; 685 bool pcie_dev_rdy; 686 bool pcie_bus_width; 687 }; 688 689 struct amdgpu_atcs { 690 struct amdgpu_atcs_functions functions; 691 }; 692 693 /* 694 * Firmware VRAM reservation 695 */ 696 struct amdgpu_fw_vram_usage { 697 u64 start_offset; 698 u64 size; 699 struct amdgpu_bo *reserved_bo; 700 void *va; 701 }; 702 703 /* 704 * CGS 705 */ 706 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 707 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 708 709 /* 710 * Core structure, functions and helpers. 711 */ 712 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 713 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 714 715 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 716 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 717 718 719 /* 720 * amdgpu nbio functions 721 * 722 */ 723 struct nbio_hdp_flush_reg { 724 u32 ref_and_mask_cp0; 725 u32 ref_and_mask_cp1; 726 u32 ref_and_mask_cp2; 727 u32 ref_and_mask_cp3; 728 u32 ref_and_mask_cp4; 729 u32 ref_and_mask_cp5; 730 u32 ref_and_mask_cp6; 731 u32 ref_and_mask_cp7; 732 u32 ref_and_mask_cp8; 733 u32 ref_and_mask_cp9; 734 u32 ref_and_mask_sdma0; 735 u32 ref_and_mask_sdma1; 736 }; 737 738 struct amdgpu_nbio_funcs { 739 const struct nbio_hdp_flush_reg *hdp_flush_reg; 740 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 741 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 742 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 743 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 744 u32 (*get_rev_id)(struct amdgpu_device *adev); 745 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 746 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 747 u32 (*get_memsize)(struct amdgpu_device *adev); 748 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 749 bool use_doorbell, int doorbell_index); 750 void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 751 bool enable); 752 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 753 bool enable); 754 void (*ih_doorbell_range)(struct amdgpu_device *adev, 755 bool use_doorbell, int doorbell_index); 756 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 757 bool enable); 758 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 759 bool enable); 760 void (*get_clockgating_state)(struct amdgpu_device *adev, 761 u32 *flags); 762 void (*ih_control)(struct amdgpu_device *adev); 763 void (*init_registers)(struct amdgpu_device *adev); 764 void (*detect_hw_virt)(struct amdgpu_device *adev); 765 }; 766 767 struct amdgpu_df_funcs { 768 void (*init)(struct amdgpu_device *adev); 769 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 770 bool enable); 771 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 772 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 773 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 774 bool enable); 775 void (*get_clockgating_state)(struct amdgpu_device *adev, 776 u32 *flags); 777 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 778 bool enable); 779 }; 780 /* Define the HW IP blocks will be used in driver , add more if necessary */ 781 enum amd_hw_ip_block_type { 782 GC_HWIP = 1, 783 HDP_HWIP, 784 SDMA0_HWIP, 785 SDMA1_HWIP, 786 MMHUB_HWIP, 787 ATHUB_HWIP, 788 NBIO_HWIP, 789 MP0_HWIP, 790 MP1_HWIP, 791 UVD_HWIP, 792 VCN_HWIP = UVD_HWIP, 793 VCE_HWIP, 794 DF_HWIP, 795 DCE_HWIP, 796 OSSSYS_HWIP, 797 SMUIO_HWIP, 798 PWR_HWIP, 799 NBIF_HWIP, 800 THM_HWIP, 801 CLK_HWIP, 802 MAX_HWIP 803 }; 804 805 #define HWIP_MAX_INSTANCE 6 806 807 struct amd_powerplay { 808 void *pp_handle; 809 const struct amd_pm_funcs *pp_funcs; 810 uint32_t pp_feature; 811 }; 812 813 #define AMDGPU_RESET_MAGIC_NUM 64 814 struct amdgpu_device { 815 struct device *dev; 816 struct drm_device *ddev; 817 struct pci_dev *pdev; 818 819 #ifdef CONFIG_DRM_AMD_ACP 820 struct amdgpu_acp acp; 821 #endif 822 823 /* ASIC */ 824 enum amd_asic_type asic_type; 825 uint32_t family; 826 uint32_t rev_id; 827 uint32_t external_rev_id; 828 unsigned long flags; 829 int usec_timeout; 830 const struct amdgpu_asic_funcs *asic_funcs; 831 bool shutdown; 832 bool need_dma32; 833 bool need_swiotlb; 834 bool accel_working; 835 struct notifier_block acpi_nb; 836 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 837 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 838 unsigned debugfs_count; 839 #if defined(CONFIG_DEBUG_FS) 840 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 841 #endif 842 struct amdgpu_atif *atif; 843 struct amdgpu_atcs atcs; 844 struct mutex srbm_mutex; 845 /* GRBM index mutex. Protects concurrent access to GRBM index */ 846 struct mutex grbm_idx_mutex; 847 struct dev_pm_domain vga_pm_domain; 848 bool have_disp_power_ref; 849 850 /* BIOS */ 851 bool is_atom_fw; 852 uint8_t *bios; 853 uint32_t bios_size; 854 struct amdgpu_bo *stolen_vga_memory; 855 uint32_t bios_scratch_reg_offset; 856 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 857 858 /* Register/doorbell mmio */ 859 resource_size_t rmmio_base; 860 resource_size_t rmmio_size; 861 void __iomem *rmmio; 862 /* protects concurrent MM_INDEX/DATA based register access */ 863 spinlock_t mmio_idx_lock; 864 /* protects concurrent SMC based register access */ 865 spinlock_t smc_idx_lock; 866 amdgpu_rreg_t smc_rreg; 867 amdgpu_wreg_t smc_wreg; 868 /* protects concurrent PCIE register access */ 869 spinlock_t pcie_idx_lock; 870 amdgpu_rreg_t pcie_rreg; 871 amdgpu_wreg_t pcie_wreg; 872 amdgpu_rreg_t pciep_rreg; 873 amdgpu_wreg_t pciep_wreg; 874 /* protects concurrent UVD register access */ 875 spinlock_t uvd_ctx_idx_lock; 876 amdgpu_rreg_t uvd_ctx_rreg; 877 amdgpu_wreg_t uvd_ctx_wreg; 878 /* protects concurrent DIDT register access */ 879 spinlock_t didt_idx_lock; 880 amdgpu_rreg_t didt_rreg; 881 amdgpu_wreg_t didt_wreg; 882 /* protects concurrent gc_cac register access */ 883 spinlock_t gc_cac_idx_lock; 884 amdgpu_rreg_t gc_cac_rreg; 885 amdgpu_wreg_t gc_cac_wreg; 886 /* protects concurrent se_cac register access */ 887 spinlock_t se_cac_idx_lock; 888 amdgpu_rreg_t se_cac_rreg; 889 amdgpu_wreg_t se_cac_wreg; 890 /* protects concurrent ENDPOINT (audio) register access */ 891 spinlock_t audio_endpt_idx_lock; 892 amdgpu_block_rreg_t audio_endpt_rreg; 893 amdgpu_block_wreg_t audio_endpt_wreg; 894 void __iomem *rio_mem; 895 resource_size_t rio_mem_size; 896 struct amdgpu_doorbell doorbell; 897 898 /* clock/pll info */ 899 struct amdgpu_clock clock; 900 901 /* MC */ 902 struct amdgpu_gmc gmc; 903 struct amdgpu_gart gart; 904 dma_addr_t dummy_page_addr; 905 struct amdgpu_vm_manager vm_manager; 906 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 907 908 /* memory management */ 909 struct amdgpu_mman mman; 910 struct amdgpu_vram_scratch vram_scratch; 911 struct amdgpu_wb wb; 912 atomic64_t num_bytes_moved; 913 atomic64_t num_evictions; 914 atomic64_t num_vram_cpu_page_faults; 915 atomic_t gpu_reset_counter; 916 atomic_t vram_lost_counter; 917 918 /* data for buffer migration throttling */ 919 struct { 920 spinlock_t lock; 921 s64 last_update_us; 922 s64 accum_us; /* accumulated microseconds */ 923 s64 accum_us_vis; /* for visible VRAM */ 924 u32 log2_max_MBps; 925 } mm_stats; 926 927 /* display */ 928 bool enable_virtual_display; 929 struct amdgpu_mode_info mode_info; 930 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 931 struct work_struct hotplug_work; 932 struct amdgpu_irq_src crtc_irq; 933 struct amdgpu_irq_src pageflip_irq; 934 struct amdgpu_irq_src hpd_irq; 935 936 /* rings */ 937 u64 fence_context; 938 unsigned num_rings; 939 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 940 bool ib_pool_ready; 941 struct amdgpu_sa_manager ring_tmp_bo; 942 943 /* interrupts */ 944 struct amdgpu_irq irq; 945 946 /* powerplay */ 947 struct amd_powerplay powerplay; 948 bool pp_force_state_enabled; 949 950 /* dpm */ 951 struct amdgpu_pm pm; 952 u32 cg_flags; 953 u32 pg_flags; 954 955 /* gfx */ 956 struct amdgpu_gfx gfx; 957 958 /* sdma */ 959 struct amdgpu_sdma sdma; 960 961 /* uvd */ 962 struct amdgpu_uvd uvd; 963 964 /* vce */ 965 struct amdgpu_vce vce; 966 967 /* vcn */ 968 struct amdgpu_vcn vcn; 969 970 /* firmwares */ 971 struct amdgpu_firmware firmware; 972 973 /* PSP */ 974 struct psp_context psp; 975 976 /* GDS */ 977 struct amdgpu_gds gds; 978 979 /* display related functionality */ 980 struct amdgpu_display_manager dm; 981 982 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 983 int num_ip_blocks; 984 struct mutex mn_lock; 985 DECLARE_HASHTABLE(mn_hash, 7); 986 987 /* tracking pinned memory */ 988 atomic64_t vram_pin_size; 989 atomic64_t visible_pin_size; 990 atomic64_t gart_pin_size; 991 992 /* amdkfd interface */ 993 struct kfd_dev *kfd; 994 995 /* soc15 register offset based on ip, instance and segment */ 996 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 997 998 const struct amdgpu_nbio_funcs *nbio_funcs; 999 const struct amdgpu_df_funcs *df_funcs; 1000 1001 /* delayed work_func for deferring clockgating during resume */ 1002 struct delayed_work late_init_work; 1003 1004 struct amdgpu_virt virt; 1005 /* firmware VRAM reservation */ 1006 struct amdgpu_fw_vram_usage fw_vram_usage; 1007 1008 /* link all shadow bo */ 1009 struct list_head shadow_list; 1010 struct mutex shadow_list_lock; 1011 /* keep an lru list of rings by HW IP */ 1012 struct list_head ring_lru_list; 1013 spinlock_t ring_lru_list_lock; 1014 1015 /* record hw reset is performed */ 1016 bool has_hw_reset; 1017 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1018 1019 /* s3/s4 mask */ 1020 bool in_suspend; 1021 1022 /* record last mm index being written through WREG32*/ 1023 unsigned long last_mm_index; 1024 bool in_gpu_reset; 1025 struct mutex lock_reset; 1026 }; 1027 1028 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1029 { 1030 return container_of(bdev, struct amdgpu_device, mman.bdev); 1031 } 1032 1033 int amdgpu_device_init(struct amdgpu_device *adev, 1034 struct drm_device *ddev, 1035 struct pci_dev *pdev, 1036 uint32_t flags); 1037 void amdgpu_device_fini(struct amdgpu_device *adev); 1038 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1039 1040 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1041 uint32_t acc_flags); 1042 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1043 uint32_t acc_flags); 1044 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1045 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1046 1047 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1048 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1049 1050 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 1051 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1052 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 1053 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 1054 1055 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1056 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1057 1058 int emu_soc_asic_init(struct amdgpu_device *adev); 1059 1060 /* 1061 * Registers read & write functions. 1062 */ 1063 1064 #define AMDGPU_REGS_IDX (1<<0) 1065 #define AMDGPU_REGS_NO_KIQ (1<<1) 1066 1067 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1068 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1069 1070 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1071 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1072 1073 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1074 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1075 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1076 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1077 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1078 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1079 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1080 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1081 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1082 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1083 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1084 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1085 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1086 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1087 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1088 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1089 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1090 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1091 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1092 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1093 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1094 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1095 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1096 #define WREG32_P(reg, val, mask) \ 1097 do { \ 1098 uint32_t tmp_ = RREG32(reg); \ 1099 tmp_ &= (mask); \ 1100 tmp_ |= ((val) & ~(mask)); \ 1101 WREG32(reg, tmp_); \ 1102 } while (0) 1103 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1104 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1105 #define WREG32_PLL_P(reg, val, mask) \ 1106 do { \ 1107 uint32_t tmp_ = RREG32_PLL(reg); \ 1108 tmp_ &= (mask); \ 1109 tmp_ |= ((val) & ~(mask)); \ 1110 WREG32_PLL(reg, tmp_); \ 1111 } while (0) 1112 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1113 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1114 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1115 1116 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 1117 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1118 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 1119 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 1120 1121 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1122 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1123 1124 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1125 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1126 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1127 1128 #define REG_GET_FIELD(value, reg, field) \ 1129 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1130 1131 #define WREG32_FIELD(reg, field, val) \ 1132 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1133 1134 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1135 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1136 1137 /* 1138 * BIOS helpers. 1139 */ 1140 #define RBIOS8(i) (adev->bios[i]) 1141 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1142 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1143 1144 /* 1145 * ASICs macro. 1146 */ 1147 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1148 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1149 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1150 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1151 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1152 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1153 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1154 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1155 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1156 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1157 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1158 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1159 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1160 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1161 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1162 1163 /* Common functions */ 1164 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1165 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1166 struct amdgpu_job* job); 1167 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1168 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1169 1170 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1171 u64 num_vis_bytes); 1172 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1173 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1174 const u32 *registers, 1175 const u32 array_size); 1176 1177 bool amdgpu_device_is_px(struct drm_device *dev); 1178 /* atpx handler */ 1179 #if defined(CONFIG_VGA_SWITCHEROO) 1180 void amdgpu_register_atpx_handler(void); 1181 void amdgpu_unregister_atpx_handler(void); 1182 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1183 bool amdgpu_is_atpx_hybrid(void); 1184 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1185 bool amdgpu_has_atpx(void); 1186 #else 1187 static inline void amdgpu_register_atpx_handler(void) {} 1188 static inline void amdgpu_unregister_atpx_handler(void) {} 1189 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1190 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1191 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1192 static inline bool amdgpu_has_atpx(void) { return false; } 1193 #endif 1194 1195 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1196 void *amdgpu_atpx_get_dhandle(void); 1197 #else 1198 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1199 #endif 1200 1201 /* 1202 * KMS 1203 */ 1204 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1205 extern const int amdgpu_max_kms_ioctl; 1206 1207 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1208 void amdgpu_driver_unload_kms(struct drm_device *dev); 1209 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1210 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1211 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1212 struct drm_file *file_priv); 1213 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1214 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1215 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1216 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1217 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1218 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1219 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1220 unsigned long arg); 1221 1222 1223 /* 1224 * functions used by amdgpu_xgmi.c 1225 */ 1226 int amdgpu_xgmi_add_device(struct amdgpu_device *adev); 1227 1228 /* 1229 * functions used by amdgpu_encoder.c 1230 */ 1231 struct amdgpu_afmt_acr { 1232 u32 clock; 1233 1234 int n_32khz; 1235 int cts_32khz; 1236 1237 int n_44_1khz; 1238 int cts_44_1khz; 1239 1240 int n_48khz; 1241 int cts_48khz; 1242 1243 }; 1244 1245 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1246 1247 /* amdgpu_acpi.c */ 1248 #if defined(CONFIG_ACPI) 1249 int amdgpu_acpi_init(struct amdgpu_device *adev); 1250 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1251 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1252 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1253 u8 perf_req, bool advertise); 1254 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1255 #else 1256 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1257 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1258 #endif 1259 1260 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1261 uint64_t addr, struct amdgpu_bo **bo, 1262 struct amdgpu_bo_va_mapping **mapping); 1263 1264 #if defined(CONFIG_DRM_AMD_DC) 1265 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1266 #else 1267 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1268 #endif 1269 1270 #include "amdgpu_object.h" 1271 #endif 1272