1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_gds.h" 55 #include "amd_powerplay.h" 56 #include "amdgpu_acp.h" 57 58 #include "gpu_scheduler.h" 59 60 /* 61 * Modules parameters. 62 */ 63 extern int amdgpu_modeset; 64 extern int amdgpu_vram_limit; 65 extern int amdgpu_gart_size; 66 extern int amdgpu_benchmarking; 67 extern int amdgpu_testing; 68 extern int amdgpu_audio; 69 extern int amdgpu_disp_priority; 70 extern int amdgpu_hw_i2c; 71 extern int amdgpu_pcie_gen2; 72 extern int amdgpu_msi; 73 extern int amdgpu_lockup_timeout; 74 extern int amdgpu_dpm; 75 extern int amdgpu_smc_load_fw; 76 extern int amdgpu_aspm; 77 extern int amdgpu_runtime_pm; 78 extern unsigned amdgpu_ip_block_mask; 79 extern int amdgpu_bapm; 80 extern int amdgpu_deep_color; 81 extern int amdgpu_vm_size; 82 extern int amdgpu_vm_block_size; 83 extern int amdgpu_vm_fault_stop; 84 extern int amdgpu_vm_debug; 85 extern int amdgpu_sched_jobs; 86 extern int amdgpu_sched_hw_submission; 87 extern int amdgpu_powerplay; 88 89 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 90 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 91 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 92 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 93 #define AMDGPU_IB_POOL_SIZE 16 94 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 95 #define AMDGPUFB_CONN_LIMIT 4 96 #define AMDGPU_BIOS_NUM_SCRATCH 8 97 98 /* max number of rings */ 99 #define AMDGPU_MAX_RINGS 16 100 #define AMDGPU_MAX_GFX_RINGS 1 101 #define AMDGPU_MAX_COMPUTE_RINGS 8 102 #define AMDGPU_MAX_VCE_RINGS 2 103 104 /* max number of IP instances */ 105 #define AMDGPU_MAX_SDMA_INSTANCES 2 106 107 /* hardcode that limit for now */ 108 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 109 110 /* hard reset data */ 111 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 112 113 /* reset flags */ 114 #define AMDGPU_RESET_GFX (1 << 0) 115 #define AMDGPU_RESET_COMPUTE (1 << 1) 116 #define AMDGPU_RESET_DMA (1 << 2) 117 #define AMDGPU_RESET_CP (1 << 3) 118 #define AMDGPU_RESET_GRBM (1 << 4) 119 #define AMDGPU_RESET_DMA1 (1 << 5) 120 #define AMDGPU_RESET_RLC (1 << 6) 121 #define AMDGPU_RESET_SEM (1 << 7) 122 #define AMDGPU_RESET_IH (1 << 8) 123 #define AMDGPU_RESET_VMC (1 << 9) 124 #define AMDGPU_RESET_MC (1 << 10) 125 #define AMDGPU_RESET_DISPLAY (1 << 11) 126 #define AMDGPU_RESET_UVD (1 << 12) 127 #define AMDGPU_RESET_VCE (1 << 13) 128 #define AMDGPU_RESET_VCE1 (1 << 14) 129 130 /* CG block flags */ 131 #define AMDGPU_CG_BLOCK_GFX (1 << 0) 132 #define AMDGPU_CG_BLOCK_MC (1 << 1) 133 #define AMDGPU_CG_BLOCK_SDMA (1 << 2) 134 #define AMDGPU_CG_BLOCK_UVD (1 << 3) 135 #define AMDGPU_CG_BLOCK_VCE (1 << 4) 136 #define AMDGPU_CG_BLOCK_HDP (1 << 5) 137 #define AMDGPU_CG_BLOCK_BIF (1 << 6) 138 139 /* CG flags */ 140 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0) 141 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1) 142 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2) 143 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3) 144 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4) 145 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 146 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6) 147 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7) 148 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8) 149 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9) 150 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10) 151 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11) 152 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12) 153 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13) 154 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14) 155 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15) 156 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16) 157 158 /* PG flags */ 159 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) 160 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) 161 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) 162 #define AMDGPU_PG_SUPPORT_UVD (1 << 3) 163 #define AMDGPU_PG_SUPPORT_VCE (1 << 4) 164 #define AMDGPU_PG_SUPPORT_CP (1 << 5) 165 #define AMDGPU_PG_SUPPORT_GDS (1 << 6) 166 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7) 167 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8) 168 #define AMDGPU_PG_SUPPORT_ACP (1 << 9) 169 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10) 170 171 /* GFX current status */ 172 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 173 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 174 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 175 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 176 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 177 178 /* max cursor sizes (in pixels) */ 179 #define CIK_CURSOR_WIDTH 128 180 #define CIK_CURSOR_HEIGHT 128 181 182 struct amdgpu_device; 183 struct amdgpu_fence; 184 struct amdgpu_ib; 185 struct amdgpu_vm; 186 struct amdgpu_ring; 187 struct amdgpu_cs_parser; 188 struct amdgpu_job; 189 struct amdgpu_irq_src; 190 struct amdgpu_fpriv; 191 192 enum amdgpu_cp_irq { 193 AMDGPU_CP_IRQ_GFX_EOP = 0, 194 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 195 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 198 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 199 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 202 203 AMDGPU_CP_IRQ_LAST 204 }; 205 206 enum amdgpu_sdma_irq { 207 AMDGPU_SDMA_IRQ_TRAP0 = 0, 208 AMDGPU_SDMA_IRQ_TRAP1, 209 210 AMDGPU_SDMA_IRQ_LAST 211 }; 212 213 enum amdgpu_thermal_irq { 214 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 215 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 216 217 AMDGPU_THERMAL_IRQ_LAST 218 }; 219 220 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 221 enum amd_ip_block_type block_type, 222 enum amd_clockgating_state state); 223 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 224 enum amd_ip_block_type block_type, 225 enum amd_powergating_state state); 226 227 struct amdgpu_ip_block_version { 228 enum amd_ip_block_type type; 229 u32 major; 230 u32 minor; 231 u32 rev; 232 const struct amd_ip_funcs *funcs; 233 }; 234 235 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 236 enum amd_ip_block_type type, 237 u32 major, u32 minor); 238 239 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 240 struct amdgpu_device *adev, 241 enum amd_ip_block_type type); 242 243 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 244 struct amdgpu_buffer_funcs { 245 /* maximum bytes in a single operation */ 246 uint32_t copy_max_bytes; 247 248 /* number of dw to reserve per operation */ 249 unsigned copy_num_dw; 250 251 /* used for buffer migration */ 252 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 253 /* src addr in bytes */ 254 uint64_t src_offset, 255 /* dst addr in bytes */ 256 uint64_t dst_offset, 257 /* number of byte to transfer */ 258 uint32_t byte_count); 259 260 /* maximum bytes in a single operation */ 261 uint32_t fill_max_bytes; 262 263 /* number of dw to reserve per operation */ 264 unsigned fill_num_dw; 265 266 /* used for buffer clearing */ 267 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 268 /* value to write to memory */ 269 uint32_t src_data, 270 /* dst addr in bytes */ 271 uint64_t dst_offset, 272 /* number of byte to fill */ 273 uint32_t byte_count); 274 }; 275 276 /* provided by hw blocks that can write ptes, e.g., sdma */ 277 struct amdgpu_vm_pte_funcs { 278 /* copy pte entries from GART */ 279 void (*copy_pte)(struct amdgpu_ib *ib, 280 uint64_t pe, uint64_t src, 281 unsigned count); 282 /* write pte one entry at a time with addr mapping */ 283 void (*write_pte)(struct amdgpu_ib *ib, 284 const dma_addr_t *pages_addr, uint64_t pe, 285 uint64_t addr, unsigned count, 286 uint32_t incr, uint32_t flags); 287 /* for linear pte/pde updates without addr mapping */ 288 void (*set_pte_pde)(struct amdgpu_ib *ib, 289 uint64_t pe, 290 uint64_t addr, unsigned count, 291 uint32_t incr, uint32_t flags); 292 }; 293 294 /* provided by the gmc block */ 295 struct amdgpu_gart_funcs { 296 /* flush the vm tlb via mmio */ 297 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 298 uint32_t vmid); 299 /* write pte/pde updates using the cpu */ 300 int (*set_pte_pde)(struct amdgpu_device *adev, 301 void *cpu_pt_addr, /* cpu addr of page table */ 302 uint32_t gpu_page_idx, /* pte/pde to update */ 303 uint64_t addr, /* addr to write into pte/pde */ 304 uint32_t flags); /* access flags */ 305 }; 306 307 /* provided by the ih block */ 308 struct amdgpu_ih_funcs { 309 /* ring read/write ptr handling, called from interrupt context */ 310 u32 (*get_wptr)(struct amdgpu_device *adev); 311 void (*decode_iv)(struct amdgpu_device *adev, 312 struct amdgpu_iv_entry *entry); 313 void (*set_rptr)(struct amdgpu_device *adev); 314 }; 315 316 /* provided by hw blocks that expose a ring buffer for commands */ 317 struct amdgpu_ring_funcs { 318 /* ring read/write ptr handling */ 319 u32 (*get_rptr)(struct amdgpu_ring *ring); 320 u32 (*get_wptr)(struct amdgpu_ring *ring); 321 void (*set_wptr)(struct amdgpu_ring *ring); 322 /* validating and patching of IBs */ 323 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 324 /* command emit functions */ 325 void (*emit_ib)(struct amdgpu_ring *ring, 326 struct amdgpu_ib *ib); 327 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 328 uint64_t seq, unsigned flags); 329 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 330 uint64_t pd_addr); 331 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 332 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 333 uint32_t gds_base, uint32_t gds_size, 334 uint32_t gws_base, uint32_t gws_size, 335 uint32_t oa_base, uint32_t oa_size); 336 /* testing functions */ 337 int (*test_ring)(struct amdgpu_ring *ring); 338 int (*test_ib)(struct amdgpu_ring *ring); 339 /* insert NOP packets */ 340 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 341 /* pad the indirect buffer to the necessary number of dw */ 342 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 343 }; 344 345 /* 346 * BIOS. 347 */ 348 bool amdgpu_get_bios(struct amdgpu_device *adev); 349 bool amdgpu_read_bios(struct amdgpu_device *adev); 350 351 /* 352 * Dummy page 353 */ 354 struct amdgpu_dummy_page { 355 struct page *page; 356 dma_addr_t addr; 357 }; 358 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 359 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 360 361 362 /* 363 * Clocks 364 */ 365 366 #define AMDGPU_MAX_PPLL 3 367 368 struct amdgpu_clock { 369 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 370 struct amdgpu_pll spll; 371 struct amdgpu_pll mpll; 372 /* 10 Khz units */ 373 uint32_t default_mclk; 374 uint32_t default_sclk; 375 uint32_t default_dispclk; 376 uint32_t current_dispclk; 377 uint32_t dp_extclk; 378 uint32_t max_pixel_clock; 379 }; 380 381 /* 382 * Fences. 383 */ 384 struct amdgpu_fence_driver { 385 uint64_t gpu_addr; 386 volatile uint32_t *cpu_addr; 387 /* sync_seq is protected by ring emission lock */ 388 uint64_t sync_seq; 389 atomic64_t last_seq; 390 bool initialized; 391 struct amdgpu_irq_src *irq_src; 392 unsigned irq_type; 393 struct timer_list fallback_timer; 394 wait_queue_head_t fence_queue; 395 }; 396 397 /* some special values for the owner field */ 398 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 399 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 400 401 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 402 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 403 404 struct amdgpu_fence { 405 struct fence base; 406 407 /* RB, DMA, etc. */ 408 struct amdgpu_ring *ring; 409 uint64_t seq; 410 411 /* filp or special value for fence creator */ 412 void *owner; 413 414 wait_queue_t fence_wake; 415 }; 416 417 struct amdgpu_user_fence { 418 /* write-back bo */ 419 struct amdgpu_bo *bo; 420 /* write-back address offset to bo start */ 421 uint32_t offset; 422 }; 423 424 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 425 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 426 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 427 428 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 429 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 430 struct amdgpu_irq_src *irq_src, 431 unsigned irq_type); 432 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 433 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 434 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, 435 struct amdgpu_fence **fence); 436 void amdgpu_fence_process(struct amdgpu_ring *ring); 437 int amdgpu_fence_wait_next(struct amdgpu_ring *ring); 438 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 439 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 440 441 /* 442 * TTM. 443 */ 444 struct amdgpu_mman { 445 struct ttm_bo_global_ref bo_global_ref; 446 struct drm_global_reference mem_global_ref; 447 struct ttm_bo_device bdev; 448 bool mem_global_referenced; 449 bool initialized; 450 451 #if defined(CONFIG_DEBUG_FS) 452 struct dentry *vram; 453 struct dentry *gtt; 454 #endif 455 456 /* buffer handling */ 457 const struct amdgpu_buffer_funcs *buffer_funcs; 458 struct amdgpu_ring *buffer_funcs_ring; 459 }; 460 461 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 462 uint64_t src_offset, 463 uint64_t dst_offset, 464 uint32_t byte_count, 465 struct reservation_object *resv, 466 struct fence **fence); 467 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 468 469 struct amdgpu_bo_list_entry { 470 struct amdgpu_bo *robj; 471 struct ttm_validate_buffer tv; 472 struct amdgpu_bo_va *bo_va; 473 uint32_t priority; 474 }; 475 476 struct amdgpu_bo_va_mapping { 477 struct list_head list; 478 struct interval_tree_node it; 479 uint64_t offset; 480 uint32_t flags; 481 }; 482 483 /* bo virtual addresses in a specific vm */ 484 struct amdgpu_bo_va { 485 struct mutex mutex; 486 /* protected by bo being reserved */ 487 struct list_head bo_list; 488 struct fence *last_pt_update; 489 unsigned ref_count; 490 491 /* protected by vm mutex and spinlock */ 492 struct list_head vm_status; 493 494 /* mappings for this bo_va */ 495 struct list_head invalids; 496 struct list_head valids; 497 498 /* constant after initialization */ 499 struct amdgpu_vm *vm; 500 struct amdgpu_bo *bo; 501 }; 502 503 #define AMDGPU_GEM_DOMAIN_MAX 0x3 504 505 struct amdgpu_bo { 506 /* Protected by gem.mutex */ 507 struct list_head list; 508 /* Protected by tbo.reserved */ 509 u32 prefered_domains; 510 u32 allowed_domains; 511 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 512 struct ttm_placement placement; 513 struct ttm_buffer_object tbo; 514 struct ttm_bo_kmap_obj kmap; 515 u64 flags; 516 unsigned pin_count; 517 void *kptr; 518 u64 tiling_flags; 519 u64 metadata_flags; 520 void *metadata; 521 u32 metadata_size; 522 /* list of all virtual address to which this bo 523 * is associated to 524 */ 525 struct list_head va; 526 /* Constant after initialization */ 527 struct amdgpu_device *adev; 528 struct drm_gem_object gem_base; 529 struct amdgpu_bo *parent; 530 531 struct ttm_bo_kmap_obj dma_buf_vmap; 532 pid_t pid; 533 struct amdgpu_mn *mn; 534 struct list_head mn_list; 535 }; 536 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 537 538 void amdgpu_gem_object_free(struct drm_gem_object *obj); 539 int amdgpu_gem_object_open(struct drm_gem_object *obj, 540 struct drm_file *file_priv); 541 void amdgpu_gem_object_close(struct drm_gem_object *obj, 542 struct drm_file *file_priv); 543 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 544 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 545 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 546 struct dma_buf_attachment *attach, 547 struct sg_table *sg); 548 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 549 struct drm_gem_object *gobj, 550 int flags); 551 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 552 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 553 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 554 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 555 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 556 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 557 558 /* sub-allocation manager, it has to be protected by another lock. 559 * By conception this is an helper for other part of the driver 560 * like the indirect buffer or semaphore, which both have their 561 * locking. 562 * 563 * Principe is simple, we keep a list of sub allocation in offset 564 * order (first entry has offset == 0, last entry has the highest 565 * offset). 566 * 567 * When allocating new object we first check if there is room at 568 * the end total_size - (last_object_offset + last_object_size) >= 569 * alloc_size. If so we allocate new object there. 570 * 571 * When there is not enough room at the end, we start waiting for 572 * each sub object until we reach object_offset+object_size >= 573 * alloc_size, this object then become the sub object we return. 574 * 575 * Alignment can't be bigger than page size. 576 * 577 * Hole are not considered for allocation to keep things simple. 578 * Assumption is that there won't be hole (all object on same 579 * alignment). 580 */ 581 struct amdgpu_sa_manager { 582 wait_queue_head_t wq; 583 struct amdgpu_bo *bo; 584 struct list_head *hole; 585 struct list_head flist[AMDGPU_MAX_RINGS]; 586 struct list_head olist; 587 unsigned size; 588 uint64_t gpu_addr; 589 void *cpu_ptr; 590 uint32_t domain; 591 uint32_t align; 592 }; 593 594 struct amdgpu_sa_bo; 595 596 /* sub-allocation buffer */ 597 struct amdgpu_sa_bo { 598 struct list_head olist; 599 struct list_head flist; 600 struct amdgpu_sa_manager *manager; 601 unsigned soffset; 602 unsigned eoffset; 603 struct fence *fence; 604 }; 605 606 /* 607 * GEM objects. 608 */ 609 struct amdgpu_gem { 610 struct mutex mutex; 611 struct list_head objects; 612 }; 613 614 int amdgpu_gem_init(struct amdgpu_device *adev); 615 void amdgpu_gem_fini(struct amdgpu_device *adev); 616 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 617 int alignment, u32 initial_domain, 618 u64 flags, bool kernel, 619 struct drm_gem_object **obj); 620 621 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 622 struct drm_device *dev, 623 struct drm_mode_create_dumb *args); 624 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 625 struct drm_device *dev, 626 uint32_t handle, uint64_t *offset_p); 627 /* 628 * Synchronization 629 */ 630 struct amdgpu_sync { 631 DECLARE_HASHTABLE(fences, 4); 632 struct fence *last_vm_update; 633 }; 634 635 void amdgpu_sync_create(struct amdgpu_sync *sync); 636 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 637 struct fence *f); 638 int amdgpu_sync_resv(struct amdgpu_device *adev, 639 struct amdgpu_sync *sync, 640 struct reservation_object *resv, 641 void *owner); 642 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 643 int amdgpu_sync_wait(struct amdgpu_sync *sync); 644 void amdgpu_sync_free(struct amdgpu_sync *sync); 645 646 /* 647 * GART structures, functions & helpers 648 */ 649 struct amdgpu_mc; 650 651 #define AMDGPU_GPU_PAGE_SIZE 4096 652 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 653 #define AMDGPU_GPU_PAGE_SHIFT 12 654 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 655 656 struct amdgpu_gart { 657 dma_addr_t table_addr; 658 struct amdgpu_bo *robj; 659 void *ptr; 660 unsigned num_gpu_pages; 661 unsigned num_cpu_pages; 662 unsigned table_size; 663 struct page **pages; 664 dma_addr_t *pages_addr; 665 bool ready; 666 const struct amdgpu_gart_funcs *gart_funcs; 667 }; 668 669 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 670 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 671 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 672 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 673 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 674 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 675 int amdgpu_gart_init(struct amdgpu_device *adev); 676 void amdgpu_gart_fini(struct amdgpu_device *adev); 677 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 678 int pages); 679 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 680 int pages, struct page **pagelist, 681 dma_addr_t *dma_addr, uint32_t flags); 682 683 /* 684 * GPU MC structures, functions & helpers 685 */ 686 struct amdgpu_mc { 687 resource_size_t aper_size; 688 resource_size_t aper_base; 689 resource_size_t agp_base; 690 /* for some chips with <= 32MB we need to lie 691 * about vram size near mc fb location */ 692 u64 mc_vram_size; 693 u64 visible_vram_size; 694 u64 gtt_size; 695 u64 gtt_start; 696 u64 gtt_end; 697 u64 vram_start; 698 u64 vram_end; 699 unsigned vram_width; 700 u64 real_vram_size; 701 int vram_mtrr; 702 u64 gtt_base_align; 703 u64 mc_mask; 704 const struct firmware *fw; /* MC firmware */ 705 uint32_t fw_version; 706 struct amdgpu_irq_src vm_fault; 707 uint32_t vram_type; 708 }; 709 710 /* 711 * GPU doorbell structures, functions & helpers 712 */ 713 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 714 { 715 AMDGPU_DOORBELL_KIQ = 0x000, 716 AMDGPU_DOORBELL_HIQ = 0x001, 717 AMDGPU_DOORBELL_DIQ = 0x002, 718 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 719 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 720 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 721 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 722 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 723 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 724 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 725 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 726 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 727 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 728 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 729 AMDGPU_DOORBELL_IH = 0x1E8, 730 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 731 AMDGPU_DOORBELL_INVALID = 0xFFFF 732 } AMDGPU_DOORBELL_ASSIGNMENT; 733 734 struct amdgpu_doorbell { 735 /* doorbell mmio */ 736 resource_size_t base; 737 resource_size_t size; 738 u32 __iomem *ptr; 739 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 740 }; 741 742 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 743 phys_addr_t *aperture_base, 744 size_t *aperture_size, 745 size_t *start_offset); 746 747 /* 748 * IRQS. 749 */ 750 751 struct amdgpu_flip_work { 752 struct work_struct flip_work; 753 struct work_struct unpin_work; 754 struct amdgpu_device *adev; 755 int crtc_id; 756 uint64_t base; 757 struct drm_pending_vblank_event *event; 758 struct amdgpu_bo *old_rbo; 759 struct fence *excl; 760 unsigned shared_count; 761 struct fence **shared; 762 }; 763 764 765 /* 766 * CP & rings. 767 */ 768 769 struct amdgpu_ib { 770 struct amdgpu_sa_bo *sa_bo; 771 uint32_t length_dw; 772 uint64_t gpu_addr; 773 uint32_t *ptr; 774 struct amdgpu_fence *fence; 775 struct amdgpu_user_fence *user; 776 bool grabbed_vmid; 777 struct amdgpu_vm *vm; 778 struct amdgpu_ctx *ctx; 779 uint32_t gds_base, gds_size; 780 uint32_t gws_base, gws_size; 781 uint32_t oa_base, oa_size; 782 uint32_t flags; 783 /* resulting sequence number */ 784 uint64_t sequence; 785 }; 786 787 enum amdgpu_ring_type { 788 AMDGPU_RING_TYPE_GFX, 789 AMDGPU_RING_TYPE_COMPUTE, 790 AMDGPU_RING_TYPE_SDMA, 791 AMDGPU_RING_TYPE_UVD, 792 AMDGPU_RING_TYPE_VCE 793 }; 794 795 extern struct amd_sched_backend_ops amdgpu_sched_ops; 796 797 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 798 struct amdgpu_job **job); 799 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 800 struct amdgpu_job **job); 801 void amdgpu_job_free(struct amdgpu_job *job); 802 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 803 void *owner, struct fence **f); 804 805 struct amdgpu_ring { 806 struct amdgpu_device *adev; 807 const struct amdgpu_ring_funcs *funcs; 808 struct amdgpu_fence_driver fence_drv; 809 struct amd_gpu_scheduler sched; 810 811 spinlock_t fence_lock; 812 struct amdgpu_bo *ring_obj; 813 volatile uint32_t *ring; 814 unsigned rptr_offs; 815 u64 next_rptr_gpu_addr; 816 volatile u32 *next_rptr_cpu_addr; 817 unsigned wptr; 818 unsigned wptr_old; 819 unsigned ring_size; 820 unsigned max_dw; 821 int count_dw; 822 uint64_t gpu_addr; 823 uint32_t align_mask; 824 uint32_t ptr_mask; 825 bool ready; 826 u32 nop; 827 u32 idx; 828 u32 me; 829 u32 pipe; 830 u32 queue; 831 struct amdgpu_bo *mqd_obj; 832 u32 doorbell_index; 833 bool use_doorbell; 834 unsigned wptr_offs; 835 unsigned next_rptr_offs; 836 unsigned fence_offs; 837 struct amdgpu_ctx *current_ctx; 838 enum amdgpu_ring_type type; 839 char name[16]; 840 bool is_pte_ring; 841 }; 842 843 /* 844 * VM 845 */ 846 847 /* maximum number of VMIDs */ 848 #define AMDGPU_NUM_VM 16 849 850 /* number of entries in page table */ 851 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 852 853 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 854 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 855 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 856 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 857 858 #define AMDGPU_PTE_VALID (1 << 0) 859 #define AMDGPU_PTE_SYSTEM (1 << 1) 860 #define AMDGPU_PTE_SNOOPED (1 << 2) 861 862 /* VI only */ 863 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 864 865 #define AMDGPU_PTE_READABLE (1 << 5) 866 #define AMDGPU_PTE_WRITEABLE (1 << 6) 867 868 /* PTE (Page Table Entry) fragment field for different page sizes */ 869 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 870 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 871 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 872 873 /* How to programm VM fault handling */ 874 #define AMDGPU_VM_FAULT_STOP_NEVER 0 875 #define AMDGPU_VM_FAULT_STOP_FIRST 1 876 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 877 878 struct amdgpu_vm_pt { 879 struct amdgpu_bo_list_entry entry; 880 uint64_t addr; 881 }; 882 883 struct amdgpu_vm_id { 884 unsigned id; 885 uint64_t pd_gpu_addr; 886 /* last flushed PD/PT update */ 887 struct fence *flushed_updates; 888 }; 889 890 struct amdgpu_vm { 891 /* tree of virtual addresses mapped */ 892 spinlock_t it_lock; 893 struct rb_root va; 894 895 /* protecting invalidated */ 896 spinlock_t status_lock; 897 898 /* BOs moved, but not yet updated in the PT */ 899 struct list_head invalidated; 900 901 /* BOs cleared in the PT because of a move */ 902 struct list_head cleared; 903 904 /* BO mappings freed, but not yet updated in the PT */ 905 struct list_head freed; 906 907 /* contains the page directory */ 908 struct amdgpu_bo *page_directory; 909 unsigned max_pde_used; 910 struct fence *page_directory_fence; 911 912 /* array of page tables, one for each page directory entry */ 913 struct amdgpu_vm_pt *page_tables; 914 915 /* for id and flush management per ring */ 916 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; 917 918 /* protecting freed */ 919 spinlock_t freed_lock; 920 }; 921 922 struct amdgpu_vm_manager_id { 923 struct list_head list; 924 struct fence *active; 925 atomic_long_t owner; 926 }; 927 928 struct amdgpu_vm_manager { 929 /* Handling of VMIDs */ 930 struct mutex lock; 931 unsigned num_ids; 932 struct list_head ids_lru; 933 struct amdgpu_vm_manager_id ids[AMDGPU_NUM_VM]; 934 935 uint32_t max_pfn; 936 /* vram base address for page table entry */ 937 u64 vram_base_offset; 938 /* is vm enabled? */ 939 bool enabled; 940 /* vm pte handling */ 941 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 942 struct amdgpu_ring *vm_pte_funcs_ring; 943 }; 944 945 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 946 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 947 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 948 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 949 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 950 struct list_head *validated, 951 struct amdgpu_bo_list_entry *entry); 952 void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates); 953 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, 954 struct amdgpu_vm *vm); 955 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 956 struct amdgpu_sync *sync, struct fence *fence); 957 void amdgpu_vm_flush(struct amdgpu_ring *ring, 958 struct amdgpu_vm *vm, 959 struct fence *updates); 960 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 961 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 962 struct amdgpu_vm *vm); 963 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 964 struct amdgpu_vm *vm); 965 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, 966 struct amdgpu_sync *sync); 967 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 968 struct amdgpu_bo_va *bo_va, 969 struct ttm_mem_reg *mem); 970 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 971 struct amdgpu_bo *bo); 972 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 973 struct amdgpu_bo *bo); 974 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 975 struct amdgpu_vm *vm, 976 struct amdgpu_bo *bo); 977 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 978 struct amdgpu_bo_va *bo_va, 979 uint64_t addr, uint64_t offset, 980 uint64_t size, uint32_t flags); 981 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 982 struct amdgpu_bo_va *bo_va, 983 uint64_t addr); 984 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 985 struct amdgpu_bo_va *bo_va); 986 987 /* 988 * context related structures 989 */ 990 991 struct amdgpu_ctx_ring { 992 uint64_t sequence; 993 struct fence **fences; 994 struct amd_sched_entity entity; 995 }; 996 997 struct amdgpu_ctx { 998 struct kref refcount; 999 struct amdgpu_device *adev; 1000 unsigned reset_counter; 1001 spinlock_t ring_lock; 1002 struct fence **fences; 1003 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 1004 }; 1005 1006 struct amdgpu_ctx_mgr { 1007 struct amdgpu_device *adev; 1008 struct mutex lock; 1009 /* protected by lock */ 1010 struct idr ctx_handles; 1011 }; 1012 1013 int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri, 1014 struct amdgpu_ctx *ctx); 1015 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx); 1016 1017 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 1018 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 1019 1020 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 1021 struct fence *fence); 1022 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 1023 struct amdgpu_ring *ring, uint64_t seq); 1024 1025 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 1026 struct drm_file *filp); 1027 1028 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1029 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 1030 1031 /* 1032 * file private structure 1033 */ 1034 1035 struct amdgpu_fpriv { 1036 struct amdgpu_vm vm; 1037 struct mutex bo_list_lock; 1038 struct idr bo_list_handles; 1039 struct amdgpu_ctx_mgr ctx_mgr; 1040 }; 1041 1042 /* 1043 * residency list 1044 */ 1045 1046 struct amdgpu_bo_list { 1047 struct mutex lock; 1048 struct amdgpu_bo *gds_obj; 1049 struct amdgpu_bo *gws_obj; 1050 struct amdgpu_bo *oa_obj; 1051 bool has_userptr; 1052 unsigned num_entries; 1053 struct amdgpu_bo_list_entry *array; 1054 }; 1055 1056 struct amdgpu_bo_list * 1057 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1058 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 1059 struct list_head *validated); 1060 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1061 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1062 1063 /* 1064 * GFX stuff 1065 */ 1066 #include "clearstate_defs.h" 1067 1068 struct amdgpu_rlc { 1069 /* for power gating */ 1070 struct amdgpu_bo *save_restore_obj; 1071 uint64_t save_restore_gpu_addr; 1072 volatile uint32_t *sr_ptr; 1073 const u32 *reg_list; 1074 u32 reg_list_size; 1075 /* for clear state */ 1076 struct amdgpu_bo *clear_state_obj; 1077 uint64_t clear_state_gpu_addr; 1078 volatile uint32_t *cs_ptr; 1079 const struct cs_section_def *cs_data; 1080 u32 clear_state_size; 1081 /* for cp tables */ 1082 struct amdgpu_bo *cp_table_obj; 1083 uint64_t cp_table_gpu_addr; 1084 volatile uint32_t *cp_table_ptr; 1085 u32 cp_table_size; 1086 }; 1087 1088 struct amdgpu_mec { 1089 struct amdgpu_bo *hpd_eop_obj; 1090 u64 hpd_eop_gpu_addr; 1091 u32 num_pipe; 1092 u32 num_mec; 1093 u32 num_queue; 1094 }; 1095 1096 /* 1097 * GPU scratch registers structures, functions & helpers 1098 */ 1099 struct amdgpu_scratch { 1100 unsigned num_reg; 1101 uint32_t reg_base; 1102 bool free[32]; 1103 uint32_t reg[32]; 1104 }; 1105 1106 /* 1107 * GFX configurations 1108 */ 1109 struct amdgpu_gca_config { 1110 unsigned max_shader_engines; 1111 unsigned max_tile_pipes; 1112 unsigned max_cu_per_sh; 1113 unsigned max_sh_per_se; 1114 unsigned max_backends_per_se; 1115 unsigned max_texture_channel_caches; 1116 unsigned max_gprs; 1117 unsigned max_gs_threads; 1118 unsigned max_hw_contexts; 1119 unsigned sc_prim_fifo_size_frontend; 1120 unsigned sc_prim_fifo_size_backend; 1121 unsigned sc_hiz_tile_fifo_size; 1122 unsigned sc_earlyz_tile_fifo_size; 1123 1124 unsigned num_tile_pipes; 1125 unsigned backend_enable_mask; 1126 unsigned mem_max_burst_length_bytes; 1127 unsigned mem_row_size_in_kb; 1128 unsigned shader_engine_tile_size; 1129 unsigned num_gpus; 1130 unsigned multi_gpu_tile_size; 1131 unsigned mc_arb_ramcfg; 1132 unsigned gb_addr_config; 1133 1134 uint32_t tile_mode_array[32]; 1135 uint32_t macrotile_mode_array[16]; 1136 }; 1137 1138 struct amdgpu_gfx { 1139 struct mutex gpu_clock_mutex; 1140 struct amdgpu_gca_config config; 1141 struct amdgpu_rlc rlc; 1142 struct amdgpu_mec mec; 1143 struct amdgpu_scratch scratch; 1144 const struct firmware *me_fw; /* ME firmware */ 1145 uint32_t me_fw_version; 1146 const struct firmware *pfp_fw; /* PFP firmware */ 1147 uint32_t pfp_fw_version; 1148 const struct firmware *ce_fw; /* CE firmware */ 1149 uint32_t ce_fw_version; 1150 const struct firmware *rlc_fw; /* RLC firmware */ 1151 uint32_t rlc_fw_version; 1152 const struct firmware *mec_fw; /* MEC firmware */ 1153 uint32_t mec_fw_version; 1154 const struct firmware *mec2_fw; /* MEC2 firmware */ 1155 uint32_t mec2_fw_version; 1156 uint32_t me_feature_version; 1157 uint32_t ce_feature_version; 1158 uint32_t pfp_feature_version; 1159 uint32_t rlc_feature_version; 1160 uint32_t mec_feature_version; 1161 uint32_t mec2_feature_version; 1162 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1163 unsigned num_gfx_rings; 1164 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1165 unsigned num_compute_rings; 1166 struct amdgpu_irq_src eop_irq; 1167 struct amdgpu_irq_src priv_reg_irq; 1168 struct amdgpu_irq_src priv_inst_irq; 1169 /* gfx status */ 1170 uint32_t gfx_current_status; 1171 /* ce ram size*/ 1172 unsigned ce_ram_size; 1173 }; 1174 1175 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 1176 unsigned size, struct amdgpu_ib *ib); 1177 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib); 1178 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 1179 struct amdgpu_ib *ib, void *owner, 1180 struct fence *last_vm_update, 1181 struct fence **f); 1182 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1183 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1184 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1185 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1186 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 1187 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 1188 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1189 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1190 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1191 uint32_t **data); 1192 int amdgpu_ring_restore(struct amdgpu_ring *ring, 1193 unsigned size, uint32_t *data); 1194 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1195 unsigned ring_size, u32 nop, u32 align_mask, 1196 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1197 enum amdgpu_ring_type ring_type); 1198 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1199 struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f); 1200 1201 /* 1202 * CS. 1203 */ 1204 struct amdgpu_cs_chunk { 1205 uint32_t chunk_id; 1206 uint32_t length_dw; 1207 uint32_t *kdata; 1208 }; 1209 1210 struct amdgpu_cs_parser { 1211 struct amdgpu_device *adev; 1212 struct drm_file *filp; 1213 struct amdgpu_ctx *ctx; 1214 1215 /* chunks */ 1216 unsigned nchunks; 1217 struct amdgpu_cs_chunk *chunks; 1218 1219 /* scheduler job object */ 1220 struct amdgpu_job *job; 1221 1222 /* buffer objects */ 1223 struct ww_acquire_ctx ticket; 1224 struct amdgpu_bo_list *bo_list; 1225 struct amdgpu_bo_list_entry vm_pd; 1226 struct list_head validated; 1227 struct fence *fence; 1228 uint64_t bytes_moved_threshold; 1229 uint64_t bytes_moved; 1230 1231 /* user fence */ 1232 struct amdgpu_bo_list_entry uf_entry; 1233 }; 1234 1235 struct amdgpu_job { 1236 struct amd_sched_job base; 1237 struct amdgpu_device *adev; 1238 struct amdgpu_ring *ring; 1239 struct amdgpu_sync sync; 1240 struct amdgpu_ib *ibs; 1241 uint32_t num_ibs; 1242 void *owner; 1243 struct amdgpu_user_fence uf; 1244 }; 1245 #define to_amdgpu_job(sched_job) \ 1246 container_of((sched_job), struct amdgpu_job, base) 1247 1248 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 1249 uint32_t ib_idx, int idx) 1250 { 1251 return p->job->ibs[ib_idx].ptr[idx]; 1252 } 1253 1254 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 1255 uint32_t ib_idx, int idx, 1256 uint32_t value) 1257 { 1258 p->job->ibs[ib_idx].ptr[idx] = value; 1259 } 1260 1261 /* 1262 * Writeback 1263 */ 1264 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1265 1266 struct amdgpu_wb { 1267 struct amdgpu_bo *wb_obj; 1268 volatile uint32_t *wb; 1269 uint64_t gpu_addr; 1270 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1271 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1272 }; 1273 1274 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1275 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1276 1277 1278 1279 enum amdgpu_int_thermal_type { 1280 THERMAL_TYPE_NONE, 1281 THERMAL_TYPE_EXTERNAL, 1282 THERMAL_TYPE_EXTERNAL_GPIO, 1283 THERMAL_TYPE_RV6XX, 1284 THERMAL_TYPE_RV770, 1285 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1286 THERMAL_TYPE_EVERGREEN, 1287 THERMAL_TYPE_SUMO, 1288 THERMAL_TYPE_NI, 1289 THERMAL_TYPE_SI, 1290 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1291 THERMAL_TYPE_CI, 1292 THERMAL_TYPE_KV, 1293 }; 1294 1295 enum amdgpu_dpm_auto_throttle_src { 1296 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1297 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1298 }; 1299 1300 enum amdgpu_dpm_event_src { 1301 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1302 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1303 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1304 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1305 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1306 }; 1307 1308 #define AMDGPU_MAX_VCE_LEVELS 6 1309 1310 enum amdgpu_vce_level { 1311 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1312 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1313 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1314 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1315 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1316 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1317 }; 1318 1319 struct amdgpu_ps { 1320 u32 caps; /* vbios flags */ 1321 u32 class; /* vbios flags */ 1322 u32 class2; /* vbios flags */ 1323 /* UVD clocks */ 1324 u32 vclk; 1325 u32 dclk; 1326 /* VCE clocks */ 1327 u32 evclk; 1328 u32 ecclk; 1329 bool vce_active; 1330 enum amdgpu_vce_level vce_level; 1331 /* asic priv */ 1332 void *ps_priv; 1333 }; 1334 1335 struct amdgpu_dpm_thermal { 1336 /* thermal interrupt work */ 1337 struct work_struct work; 1338 /* low temperature threshold */ 1339 int min_temp; 1340 /* high temperature threshold */ 1341 int max_temp; 1342 /* was last interrupt low to high or high to low */ 1343 bool high_to_low; 1344 /* interrupt source */ 1345 struct amdgpu_irq_src irq; 1346 }; 1347 1348 enum amdgpu_clk_action 1349 { 1350 AMDGPU_SCLK_UP = 1, 1351 AMDGPU_SCLK_DOWN 1352 }; 1353 1354 struct amdgpu_blacklist_clocks 1355 { 1356 u32 sclk; 1357 u32 mclk; 1358 enum amdgpu_clk_action action; 1359 }; 1360 1361 struct amdgpu_clock_and_voltage_limits { 1362 u32 sclk; 1363 u32 mclk; 1364 u16 vddc; 1365 u16 vddci; 1366 }; 1367 1368 struct amdgpu_clock_array { 1369 u32 count; 1370 u32 *values; 1371 }; 1372 1373 struct amdgpu_clock_voltage_dependency_entry { 1374 u32 clk; 1375 u16 v; 1376 }; 1377 1378 struct amdgpu_clock_voltage_dependency_table { 1379 u32 count; 1380 struct amdgpu_clock_voltage_dependency_entry *entries; 1381 }; 1382 1383 union amdgpu_cac_leakage_entry { 1384 struct { 1385 u16 vddc; 1386 u32 leakage; 1387 }; 1388 struct { 1389 u16 vddc1; 1390 u16 vddc2; 1391 u16 vddc3; 1392 }; 1393 }; 1394 1395 struct amdgpu_cac_leakage_table { 1396 u32 count; 1397 union amdgpu_cac_leakage_entry *entries; 1398 }; 1399 1400 struct amdgpu_phase_shedding_limits_entry { 1401 u16 voltage; 1402 u32 sclk; 1403 u32 mclk; 1404 }; 1405 1406 struct amdgpu_phase_shedding_limits_table { 1407 u32 count; 1408 struct amdgpu_phase_shedding_limits_entry *entries; 1409 }; 1410 1411 struct amdgpu_uvd_clock_voltage_dependency_entry { 1412 u32 vclk; 1413 u32 dclk; 1414 u16 v; 1415 }; 1416 1417 struct amdgpu_uvd_clock_voltage_dependency_table { 1418 u8 count; 1419 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1420 }; 1421 1422 struct amdgpu_vce_clock_voltage_dependency_entry { 1423 u32 ecclk; 1424 u32 evclk; 1425 u16 v; 1426 }; 1427 1428 struct amdgpu_vce_clock_voltage_dependency_table { 1429 u8 count; 1430 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1431 }; 1432 1433 struct amdgpu_ppm_table { 1434 u8 ppm_design; 1435 u16 cpu_core_number; 1436 u32 platform_tdp; 1437 u32 small_ac_platform_tdp; 1438 u32 platform_tdc; 1439 u32 small_ac_platform_tdc; 1440 u32 apu_tdp; 1441 u32 dgpu_tdp; 1442 u32 dgpu_ulv_power; 1443 u32 tj_max; 1444 }; 1445 1446 struct amdgpu_cac_tdp_table { 1447 u16 tdp; 1448 u16 configurable_tdp; 1449 u16 tdc; 1450 u16 battery_power_limit; 1451 u16 small_power_limit; 1452 u16 low_cac_leakage; 1453 u16 high_cac_leakage; 1454 u16 maximum_power_delivery_limit; 1455 }; 1456 1457 struct amdgpu_dpm_dynamic_state { 1458 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1459 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1460 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1461 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1462 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1463 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1464 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1465 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1466 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1467 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1468 struct amdgpu_clock_array valid_sclk_values; 1469 struct amdgpu_clock_array valid_mclk_values; 1470 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1471 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1472 u32 mclk_sclk_ratio; 1473 u32 sclk_mclk_delta; 1474 u16 vddc_vddci_delta; 1475 u16 min_vddc_for_pcie_gen2; 1476 struct amdgpu_cac_leakage_table cac_leakage_table; 1477 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1478 struct amdgpu_ppm_table *ppm_table; 1479 struct amdgpu_cac_tdp_table *cac_tdp_table; 1480 }; 1481 1482 struct amdgpu_dpm_fan { 1483 u16 t_min; 1484 u16 t_med; 1485 u16 t_high; 1486 u16 pwm_min; 1487 u16 pwm_med; 1488 u16 pwm_high; 1489 u8 t_hyst; 1490 u32 cycle_delay; 1491 u16 t_max; 1492 u8 control_mode; 1493 u16 default_max_fan_pwm; 1494 u16 default_fan_output_sensitivity; 1495 u16 fan_output_sensitivity; 1496 bool ucode_fan_control; 1497 }; 1498 1499 enum amdgpu_pcie_gen { 1500 AMDGPU_PCIE_GEN1 = 0, 1501 AMDGPU_PCIE_GEN2 = 1, 1502 AMDGPU_PCIE_GEN3 = 2, 1503 AMDGPU_PCIE_GEN_INVALID = 0xffff 1504 }; 1505 1506 enum amdgpu_dpm_forced_level { 1507 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1508 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1509 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1510 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3, 1511 }; 1512 1513 struct amdgpu_vce_state { 1514 /* vce clocks */ 1515 u32 evclk; 1516 u32 ecclk; 1517 /* gpu clocks */ 1518 u32 sclk; 1519 u32 mclk; 1520 u8 clk_idx; 1521 u8 pstate; 1522 }; 1523 1524 struct amdgpu_dpm_funcs { 1525 int (*get_temperature)(struct amdgpu_device *adev); 1526 int (*pre_set_power_state)(struct amdgpu_device *adev); 1527 int (*set_power_state)(struct amdgpu_device *adev); 1528 void (*post_set_power_state)(struct amdgpu_device *adev); 1529 void (*display_configuration_changed)(struct amdgpu_device *adev); 1530 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1531 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1532 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1533 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1534 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1535 bool (*vblank_too_short)(struct amdgpu_device *adev); 1536 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1537 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1538 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1539 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1540 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1541 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1542 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1543 }; 1544 1545 struct amdgpu_dpm { 1546 struct amdgpu_ps *ps; 1547 /* number of valid power states */ 1548 int num_ps; 1549 /* current power state that is active */ 1550 struct amdgpu_ps *current_ps; 1551 /* requested power state */ 1552 struct amdgpu_ps *requested_ps; 1553 /* boot up power state */ 1554 struct amdgpu_ps *boot_ps; 1555 /* default uvd power state */ 1556 struct amdgpu_ps *uvd_ps; 1557 /* vce requirements */ 1558 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1559 enum amdgpu_vce_level vce_level; 1560 enum amd_pm_state_type state; 1561 enum amd_pm_state_type user_state; 1562 u32 platform_caps; 1563 u32 voltage_response_time; 1564 u32 backbias_response_time; 1565 void *priv; 1566 u32 new_active_crtcs; 1567 int new_active_crtc_count; 1568 u32 current_active_crtcs; 1569 int current_active_crtc_count; 1570 struct amdgpu_dpm_dynamic_state dyn_state; 1571 struct amdgpu_dpm_fan fan; 1572 u32 tdp_limit; 1573 u32 near_tdp_limit; 1574 u32 near_tdp_limit_adjusted; 1575 u32 sq_ramping_threshold; 1576 u32 cac_leakage; 1577 u16 tdp_od_limit; 1578 u32 tdp_adjustment; 1579 u16 load_line_slope; 1580 bool power_control; 1581 bool ac_power; 1582 /* special states active */ 1583 bool thermal_active; 1584 bool uvd_active; 1585 bool vce_active; 1586 /* thermal handling */ 1587 struct amdgpu_dpm_thermal thermal; 1588 /* forced levels */ 1589 enum amdgpu_dpm_forced_level forced_level; 1590 }; 1591 1592 struct amdgpu_pm { 1593 struct mutex mutex; 1594 u32 current_sclk; 1595 u32 current_mclk; 1596 u32 default_sclk; 1597 u32 default_mclk; 1598 struct amdgpu_i2c_chan *i2c_bus; 1599 /* internal thermal controller on rv6xx+ */ 1600 enum amdgpu_int_thermal_type int_thermal_type; 1601 struct device *int_hwmon_dev; 1602 /* fan control parameters */ 1603 bool no_fan; 1604 u8 fan_pulses_per_revolution; 1605 u8 fan_min_rpm; 1606 u8 fan_max_rpm; 1607 /* dpm */ 1608 bool dpm_enabled; 1609 bool sysfs_initialized; 1610 struct amdgpu_dpm dpm; 1611 const struct firmware *fw; /* SMC firmware */ 1612 uint32_t fw_version; 1613 const struct amdgpu_dpm_funcs *funcs; 1614 uint32_t pcie_gen_mask; 1615 uint32_t pcie_mlw_mask; 1616 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ 1617 }; 1618 1619 void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1620 1621 /* 1622 * UVD 1623 */ 1624 #define AMDGPU_MAX_UVD_HANDLES 10 1625 #define AMDGPU_UVD_STACK_SIZE (1024*1024) 1626 #define AMDGPU_UVD_HEAP_SIZE (1024*1024) 1627 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1628 1629 struct amdgpu_uvd { 1630 struct amdgpu_bo *vcpu_bo; 1631 void *cpu_addr; 1632 uint64_t gpu_addr; 1633 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1634 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1635 struct delayed_work idle_work; 1636 const struct firmware *fw; /* UVD firmware */ 1637 struct amdgpu_ring ring; 1638 struct amdgpu_irq_src irq; 1639 bool address_64_bit; 1640 }; 1641 1642 /* 1643 * VCE 1644 */ 1645 #define AMDGPU_MAX_VCE_HANDLES 16 1646 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1647 1648 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1649 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1650 1651 struct amdgpu_vce { 1652 struct amdgpu_bo *vcpu_bo; 1653 uint64_t gpu_addr; 1654 unsigned fw_version; 1655 unsigned fb_version; 1656 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1657 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1658 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1659 struct delayed_work idle_work; 1660 const struct firmware *fw; /* VCE firmware */ 1661 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1662 struct amdgpu_irq_src irq; 1663 unsigned harvest_config; 1664 }; 1665 1666 /* 1667 * SDMA 1668 */ 1669 struct amdgpu_sdma_instance { 1670 /* SDMA firmware */ 1671 const struct firmware *fw; 1672 uint32_t fw_version; 1673 uint32_t feature_version; 1674 1675 struct amdgpu_ring ring; 1676 bool burst_nop; 1677 }; 1678 1679 struct amdgpu_sdma { 1680 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1681 struct amdgpu_irq_src trap_irq; 1682 struct amdgpu_irq_src illegal_inst_irq; 1683 int num_instances; 1684 }; 1685 1686 /* 1687 * Firmware 1688 */ 1689 struct amdgpu_firmware { 1690 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1691 bool smu_load; 1692 struct amdgpu_bo *fw_buf; 1693 unsigned int fw_size; 1694 }; 1695 1696 /* 1697 * Benchmarking 1698 */ 1699 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1700 1701 1702 /* 1703 * Testing 1704 */ 1705 void amdgpu_test_moves(struct amdgpu_device *adev); 1706 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1707 struct amdgpu_ring *cpA, 1708 struct amdgpu_ring *cpB); 1709 void amdgpu_test_syncing(struct amdgpu_device *adev); 1710 1711 /* 1712 * MMU Notifier 1713 */ 1714 #if defined(CONFIG_MMU_NOTIFIER) 1715 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1716 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1717 #else 1718 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1719 { 1720 return -ENODEV; 1721 } 1722 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1723 #endif 1724 1725 /* 1726 * Debugfs 1727 */ 1728 struct amdgpu_debugfs { 1729 struct drm_info_list *files; 1730 unsigned num_files; 1731 }; 1732 1733 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1734 struct drm_info_list *files, 1735 unsigned nfiles); 1736 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1737 1738 #if defined(CONFIG_DEBUG_FS) 1739 int amdgpu_debugfs_init(struct drm_minor *minor); 1740 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1741 #endif 1742 1743 /* 1744 * amdgpu smumgr functions 1745 */ 1746 struct amdgpu_smumgr_funcs { 1747 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1748 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1749 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1750 }; 1751 1752 /* 1753 * amdgpu smumgr 1754 */ 1755 struct amdgpu_smumgr { 1756 struct amdgpu_bo *toc_buf; 1757 struct amdgpu_bo *smu_buf; 1758 /* asic priv smu data */ 1759 void *priv; 1760 spinlock_t smu_lock; 1761 /* smumgr functions */ 1762 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1763 /* ucode loading complete flag */ 1764 uint32_t fw_flags; 1765 }; 1766 1767 /* 1768 * ASIC specific register table accessible by UMD 1769 */ 1770 struct amdgpu_allowed_register_entry { 1771 uint32_t reg_offset; 1772 bool untouched; 1773 bool grbm_indexed; 1774 }; 1775 1776 struct amdgpu_cu_info { 1777 uint32_t number; /* total active CU number */ 1778 uint32_t ao_cu_mask; 1779 uint32_t bitmap[4][4]; 1780 }; 1781 1782 1783 /* 1784 * ASIC specific functions. 1785 */ 1786 struct amdgpu_asic_funcs { 1787 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1788 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1789 u8 *bios, u32 length_bytes); 1790 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1791 u32 sh_num, u32 reg_offset, u32 *value); 1792 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1793 int (*reset)(struct amdgpu_device *adev); 1794 /* wait for mc_idle */ 1795 int (*wait_for_mc_idle)(struct amdgpu_device *adev); 1796 /* get the reference clock */ 1797 u32 (*get_xclk)(struct amdgpu_device *adev); 1798 /* get the gpu clock counter */ 1799 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1800 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); 1801 /* MM block clocks */ 1802 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1803 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1804 }; 1805 1806 /* 1807 * IOCTL. 1808 */ 1809 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1810 struct drm_file *filp); 1811 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1812 struct drm_file *filp); 1813 1814 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1815 struct drm_file *filp); 1816 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1817 struct drm_file *filp); 1818 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1819 struct drm_file *filp); 1820 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1821 struct drm_file *filp); 1822 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1823 struct drm_file *filp); 1824 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1825 struct drm_file *filp); 1826 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1827 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1828 1829 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1830 struct drm_file *filp); 1831 1832 /* VRAM scratch page for HDP bug, default vram page */ 1833 struct amdgpu_vram_scratch { 1834 struct amdgpu_bo *robj; 1835 volatile uint32_t *ptr; 1836 u64 gpu_addr; 1837 }; 1838 1839 /* 1840 * ACPI 1841 */ 1842 struct amdgpu_atif_notification_cfg { 1843 bool enabled; 1844 int command_code; 1845 }; 1846 1847 struct amdgpu_atif_notifications { 1848 bool display_switch; 1849 bool expansion_mode_change; 1850 bool thermal_state; 1851 bool forced_power_state; 1852 bool system_power_state; 1853 bool display_conf_change; 1854 bool px_gfx_switch; 1855 bool brightness_change; 1856 bool dgpu_display_event; 1857 }; 1858 1859 struct amdgpu_atif_functions { 1860 bool system_params; 1861 bool sbios_requests; 1862 bool select_active_disp; 1863 bool lid_state; 1864 bool get_tv_standard; 1865 bool set_tv_standard; 1866 bool get_panel_expansion_mode; 1867 bool set_panel_expansion_mode; 1868 bool temperature_change; 1869 bool graphics_device_types; 1870 }; 1871 1872 struct amdgpu_atif { 1873 struct amdgpu_atif_notifications notifications; 1874 struct amdgpu_atif_functions functions; 1875 struct amdgpu_atif_notification_cfg notification_cfg; 1876 struct amdgpu_encoder *encoder_for_bl; 1877 }; 1878 1879 struct amdgpu_atcs_functions { 1880 bool get_ext_state; 1881 bool pcie_perf_req; 1882 bool pcie_dev_rdy; 1883 bool pcie_bus_width; 1884 }; 1885 1886 struct amdgpu_atcs { 1887 struct amdgpu_atcs_functions functions; 1888 }; 1889 1890 /* 1891 * CGS 1892 */ 1893 void *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1894 void amdgpu_cgs_destroy_device(void *cgs_device); 1895 1896 1897 /* 1898 * CGS 1899 */ 1900 void *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1901 void amdgpu_cgs_destroy_device(void *cgs_device); 1902 1903 1904 /* GPU virtualization */ 1905 struct amdgpu_virtualization { 1906 bool supports_sr_iov; 1907 }; 1908 1909 /* 1910 * Core structure, functions and helpers. 1911 */ 1912 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1913 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1914 1915 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1916 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1917 1918 struct amdgpu_ip_block_status { 1919 bool valid; 1920 bool sw; 1921 bool hw; 1922 }; 1923 1924 struct amdgpu_device { 1925 struct device *dev; 1926 struct drm_device *ddev; 1927 struct pci_dev *pdev; 1928 1929 #ifdef CONFIG_DRM_AMD_ACP 1930 struct amdgpu_acp acp; 1931 #endif 1932 1933 /* ASIC */ 1934 enum amd_asic_type asic_type; 1935 uint32_t family; 1936 uint32_t rev_id; 1937 uint32_t external_rev_id; 1938 unsigned long flags; 1939 int usec_timeout; 1940 const struct amdgpu_asic_funcs *asic_funcs; 1941 bool shutdown; 1942 bool suspend; 1943 bool need_dma32; 1944 bool accel_working; 1945 struct work_struct reset_work; 1946 struct notifier_block acpi_nb; 1947 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1948 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1949 unsigned debugfs_count; 1950 #if defined(CONFIG_DEBUG_FS) 1951 struct dentry *debugfs_regs; 1952 #endif 1953 struct amdgpu_atif atif; 1954 struct amdgpu_atcs atcs; 1955 struct mutex srbm_mutex; 1956 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1957 struct mutex grbm_idx_mutex; 1958 struct dev_pm_domain vga_pm_domain; 1959 bool have_disp_power_ref; 1960 1961 /* BIOS */ 1962 uint8_t *bios; 1963 bool is_atom_bios; 1964 uint16_t bios_header_start; 1965 struct amdgpu_bo *stollen_vga_memory; 1966 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1967 1968 /* Register/doorbell mmio */ 1969 resource_size_t rmmio_base; 1970 resource_size_t rmmio_size; 1971 void __iomem *rmmio; 1972 /* protects concurrent MM_INDEX/DATA based register access */ 1973 spinlock_t mmio_idx_lock; 1974 /* protects concurrent SMC based register access */ 1975 spinlock_t smc_idx_lock; 1976 amdgpu_rreg_t smc_rreg; 1977 amdgpu_wreg_t smc_wreg; 1978 /* protects concurrent PCIE register access */ 1979 spinlock_t pcie_idx_lock; 1980 amdgpu_rreg_t pcie_rreg; 1981 amdgpu_wreg_t pcie_wreg; 1982 /* protects concurrent UVD register access */ 1983 spinlock_t uvd_ctx_idx_lock; 1984 amdgpu_rreg_t uvd_ctx_rreg; 1985 amdgpu_wreg_t uvd_ctx_wreg; 1986 /* protects concurrent DIDT register access */ 1987 spinlock_t didt_idx_lock; 1988 amdgpu_rreg_t didt_rreg; 1989 amdgpu_wreg_t didt_wreg; 1990 /* protects concurrent ENDPOINT (audio) register access */ 1991 spinlock_t audio_endpt_idx_lock; 1992 amdgpu_block_rreg_t audio_endpt_rreg; 1993 amdgpu_block_wreg_t audio_endpt_wreg; 1994 void __iomem *rio_mem; 1995 resource_size_t rio_mem_size; 1996 struct amdgpu_doorbell doorbell; 1997 1998 /* clock/pll info */ 1999 struct amdgpu_clock clock; 2000 2001 /* MC */ 2002 struct amdgpu_mc mc; 2003 struct amdgpu_gart gart; 2004 struct amdgpu_dummy_page dummy_page; 2005 struct amdgpu_vm_manager vm_manager; 2006 2007 /* memory management */ 2008 struct amdgpu_mman mman; 2009 struct amdgpu_gem gem; 2010 struct amdgpu_vram_scratch vram_scratch; 2011 struct amdgpu_wb wb; 2012 atomic64_t vram_usage; 2013 atomic64_t vram_vis_usage; 2014 atomic64_t gtt_usage; 2015 atomic64_t num_bytes_moved; 2016 atomic_t gpu_reset_counter; 2017 2018 /* display */ 2019 struct amdgpu_mode_info mode_info; 2020 struct work_struct hotplug_work; 2021 struct amdgpu_irq_src crtc_irq; 2022 struct amdgpu_irq_src pageflip_irq; 2023 struct amdgpu_irq_src hpd_irq; 2024 2025 /* rings */ 2026 unsigned fence_context; 2027 unsigned num_rings; 2028 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 2029 bool ib_pool_ready; 2030 struct amdgpu_sa_manager ring_tmp_bo; 2031 2032 /* interrupts */ 2033 struct amdgpu_irq irq; 2034 2035 /* powerplay */ 2036 struct amd_powerplay powerplay; 2037 bool pp_enabled; 2038 bool pp_force_state_enabled; 2039 2040 /* dpm */ 2041 struct amdgpu_pm pm; 2042 u32 cg_flags; 2043 u32 pg_flags; 2044 2045 /* amdgpu smumgr */ 2046 struct amdgpu_smumgr smu; 2047 2048 /* gfx */ 2049 struct amdgpu_gfx gfx; 2050 2051 /* sdma */ 2052 struct amdgpu_sdma sdma; 2053 2054 /* uvd */ 2055 bool has_uvd; 2056 struct amdgpu_uvd uvd; 2057 2058 /* vce */ 2059 struct amdgpu_vce vce; 2060 2061 /* firmwares */ 2062 struct amdgpu_firmware firmware; 2063 2064 /* GDS */ 2065 struct amdgpu_gds gds; 2066 2067 const struct amdgpu_ip_block_version *ip_blocks; 2068 int num_ip_blocks; 2069 struct amdgpu_ip_block_status *ip_block_status; 2070 struct mutex mn_lock; 2071 DECLARE_HASHTABLE(mn_hash, 7); 2072 2073 /* tracking pinned memory */ 2074 u64 vram_pin_size; 2075 u64 gart_pin_size; 2076 2077 /* amdkfd interface */ 2078 struct kfd_dev *kfd; 2079 2080 /* kernel conext for IB submission */ 2081 struct amdgpu_ctx kernel_ctx; 2082 2083 struct amdgpu_virtualization virtualization; 2084 }; 2085 2086 bool amdgpu_device_is_px(struct drm_device *dev); 2087 int amdgpu_device_init(struct amdgpu_device *adev, 2088 struct drm_device *ddev, 2089 struct pci_dev *pdev, 2090 uint32_t flags); 2091 void amdgpu_device_fini(struct amdgpu_device *adev); 2092 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2093 2094 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2095 bool always_indirect); 2096 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2097 bool always_indirect); 2098 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2099 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2100 2101 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2102 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2103 2104 /* 2105 * Cast helper 2106 */ 2107 extern const struct fence_ops amdgpu_fence_ops; 2108 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) 2109 { 2110 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 2111 2112 if (__f->base.ops == &amdgpu_fence_ops) 2113 return __f; 2114 2115 return NULL; 2116 } 2117 2118 /* 2119 * Registers read & write functions. 2120 */ 2121 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2122 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2123 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2124 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2125 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2126 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2127 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2128 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2129 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2130 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2131 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2132 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2133 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2134 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2135 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2136 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2137 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2138 #define WREG32_P(reg, val, mask) \ 2139 do { \ 2140 uint32_t tmp_ = RREG32(reg); \ 2141 tmp_ &= (mask); \ 2142 tmp_ |= ((val) & ~(mask)); \ 2143 WREG32(reg, tmp_); \ 2144 } while (0) 2145 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2146 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2147 #define WREG32_PLL_P(reg, val, mask) \ 2148 do { \ 2149 uint32_t tmp_ = RREG32_PLL(reg); \ 2150 tmp_ &= (mask); \ 2151 tmp_ |= ((val) & ~(mask)); \ 2152 WREG32_PLL(reg, tmp_); \ 2153 } while (0) 2154 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2155 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2156 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2157 2158 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2159 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2160 2161 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2162 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2163 2164 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2165 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2166 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2167 2168 #define REG_GET_FIELD(value, reg, field) \ 2169 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2170 2171 /* 2172 * BIOS helpers. 2173 */ 2174 #define RBIOS8(i) (adev->bios[i]) 2175 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2176 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2177 2178 /* 2179 * RING helpers. 2180 */ 2181 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2182 { 2183 if (ring->count_dw <= 0) 2184 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2185 ring->ring[ring->wptr++] = v; 2186 ring->wptr &= ring->ptr_mask; 2187 ring->count_dw--; 2188 } 2189 2190 static inline struct amdgpu_sdma_instance * 2191 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 2192 { 2193 struct amdgpu_device *adev = ring->adev; 2194 int i; 2195 2196 for (i = 0; i < adev->sdma.num_instances; i++) 2197 if (&adev->sdma.instance[i].ring == ring) 2198 break; 2199 2200 if (i < AMDGPU_MAX_SDMA_INSTANCES) 2201 return &adev->sdma.instance[i]; 2202 else 2203 return NULL; 2204 } 2205 2206 /* 2207 * ASICs macro. 2208 */ 2209 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2210 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2211 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) 2212 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2213 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2214 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2215 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2216 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2217 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 2218 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2219 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) 2220 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2221 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2222 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2223 #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags))) 2224 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2225 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2226 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2227 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2228 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2229 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2230 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2231 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) 2232 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2233 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2234 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2235 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2236 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 2237 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2238 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2239 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2240 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2241 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2242 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2243 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2244 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2245 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2246 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2247 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2248 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2249 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2250 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) 2251 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2252 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2253 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2254 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2255 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2256 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 2257 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 2258 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2259 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2260 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2261 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2262 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2263 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2264 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2265 2266 #define amdgpu_dpm_get_temperature(adev) \ 2267 ((adev)->pp_enabled ? \ 2268 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ 2269 (adev)->pm.funcs->get_temperature((adev))) 2270 2271 #define amdgpu_dpm_set_fan_control_mode(adev, m) \ 2272 ((adev)->pp_enabled ? \ 2273 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ 2274 (adev)->pm.funcs->set_fan_control_mode((adev), (m))) 2275 2276 #define amdgpu_dpm_get_fan_control_mode(adev) \ 2277 ((adev)->pp_enabled ? \ 2278 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ 2279 (adev)->pm.funcs->get_fan_control_mode((adev))) 2280 2281 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ 2282 ((adev)->pp_enabled ? \ 2283 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 2284 (adev)->pm.funcs->set_fan_speed_percent((adev), (s))) 2285 2286 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ 2287 ((adev)->pp_enabled ? \ 2288 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 2289 (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) 2290 2291 #define amdgpu_dpm_get_sclk(adev, l) \ 2292 ((adev)->pp_enabled ? \ 2293 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ 2294 (adev)->pm.funcs->get_sclk((adev), (l))) 2295 2296 #define amdgpu_dpm_get_mclk(adev, l) \ 2297 ((adev)->pp_enabled ? \ 2298 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ 2299 (adev)->pm.funcs->get_mclk((adev), (l))) 2300 2301 2302 #define amdgpu_dpm_force_performance_level(adev, l) \ 2303 ((adev)->pp_enabled ? \ 2304 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ 2305 (adev)->pm.funcs->force_performance_level((adev), (l))) 2306 2307 #define amdgpu_dpm_powergate_uvd(adev, g) \ 2308 ((adev)->pp_enabled ? \ 2309 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ 2310 (adev)->pm.funcs->powergate_uvd((adev), (g))) 2311 2312 #define amdgpu_dpm_powergate_vce(adev, g) \ 2313 ((adev)->pp_enabled ? \ 2314 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ 2315 (adev)->pm.funcs->powergate_vce((adev), (g))) 2316 2317 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \ 2318 ((adev)->pp_enabled ? \ 2319 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \ 2320 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))) 2321 2322 #define amdgpu_dpm_get_current_power_state(adev) \ 2323 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) 2324 2325 #define amdgpu_dpm_get_performance_level(adev) \ 2326 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) 2327 2328 #define amdgpu_dpm_get_pp_num_states(adev, data) \ 2329 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data) 2330 2331 #define amdgpu_dpm_get_pp_table(adev, table) \ 2332 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table) 2333 2334 #define amdgpu_dpm_set_pp_table(adev, buf, size) \ 2335 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size) 2336 2337 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \ 2338 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf) 2339 2340 #define amdgpu_dpm_force_clock_level(adev, type, level) \ 2341 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level) 2342 2343 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ 2344 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) 2345 2346 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2347 2348 /* Common functions */ 2349 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2350 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2351 bool amdgpu_card_posted(struct amdgpu_device *adev); 2352 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2353 2354 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2355 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2356 u32 ip_instance, u32 ring, 2357 struct amdgpu_ring **out_ring); 2358 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2359 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2360 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2361 uint32_t flags); 2362 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 2363 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 2364 unsigned long end); 2365 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2366 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2367 struct ttm_mem_reg *mem); 2368 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2369 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2370 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2371 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2372 const u32 *registers, 2373 const u32 array_size); 2374 2375 bool amdgpu_device_is_px(struct drm_device *dev); 2376 /* atpx handler */ 2377 #if defined(CONFIG_VGA_SWITCHEROO) 2378 void amdgpu_register_atpx_handler(void); 2379 void amdgpu_unregister_atpx_handler(void); 2380 #else 2381 static inline void amdgpu_register_atpx_handler(void) {} 2382 static inline void amdgpu_unregister_atpx_handler(void) {} 2383 #endif 2384 2385 /* 2386 * KMS 2387 */ 2388 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2389 extern int amdgpu_max_kms_ioctl; 2390 2391 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2392 int amdgpu_driver_unload_kms(struct drm_device *dev); 2393 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2394 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2395 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2396 struct drm_file *file_priv); 2397 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2398 struct drm_file *file_priv); 2399 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2400 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2401 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 2402 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2403 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2404 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 2405 int *max_error, 2406 struct timeval *vblank_time, 2407 unsigned flags); 2408 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2409 unsigned long arg); 2410 2411 /* 2412 * functions used by amdgpu_encoder.c 2413 */ 2414 struct amdgpu_afmt_acr { 2415 u32 clock; 2416 2417 int n_32khz; 2418 int cts_32khz; 2419 2420 int n_44_1khz; 2421 int cts_44_1khz; 2422 2423 int n_48khz; 2424 int cts_48khz; 2425 2426 }; 2427 2428 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2429 2430 /* amdgpu_acpi.c */ 2431 #if defined(CONFIG_ACPI) 2432 int amdgpu_acpi_init(struct amdgpu_device *adev); 2433 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2434 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2435 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2436 u8 perf_req, bool advertise); 2437 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2438 #else 2439 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2440 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2441 #endif 2442 2443 struct amdgpu_bo_va_mapping * 2444 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2445 uint64_t addr, struct amdgpu_bo **bo); 2446 2447 #include "amdgpu_object.h" 2448 2449 #endif 2450