1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include "amdgpu_ctx.h" 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/rbtree.h> 38 #include <linux/hashtable.h> 39 #include <linux/dma-fence.h> 40 41 #include <drm/ttm/ttm_bo_api.h> 42 #include <drm/ttm/ttm_bo_driver.h> 43 #include <drm/ttm/ttm_placement.h> 44 #include <drm/ttm/ttm_module.h> 45 #include <drm/ttm/ttm_execbuf_util.h> 46 47 #include <drm/amdgpu_drm.h> 48 #include <drm/drm_gem.h> 49 #include <drm/drm_ioctl.h> 50 #include <drm/gpu_scheduler.h> 51 52 #include <kgd_kfd_interface.h> 53 #include "dm_pp_interface.h" 54 #include "kgd_pp_interface.h" 55 56 #include "amd_shared.h" 57 #include "amdgpu_mode.h" 58 #include "amdgpu_ih.h" 59 #include "amdgpu_irq.h" 60 #include "amdgpu_ucode.h" 61 #include "amdgpu_ttm.h" 62 #include "amdgpu_psp.h" 63 #include "amdgpu_gds.h" 64 #include "amdgpu_sync.h" 65 #include "amdgpu_ring.h" 66 #include "amdgpu_vm.h" 67 #include "amdgpu_dpm.h" 68 #include "amdgpu_acp.h" 69 #include "amdgpu_uvd.h" 70 #include "amdgpu_vce.h" 71 #include "amdgpu_vcn.h" 72 #include "amdgpu_mn.h" 73 #include "amdgpu_gmc.h" 74 #include "amdgpu_gfx.h" 75 #include "amdgpu_sdma.h" 76 #include "amdgpu_dm.h" 77 #include "amdgpu_virt.h" 78 #include "amdgpu_csa.h" 79 #include "amdgpu_gart.h" 80 #include "amdgpu_debugfs.h" 81 #include "amdgpu_job.h" 82 #include "amdgpu_bo_list.h" 83 #include "amdgpu_gem.h" 84 #include "amdgpu_doorbell.h" 85 #include "amdgpu_amdkfd.h" 86 #include "amdgpu_smu.h" 87 #include "amdgpu_discovery.h" 88 #include "amdgpu_mes.h" 89 90 #define MAX_GPU_INSTANCE 16 91 92 struct amdgpu_gpu_instance 93 { 94 struct amdgpu_device *adev; 95 int mgpu_fan_enabled; 96 }; 97 98 struct amdgpu_mgpu_info 99 { 100 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 101 struct mutex mutex; 102 uint32_t num_gpu; 103 uint32_t num_dgpu; 104 uint32_t num_apu; 105 }; 106 107 /* 108 * Modules parameters. 109 */ 110 extern int amdgpu_modeset; 111 extern int amdgpu_vram_limit; 112 extern int amdgpu_vis_vram_limit; 113 extern int amdgpu_gart_size; 114 extern int amdgpu_gtt_size; 115 extern int amdgpu_moverate; 116 extern int amdgpu_benchmarking; 117 extern int amdgpu_testing; 118 extern int amdgpu_audio; 119 extern int amdgpu_disp_priority; 120 extern int amdgpu_hw_i2c; 121 extern int amdgpu_pcie_gen2; 122 extern int amdgpu_msi; 123 extern int amdgpu_dpm; 124 extern int amdgpu_fw_load_type; 125 extern int amdgpu_aspm; 126 extern int amdgpu_runtime_pm; 127 extern uint amdgpu_ip_block_mask; 128 extern int amdgpu_bapm; 129 extern int amdgpu_deep_color; 130 extern int amdgpu_vm_size; 131 extern int amdgpu_vm_block_size; 132 extern int amdgpu_vm_fragment_size; 133 extern int amdgpu_vm_fault_stop; 134 extern int amdgpu_vm_debug; 135 extern int amdgpu_vm_update_mode; 136 extern int amdgpu_dc; 137 extern int amdgpu_sched_jobs; 138 extern int amdgpu_sched_hw_submission; 139 extern uint amdgpu_pcie_gen_cap; 140 extern uint amdgpu_pcie_lane_cap; 141 extern uint amdgpu_cg_mask; 142 extern uint amdgpu_pg_mask; 143 extern uint amdgpu_sdma_phase_quantum; 144 extern char *amdgpu_disable_cu; 145 extern char *amdgpu_virtual_display; 146 extern uint amdgpu_pp_feature_mask; 147 extern int amdgpu_ngg; 148 extern int amdgpu_prim_buf_per_se; 149 extern int amdgpu_pos_buf_per_se; 150 extern int amdgpu_cntl_sb_buf_per_se; 151 extern int amdgpu_param_buf_per_se; 152 extern int amdgpu_job_hang_limit; 153 extern int amdgpu_lbpw; 154 extern int amdgpu_compute_multipipe; 155 extern int amdgpu_gpu_recovery; 156 extern int amdgpu_emu_mode; 157 extern uint amdgpu_smu_memory_pool_size; 158 extern uint amdgpu_dc_feature_mask; 159 extern uint amdgpu_dm_abm_level; 160 extern struct amdgpu_mgpu_info mgpu_info; 161 extern int amdgpu_ras_enable; 162 extern uint amdgpu_ras_mask; 163 extern int amdgpu_async_gfx_ring; 164 extern int amdgpu_mcbp; 165 extern int amdgpu_discovery; 166 extern int amdgpu_mes; 167 168 #ifdef CONFIG_DRM_AMDGPU_SI 169 extern int amdgpu_si_support; 170 #endif 171 #ifdef CONFIG_DRM_AMDGPU_CIK 172 extern int amdgpu_cik_support; 173 #endif 174 175 #define AMDGPU_VM_MAX_NUM_CTX 4096 176 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 177 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 178 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 179 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 180 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 181 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 182 #define AMDGPU_IB_POOL_SIZE 16 183 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 184 #define AMDGPUFB_CONN_LIMIT 4 185 #define AMDGPU_BIOS_NUM_SCRATCH 16 186 187 /* hard reset data */ 188 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 189 190 /* reset flags */ 191 #define AMDGPU_RESET_GFX (1 << 0) 192 #define AMDGPU_RESET_COMPUTE (1 << 1) 193 #define AMDGPU_RESET_DMA (1 << 2) 194 #define AMDGPU_RESET_CP (1 << 3) 195 #define AMDGPU_RESET_GRBM (1 << 4) 196 #define AMDGPU_RESET_DMA1 (1 << 5) 197 #define AMDGPU_RESET_RLC (1 << 6) 198 #define AMDGPU_RESET_SEM (1 << 7) 199 #define AMDGPU_RESET_IH (1 << 8) 200 #define AMDGPU_RESET_VMC (1 << 9) 201 #define AMDGPU_RESET_MC (1 << 10) 202 #define AMDGPU_RESET_DISPLAY (1 << 11) 203 #define AMDGPU_RESET_UVD (1 << 12) 204 #define AMDGPU_RESET_VCE (1 << 13) 205 #define AMDGPU_RESET_VCE1 (1 << 14) 206 207 /* max cursor sizes (in pixels) */ 208 #define CIK_CURSOR_WIDTH 128 209 #define CIK_CURSOR_HEIGHT 128 210 211 struct amdgpu_device; 212 struct amdgpu_ib; 213 struct amdgpu_cs_parser; 214 struct amdgpu_job; 215 struct amdgpu_irq_src; 216 struct amdgpu_fpriv; 217 struct amdgpu_bo_va_mapping; 218 struct amdgpu_atif; 219 struct kfd_vm_fault_info; 220 221 enum amdgpu_cp_irq { 222 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 223 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 224 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 225 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 226 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 227 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 228 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 229 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 230 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 231 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 232 233 AMDGPU_CP_IRQ_LAST 234 }; 235 236 enum amdgpu_thermal_irq { 237 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 238 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 239 240 AMDGPU_THERMAL_IRQ_LAST 241 }; 242 243 enum amdgpu_kiq_irq { 244 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 245 AMDGPU_CP_KIQ_IRQ_LAST 246 }; 247 248 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 249 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 250 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 251 252 int amdgpu_device_ip_set_clockgating_state(void *dev, 253 enum amd_ip_block_type block_type, 254 enum amd_clockgating_state state); 255 int amdgpu_device_ip_set_powergating_state(void *dev, 256 enum amd_ip_block_type block_type, 257 enum amd_powergating_state state); 258 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 259 u32 *flags); 260 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 261 enum amd_ip_block_type block_type); 262 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 263 enum amd_ip_block_type block_type); 264 265 #define AMDGPU_MAX_IP_NUM 16 266 267 struct amdgpu_ip_block_status { 268 bool valid; 269 bool sw; 270 bool hw; 271 bool late_initialized; 272 bool hang; 273 }; 274 275 struct amdgpu_ip_block_version { 276 const enum amd_ip_block_type type; 277 const u32 major; 278 const u32 minor; 279 const u32 rev; 280 const struct amd_ip_funcs *funcs; 281 }; 282 283 struct amdgpu_ip_block { 284 struct amdgpu_ip_block_status status; 285 const struct amdgpu_ip_block_version *version; 286 }; 287 288 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 289 enum amd_ip_block_type type, 290 u32 major, u32 minor); 291 292 struct amdgpu_ip_block * 293 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 294 enum amd_ip_block_type type); 295 296 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 297 const struct amdgpu_ip_block_version *ip_block_version); 298 299 /* 300 * BIOS. 301 */ 302 bool amdgpu_get_bios(struct amdgpu_device *adev); 303 bool amdgpu_read_bios(struct amdgpu_device *adev); 304 305 /* 306 * Clocks 307 */ 308 309 #define AMDGPU_MAX_PPLL 3 310 311 struct amdgpu_clock { 312 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 313 struct amdgpu_pll spll; 314 struct amdgpu_pll mpll; 315 /* 10 Khz units */ 316 uint32_t default_mclk; 317 uint32_t default_sclk; 318 uint32_t default_dispclk; 319 uint32_t current_dispclk; 320 uint32_t dp_extclk; 321 uint32_t max_pixel_clock; 322 }; 323 324 /* sub-allocation manager, it has to be protected by another lock. 325 * By conception this is an helper for other part of the driver 326 * like the indirect buffer or semaphore, which both have their 327 * locking. 328 * 329 * Principe is simple, we keep a list of sub allocation in offset 330 * order (first entry has offset == 0, last entry has the highest 331 * offset). 332 * 333 * When allocating new object we first check if there is room at 334 * the end total_size - (last_object_offset + last_object_size) >= 335 * alloc_size. If so we allocate new object there. 336 * 337 * When there is not enough room at the end, we start waiting for 338 * each sub object until we reach object_offset+object_size >= 339 * alloc_size, this object then become the sub object we return. 340 * 341 * Alignment can't be bigger than page size. 342 * 343 * Hole are not considered for allocation to keep things simple. 344 * Assumption is that there won't be hole (all object on same 345 * alignment). 346 */ 347 348 #define AMDGPU_SA_NUM_FENCE_LISTS 32 349 350 struct amdgpu_sa_manager { 351 wait_queue_head_t wq; 352 struct amdgpu_bo *bo; 353 struct list_head *hole; 354 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 355 struct list_head olist; 356 unsigned size; 357 uint64_t gpu_addr; 358 void *cpu_ptr; 359 uint32_t domain; 360 uint32_t align; 361 }; 362 363 /* sub-allocation buffer */ 364 struct amdgpu_sa_bo { 365 struct list_head olist; 366 struct list_head flist; 367 struct amdgpu_sa_manager *manager; 368 unsigned soffset; 369 unsigned eoffset; 370 struct dma_fence *fence; 371 }; 372 373 int amdgpu_fence_slab_init(void); 374 void amdgpu_fence_slab_fini(void); 375 376 /* 377 * IRQS. 378 */ 379 380 struct amdgpu_flip_work { 381 struct delayed_work flip_work; 382 struct work_struct unpin_work; 383 struct amdgpu_device *adev; 384 int crtc_id; 385 u32 target_vblank; 386 uint64_t base; 387 struct drm_pending_vblank_event *event; 388 struct amdgpu_bo *old_abo; 389 struct dma_fence *excl; 390 unsigned shared_count; 391 struct dma_fence **shared; 392 struct dma_fence_cb cb; 393 bool async; 394 }; 395 396 397 /* 398 * CP & rings. 399 */ 400 401 struct amdgpu_ib { 402 struct amdgpu_sa_bo *sa_bo; 403 uint32_t length_dw; 404 uint64_t gpu_addr; 405 uint32_t *ptr; 406 uint32_t flags; 407 }; 408 409 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 410 411 /* 412 * file private structure 413 */ 414 415 struct amdgpu_fpriv { 416 struct amdgpu_vm vm; 417 struct amdgpu_bo_va *prt_va; 418 struct amdgpu_bo_va *csa_va; 419 struct mutex bo_list_lock; 420 struct idr bo_list_handles; 421 struct amdgpu_ctx_mgr ctx_mgr; 422 }; 423 424 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 425 int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev); 426 427 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 428 unsigned size, struct amdgpu_ib *ib); 429 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 430 struct dma_fence *f); 431 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 432 struct amdgpu_ib *ibs, struct amdgpu_job *job, 433 struct dma_fence **f); 434 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 435 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 436 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 437 438 /* 439 * CS. 440 */ 441 struct amdgpu_cs_chunk { 442 uint32_t chunk_id; 443 uint32_t length_dw; 444 void *kdata; 445 }; 446 447 struct amdgpu_cs_post_dep { 448 struct drm_syncobj *syncobj; 449 struct dma_fence_chain *chain; 450 u64 point; 451 }; 452 453 struct amdgpu_cs_parser { 454 struct amdgpu_device *adev; 455 struct drm_file *filp; 456 struct amdgpu_ctx *ctx; 457 458 /* chunks */ 459 unsigned nchunks; 460 struct amdgpu_cs_chunk *chunks; 461 462 /* scheduler job object */ 463 struct amdgpu_job *job; 464 struct drm_sched_entity *entity; 465 466 /* buffer objects */ 467 struct ww_acquire_ctx ticket; 468 struct amdgpu_bo_list *bo_list; 469 struct amdgpu_mn *mn; 470 struct amdgpu_bo_list_entry vm_pd; 471 struct list_head validated; 472 struct dma_fence *fence; 473 uint64_t bytes_moved_threshold; 474 uint64_t bytes_moved_vis_threshold; 475 uint64_t bytes_moved; 476 uint64_t bytes_moved_vis; 477 struct amdgpu_bo_list_entry *evictable; 478 479 /* user fence */ 480 struct amdgpu_bo_list_entry uf_entry; 481 482 unsigned num_post_deps; 483 struct amdgpu_cs_post_dep *post_deps; 484 }; 485 486 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 487 uint32_t ib_idx, int idx) 488 { 489 return p->job->ibs[ib_idx].ptr[idx]; 490 } 491 492 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 493 uint32_t ib_idx, int idx, 494 uint32_t value) 495 { 496 p->job->ibs[ib_idx].ptr[idx] = value; 497 } 498 499 /* 500 * Writeback 501 */ 502 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 503 504 struct amdgpu_wb { 505 struct amdgpu_bo *wb_obj; 506 volatile uint32_t *wb; 507 uint64_t gpu_addr; 508 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 509 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 510 }; 511 512 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 513 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 514 515 /* 516 * Benchmarking 517 */ 518 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 519 520 521 /* 522 * Testing 523 */ 524 void amdgpu_test_moves(struct amdgpu_device *adev); 525 526 /* 527 * ASIC specific register table accessible by UMD 528 */ 529 struct amdgpu_allowed_register_entry { 530 uint32_t reg_offset; 531 bool grbm_indexed; 532 }; 533 534 /* 535 * ASIC specific functions. 536 */ 537 struct amdgpu_asic_funcs { 538 bool (*read_disabled_bios)(struct amdgpu_device *adev); 539 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 540 u8 *bios, u32 length_bytes); 541 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 542 u32 sh_num, u32 reg_offset, u32 *value); 543 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 544 int (*reset)(struct amdgpu_device *adev); 545 /* get the reference clock */ 546 u32 (*get_xclk)(struct amdgpu_device *adev); 547 /* MM block clocks */ 548 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 549 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 550 /* static power management */ 551 int (*get_pcie_lanes)(struct amdgpu_device *adev); 552 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 553 /* get config memsize register */ 554 u32 (*get_config_memsize)(struct amdgpu_device *adev); 555 /* flush hdp write queue */ 556 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 557 /* invalidate hdp read cache */ 558 void (*invalidate_hdp)(struct amdgpu_device *adev, 559 struct amdgpu_ring *ring); 560 /* check if the asic needs a full reset of if soft reset will work */ 561 bool (*need_full_reset)(struct amdgpu_device *adev); 562 /* initialize doorbell layout for specific asic*/ 563 void (*init_doorbell_index)(struct amdgpu_device *adev); 564 /* PCIe bandwidth usage */ 565 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 566 uint64_t *count1); 567 /* do we need to reset the asic at init time (e.g., kexec) */ 568 bool (*need_reset_on_init)(struct amdgpu_device *adev); 569 /* PCIe replay counter */ 570 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 571 }; 572 573 /* 574 * IOCTL. 575 */ 576 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 577 struct drm_file *filp); 578 579 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 580 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 581 struct drm_file *filp); 582 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 583 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 584 struct drm_file *filp); 585 586 /* VRAM scratch page for HDP bug, default vram page */ 587 struct amdgpu_vram_scratch { 588 struct amdgpu_bo *robj; 589 volatile uint32_t *ptr; 590 u64 gpu_addr; 591 }; 592 593 /* 594 * ACPI 595 */ 596 struct amdgpu_atcs_functions { 597 bool get_ext_state; 598 bool pcie_perf_req; 599 bool pcie_dev_rdy; 600 bool pcie_bus_width; 601 }; 602 603 struct amdgpu_atcs { 604 struct amdgpu_atcs_functions functions; 605 }; 606 607 /* 608 * Firmware VRAM reservation 609 */ 610 struct amdgpu_fw_vram_usage { 611 u64 start_offset; 612 u64 size; 613 struct amdgpu_bo *reserved_bo; 614 void *va; 615 }; 616 617 /* 618 * CGS 619 */ 620 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 621 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 622 623 /* 624 * Core structure, functions and helpers. 625 */ 626 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 627 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 628 629 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 630 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 631 632 633 /* 634 * amdgpu nbio functions 635 * 636 */ 637 struct nbio_hdp_flush_reg { 638 u32 ref_and_mask_cp0; 639 u32 ref_and_mask_cp1; 640 u32 ref_and_mask_cp2; 641 u32 ref_and_mask_cp3; 642 u32 ref_and_mask_cp4; 643 u32 ref_and_mask_cp5; 644 u32 ref_and_mask_cp6; 645 u32 ref_and_mask_cp7; 646 u32 ref_and_mask_cp8; 647 u32 ref_and_mask_cp9; 648 u32 ref_and_mask_sdma0; 649 u32 ref_and_mask_sdma1; 650 }; 651 652 struct amdgpu_mmio_remap { 653 u32 reg_offset; 654 resource_size_t bus_addr; 655 }; 656 657 struct amdgpu_nbio_funcs { 658 const struct nbio_hdp_flush_reg *hdp_flush_reg; 659 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 660 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 661 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 662 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 663 u32 (*get_rev_id)(struct amdgpu_device *adev); 664 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 665 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 666 u32 (*get_memsize)(struct amdgpu_device *adev); 667 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 668 bool use_doorbell, int doorbell_index, int doorbell_size); 669 void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell, 670 int doorbell_index); 671 void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 672 bool enable); 673 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 674 bool enable); 675 void (*ih_doorbell_range)(struct amdgpu_device *adev, 676 bool use_doorbell, int doorbell_index); 677 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 678 bool enable); 679 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 680 bool enable); 681 void (*get_clockgating_state)(struct amdgpu_device *adev, 682 u32 *flags); 683 void (*ih_control)(struct amdgpu_device *adev); 684 void (*init_registers)(struct amdgpu_device *adev); 685 void (*detect_hw_virt)(struct amdgpu_device *adev); 686 void (*remap_hdp_registers)(struct amdgpu_device *adev); 687 }; 688 689 struct amdgpu_df_funcs { 690 void (*sw_init)(struct amdgpu_device *adev); 691 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 692 bool enable); 693 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 694 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 695 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 696 bool enable); 697 void (*get_clockgating_state)(struct amdgpu_device *adev, 698 u32 *flags); 699 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 700 bool enable); 701 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config, 702 int is_enable); 703 int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config, 704 int is_disable); 705 void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config, 706 uint64_t *count); 707 }; 708 /* Define the HW IP blocks will be used in driver , add more if necessary */ 709 enum amd_hw_ip_block_type { 710 GC_HWIP = 1, 711 HDP_HWIP, 712 SDMA0_HWIP, 713 SDMA1_HWIP, 714 MMHUB_HWIP, 715 ATHUB_HWIP, 716 NBIO_HWIP, 717 MP0_HWIP, 718 MP1_HWIP, 719 UVD_HWIP, 720 VCN_HWIP = UVD_HWIP, 721 VCE_HWIP, 722 DF_HWIP, 723 DCE_HWIP, 724 OSSSYS_HWIP, 725 SMUIO_HWIP, 726 PWR_HWIP, 727 NBIF_HWIP, 728 THM_HWIP, 729 CLK_HWIP, 730 MAX_HWIP 731 }; 732 733 #define HWIP_MAX_INSTANCE 6 734 735 struct amd_powerplay { 736 void *pp_handle; 737 const struct amd_pm_funcs *pp_funcs; 738 }; 739 740 #define AMDGPU_RESET_MAGIC_NUM 64 741 #define AMDGPU_MAX_DF_PERFMONS 4 742 struct amdgpu_device { 743 struct device *dev; 744 struct drm_device *ddev; 745 struct pci_dev *pdev; 746 747 #ifdef CONFIG_DRM_AMD_ACP 748 struct amdgpu_acp acp; 749 #endif 750 751 /* ASIC */ 752 enum amd_asic_type asic_type; 753 uint32_t family; 754 uint32_t rev_id; 755 uint32_t external_rev_id; 756 unsigned long flags; 757 int usec_timeout; 758 const struct amdgpu_asic_funcs *asic_funcs; 759 bool shutdown; 760 bool need_dma32; 761 bool need_swiotlb; 762 bool accel_working; 763 struct notifier_block acpi_nb; 764 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 765 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 766 unsigned debugfs_count; 767 #if defined(CONFIG_DEBUG_FS) 768 struct dentry *debugfs_preempt; 769 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 770 #endif 771 struct amdgpu_atif *atif; 772 struct amdgpu_atcs atcs; 773 struct mutex srbm_mutex; 774 /* GRBM index mutex. Protects concurrent access to GRBM index */ 775 struct mutex grbm_idx_mutex; 776 struct dev_pm_domain vga_pm_domain; 777 bool have_disp_power_ref; 778 bool have_atomics_support; 779 780 /* BIOS */ 781 bool is_atom_fw; 782 uint8_t *bios; 783 uint32_t bios_size; 784 struct amdgpu_bo *stolen_vga_memory; 785 uint32_t bios_scratch_reg_offset; 786 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 787 788 /* Register/doorbell mmio */ 789 resource_size_t rmmio_base; 790 resource_size_t rmmio_size; 791 void __iomem *rmmio; 792 /* protects concurrent MM_INDEX/DATA based register access */ 793 spinlock_t mmio_idx_lock; 794 struct amdgpu_mmio_remap rmmio_remap; 795 /* protects concurrent SMC based register access */ 796 spinlock_t smc_idx_lock; 797 amdgpu_rreg_t smc_rreg; 798 amdgpu_wreg_t smc_wreg; 799 /* protects concurrent PCIE register access */ 800 spinlock_t pcie_idx_lock; 801 amdgpu_rreg_t pcie_rreg; 802 amdgpu_wreg_t pcie_wreg; 803 amdgpu_rreg_t pciep_rreg; 804 amdgpu_wreg_t pciep_wreg; 805 /* protects concurrent UVD register access */ 806 spinlock_t uvd_ctx_idx_lock; 807 amdgpu_rreg_t uvd_ctx_rreg; 808 amdgpu_wreg_t uvd_ctx_wreg; 809 /* protects concurrent DIDT register access */ 810 spinlock_t didt_idx_lock; 811 amdgpu_rreg_t didt_rreg; 812 amdgpu_wreg_t didt_wreg; 813 /* protects concurrent gc_cac register access */ 814 spinlock_t gc_cac_idx_lock; 815 amdgpu_rreg_t gc_cac_rreg; 816 amdgpu_wreg_t gc_cac_wreg; 817 /* protects concurrent se_cac register access */ 818 spinlock_t se_cac_idx_lock; 819 amdgpu_rreg_t se_cac_rreg; 820 amdgpu_wreg_t se_cac_wreg; 821 /* protects concurrent ENDPOINT (audio) register access */ 822 spinlock_t audio_endpt_idx_lock; 823 amdgpu_block_rreg_t audio_endpt_rreg; 824 amdgpu_block_wreg_t audio_endpt_wreg; 825 void __iomem *rio_mem; 826 resource_size_t rio_mem_size; 827 struct amdgpu_doorbell doorbell; 828 829 /* clock/pll info */ 830 struct amdgpu_clock clock; 831 832 /* MC */ 833 struct amdgpu_gmc gmc; 834 struct amdgpu_gart gart; 835 dma_addr_t dummy_page_addr; 836 struct amdgpu_vm_manager vm_manager; 837 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 838 839 /* memory management */ 840 struct amdgpu_mman mman; 841 struct amdgpu_vram_scratch vram_scratch; 842 struct amdgpu_wb wb; 843 atomic64_t num_bytes_moved; 844 atomic64_t num_evictions; 845 atomic64_t num_vram_cpu_page_faults; 846 atomic_t gpu_reset_counter; 847 atomic_t vram_lost_counter; 848 849 /* data for buffer migration throttling */ 850 struct { 851 spinlock_t lock; 852 s64 last_update_us; 853 s64 accum_us; /* accumulated microseconds */ 854 s64 accum_us_vis; /* for visible VRAM */ 855 u32 log2_max_MBps; 856 } mm_stats; 857 858 /* display */ 859 bool enable_virtual_display; 860 struct amdgpu_mode_info mode_info; 861 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 862 struct work_struct hotplug_work; 863 struct amdgpu_irq_src crtc_irq; 864 struct amdgpu_irq_src vupdate_irq; 865 struct amdgpu_irq_src pageflip_irq; 866 struct amdgpu_irq_src hpd_irq; 867 868 /* rings */ 869 u64 fence_context; 870 unsigned num_rings; 871 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 872 bool ib_pool_ready; 873 struct amdgpu_sa_manager ring_tmp_bo; 874 875 /* interrupts */ 876 struct amdgpu_irq irq; 877 878 /* powerplay */ 879 struct amd_powerplay powerplay; 880 bool pp_force_state_enabled; 881 882 /* smu */ 883 struct smu_context smu; 884 885 /* dpm */ 886 struct amdgpu_pm pm; 887 u32 cg_flags; 888 u32 pg_flags; 889 890 /* gfx */ 891 struct amdgpu_gfx gfx; 892 893 /* sdma */ 894 struct amdgpu_sdma sdma; 895 896 /* uvd */ 897 struct amdgpu_uvd uvd; 898 899 /* vce */ 900 struct amdgpu_vce vce; 901 902 /* vcn */ 903 struct amdgpu_vcn vcn; 904 905 /* firmwares */ 906 struct amdgpu_firmware firmware; 907 908 /* PSP */ 909 struct psp_context psp; 910 911 /* GDS */ 912 struct amdgpu_gds gds; 913 914 /* KFD */ 915 struct amdgpu_kfd_dev kfd; 916 917 /* display related functionality */ 918 struct amdgpu_display_manager dm; 919 920 /* discovery */ 921 uint8_t *discovery; 922 923 /* mes */ 924 bool enable_mes; 925 struct amdgpu_mes mes; 926 927 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 928 int num_ip_blocks; 929 struct mutex mn_lock; 930 DECLARE_HASHTABLE(mn_hash, 7); 931 932 /* tracking pinned memory */ 933 atomic64_t vram_pin_size; 934 atomic64_t visible_pin_size; 935 atomic64_t gart_pin_size; 936 937 /* soc15 register offset based on ip, instance and segment */ 938 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 939 940 const struct amdgpu_nbio_funcs *nbio_funcs; 941 const struct amdgpu_df_funcs *df_funcs; 942 943 /* delayed work_func for deferring clockgating during resume */ 944 struct delayed_work delayed_init_work; 945 946 struct amdgpu_virt virt; 947 /* firmware VRAM reservation */ 948 struct amdgpu_fw_vram_usage fw_vram_usage; 949 950 /* link all shadow bo */ 951 struct list_head shadow_list; 952 struct mutex shadow_list_lock; 953 /* keep an lru list of rings by HW IP */ 954 struct list_head ring_lru_list; 955 spinlock_t ring_lru_list_lock; 956 957 /* record hw reset is performed */ 958 bool has_hw_reset; 959 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 960 961 /* s3/s4 mask */ 962 bool in_suspend; 963 964 /* record last mm index being written through WREG32*/ 965 unsigned long last_mm_index; 966 bool in_gpu_reset; 967 struct mutex lock_reset; 968 struct amdgpu_doorbell_index doorbell_index; 969 970 int asic_reset_res; 971 struct work_struct xgmi_reset_work; 972 973 bool in_baco_reset; 974 975 long gfx_timeout; 976 long sdma_timeout; 977 long video_timeout; 978 long compute_timeout; 979 980 uint64_t unique_id; 981 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 982 }; 983 984 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 985 { 986 return container_of(bdev, struct amdgpu_device, mman.bdev); 987 } 988 989 int amdgpu_device_init(struct amdgpu_device *adev, 990 struct drm_device *ddev, 991 struct pci_dev *pdev, 992 uint32_t flags); 993 void amdgpu_device_fini(struct amdgpu_device *adev); 994 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 995 996 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 997 uint32_t acc_flags); 998 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 999 uint32_t acc_flags); 1000 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1001 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1002 1003 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1004 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1005 1006 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1007 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1008 1009 int emu_soc_asic_init(struct amdgpu_device *adev); 1010 1011 /* 1012 * Registers read & write functions. 1013 */ 1014 1015 #define AMDGPU_REGS_IDX (1<<0) 1016 #define AMDGPU_REGS_NO_KIQ (1<<1) 1017 1018 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1019 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1020 1021 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1022 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1023 1024 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1025 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1026 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1027 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1028 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1029 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1030 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1031 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1032 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1033 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1034 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1035 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1036 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1037 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1038 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1039 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1040 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1041 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1042 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1043 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1044 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1045 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1046 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1047 #define WREG32_P(reg, val, mask) \ 1048 do { \ 1049 uint32_t tmp_ = RREG32(reg); \ 1050 tmp_ &= (mask); \ 1051 tmp_ |= ((val) & ~(mask)); \ 1052 WREG32(reg, tmp_); \ 1053 } while (0) 1054 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1055 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1056 #define WREG32_PLL_P(reg, val, mask) \ 1057 do { \ 1058 uint32_t tmp_ = RREG32_PLL(reg); \ 1059 tmp_ &= (mask); \ 1060 tmp_ |= ((val) & ~(mask)); \ 1061 WREG32_PLL(reg, tmp_); \ 1062 } while (0) 1063 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1064 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1065 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1066 1067 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1068 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1069 1070 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1071 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1072 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1073 1074 #define REG_GET_FIELD(value, reg, field) \ 1075 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1076 1077 #define WREG32_FIELD(reg, field, val) \ 1078 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1079 1080 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1081 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1082 1083 /* 1084 * BIOS helpers. 1085 */ 1086 #define RBIOS8(i) (adev->bios[i]) 1087 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1088 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1089 1090 /* 1091 * ASICs macro. 1092 */ 1093 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1094 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1095 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1096 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1097 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1098 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1099 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1100 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1101 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1102 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1103 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1104 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1105 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1106 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1107 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1108 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1109 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1110 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1111 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1112 1113 /* Common functions */ 1114 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1115 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1116 struct amdgpu_job* job); 1117 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1118 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1119 1120 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1121 u64 num_vis_bytes); 1122 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1123 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1124 const u32 *registers, 1125 const u32 array_size); 1126 1127 bool amdgpu_device_is_px(struct drm_device *dev); 1128 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1129 struct amdgpu_device *peer_adev); 1130 1131 /* atpx handler */ 1132 #if defined(CONFIG_VGA_SWITCHEROO) 1133 void amdgpu_register_atpx_handler(void); 1134 void amdgpu_unregister_atpx_handler(void); 1135 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1136 bool amdgpu_is_atpx_hybrid(void); 1137 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1138 bool amdgpu_has_atpx(void); 1139 #else 1140 static inline void amdgpu_register_atpx_handler(void) {} 1141 static inline void amdgpu_unregister_atpx_handler(void) {} 1142 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1143 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1144 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1145 static inline bool amdgpu_has_atpx(void) { return false; } 1146 #endif 1147 1148 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1149 void *amdgpu_atpx_get_dhandle(void); 1150 #else 1151 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1152 #endif 1153 1154 /* 1155 * KMS 1156 */ 1157 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1158 extern const int amdgpu_max_kms_ioctl; 1159 1160 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1161 void amdgpu_driver_unload_kms(struct drm_device *dev); 1162 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1163 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1164 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1165 struct drm_file *file_priv); 1166 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1167 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1168 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1169 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1170 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1171 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1172 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1173 unsigned long arg); 1174 1175 /* 1176 * functions used by amdgpu_encoder.c 1177 */ 1178 struct amdgpu_afmt_acr { 1179 u32 clock; 1180 1181 int n_32khz; 1182 int cts_32khz; 1183 1184 int n_44_1khz; 1185 int cts_44_1khz; 1186 1187 int n_48khz; 1188 int cts_48khz; 1189 1190 }; 1191 1192 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1193 1194 /* amdgpu_acpi.c */ 1195 #if defined(CONFIG_ACPI) 1196 int amdgpu_acpi_init(struct amdgpu_device *adev); 1197 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1198 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1199 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1200 u8 perf_req, bool advertise); 1201 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1202 1203 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1204 struct amdgpu_dm_backlight_caps *caps); 1205 #else 1206 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1207 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1208 #endif 1209 1210 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1211 uint64_t addr, struct amdgpu_bo **bo, 1212 struct amdgpu_bo_va_mapping **mapping); 1213 1214 #if defined(CONFIG_DRM_AMD_DC) 1215 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1216 #else 1217 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1218 #endif 1219 1220 1221 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1222 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1223 1224 #include "amdgpu_object.h" 1225 1226 /* used by df_v3_6.c and amdgpu_pmu.c */ 1227 #define AMDGPU_PMU_ATTR(_name, _object) \ 1228 static ssize_t \ 1229 _name##_show(struct device *dev, \ 1230 struct device_attribute *attr, \ 1231 char *page) \ 1232 { \ 1233 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1234 return sprintf(page, _object "\n"); \ 1235 } \ 1236 \ 1237 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1238 1239 #endif 1240 1241