1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_execbuf_util.h> 59 60 #include <drm/amdgpu_drm.h> 61 #include <drm/drm_gem.h> 62 #include <drm/drm_ioctl.h> 63 #include <drm/gpu_scheduler.h> 64 65 #include <kgd_kfd_interface.h> 66 #include "dm_pp_interface.h" 67 #include "kgd_pp_interface.h" 68 69 #include "amd_shared.h" 70 #include "amdgpu_mode.h" 71 #include "amdgpu_ih.h" 72 #include "amdgpu_irq.h" 73 #include "amdgpu_ucode.h" 74 #include "amdgpu_ttm.h" 75 #include "amdgpu_psp.h" 76 #include "amdgpu_gds.h" 77 #include "amdgpu_sync.h" 78 #include "amdgpu_ring.h" 79 #include "amdgpu_vm.h" 80 #include "amdgpu_dpm.h" 81 #include "amdgpu_acp.h" 82 #include "amdgpu_uvd.h" 83 #include "amdgpu_vce.h" 84 #include "amdgpu_vcn.h" 85 #include "amdgpu_jpeg.h" 86 #include "amdgpu_mn.h" 87 #include "amdgpu_gmc.h" 88 #include "amdgpu_gfx.h" 89 #include "amdgpu_sdma.h" 90 #include "amdgpu_nbio.h" 91 #include "amdgpu_hdp.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_smu.h" 103 #include "amdgpu_discovery.h" 104 #include "amdgpu_mes.h" 105 #include "amdgpu_umc.h" 106 #include "amdgpu_mmhub.h" 107 #include "amdgpu_gfxhub.h" 108 #include "amdgpu_df.h" 109 #include "amdgpu_smuio.h" 110 #include "amdgpu_hdp.h" 111 112 #define MAX_GPU_INSTANCE 16 113 114 struct amdgpu_gpu_instance 115 { 116 struct amdgpu_device *adev; 117 int mgpu_fan_enabled; 118 }; 119 120 struct amdgpu_mgpu_info 121 { 122 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 123 struct mutex mutex; 124 uint32_t num_gpu; 125 uint32_t num_dgpu; 126 uint32_t num_apu; 127 128 /* delayed reset_func for XGMI configuration if necessary */ 129 struct delayed_work delayed_reset_work; 130 bool pending_reset; 131 }; 132 133 struct amdgpu_watchdog_timer 134 { 135 bool timeout_fatal_disable; 136 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 137 }; 138 139 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 140 141 /* 142 * Modules parameters. 143 */ 144 extern int amdgpu_modeset; 145 extern int amdgpu_vram_limit; 146 extern int amdgpu_vis_vram_limit; 147 extern int amdgpu_gart_size; 148 extern int amdgpu_gtt_size; 149 extern int amdgpu_moverate; 150 extern int amdgpu_benchmarking; 151 extern int amdgpu_testing; 152 extern int amdgpu_audio; 153 extern int amdgpu_disp_priority; 154 extern int amdgpu_hw_i2c; 155 extern int amdgpu_pcie_gen2; 156 extern int amdgpu_msi; 157 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 158 extern int amdgpu_dpm; 159 extern int amdgpu_fw_load_type; 160 extern int amdgpu_aspm; 161 extern int amdgpu_runtime_pm; 162 extern uint amdgpu_ip_block_mask; 163 extern int amdgpu_bapm; 164 extern int amdgpu_deep_color; 165 extern int amdgpu_vm_size; 166 extern int amdgpu_vm_block_size; 167 extern int amdgpu_vm_fragment_size; 168 extern int amdgpu_vm_fault_stop; 169 extern int amdgpu_vm_debug; 170 extern int amdgpu_vm_update_mode; 171 extern int amdgpu_exp_hw_support; 172 extern int amdgpu_dc; 173 extern int amdgpu_sched_jobs; 174 extern int amdgpu_sched_hw_submission; 175 extern uint amdgpu_pcie_gen_cap; 176 extern uint amdgpu_pcie_lane_cap; 177 extern uint amdgpu_cg_mask; 178 extern uint amdgpu_pg_mask; 179 extern uint amdgpu_sdma_phase_quantum; 180 extern char *amdgpu_disable_cu; 181 extern char *amdgpu_virtual_display; 182 extern uint amdgpu_pp_feature_mask; 183 extern uint amdgpu_force_long_training; 184 extern int amdgpu_job_hang_limit; 185 extern int amdgpu_lbpw; 186 extern int amdgpu_compute_multipipe; 187 extern int amdgpu_gpu_recovery; 188 extern int amdgpu_emu_mode; 189 extern uint amdgpu_smu_memory_pool_size; 190 extern int amdgpu_smu_pptable_id; 191 extern uint amdgpu_dc_feature_mask; 192 extern uint amdgpu_freesync_vid_mode; 193 extern uint amdgpu_dc_debug_mask; 194 extern uint amdgpu_dm_abm_level; 195 extern int amdgpu_backlight; 196 extern struct amdgpu_mgpu_info mgpu_info; 197 extern int amdgpu_ras_enable; 198 extern uint amdgpu_ras_mask; 199 extern int amdgpu_bad_page_threshold; 200 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 201 extern int amdgpu_async_gfx_ring; 202 extern int amdgpu_mcbp; 203 extern int amdgpu_discovery; 204 extern int amdgpu_mes; 205 extern int amdgpu_noretry; 206 extern int amdgpu_force_asic_type; 207 #ifdef CONFIG_HSA_AMD 208 extern int sched_policy; 209 extern bool debug_evictions; 210 extern bool no_system_mem_limit; 211 #else 212 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 213 static const bool __maybe_unused debug_evictions; /* = false */ 214 static const bool __maybe_unused no_system_mem_limit; 215 #endif 216 217 extern int amdgpu_tmz; 218 extern int amdgpu_reset_method; 219 220 #ifdef CONFIG_DRM_AMDGPU_SI 221 extern int amdgpu_si_support; 222 #endif 223 #ifdef CONFIG_DRM_AMDGPU_CIK 224 extern int amdgpu_cik_support; 225 #endif 226 extern int amdgpu_num_kcq; 227 228 #define AMDGPU_VM_MAX_NUM_CTX 4096 229 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 230 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 231 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 232 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 233 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 234 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 235 #define AMDGPUFB_CONN_LIMIT 4 236 #define AMDGPU_BIOS_NUM_SCRATCH 16 237 238 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 239 240 /* hard reset data */ 241 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 242 243 /* reset flags */ 244 #define AMDGPU_RESET_GFX (1 << 0) 245 #define AMDGPU_RESET_COMPUTE (1 << 1) 246 #define AMDGPU_RESET_DMA (1 << 2) 247 #define AMDGPU_RESET_CP (1 << 3) 248 #define AMDGPU_RESET_GRBM (1 << 4) 249 #define AMDGPU_RESET_DMA1 (1 << 5) 250 #define AMDGPU_RESET_RLC (1 << 6) 251 #define AMDGPU_RESET_SEM (1 << 7) 252 #define AMDGPU_RESET_IH (1 << 8) 253 #define AMDGPU_RESET_VMC (1 << 9) 254 #define AMDGPU_RESET_MC (1 << 10) 255 #define AMDGPU_RESET_DISPLAY (1 << 11) 256 #define AMDGPU_RESET_UVD (1 << 12) 257 #define AMDGPU_RESET_VCE (1 << 13) 258 #define AMDGPU_RESET_VCE1 (1 << 14) 259 260 /* max cursor sizes (in pixels) */ 261 #define CIK_CURSOR_WIDTH 128 262 #define CIK_CURSOR_HEIGHT 128 263 264 struct amdgpu_device; 265 struct amdgpu_ib; 266 struct amdgpu_cs_parser; 267 struct amdgpu_job; 268 struct amdgpu_irq_src; 269 struct amdgpu_fpriv; 270 struct amdgpu_bo_va_mapping; 271 struct amdgpu_atif; 272 struct kfd_vm_fault_info; 273 struct amdgpu_hive_info; 274 275 enum amdgpu_cp_irq { 276 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 277 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 278 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 279 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 280 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 281 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 282 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 283 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 284 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 285 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 286 287 AMDGPU_CP_IRQ_LAST 288 }; 289 290 enum amdgpu_thermal_irq { 291 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 292 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 293 294 AMDGPU_THERMAL_IRQ_LAST 295 }; 296 297 enum amdgpu_kiq_irq { 298 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 299 AMDGPU_CP_KIQ_IRQ_LAST 300 }; 301 302 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 303 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 304 #define MAX_KIQ_REG_TRY 1000 305 306 int amdgpu_device_ip_set_clockgating_state(void *dev, 307 enum amd_ip_block_type block_type, 308 enum amd_clockgating_state state); 309 int amdgpu_device_ip_set_powergating_state(void *dev, 310 enum amd_ip_block_type block_type, 311 enum amd_powergating_state state); 312 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 313 u32 *flags); 314 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 315 enum amd_ip_block_type block_type); 316 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 317 enum amd_ip_block_type block_type); 318 319 #define AMDGPU_MAX_IP_NUM 16 320 321 struct amdgpu_ip_block_status { 322 bool valid; 323 bool sw; 324 bool hw; 325 bool late_initialized; 326 bool hang; 327 }; 328 329 struct amdgpu_ip_block_version { 330 const enum amd_ip_block_type type; 331 const u32 major; 332 const u32 minor; 333 const u32 rev; 334 const struct amd_ip_funcs *funcs; 335 }; 336 337 #define HW_REV(_Major, _Minor, _Rev) \ 338 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 339 340 struct amdgpu_ip_block { 341 struct amdgpu_ip_block_status status; 342 const struct amdgpu_ip_block_version *version; 343 }; 344 345 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 346 enum amd_ip_block_type type, 347 u32 major, u32 minor); 348 349 struct amdgpu_ip_block * 350 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 351 enum amd_ip_block_type type); 352 353 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 354 const struct amdgpu_ip_block_version *ip_block_version); 355 356 /* 357 * BIOS. 358 */ 359 bool amdgpu_get_bios(struct amdgpu_device *adev); 360 bool amdgpu_read_bios(struct amdgpu_device *adev); 361 362 /* 363 * Clocks 364 */ 365 366 #define AMDGPU_MAX_PPLL 3 367 368 struct amdgpu_clock { 369 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 370 struct amdgpu_pll spll; 371 struct amdgpu_pll mpll; 372 /* 10 Khz units */ 373 uint32_t default_mclk; 374 uint32_t default_sclk; 375 uint32_t default_dispclk; 376 uint32_t current_dispclk; 377 uint32_t dp_extclk; 378 uint32_t max_pixel_clock; 379 }; 380 381 /* sub-allocation manager, it has to be protected by another lock. 382 * By conception this is an helper for other part of the driver 383 * like the indirect buffer or semaphore, which both have their 384 * locking. 385 * 386 * Principe is simple, we keep a list of sub allocation in offset 387 * order (first entry has offset == 0, last entry has the highest 388 * offset). 389 * 390 * When allocating new object we first check if there is room at 391 * the end total_size - (last_object_offset + last_object_size) >= 392 * alloc_size. If so we allocate new object there. 393 * 394 * When there is not enough room at the end, we start waiting for 395 * each sub object until we reach object_offset+object_size >= 396 * alloc_size, this object then become the sub object we return. 397 * 398 * Alignment can't be bigger than page size. 399 * 400 * Hole are not considered for allocation to keep things simple. 401 * Assumption is that there won't be hole (all object on same 402 * alignment). 403 */ 404 405 #define AMDGPU_SA_NUM_FENCE_LISTS 32 406 407 struct amdgpu_sa_manager { 408 wait_queue_head_t wq; 409 struct amdgpu_bo *bo; 410 struct list_head *hole; 411 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 412 struct list_head olist; 413 unsigned size; 414 uint64_t gpu_addr; 415 void *cpu_ptr; 416 uint32_t domain; 417 uint32_t align; 418 }; 419 420 /* sub-allocation buffer */ 421 struct amdgpu_sa_bo { 422 struct list_head olist; 423 struct list_head flist; 424 struct amdgpu_sa_manager *manager; 425 unsigned soffset; 426 unsigned eoffset; 427 struct dma_fence *fence; 428 }; 429 430 int amdgpu_fence_slab_init(void); 431 void amdgpu_fence_slab_fini(void); 432 433 /* 434 * IRQS. 435 */ 436 437 struct amdgpu_flip_work { 438 struct delayed_work flip_work; 439 struct work_struct unpin_work; 440 struct amdgpu_device *adev; 441 int crtc_id; 442 u32 target_vblank; 443 uint64_t base; 444 struct drm_pending_vblank_event *event; 445 struct amdgpu_bo *old_abo; 446 struct dma_fence *excl; 447 unsigned shared_count; 448 struct dma_fence **shared; 449 struct dma_fence_cb cb; 450 bool async; 451 }; 452 453 454 /* 455 * CP & rings. 456 */ 457 458 struct amdgpu_ib { 459 struct amdgpu_sa_bo *sa_bo; 460 uint32_t length_dw; 461 uint64_t gpu_addr; 462 uint32_t *ptr; 463 uint32_t flags; 464 }; 465 466 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 467 468 /* 469 * file private structure 470 */ 471 472 struct amdgpu_fpriv { 473 struct amdgpu_vm vm; 474 struct amdgpu_bo_va *prt_va; 475 struct amdgpu_bo_va *csa_va; 476 struct mutex bo_list_lock; 477 struct idr bo_list_handles; 478 struct amdgpu_ctx_mgr ctx_mgr; 479 }; 480 481 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 482 483 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 484 unsigned size, 485 enum amdgpu_ib_pool_type pool, 486 struct amdgpu_ib *ib); 487 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 488 struct dma_fence *f); 489 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 490 struct amdgpu_ib *ibs, struct amdgpu_job *job, 491 struct dma_fence **f); 492 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 493 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 494 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 495 496 /* 497 * CS. 498 */ 499 struct amdgpu_cs_chunk { 500 uint32_t chunk_id; 501 uint32_t length_dw; 502 void *kdata; 503 }; 504 505 struct amdgpu_cs_post_dep { 506 struct drm_syncobj *syncobj; 507 struct dma_fence_chain *chain; 508 u64 point; 509 }; 510 511 struct amdgpu_cs_parser { 512 struct amdgpu_device *adev; 513 struct drm_file *filp; 514 struct amdgpu_ctx *ctx; 515 516 /* chunks */ 517 unsigned nchunks; 518 struct amdgpu_cs_chunk *chunks; 519 520 /* scheduler job object */ 521 struct amdgpu_job *job; 522 struct drm_sched_entity *entity; 523 524 /* buffer objects */ 525 struct ww_acquire_ctx ticket; 526 struct amdgpu_bo_list *bo_list; 527 struct amdgpu_mn *mn; 528 struct amdgpu_bo_list_entry vm_pd; 529 struct list_head validated; 530 struct dma_fence *fence; 531 uint64_t bytes_moved_threshold; 532 uint64_t bytes_moved_vis_threshold; 533 uint64_t bytes_moved; 534 uint64_t bytes_moved_vis; 535 536 /* user fence */ 537 struct amdgpu_bo_list_entry uf_entry; 538 539 unsigned num_post_deps; 540 struct amdgpu_cs_post_dep *post_deps; 541 }; 542 543 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 544 uint32_t ib_idx, int idx) 545 { 546 return p->job->ibs[ib_idx].ptr[idx]; 547 } 548 549 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 550 uint32_t ib_idx, int idx, 551 uint32_t value) 552 { 553 p->job->ibs[ib_idx].ptr[idx] = value; 554 } 555 556 /* 557 * Writeback 558 */ 559 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 560 561 struct amdgpu_wb { 562 struct amdgpu_bo *wb_obj; 563 volatile uint32_t *wb; 564 uint64_t gpu_addr; 565 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 566 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 567 }; 568 569 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 570 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 571 572 /* 573 * Benchmarking 574 */ 575 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 576 577 578 /* 579 * Testing 580 */ 581 void amdgpu_test_moves(struct amdgpu_device *adev); 582 583 /* 584 * ASIC specific register table accessible by UMD 585 */ 586 struct amdgpu_allowed_register_entry { 587 uint32_t reg_offset; 588 bool grbm_indexed; 589 }; 590 591 enum amd_reset_method { 592 AMD_RESET_METHOD_LEGACY = 0, 593 AMD_RESET_METHOD_MODE0, 594 AMD_RESET_METHOD_MODE1, 595 AMD_RESET_METHOD_MODE2, 596 AMD_RESET_METHOD_BACO, 597 AMD_RESET_METHOD_PCI, 598 }; 599 600 struct amdgpu_video_codec_info { 601 u32 codec_type; 602 u32 max_width; 603 u32 max_height; 604 u32 max_pixels_per_frame; 605 u32 max_level; 606 }; 607 608 struct amdgpu_video_codecs { 609 const u32 codec_count; 610 const struct amdgpu_video_codec_info *codec_array; 611 }; 612 613 /* 614 * ASIC specific functions. 615 */ 616 struct amdgpu_asic_funcs { 617 bool (*read_disabled_bios)(struct amdgpu_device *adev); 618 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 619 u8 *bios, u32 length_bytes); 620 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 621 u32 sh_num, u32 reg_offset, u32 *value); 622 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 623 int (*reset)(struct amdgpu_device *adev); 624 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 625 /* get the reference clock */ 626 u32 (*get_xclk)(struct amdgpu_device *adev); 627 /* MM block clocks */ 628 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 629 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 630 /* static power management */ 631 int (*get_pcie_lanes)(struct amdgpu_device *adev); 632 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 633 /* get config memsize register */ 634 u32 (*get_config_memsize)(struct amdgpu_device *adev); 635 /* flush hdp write queue */ 636 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 637 /* invalidate hdp read cache */ 638 void (*invalidate_hdp)(struct amdgpu_device *adev, 639 struct amdgpu_ring *ring); 640 /* check if the asic needs a full reset of if soft reset will work */ 641 bool (*need_full_reset)(struct amdgpu_device *adev); 642 /* initialize doorbell layout for specific asic*/ 643 void (*init_doorbell_index)(struct amdgpu_device *adev); 644 /* PCIe bandwidth usage */ 645 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 646 uint64_t *count1); 647 /* do we need to reset the asic at init time (e.g., kexec) */ 648 bool (*need_reset_on_init)(struct amdgpu_device *adev); 649 /* PCIe replay counter */ 650 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 651 /* device supports BACO */ 652 bool (*supports_baco)(struct amdgpu_device *adev); 653 /* pre asic_init quirks */ 654 void (*pre_asic_init)(struct amdgpu_device *adev); 655 /* enter/exit umd stable pstate */ 656 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 657 /* query video codecs */ 658 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 659 const struct amdgpu_video_codecs **codecs); 660 }; 661 662 /* 663 * IOCTL. 664 */ 665 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 666 struct drm_file *filp); 667 668 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 669 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 670 struct drm_file *filp); 671 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 672 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 673 struct drm_file *filp); 674 675 /* VRAM scratch page for HDP bug, default vram page */ 676 struct amdgpu_vram_scratch { 677 struct amdgpu_bo *robj; 678 volatile uint32_t *ptr; 679 u64 gpu_addr; 680 }; 681 682 /* 683 * ACPI 684 */ 685 struct amdgpu_atcs_functions { 686 bool get_ext_state; 687 bool pcie_perf_req; 688 bool pcie_dev_rdy; 689 bool pcie_bus_width; 690 }; 691 692 struct amdgpu_atcs { 693 struct amdgpu_atcs_functions functions; 694 }; 695 696 /* 697 * CGS 698 */ 699 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 700 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 701 702 /* 703 * Core structure, functions and helpers. 704 */ 705 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 706 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 707 708 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 709 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 710 711 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 712 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 713 714 struct amdgpu_mmio_remap { 715 u32 reg_offset; 716 resource_size_t bus_addr; 717 }; 718 719 /* Define the HW IP blocks will be used in driver , add more if necessary */ 720 enum amd_hw_ip_block_type { 721 GC_HWIP = 1, 722 HDP_HWIP, 723 SDMA0_HWIP, 724 SDMA1_HWIP, 725 SDMA2_HWIP, 726 SDMA3_HWIP, 727 SDMA4_HWIP, 728 SDMA5_HWIP, 729 SDMA6_HWIP, 730 SDMA7_HWIP, 731 MMHUB_HWIP, 732 ATHUB_HWIP, 733 NBIO_HWIP, 734 MP0_HWIP, 735 MP1_HWIP, 736 UVD_HWIP, 737 VCN_HWIP = UVD_HWIP, 738 JPEG_HWIP = VCN_HWIP, 739 VCE_HWIP, 740 DF_HWIP, 741 DCE_HWIP, 742 OSSSYS_HWIP, 743 SMUIO_HWIP, 744 PWR_HWIP, 745 NBIF_HWIP, 746 THM_HWIP, 747 CLK_HWIP, 748 UMC_HWIP, 749 RSMU_HWIP, 750 MAX_HWIP 751 }; 752 753 #define HWIP_MAX_INSTANCE 8 754 755 struct amd_powerplay { 756 void *pp_handle; 757 const struct amd_pm_funcs *pp_funcs; 758 }; 759 760 /* polaris10 kickers */ 761 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 762 ((rid == 0xE3) || \ 763 (rid == 0xE4) || \ 764 (rid == 0xE5) || \ 765 (rid == 0xE7) || \ 766 (rid == 0xEF))) || \ 767 ((did == 0x6FDF) && \ 768 ((rid == 0xE7) || \ 769 (rid == 0xEF) || \ 770 (rid == 0xFF)))) 771 772 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 773 ((rid == 0xE1) || \ 774 (rid == 0xF7))) 775 776 /* polaris11 kickers */ 777 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 778 ((rid == 0xE0) || \ 779 (rid == 0xE5))) || \ 780 ((did == 0x67FF) && \ 781 ((rid == 0xCF) || \ 782 (rid == 0xEF) || \ 783 (rid == 0xFF)))) 784 785 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 786 ((rid == 0xE2))) 787 788 /* polaris12 kickers */ 789 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 790 ((rid == 0xC0) || \ 791 (rid == 0xC1) || \ 792 (rid == 0xC3) || \ 793 (rid == 0xC7))) || \ 794 ((did == 0x6981) && \ 795 ((rid == 0x00) || \ 796 (rid == 0x01) || \ 797 (rid == 0x10)))) 798 799 #define AMDGPU_RESET_MAGIC_NUM 64 800 #define AMDGPU_MAX_DF_PERFMONS 4 801 struct amdgpu_device { 802 struct device *dev; 803 struct pci_dev *pdev; 804 struct drm_device ddev; 805 806 #ifdef CONFIG_DRM_AMD_ACP 807 struct amdgpu_acp acp; 808 #endif 809 struct amdgpu_hive_info *hive; 810 /* ASIC */ 811 enum amd_asic_type asic_type; 812 uint32_t family; 813 uint32_t rev_id; 814 uint32_t external_rev_id; 815 unsigned long flags; 816 unsigned long apu_flags; 817 int usec_timeout; 818 const struct amdgpu_asic_funcs *asic_funcs; 819 bool shutdown; 820 bool need_swiotlb; 821 bool accel_working; 822 struct notifier_block acpi_nb; 823 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 824 struct debugfs_blob_wrapper debugfs_vbios_blob; 825 struct amdgpu_atif *atif; 826 struct amdgpu_atcs atcs; 827 struct mutex srbm_mutex; 828 /* GRBM index mutex. Protects concurrent access to GRBM index */ 829 struct mutex grbm_idx_mutex; 830 struct dev_pm_domain vga_pm_domain; 831 bool have_disp_power_ref; 832 bool have_atomics_support; 833 834 /* BIOS */ 835 bool is_atom_fw; 836 uint8_t *bios; 837 uint32_t bios_size; 838 uint32_t bios_scratch_reg_offset; 839 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 840 841 /* Register/doorbell mmio */ 842 resource_size_t rmmio_base; 843 resource_size_t rmmio_size; 844 void __iomem *rmmio; 845 /* protects concurrent MM_INDEX/DATA based register access */ 846 spinlock_t mmio_idx_lock; 847 struct amdgpu_mmio_remap rmmio_remap; 848 /* protects concurrent SMC based register access */ 849 spinlock_t smc_idx_lock; 850 amdgpu_rreg_t smc_rreg; 851 amdgpu_wreg_t smc_wreg; 852 /* protects concurrent PCIE register access */ 853 spinlock_t pcie_idx_lock; 854 amdgpu_rreg_t pcie_rreg; 855 amdgpu_wreg_t pcie_wreg; 856 amdgpu_rreg_t pciep_rreg; 857 amdgpu_wreg_t pciep_wreg; 858 amdgpu_rreg64_t pcie_rreg64; 859 amdgpu_wreg64_t pcie_wreg64; 860 /* protects concurrent UVD register access */ 861 spinlock_t uvd_ctx_idx_lock; 862 amdgpu_rreg_t uvd_ctx_rreg; 863 amdgpu_wreg_t uvd_ctx_wreg; 864 /* protects concurrent DIDT register access */ 865 spinlock_t didt_idx_lock; 866 amdgpu_rreg_t didt_rreg; 867 amdgpu_wreg_t didt_wreg; 868 /* protects concurrent gc_cac register access */ 869 spinlock_t gc_cac_idx_lock; 870 amdgpu_rreg_t gc_cac_rreg; 871 amdgpu_wreg_t gc_cac_wreg; 872 /* protects concurrent se_cac register access */ 873 spinlock_t se_cac_idx_lock; 874 amdgpu_rreg_t se_cac_rreg; 875 amdgpu_wreg_t se_cac_wreg; 876 /* protects concurrent ENDPOINT (audio) register access */ 877 spinlock_t audio_endpt_idx_lock; 878 amdgpu_block_rreg_t audio_endpt_rreg; 879 amdgpu_block_wreg_t audio_endpt_wreg; 880 struct amdgpu_doorbell doorbell; 881 882 /* clock/pll info */ 883 struct amdgpu_clock clock; 884 885 /* MC */ 886 struct amdgpu_gmc gmc; 887 struct amdgpu_gart gart; 888 dma_addr_t dummy_page_addr; 889 struct amdgpu_vm_manager vm_manager; 890 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 891 unsigned num_vmhubs; 892 893 /* memory management */ 894 struct amdgpu_mman mman; 895 struct amdgpu_vram_scratch vram_scratch; 896 struct amdgpu_wb wb; 897 atomic64_t num_bytes_moved; 898 atomic64_t num_evictions; 899 atomic64_t num_vram_cpu_page_faults; 900 atomic_t gpu_reset_counter; 901 atomic_t vram_lost_counter; 902 903 /* data for buffer migration throttling */ 904 struct { 905 spinlock_t lock; 906 s64 last_update_us; 907 s64 accum_us; /* accumulated microseconds */ 908 s64 accum_us_vis; /* for visible VRAM */ 909 u32 log2_max_MBps; 910 } mm_stats; 911 912 /* display */ 913 bool enable_virtual_display; 914 struct amdgpu_mode_info mode_info; 915 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 916 struct work_struct hotplug_work; 917 struct amdgpu_irq_src crtc_irq; 918 struct amdgpu_irq_src vline0_irq; 919 struct amdgpu_irq_src vupdate_irq; 920 struct amdgpu_irq_src pageflip_irq; 921 struct amdgpu_irq_src hpd_irq; 922 struct amdgpu_irq_src dmub_trace_irq; 923 924 /* rings */ 925 u64 fence_context; 926 unsigned num_rings; 927 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 928 bool ib_pool_ready; 929 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 930 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 931 932 /* interrupts */ 933 struct amdgpu_irq irq; 934 935 /* powerplay */ 936 struct amd_powerplay powerplay; 937 bool pp_force_state_enabled; 938 939 /* smu */ 940 struct smu_context smu; 941 942 /* dpm */ 943 struct amdgpu_pm pm; 944 u32 cg_flags; 945 u32 pg_flags; 946 947 /* nbio */ 948 struct amdgpu_nbio nbio; 949 950 /* hdp */ 951 struct amdgpu_hdp hdp; 952 953 /* smuio */ 954 struct amdgpu_smuio smuio; 955 956 /* mmhub */ 957 struct amdgpu_mmhub mmhub; 958 959 /* gfxhub */ 960 struct amdgpu_gfxhub gfxhub; 961 962 /* gfx */ 963 struct amdgpu_gfx gfx; 964 965 /* sdma */ 966 struct amdgpu_sdma sdma; 967 968 /* uvd */ 969 struct amdgpu_uvd uvd; 970 971 /* vce */ 972 struct amdgpu_vce vce; 973 974 /* vcn */ 975 struct amdgpu_vcn vcn; 976 977 /* jpeg */ 978 struct amdgpu_jpeg jpeg; 979 980 /* firmwares */ 981 struct amdgpu_firmware firmware; 982 983 /* PSP */ 984 struct psp_context psp; 985 986 /* GDS */ 987 struct amdgpu_gds gds; 988 989 /* KFD */ 990 struct amdgpu_kfd_dev kfd; 991 992 /* UMC */ 993 struct amdgpu_umc umc; 994 995 /* display related functionality */ 996 struct amdgpu_display_manager dm; 997 998 /* mes */ 999 bool enable_mes; 1000 struct amdgpu_mes mes; 1001 1002 /* df */ 1003 struct amdgpu_df df; 1004 1005 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1006 int num_ip_blocks; 1007 struct mutex mn_lock; 1008 DECLARE_HASHTABLE(mn_hash, 7); 1009 1010 /* tracking pinned memory */ 1011 atomic64_t vram_pin_size; 1012 atomic64_t visible_pin_size; 1013 atomic64_t gart_pin_size; 1014 1015 /* soc15 register offset based on ip, instance and segment */ 1016 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1017 1018 /* delayed work_func for deferring clockgating during resume */ 1019 struct delayed_work delayed_init_work; 1020 1021 struct amdgpu_virt virt; 1022 1023 /* link all shadow bo */ 1024 struct list_head shadow_list; 1025 struct mutex shadow_list_lock; 1026 1027 /* record hw reset is performed */ 1028 bool has_hw_reset; 1029 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1030 1031 /* s3/s4 mask */ 1032 bool in_suspend; 1033 bool in_s3; 1034 bool in_s4; 1035 bool in_s0ix; 1036 1037 atomic_t in_gpu_reset; 1038 enum pp_mp1_state mp1_state; 1039 struct rw_semaphore reset_sem; 1040 struct amdgpu_doorbell_index doorbell_index; 1041 1042 struct mutex notifier_lock; 1043 1044 int asic_reset_res; 1045 struct work_struct xgmi_reset_work; 1046 struct list_head reset_list; 1047 1048 long gfx_timeout; 1049 long sdma_timeout; 1050 long video_timeout; 1051 long compute_timeout; 1052 1053 uint64_t unique_id; 1054 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1055 1056 /* enable runtime pm on the device */ 1057 bool runpm; 1058 bool in_runpm; 1059 bool has_pr3; 1060 1061 bool pm_sysfs_en; 1062 bool ucode_sysfs_en; 1063 1064 /* Chip product information */ 1065 char product_number[16]; 1066 char product_name[32]; 1067 char serial[20]; 1068 1069 struct amdgpu_autodump autodump; 1070 1071 atomic_t throttling_logging_enabled; 1072 struct ratelimit_state throttling_logging_rs; 1073 uint32_t ras_features; 1074 1075 bool in_pci_err_recovery; 1076 struct pci_saved_state *pci_state; 1077 }; 1078 1079 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1080 { 1081 return container_of(ddev, struct amdgpu_device, ddev); 1082 } 1083 1084 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1085 { 1086 return &adev->ddev; 1087 } 1088 1089 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1090 { 1091 return container_of(bdev, struct amdgpu_device, mman.bdev); 1092 } 1093 1094 int amdgpu_device_init(struct amdgpu_device *adev, 1095 uint32_t flags); 1096 void amdgpu_device_fini(struct amdgpu_device *adev); 1097 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1098 1099 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1100 uint32_t *buf, size_t size, bool write); 1101 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1102 uint32_t reg, uint32_t acc_flags); 1103 void amdgpu_device_wreg(struct amdgpu_device *adev, 1104 uint32_t reg, uint32_t v, 1105 uint32_t acc_flags); 1106 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1107 uint32_t reg, uint32_t v); 1108 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1109 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1110 1111 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1112 u32 pcie_index, u32 pcie_data, 1113 u32 reg_addr); 1114 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1115 u32 pcie_index, u32 pcie_data, 1116 u32 reg_addr); 1117 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1118 u32 pcie_index, u32 pcie_data, 1119 u32 reg_addr, u32 reg_data); 1120 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1121 u32 pcie_index, u32 pcie_data, 1122 u32 reg_addr, u64 reg_data); 1123 1124 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1125 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1126 1127 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1128 struct amdgpu_job *job, 1129 bool *need_full_reset_arg); 1130 1131 int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, 1132 struct list_head *device_list_handle, 1133 bool *need_full_reset_arg, 1134 bool skip_hw_reset); 1135 1136 int emu_soc_asic_init(struct amdgpu_device *adev); 1137 1138 /* 1139 * Registers read & write functions. 1140 */ 1141 #define AMDGPU_REGS_NO_KIQ (1<<1) 1142 1143 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1144 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1145 1146 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1147 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1148 1149 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1150 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1151 1152 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1153 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1154 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1155 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1156 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1157 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1158 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1159 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1160 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1161 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1162 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1163 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1164 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1165 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1166 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1167 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1168 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1169 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1170 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1171 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1172 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1173 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1174 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1175 #define WREG32_P(reg, val, mask) \ 1176 do { \ 1177 uint32_t tmp_ = RREG32(reg); \ 1178 tmp_ &= (mask); \ 1179 tmp_ |= ((val) & ~(mask)); \ 1180 WREG32(reg, tmp_); \ 1181 } while (0) 1182 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1183 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1184 #define WREG32_PLL_P(reg, val, mask) \ 1185 do { \ 1186 uint32_t tmp_ = RREG32_PLL(reg); \ 1187 tmp_ &= (mask); \ 1188 tmp_ |= ((val) & ~(mask)); \ 1189 WREG32_PLL(reg, tmp_); \ 1190 } while (0) 1191 1192 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1193 do { \ 1194 u32 tmp = RREG32_SMC(_Reg); \ 1195 tmp &= (_Mask); \ 1196 tmp |= ((_Val) & ~(_Mask)); \ 1197 WREG32_SMC(_Reg, tmp); \ 1198 } while (0) 1199 1200 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1201 1202 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1203 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1204 1205 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1206 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1207 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1208 1209 #define REG_GET_FIELD(value, reg, field) \ 1210 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1211 1212 #define WREG32_FIELD(reg, field, val) \ 1213 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1214 1215 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1216 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1217 1218 /* 1219 * BIOS helpers. 1220 */ 1221 #define RBIOS8(i) (adev->bios[i]) 1222 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1223 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1224 1225 /* 1226 * ASICs macro. 1227 */ 1228 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1229 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1230 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1231 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1232 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1233 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1234 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1235 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1236 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1237 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1238 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1239 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1240 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1241 #define amdgpu_asic_flush_hdp(adev, r) \ 1242 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1243 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1244 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r))) 1245 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1246 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1247 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1248 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1249 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1250 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1251 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1252 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1253 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1254 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1255 1256 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1257 1258 /* Common functions */ 1259 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1260 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1261 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1262 struct amdgpu_job* job); 1263 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1264 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1265 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1266 1267 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1268 u64 num_vis_bytes); 1269 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1270 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1271 const u32 *registers, 1272 const u32 array_size); 1273 1274 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1275 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1276 bool amdgpu_device_supports_px(struct drm_device *dev); 1277 bool amdgpu_device_supports_boco(struct drm_device *dev); 1278 bool amdgpu_device_supports_baco(struct drm_device *dev); 1279 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1280 struct amdgpu_device *peer_adev); 1281 int amdgpu_device_baco_enter(struct drm_device *dev); 1282 int amdgpu_device_baco_exit(struct drm_device *dev); 1283 1284 /* atpx handler */ 1285 #if defined(CONFIG_VGA_SWITCHEROO) 1286 void amdgpu_register_atpx_handler(void); 1287 void amdgpu_unregister_atpx_handler(void); 1288 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1289 bool amdgpu_is_atpx_hybrid(void); 1290 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1291 bool amdgpu_has_atpx(void); 1292 #else 1293 static inline void amdgpu_register_atpx_handler(void) {} 1294 static inline void amdgpu_unregister_atpx_handler(void) {} 1295 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1296 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1297 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1298 static inline bool amdgpu_has_atpx(void) { return false; } 1299 #endif 1300 1301 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1302 void *amdgpu_atpx_get_dhandle(void); 1303 #else 1304 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1305 #endif 1306 1307 /* 1308 * KMS 1309 */ 1310 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1311 extern const int amdgpu_max_kms_ioctl; 1312 1313 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1314 void amdgpu_driver_unload_kms(struct drm_device *dev); 1315 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1316 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1317 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1318 struct drm_file *file_priv); 1319 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1320 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1321 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1322 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1323 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1324 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1325 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1326 unsigned long arg); 1327 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1328 struct drm_file *filp); 1329 1330 /* 1331 * functions used by amdgpu_encoder.c 1332 */ 1333 struct amdgpu_afmt_acr { 1334 u32 clock; 1335 1336 int n_32khz; 1337 int cts_32khz; 1338 1339 int n_44_1khz; 1340 int cts_44_1khz; 1341 1342 int n_48khz; 1343 int cts_48khz; 1344 1345 }; 1346 1347 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1348 1349 /* amdgpu_acpi.c */ 1350 #if defined(CONFIG_ACPI) 1351 int amdgpu_acpi_init(struct amdgpu_device *adev); 1352 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1353 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1354 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1355 u8 perf_req, bool advertise); 1356 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1357 1358 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1359 struct amdgpu_dm_backlight_caps *caps); 1360 bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev); 1361 #else 1362 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1363 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1364 static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; } 1365 #endif 1366 1367 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1368 uint64_t addr, struct amdgpu_bo **bo, 1369 struct amdgpu_bo_va_mapping **mapping); 1370 1371 #if defined(CONFIG_DRM_AMD_DC) 1372 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1373 #else 1374 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1375 #endif 1376 1377 1378 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1379 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1380 1381 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1382 pci_channel_state_t state); 1383 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1384 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1385 void amdgpu_pci_resume(struct pci_dev *pdev); 1386 1387 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1388 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1389 1390 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1391 1392 #include "amdgpu_object.h" 1393 1394 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1395 { 1396 return adev->gmc.tmz_enabled; 1397 } 1398 1399 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1400 { 1401 return atomic_read(&adev->in_gpu_reset); 1402 } 1403 #endif 1404