1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 53 #include <drm/ttm/ttm_bo_api.h> 54 #include <drm/ttm/ttm_bo_driver.h> 55 #include <drm/ttm/ttm_placement.h> 56 #include <drm/ttm/ttm_module.h> 57 #include <drm/ttm/ttm_execbuf_util.h> 58 59 #include <drm/amdgpu_drm.h> 60 #include <drm/drm_gem.h> 61 #include <drm/drm_ioctl.h> 62 #include <drm/gpu_scheduler.h> 63 64 #include <kgd_kfd_interface.h> 65 #include "dm_pp_interface.h" 66 #include "kgd_pp_interface.h" 67 68 #include "amd_shared.h" 69 #include "amdgpu_mode.h" 70 #include "amdgpu_ih.h" 71 #include "amdgpu_irq.h" 72 #include "amdgpu_ucode.h" 73 #include "amdgpu_ttm.h" 74 #include "amdgpu_psp.h" 75 #include "amdgpu_gds.h" 76 #include "amdgpu_sync.h" 77 #include "amdgpu_ring.h" 78 #include "amdgpu_vm.h" 79 #include "amdgpu_dpm.h" 80 #include "amdgpu_acp.h" 81 #include "amdgpu_uvd.h" 82 #include "amdgpu_vce.h" 83 #include "amdgpu_vcn.h" 84 #include "amdgpu_jpeg.h" 85 #include "amdgpu_mn.h" 86 #include "amdgpu_gmc.h" 87 #include "amdgpu_gfx.h" 88 #include "amdgpu_sdma.h" 89 #include "amdgpu_nbio.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_gart.h" 94 #include "amdgpu_debugfs.h" 95 #include "amdgpu_job.h" 96 #include "amdgpu_bo_list.h" 97 #include "amdgpu_gem.h" 98 #include "amdgpu_doorbell.h" 99 #include "amdgpu_amdkfd.h" 100 #include "amdgpu_smu.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_df.h" 106 107 #define MAX_GPU_INSTANCE 16 108 109 struct amdgpu_gpu_instance 110 { 111 struct amdgpu_device *adev; 112 int mgpu_fan_enabled; 113 }; 114 115 struct amdgpu_mgpu_info 116 { 117 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 118 struct mutex mutex; 119 uint32_t num_gpu; 120 uint32_t num_dgpu; 121 uint32_t num_apu; 122 }; 123 124 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 125 126 /* 127 * Modules parameters. 128 */ 129 extern int amdgpu_modeset; 130 extern int amdgpu_vram_limit; 131 extern int amdgpu_vis_vram_limit; 132 extern int amdgpu_gart_size; 133 extern int amdgpu_gtt_size; 134 extern int amdgpu_moverate; 135 extern int amdgpu_benchmarking; 136 extern int amdgpu_testing; 137 extern int amdgpu_audio; 138 extern int amdgpu_disp_priority; 139 extern int amdgpu_hw_i2c; 140 extern int amdgpu_pcie_gen2; 141 extern int amdgpu_msi; 142 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 143 extern int amdgpu_dpm; 144 extern int amdgpu_fw_load_type; 145 extern int amdgpu_aspm; 146 extern int amdgpu_runtime_pm; 147 extern uint amdgpu_ip_block_mask; 148 extern int amdgpu_bapm; 149 extern int amdgpu_deep_color; 150 extern int amdgpu_vm_size; 151 extern int amdgpu_vm_block_size; 152 extern int amdgpu_vm_fragment_size; 153 extern int amdgpu_vm_fault_stop; 154 extern int amdgpu_vm_debug; 155 extern int amdgpu_vm_update_mode; 156 extern int amdgpu_exp_hw_support; 157 extern int amdgpu_dc; 158 extern int amdgpu_sched_jobs; 159 extern int amdgpu_sched_hw_submission; 160 extern uint amdgpu_pcie_gen_cap; 161 extern uint amdgpu_pcie_lane_cap; 162 extern uint amdgpu_cg_mask; 163 extern uint amdgpu_pg_mask; 164 extern uint amdgpu_sdma_phase_quantum; 165 extern char *amdgpu_disable_cu; 166 extern char *amdgpu_virtual_display; 167 extern uint amdgpu_pp_feature_mask; 168 extern uint amdgpu_force_long_training; 169 extern int amdgpu_job_hang_limit; 170 extern int amdgpu_lbpw; 171 extern int amdgpu_compute_multipipe; 172 extern int amdgpu_gpu_recovery; 173 extern int amdgpu_emu_mode; 174 extern uint amdgpu_smu_memory_pool_size; 175 extern uint amdgpu_dc_feature_mask; 176 extern uint amdgpu_dc_debug_mask; 177 extern uint amdgpu_dm_abm_level; 178 extern struct amdgpu_mgpu_info mgpu_info; 179 extern int amdgpu_ras_enable; 180 extern uint amdgpu_ras_mask; 181 extern int amdgpu_async_gfx_ring; 182 extern int amdgpu_mcbp; 183 extern int amdgpu_discovery; 184 extern int amdgpu_mes; 185 extern int amdgpu_noretry; 186 extern int amdgpu_force_asic_type; 187 #ifdef CONFIG_HSA_AMD 188 extern int sched_policy; 189 extern bool debug_evictions; 190 #else 191 static const int sched_policy = KFD_SCHED_POLICY_HWS; 192 static const bool debug_evictions; /* = false */ 193 #endif 194 195 extern int amdgpu_tmz; 196 197 #ifdef CONFIG_DRM_AMDGPU_SI 198 extern int amdgpu_si_support; 199 #endif 200 #ifdef CONFIG_DRM_AMDGPU_CIK 201 extern int amdgpu_cik_support; 202 #endif 203 204 #define AMDGPU_VM_MAX_NUM_CTX 4096 205 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 206 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 207 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 208 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 209 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 210 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 211 #define AMDGPUFB_CONN_LIMIT 4 212 #define AMDGPU_BIOS_NUM_SCRATCH 16 213 214 /* hard reset data */ 215 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 216 217 /* reset flags */ 218 #define AMDGPU_RESET_GFX (1 << 0) 219 #define AMDGPU_RESET_COMPUTE (1 << 1) 220 #define AMDGPU_RESET_DMA (1 << 2) 221 #define AMDGPU_RESET_CP (1 << 3) 222 #define AMDGPU_RESET_GRBM (1 << 4) 223 #define AMDGPU_RESET_DMA1 (1 << 5) 224 #define AMDGPU_RESET_RLC (1 << 6) 225 #define AMDGPU_RESET_SEM (1 << 7) 226 #define AMDGPU_RESET_IH (1 << 8) 227 #define AMDGPU_RESET_VMC (1 << 9) 228 #define AMDGPU_RESET_MC (1 << 10) 229 #define AMDGPU_RESET_DISPLAY (1 << 11) 230 #define AMDGPU_RESET_UVD (1 << 12) 231 #define AMDGPU_RESET_VCE (1 << 13) 232 #define AMDGPU_RESET_VCE1 (1 << 14) 233 234 /* max cursor sizes (in pixels) */ 235 #define CIK_CURSOR_WIDTH 128 236 #define CIK_CURSOR_HEIGHT 128 237 238 struct amdgpu_device; 239 struct amdgpu_ib; 240 struct amdgpu_cs_parser; 241 struct amdgpu_job; 242 struct amdgpu_irq_src; 243 struct amdgpu_fpriv; 244 struct amdgpu_bo_va_mapping; 245 struct amdgpu_atif; 246 struct kfd_vm_fault_info; 247 248 enum amdgpu_cp_irq { 249 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 250 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 251 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 252 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 253 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 254 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 255 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 256 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 257 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 258 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 259 260 AMDGPU_CP_IRQ_LAST 261 }; 262 263 enum amdgpu_thermal_irq { 264 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 265 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 266 267 AMDGPU_THERMAL_IRQ_LAST 268 }; 269 270 enum amdgpu_kiq_irq { 271 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 272 AMDGPU_CP_KIQ_IRQ_LAST 273 }; 274 275 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 276 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 277 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 278 279 int amdgpu_device_ip_set_clockgating_state(void *dev, 280 enum amd_ip_block_type block_type, 281 enum amd_clockgating_state state); 282 int amdgpu_device_ip_set_powergating_state(void *dev, 283 enum amd_ip_block_type block_type, 284 enum amd_powergating_state state); 285 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 286 u32 *flags); 287 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 288 enum amd_ip_block_type block_type); 289 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 290 enum amd_ip_block_type block_type); 291 292 #define AMDGPU_MAX_IP_NUM 16 293 294 struct amdgpu_ip_block_status { 295 bool valid; 296 bool sw; 297 bool hw; 298 bool late_initialized; 299 bool hang; 300 }; 301 302 struct amdgpu_ip_block_version { 303 const enum amd_ip_block_type type; 304 const u32 major; 305 const u32 minor; 306 const u32 rev; 307 const struct amd_ip_funcs *funcs; 308 }; 309 310 #define HW_REV(_Major, _Minor, _Rev) \ 311 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 312 313 struct amdgpu_ip_block { 314 struct amdgpu_ip_block_status status; 315 const struct amdgpu_ip_block_version *version; 316 }; 317 318 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 319 enum amd_ip_block_type type, 320 u32 major, u32 minor); 321 322 struct amdgpu_ip_block * 323 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 324 enum amd_ip_block_type type); 325 326 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 327 const struct amdgpu_ip_block_version *ip_block_version); 328 329 /* 330 * BIOS. 331 */ 332 bool amdgpu_get_bios(struct amdgpu_device *adev); 333 bool amdgpu_read_bios(struct amdgpu_device *adev); 334 335 /* 336 * Clocks 337 */ 338 339 #define AMDGPU_MAX_PPLL 3 340 341 struct amdgpu_clock { 342 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 343 struct amdgpu_pll spll; 344 struct amdgpu_pll mpll; 345 /* 10 Khz units */ 346 uint32_t default_mclk; 347 uint32_t default_sclk; 348 uint32_t default_dispclk; 349 uint32_t current_dispclk; 350 uint32_t dp_extclk; 351 uint32_t max_pixel_clock; 352 }; 353 354 /* sub-allocation manager, it has to be protected by another lock. 355 * By conception this is an helper for other part of the driver 356 * like the indirect buffer or semaphore, which both have their 357 * locking. 358 * 359 * Principe is simple, we keep a list of sub allocation in offset 360 * order (first entry has offset == 0, last entry has the highest 361 * offset). 362 * 363 * When allocating new object we first check if there is room at 364 * the end total_size - (last_object_offset + last_object_size) >= 365 * alloc_size. If so we allocate new object there. 366 * 367 * When there is not enough room at the end, we start waiting for 368 * each sub object until we reach object_offset+object_size >= 369 * alloc_size, this object then become the sub object we return. 370 * 371 * Alignment can't be bigger than page size. 372 * 373 * Hole are not considered for allocation to keep things simple. 374 * Assumption is that there won't be hole (all object on same 375 * alignment). 376 */ 377 378 #define AMDGPU_SA_NUM_FENCE_LISTS 32 379 380 struct amdgpu_sa_manager { 381 wait_queue_head_t wq; 382 struct amdgpu_bo *bo; 383 struct list_head *hole; 384 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 385 struct list_head olist; 386 unsigned size; 387 uint64_t gpu_addr; 388 void *cpu_ptr; 389 uint32_t domain; 390 uint32_t align; 391 }; 392 393 /* sub-allocation buffer */ 394 struct amdgpu_sa_bo { 395 struct list_head olist; 396 struct list_head flist; 397 struct amdgpu_sa_manager *manager; 398 unsigned soffset; 399 unsigned eoffset; 400 struct dma_fence *fence; 401 }; 402 403 int amdgpu_fence_slab_init(void); 404 void amdgpu_fence_slab_fini(void); 405 406 /* 407 * IRQS. 408 */ 409 410 struct amdgpu_flip_work { 411 struct delayed_work flip_work; 412 struct work_struct unpin_work; 413 struct amdgpu_device *adev; 414 int crtc_id; 415 u32 target_vblank; 416 uint64_t base; 417 struct drm_pending_vblank_event *event; 418 struct amdgpu_bo *old_abo; 419 struct dma_fence *excl; 420 unsigned shared_count; 421 struct dma_fence **shared; 422 struct dma_fence_cb cb; 423 bool async; 424 }; 425 426 427 /* 428 * CP & rings. 429 */ 430 431 struct amdgpu_ib { 432 struct amdgpu_sa_bo *sa_bo; 433 uint32_t length_dw; 434 uint64_t gpu_addr; 435 uint32_t *ptr; 436 uint32_t flags; 437 }; 438 439 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 440 441 /* 442 * file private structure 443 */ 444 445 struct amdgpu_fpriv { 446 struct amdgpu_vm vm; 447 struct amdgpu_bo_va *prt_va; 448 struct amdgpu_bo_va *csa_va; 449 struct mutex bo_list_lock; 450 struct idr bo_list_handles; 451 struct amdgpu_ctx_mgr ctx_mgr; 452 }; 453 454 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 455 456 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 457 unsigned size, 458 enum amdgpu_ib_pool_type pool, 459 struct amdgpu_ib *ib); 460 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 461 struct dma_fence *f); 462 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 463 struct amdgpu_ib *ibs, struct amdgpu_job *job, 464 struct dma_fence **f); 465 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 466 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 467 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 468 469 /* 470 * CS. 471 */ 472 struct amdgpu_cs_chunk { 473 uint32_t chunk_id; 474 uint32_t length_dw; 475 void *kdata; 476 }; 477 478 struct amdgpu_cs_post_dep { 479 struct drm_syncobj *syncobj; 480 struct dma_fence_chain *chain; 481 u64 point; 482 }; 483 484 struct amdgpu_cs_parser { 485 struct amdgpu_device *adev; 486 struct drm_file *filp; 487 struct amdgpu_ctx *ctx; 488 489 /* chunks */ 490 unsigned nchunks; 491 struct amdgpu_cs_chunk *chunks; 492 493 /* scheduler job object */ 494 struct amdgpu_job *job; 495 struct drm_sched_entity *entity; 496 497 /* buffer objects */ 498 struct ww_acquire_ctx ticket; 499 struct amdgpu_bo_list *bo_list; 500 struct amdgpu_mn *mn; 501 struct amdgpu_bo_list_entry vm_pd; 502 struct list_head validated; 503 struct dma_fence *fence; 504 uint64_t bytes_moved_threshold; 505 uint64_t bytes_moved_vis_threshold; 506 uint64_t bytes_moved; 507 uint64_t bytes_moved_vis; 508 509 /* user fence */ 510 struct amdgpu_bo_list_entry uf_entry; 511 512 unsigned num_post_deps; 513 struct amdgpu_cs_post_dep *post_deps; 514 }; 515 516 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 517 uint32_t ib_idx, int idx) 518 { 519 return p->job->ibs[ib_idx].ptr[idx]; 520 } 521 522 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 523 uint32_t ib_idx, int idx, 524 uint32_t value) 525 { 526 p->job->ibs[ib_idx].ptr[idx] = value; 527 } 528 529 /* 530 * Writeback 531 */ 532 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 533 534 struct amdgpu_wb { 535 struct amdgpu_bo *wb_obj; 536 volatile uint32_t *wb; 537 uint64_t gpu_addr; 538 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 539 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 540 }; 541 542 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 543 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 544 545 /* 546 * Benchmarking 547 */ 548 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 549 550 551 /* 552 * Testing 553 */ 554 void amdgpu_test_moves(struct amdgpu_device *adev); 555 556 /* 557 * ASIC specific register table accessible by UMD 558 */ 559 struct amdgpu_allowed_register_entry { 560 uint32_t reg_offset; 561 bool grbm_indexed; 562 }; 563 564 enum amd_reset_method { 565 AMD_RESET_METHOD_LEGACY = 0, 566 AMD_RESET_METHOD_MODE0, 567 AMD_RESET_METHOD_MODE1, 568 AMD_RESET_METHOD_MODE2, 569 AMD_RESET_METHOD_BACO 570 }; 571 572 /* 573 * ASIC specific functions. 574 */ 575 struct amdgpu_asic_funcs { 576 bool (*read_disabled_bios)(struct amdgpu_device *adev); 577 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 578 u8 *bios, u32 length_bytes); 579 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 580 u32 sh_num, u32 reg_offset, u32 *value); 581 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 582 int (*reset)(struct amdgpu_device *adev); 583 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 584 /* get the reference clock */ 585 u32 (*get_xclk)(struct amdgpu_device *adev); 586 /* MM block clocks */ 587 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 588 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 589 /* static power management */ 590 int (*get_pcie_lanes)(struct amdgpu_device *adev); 591 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 592 /* get config memsize register */ 593 u32 (*get_config_memsize)(struct amdgpu_device *adev); 594 /* flush hdp write queue */ 595 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 596 /* invalidate hdp read cache */ 597 void (*invalidate_hdp)(struct amdgpu_device *adev, 598 struct amdgpu_ring *ring); 599 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev); 600 /* check if the asic needs a full reset of if soft reset will work */ 601 bool (*need_full_reset)(struct amdgpu_device *adev); 602 /* initialize doorbell layout for specific asic*/ 603 void (*init_doorbell_index)(struct amdgpu_device *adev); 604 /* PCIe bandwidth usage */ 605 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 606 uint64_t *count1); 607 /* do we need to reset the asic at init time (e.g., kexec) */ 608 bool (*need_reset_on_init)(struct amdgpu_device *adev); 609 /* PCIe replay counter */ 610 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 611 /* device supports BACO */ 612 bool (*supports_baco)(struct amdgpu_device *adev); 613 }; 614 615 /* 616 * IOCTL. 617 */ 618 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 619 struct drm_file *filp); 620 621 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 622 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 623 struct drm_file *filp); 624 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 625 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 626 struct drm_file *filp); 627 628 /* VRAM scratch page for HDP bug, default vram page */ 629 struct amdgpu_vram_scratch { 630 struct amdgpu_bo *robj; 631 volatile uint32_t *ptr; 632 u64 gpu_addr; 633 }; 634 635 /* 636 * ACPI 637 */ 638 struct amdgpu_atcs_functions { 639 bool get_ext_state; 640 bool pcie_perf_req; 641 bool pcie_dev_rdy; 642 bool pcie_bus_width; 643 }; 644 645 struct amdgpu_atcs { 646 struct amdgpu_atcs_functions functions; 647 }; 648 649 /* 650 * Firmware VRAM reservation 651 */ 652 struct amdgpu_fw_vram_usage { 653 u64 start_offset; 654 u64 size; 655 struct amdgpu_bo *reserved_bo; 656 void *va; 657 }; 658 659 /* 660 * CGS 661 */ 662 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 663 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 664 665 /* 666 * Core structure, functions and helpers. 667 */ 668 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 669 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 670 671 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 672 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 673 674 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 675 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 676 677 struct amdgpu_mmio_remap { 678 u32 reg_offset; 679 resource_size_t bus_addr; 680 }; 681 682 /* Define the HW IP blocks will be used in driver , add more if necessary */ 683 enum amd_hw_ip_block_type { 684 GC_HWIP = 1, 685 HDP_HWIP, 686 SDMA0_HWIP, 687 SDMA1_HWIP, 688 SDMA2_HWIP, 689 SDMA3_HWIP, 690 SDMA4_HWIP, 691 SDMA5_HWIP, 692 SDMA6_HWIP, 693 SDMA7_HWIP, 694 MMHUB_HWIP, 695 ATHUB_HWIP, 696 NBIO_HWIP, 697 MP0_HWIP, 698 MP1_HWIP, 699 UVD_HWIP, 700 VCN_HWIP = UVD_HWIP, 701 JPEG_HWIP = VCN_HWIP, 702 VCE_HWIP, 703 DF_HWIP, 704 DCE_HWIP, 705 OSSSYS_HWIP, 706 SMUIO_HWIP, 707 PWR_HWIP, 708 NBIF_HWIP, 709 THM_HWIP, 710 CLK_HWIP, 711 UMC_HWIP, 712 RSMU_HWIP, 713 MAX_HWIP 714 }; 715 716 #define HWIP_MAX_INSTANCE 8 717 718 struct amd_powerplay { 719 void *pp_handle; 720 const struct amd_pm_funcs *pp_funcs; 721 }; 722 723 #define AMDGPU_RESET_MAGIC_NUM 64 724 #define AMDGPU_MAX_DF_PERFMONS 4 725 struct amdgpu_device { 726 struct device *dev; 727 struct drm_device *ddev; 728 struct pci_dev *pdev; 729 730 #ifdef CONFIG_DRM_AMD_ACP 731 struct amdgpu_acp acp; 732 #endif 733 734 /* ASIC */ 735 enum amd_asic_type asic_type; 736 uint32_t family; 737 uint32_t rev_id; 738 uint32_t external_rev_id; 739 unsigned long flags; 740 unsigned long apu_flags; 741 int usec_timeout; 742 const struct amdgpu_asic_funcs *asic_funcs; 743 bool shutdown; 744 bool need_swiotlb; 745 bool accel_working; 746 struct notifier_block acpi_nb; 747 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 748 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 749 unsigned debugfs_count; 750 #if defined(CONFIG_DEBUG_FS) 751 struct dentry *debugfs_preempt; 752 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 753 #endif 754 struct amdgpu_atif *atif; 755 struct amdgpu_atcs atcs; 756 struct mutex srbm_mutex; 757 /* GRBM index mutex. Protects concurrent access to GRBM index */ 758 struct mutex grbm_idx_mutex; 759 struct dev_pm_domain vga_pm_domain; 760 bool have_disp_power_ref; 761 bool have_atomics_support; 762 763 /* BIOS */ 764 bool is_atom_fw; 765 uint8_t *bios; 766 uint32_t bios_size; 767 struct amdgpu_bo *stolen_vga_memory; 768 uint32_t bios_scratch_reg_offset; 769 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 770 771 /* Register/doorbell mmio */ 772 resource_size_t rmmio_base; 773 resource_size_t rmmio_size; 774 void __iomem *rmmio; 775 /* protects concurrent MM_INDEX/DATA based register access */ 776 spinlock_t mmio_idx_lock; 777 struct amdgpu_mmio_remap rmmio_remap; 778 /* protects concurrent SMC based register access */ 779 spinlock_t smc_idx_lock; 780 amdgpu_rreg_t smc_rreg; 781 amdgpu_wreg_t smc_wreg; 782 /* protects concurrent PCIE register access */ 783 spinlock_t pcie_idx_lock; 784 amdgpu_rreg_t pcie_rreg; 785 amdgpu_wreg_t pcie_wreg; 786 amdgpu_rreg_t pciep_rreg; 787 amdgpu_wreg_t pciep_wreg; 788 amdgpu_rreg64_t pcie_rreg64; 789 amdgpu_wreg64_t pcie_wreg64; 790 /* protects concurrent UVD register access */ 791 spinlock_t uvd_ctx_idx_lock; 792 amdgpu_rreg_t uvd_ctx_rreg; 793 amdgpu_wreg_t uvd_ctx_wreg; 794 /* protects concurrent DIDT register access */ 795 spinlock_t didt_idx_lock; 796 amdgpu_rreg_t didt_rreg; 797 amdgpu_wreg_t didt_wreg; 798 /* protects concurrent gc_cac register access */ 799 spinlock_t gc_cac_idx_lock; 800 amdgpu_rreg_t gc_cac_rreg; 801 amdgpu_wreg_t gc_cac_wreg; 802 /* protects concurrent se_cac register access */ 803 spinlock_t se_cac_idx_lock; 804 amdgpu_rreg_t se_cac_rreg; 805 amdgpu_wreg_t se_cac_wreg; 806 /* protects concurrent ENDPOINT (audio) register access */ 807 spinlock_t audio_endpt_idx_lock; 808 amdgpu_block_rreg_t audio_endpt_rreg; 809 amdgpu_block_wreg_t audio_endpt_wreg; 810 void __iomem *rio_mem; 811 resource_size_t rio_mem_size; 812 struct amdgpu_doorbell doorbell; 813 814 /* clock/pll info */ 815 struct amdgpu_clock clock; 816 817 /* MC */ 818 struct amdgpu_gmc gmc; 819 struct amdgpu_gart gart; 820 dma_addr_t dummy_page_addr; 821 struct amdgpu_vm_manager vm_manager; 822 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 823 unsigned num_vmhubs; 824 825 /* memory management */ 826 struct amdgpu_mman mman; 827 struct amdgpu_vram_scratch vram_scratch; 828 struct amdgpu_wb wb; 829 atomic64_t num_bytes_moved; 830 atomic64_t num_evictions; 831 atomic64_t num_vram_cpu_page_faults; 832 atomic_t gpu_reset_counter; 833 atomic_t vram_lost_counter; 834 835 /* data for buffer migration throttling */ 836 struct { 837 spinlock_t lock; 838 s64 last_update_us; 839 s64 accum_us; /* accumulated microseconds */ 840 s64 accum_us_vis; /* for visible VRAM */ 841 u32 log2_max_MBps; 842 } mm_stats; 843 844 /* display */ 845 bool enable_virtual_display; 846 struct amdgpu_mode_info mode_info; 847 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 848 struct work_struct hotplug_work; 849 struct amdgpu_irq_src crtc_irq; 850 struct amdgpu_irq_src vupdate_irq; 851 struct amdgpu_irq_src pageflip_irq; 852 struct amdgpu_irq_src hpd_irq; 853 854 /* rings */ 855 u64 fence_context; 856 unsigned num_rings; 857 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 858 bool ib_pool_ready; 859 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 860 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 861 862 /* interrupts */ 863 struct amdgpu_irq irq; 864 865 /* powerplay */ 866 struct amd_powerplay powerplay; 867 bool pp_force_state_enabled; 868 869 /* smu */ 870 struct smu_context smu; 871 872 /* dpm */ 873 struct amdgpu_pm pm; 874 u32 cg_flags; 875 u32 pg_flags; 876 877 /* nbio */ 878 struct amdgpu_nbio nbio; 879 880 /* mmhub */ 881 struct amdgpu_mmhub mmhub; 882 883 /* gfx */ 884 struct amdgpu_gfx gfx; 885 886 /* sdma */ 887 struct amdgpu_sdma sdma; 888 889 /* uvd */ 890 struct amdgpu_uvd uvd; 891 892 /* vce */ 893 struct amdgpu_vce vce; 894 895 /* vcn */ 896 struct amdgpu_vcn vcn; 897 898 /* jpeg */ 899 struct amdgpu_jpeg jpeg; 900 901 /* firmwares */ 902 struct amdgpu_firmware firmware; 903 904 /* PSP */ 905 struct psp_context psp; 906 907 /* GDS */ 908 struct amdgpu_gds gds; 909 910 /* KFD */ 911 struct amdgpu_kfd_dev kfd; 912 913 /* UMC */ 914 struct amdgpu_umc umc; 915 916 /* display related functionality */ 917 struct amdgpu_display_manager dm; 918 919 /* discovery */ 920 uint8_t *discovery_bin; 921 uint32_t discovery_tmr_size; 922 struct amdgpu_bo *discovery_memory; 923 924 /* mes */ 925 bool enable_mes; 926 struct amdgpu_mes mes; 927 928 /* df */ 929 struct amdgpu_df df; 930 931 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 932 int num_ip_blocks; 933 struct mutex mn_lock; 934 DECLARE_HASHTABLE(mn_hash, 7); 935 936 /* tracking pinned memory */ 937 atomic64_t vram_pin_size; 938 atomic64_t visible_pin_size; 939 atomic64_t gart_pin_size; 940 941 /* soc15 register offset based on ip, instance and segment */ 942 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 943 944 /* delayed work_func for deferring clockgating during resume */ 945 struct delayed_work delayed_init_work; 946 947 struct amdgpu_virt virt; 948 /* firmware VRAM reservation */ 949 struct amdgpu_fw_vram_usage fw_vram_usage; 950 951 /* link all shadow bo */ 952 struct list_head shadow_list; 953 struct mutex shadow_list_lock; 954 955 /* record hw reset is performed */ 956 bool has_hw_reset; 957 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 958 959 /* s3/s4 mask */ 960 bool in_suspend; 961 bool in_hibernate; 962 963 bool in_gpu_reset; 964 enum pp_mp1_state mp1_state; 965 struct mutex lock_reset; 966 struct amdgpu_doorbell_index doorbell_index; 967 968 struct mutex notifier_lock; 969 970 int asic_reset_res; 971 struct work_struct xgmi_reset_work; 972 973 long gfx_timeout; 974 long sdma_timeout; 975 long video_timeout; 976 long compute_timeout; 977 978 uint64_t unique_id; 979 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 980 981 /* enable runtime pm on the device */ 982 bool runpm; 983 bool in_runpm; 984 985 bool pm_sysfs_en; 986 bool ucode_sysfs_en; 987 988 /* Chip product information */ 989 char product_number[16]; 990 char product_name[32]; 991 char serial[20]; 992 993 struct amdgpu_autodump autodump; 994 995 atomic_t throttling_logging_enabled; 996 struct ratelimit_state throttling_logging_rs; 997 }; 998 999 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1000 { 1001 return container_of(bdev, struct amdgpu_device, mman.bdev); 1002 } 1003 1004 int amdgpu_device_init(struct amdgpu_device *adev, 1005 struct drm_device *ddev, 1006 struct pci_dev *pdev, 1007 uint32_t flags); 1008 void amdgpu_device_fini(struct amdgpu_device *adev); 1009 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1010 1011 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1012 uint32_t *buf, size_t size, bool write); 1013 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, 1014 uint32_t acc_flags); 1015 void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1016 uint32_t acc_flags); 1017 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1018 uint32_t acc_flags); 1019 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1020 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1021 1022 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1023 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1024 1025 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1026 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1027 1028 int emu_soc_asic_init(struct amdgpu_device *adev); 1029 1030 /* 1031 * Registers read & write functions. 1032 */ 1033 #define AMDGPU_REGS_NO_KIQ (1<<1) 1034 1035 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1036 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1037 1038 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1039 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1040 1041 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1042 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1043 1044 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1045 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1046 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1047 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1048 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1049 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1050 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1051 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1052 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1053 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1054 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1055 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1056 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1057 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1058 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1059 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1060 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1061 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1062 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1063 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1064 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1065 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1066 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1067 #define WREG32_P(reg, val, mask) \ 1068 do { \ 1069 uint32_t tmp_ = RREG32(reg); \ 1070 tmp_ &= (mask); \ 1071 tmp_ |= ((val) & ~(mask)); \ 1072 WREG32(reg, tmp_); \ 1073 } while (0) 1074 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1075 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1076 #define WREG32_PLL_P(reg, val, mask) \ 1077 do { \ 1078 uint32_t tmp_ = RREG32_PLL(reg); \ 1079 tmp_ &= (mask); \ 1080 tmp_ |= ((val) & ~(mask)); \ 1081 WREG32_PLL(reg, tmp_); \ 1082 } while (0) 1083 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1084 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1085 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1086 1087 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1088 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1089 1090 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1091 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1092 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1093 1094 #define REG_GET_FIELD(value, reg, field) \ 1095 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1096 1097 #define WREG32_FIELD(reg, field, val) \ 1098 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1099 1100 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1101 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1102 1103 /* 1104 * BIOS helpers. 1105 */ 1106 #define RBIOS8(i) (adev->bios[i]) 1107 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1108 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1109 1110 /* 1111 * ASICs macro. 1112 */ 1113 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1114 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1115 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1116 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1117 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1118 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1119 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1120 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1121 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1122 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1123 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1124 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1125 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1126 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1127 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1128 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1129 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1130 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1131 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1132 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1133 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1134 1135 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1136 1137 /* Common functions */ 1138 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1139 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1140 struct amdgpu_job* job); 1141 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1142 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1143 1144 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1145 u64 num_vis_bytes); 1146 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1147 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1148 const u32 *registers, 1149 const u32 array_size); 1150 1151 bool amdgpu_device_supports_boco(struct drm_device *dev); 1152 bool amdgpu_device_supports_baco(struct drm_device *dev); 1153 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1154 struct amdgpu_device *peer_adev); 1155 int amdgpu_device_baco_enter(struct drm_device *dev); 1156 int amdgpu_device_baco_exit(struct drm_device *dev); 1157 1158 /* atpx handler */ 1159 #if defined(CONFIG_VGA_SWITCHEROO) 1160 void amdgpu_register_atpx_handler(void); 1161 void amdgpu_unregister_atpx_handler(void); 1162 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1163 bool amdgpu_is_atpx_hybrid(void); 1164 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1165 bool amdgpu_has_atpx(void); 1166 #else 1167 static inline void amdgpu_register_atpx_handler(void) {} 1168 static inline void amdgpu_unregister_atpx_handler(void) {} 1169 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1170 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1171 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1172 static inline bool amdgpu_has_atpx(void) { return false; } 1173 #endif 1174 1175 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1176 void *amdgpu_atpx_get_dhandle(void); 1177 #else 1178 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1179 #endif 1180 1181 /* 1182 * KMS 1183 */ 1184 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1185 extern const int amdgpu_max_kms_ioctl; 1186 1187 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1188 void amdgpu_driver_unload_kms(struct drm_device *dev); 1189 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1190 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1191 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1192 struct drm_file *file_priv); 1193 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1194 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1195 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1196 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1197 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1198 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1199 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1200 unsigned long arg); 1201 1202 /* 1203 * functions used by amdgpu_encoder.c 1204 */ 1205 struct amdgpu_afmt_acr { 1206 u32 clock; 1207 1208 int n_32khz; 1209 int cts_32khz; 1210 1211 int n_44_1khz; 1212 int cts_44_1khz; 1213 1214 int n_48khz; 1215 int cts_48khz; 1216 1217 }; 1218 1219 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1220 1221 /* amdgpu_acpi.c */ 1222 #if defined(CONFIG_ACPI) 1223 int amdgpu_acpi_init(struct amdgpu_device *adev); 1224 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1225 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1226 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1227 u8 perf_req, bool advertise); 1228 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1229 1230 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1231 struct amdgpu_dm_backlight_caps *caps); 1232 #else 1233 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1234 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1235 #endif 1236 1237 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1238 uint64_t addr, struct amdgpu_bo **bo, 1239 struct amdgpu_bo_va_mapping **mapping); 1240 1241 #if defined(CONFIG_DRM_AMD_DC) 1242 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1243 #else 1244 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1245 #endif 1246 1247 1248 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1249 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1250 1251 #include "amdgpu_object.h" 1252 1253 /* used by df_v3_6.c and amdgpu_pmu.c */ 1254 #define AMDGPU_PMU_ATTR(_name, _object) \ 1255 static ssize_t \ 1256 _name##_show(struct device *dev, \ 1257 struct device_attribute *attr, \ 1258 char *page) \ 1259 { \ 1260 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1261 return sprintf(page, _object "\n"); \ 1262 } \ 1263 \ 1264 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1265 1266 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1267 { 1268 return adev->gmc.tmz_enabled; 1269 } 1270 1271 #endif 1272