1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include "amdgpu_ctx.h" 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/rbtree.h> 38 #include <linux/hashtable.h> 39 #include <linux/dma-fence.h> 40 41 #include <drm/ttm/ttm_bo_api.h> 42 #include <drm/ttm/ttm_bo_driver.h> 43 #include <drm/ttm/ttm_placement.h> 44 #include <drm/ttm/ttm_module.h> 45 #include <drm/ttm/ttm_execbuf_util.h> 46 47 #include <drm/drmP.h> 48 #include <drm/drm_gem.h> 49 #include <drm/amdgpu_drm.h> 50 #include <drm/gpu_scheduler.h> 51 52 #include <kgd_kfd_interface.h> 53 #include "dm_pp_interface.h" 54 #include "kgd_pp_interface.h" 55 56 #include "amd_shared.h" 57 #include "amdgpu_mode.h" 58 #include "amdgpu_ih.h" 59 #include "amdgpu_irq.h" 60 #include "amdgpu_ucode.h" 61 #include "amdgpu_ttm.h" 62 #include "amdgpu_psp.h" 63 #include "amdgpu_gds.h" 64 #include "amdgpu_sync.h" 65 #include "amdgpu_ring.h" 66 #include "amdgpu_vm.h" 67 #include "amdgpu_dpm.h" 68 #include "amdgpu_acp.h" 69 #include "amdgpu_uvd.h" 70 #include "amdgpu_vce.h" 71 #include "amdgpu_vcn.h" 72 #include "amdgpu_mn.h" 73 #include "amdgpu_gmc.h" 74 #include "amdgpu_gfx.h" 75 #include "amdgpu_sdma.h" 76 #include "amdgpu_dm.h" 77 #include "amdgpu_virt.h" 78 #include "amdgpu_csa.h" 79 #include "amdgpu_gart.h" 80 #include "amdgpu_debugfs.h" 81 #include "amdgpu_job.h" 82 #include "amdgpu_bo_list.h" 83 #include "amdgpu_gem.h" 84 #include "amdgpu_doorbell.h" 85 #include "amdgpu_amdkfd.h" 86 #include "amdgpu_smu.h" 87 88 #define MAX_GPU_INSTANCE 16 89 90 struct amdgpu_gpu_instance 91 { 92 struct amdgpu_device *adev; 93 int mgpu_fan_enabled; 94 }; 95 96 struct amdgpu_mgpu_info 97 { 98 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 99 struct mutex mutex; 100 uint32_t num_gpu; 101 uint32_t num_dgpu; 102 uint32_t num_apu; 103 }; 104 105 /* 106 * Modules parameters. 107 */ 108 extern int amdgpu_modeset; 109 extern int amdgpu_vram_limit; 110 extern int amdgpu_vis_vram_limit; 111 extern int amdgpu_gart_size; 112 extern int amdgpu_gtt_size; 113 extern int amdgpu_moverate; 114 extern int amdgpu_benchmarking; 115 extern int amdgpu_testing; 116 extern int amdgpu_audio; 117 extern int amdgpu_disp_priority; 118 extern int amdgpu_hw_i2c; 119 extern int amdgpu_pcie_gen2; 120 extern int amdgpu_msi; 121 extern int amdgpu_lockup_timeout; 122 extern int amdgpu_dpm; 123 extern int amdgpu_fw_load_type; 124 extern int amdgpu_aspm; 125 extern int amdgpu_runtime_pm; 126 extern uint amdgpu_ip_block_mask; 127 extern int amdgpu_bapm; 128 extern int amdgpu_deep_color; 129 extern int amdgpu_vm_size; 130 extern int amdgpu_vm_block_size; 131 extern int amdgpu_vm_fragment_size; 132 extern int amdgpu_vm_fault_stop; 133 extern int amdgpu_vm_debug; 134 extern int amdgpu_vm_update_mode; 135 extern int amdgpu_dc; 136 extern int amdgpu_sched_jobs; 137 extern int amdgpu_sched_hw_submission; 138 extern uint amdgpu_pcie_gen_cap; 139 extern uint amdgpu_pcie_lane_cap; 140 extern uint amdgpu_cg_mask; 141 extern uint amdgpu_pg_mask; 142 extern uint amdgpu_sdma_phase_quantum; 143 extern char *amdgpu_disable_cu; 144 extern char *amdgpu_virtual_display; 145 extern uint amdgpu_pp_feature_mask; 146 extern int amdgpu_vram_page_split; 147 extern int amdgpu_ngg; 148 extern int amdgpu_prim_buf_per_se; 149 extern int amdgpu_pos_buf_per_se; 150 extern int amdgpu_cntl_sb_buf_per_se; 151 extern int amdgpu_param_buf_per_se; 152 extern int amdgpu_job_hang_limit; 153 extern int amdgpu_lbpw; 154 extern int amdgpu_compute_multipipe; 155 extern int amdgpu_gpu_recovery; 156 extern int amdgpu_emu_mode; 157 extern uint amdgpu_smu_memory_pool_size; 158 extern uint amdgpu_dc_feature_mask; 159 extern struct amdgpu_mgpu_info mgpu_info; 160 extern int amdgpu_ras_enable; 161 extern uint amdgpu_ras_mask; 162 163 #ifdef CONFIG_DRM_AMDGPU_SI 164 extern int amdgpu_si_support; 165 #endif 166 #ifdef CONFIG_DRM_AMDGPU_CIK 167 extern int amdgpu_cik_support; 168 #endif 169 170 #define AMDGPU_VM_MAX_NUM_CTX 4096 171 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 172 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 173 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 174 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 175 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 176 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 177 #define AMDGPU_IB_POOL_SIZE 16 178 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 179 #define AMDGPUFB_CONN_LIMIT 4 180 #define AMDGPU_BIOS_NUM_SCRATCH 16 181 182 /* hard reset data */ 183 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 184 185 /* reset flags */ 186 #define AMDGPU_RESET_GFX (1 << 0) 187 #define AMDGPU_RESET_COMPUTE (1 << 1) 188 #define AMDGPU_RESET_DMA (1 << 2) 189 #define AMDGPU_RESET_CP (1 << 3) 190 #define AMDGPU_RESET_GRBM (1 << 4) 191 #define AMDGPU_RESET_DMA1 (1 << 5) 192 #define AMDGPU_RESET_RLC (1 << 6) 193 #define AMDGPU_RESET_SEM (1 << 7) 194 #define AMDGPU_RESET_IH (1 << 8) 195 #define AMDGPU_RESET_VMC (1 << 9) 196 #define AMDGPU_RESET_MC (1 << 10) 197 #define AMDGPU_RESET_DISPLAY (1 << 11) 198 #define AMDGPU_RESET_UVD (1 << 12) 199 #define AMDGPU_RESET_VCE (1 << 13) 200 #define AMDGPU_RESET_VCE1 (1 << 14) 201 202 /* max cursor sizes (in pixels) */ 203 #define CIK_CURSOR_WIDTH 128 204 #define CIK_CURSOR_HEIGHT 128 205 206 struct amdgpu_device; 207 struct amdgpu_ib; 208 struct amdgpu_cs_parser; 209 struct amdgpu_job; 210 struct amdgpu_irq_src; 211 struct amdgpu_fpriv; 212 struct amdgpu_bo_va_mapping; 213 struct amdgpu_atif; 214 215 enum amdgpu_cp_irq { 216 AMDGPU_CP_IRQ_GFX_EOP = 0, 217 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 218 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 219 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 220 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 221 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 222 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 223 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 224 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 225 226 AMDGPU_CP_IRQ_LAST 227 }; 228 229 enum amdgpu_thermal_irq { 230 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 231 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 232 233 AMDGPU_THERMAL_IRQ_LAST 234 }; 235 236 enum amdgpu_kiq_irq { 237 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 238 AMDGPU_CP_KIQ_IRQ_LAST 239 }; 240 241 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 242 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 243 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 244 245 int amdgpu_device_ip_set_clockgating_state(void *dev, 246 enum amd_ip_block_type block_type, 247 enum amd_clockgating_state state); 248 int amdgpu_device_ip_set_powergating_state(void *dev, 249 enum amd_ip_block_type block_type, 250 enum amd_powergating_state state); 251 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 252 u32 *flags); 253 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 254 enum amd_ip_block_type block_type); 255 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 256 enum amd_ip_block_type block_type); 257 258 #define AMDGPU_MAX_IP_NUM 16 259 260 struct amdgpu_ip_block_status { 261 bool valid; 262 bool sw; 263 bool hw; 264 bool late_initialized; 265 bool hang; 266 }; 267 268 struct amdgpu_ip_block_version { 269 const enum amd_ip_block_type type; 270 const u32 major; 271 const u32 minor; 272 const u32 rev; 273 const struct amd_ip_funcs *funcs; 274 }; 275 276 struct amdgpu_ip_block { 277 struct amdgpu_ip_block_status status; 278 const struct amdgpu_ip_block_version *version; 279 }; 280 281 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 282 enum amd_ip_block_type type, 283 u32 major, u32 minor); 284 285 struct amdgpu_ip_block * 286 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 287 enum amd_ip_block_type type); 288 289 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 290 const struct amdgpu_ip_block_version *ip_block_version); 291 292 /* 293 * BIOS. 294 */ 295 bool amdgpu_get_bios(struct amdgpu_device *adev); 296 bool amdgpu_read_bios(struct amdgpu_device *adev); 297 298 /* 299 * Clocks 300 */ 301 302 #define AMDGPU_MAX_PPLL 3 303 304 struct amdgpu_clock { 305 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 306 struct amdgpu_pll spll; 307 struct amdgpu_pll mpll; 308 /* 10 Khz units */ 309 uint32_t default_mclk; 310 uint32_t default_sclk; 311 uint32_t default_dispclk; 312 uint32_t current_dispclk; 313 uint32_t dp_extclk; 314 uint32_t max_pixel_clock; 315 }; 316 317 /* sub-allocation manager, it has to be protected by another lock. 318 * By conception this is an helper for other part of the driver 319 * like the indirect buffer or semaphore, which both have their 320 * locking. 321 * 322 * Principe is simple, we keep a list of sub allocation in offset 323 * order (first entry has offset == 0, last entry has the highest 324 * offset). 325 * 326 * When allocating new object we first check if there is room at 327 * the end total_size - (last_object_offset + last_object_size) >= 328 * alloc_size. If so we allocate new object there. 329 * 330 * When there is not enough room at the end, we start waiting for 331 * each sub object until we reach object_offset+object_size >= 332 * alloc_size, this object then become the sub object we return. 333 * 334 * Alignment can't be bigger than page size. 335 * 336 * Hole are not considered for allocation to keep things simple. 337 * Assumption is that there won't be hole (all object on same 338 * alignment). 339 */ 340 341 #define AMDGPU_SA_NUM_FENCE_LISTS 32 342 343 struct amdgpu_sa_manager { 344 wait_queue_head_t wq; 345 struct amdgpu_bo *bo; 346 struct list_head *hole; 347 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 348 struct list_head olist; 349 unsigned size; 350 uint64_t gpu_addr; 351 void *cpu_ptr; 352 uint32_t domain; 353 uint32_t align; 354 }; 355 356 /* sub-allocation buffer */ 357 struct amdgpu_sa_bo { 358 struct list_head olist; 359 struct list_head flist; 360 struct amdgpu_sa_manager *manager; 361 unsigned soffset; 362 unsigned eoffset; 363 struct dma_fence *fence; 364 }; 365 366 int amdgpu_fence_slab_init(void); 367 void amdgpu_fence_slab_fini(void); 368 369 /* 370 * IRQS. 371 */ 372 373 struct amdgpu_flip_work { 374 struct delayed_work flip_work; 375 struct work_struct unpin_work; 376 struct amdgpu_device *adev; 377 int crtc_id; 378 u32 target_vblank; 379 uint64_t base; 380 struct drm_pending_vblank_event *event; 381 struct amdgpu_bo *old_abo; 382 struct dma_fence *excl; 383 unsigned shared_count; 384 struct dma_fence **shared; 385 struct dma_fence_cb cb; 386 bool async; 387 }; 388 389 390 /* 391 * CP & rings. 392 */ 393 394 struct amdgpu_ib { 395 struct amdgpu_sa_bo *sa_bo; 396 uint32_t length_dw; 397 uint64_t gpu_addr; 398 uint32_t *ptr; 399 uint32_t flags; 400 }; 401 402 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 403 404 /* 405 * file private structure 406 */ 407 408 struct amdgpu_fpriv { 409 struct amdgpu_vm vm; 410 struct amdgpu_bo_va *prt_va; 411 struct amdgpu_bo_va *csa_va; 412 struct mutex bo_list_lock; 413 struct idr bo_list_handles; 414 struct amdgpu_ctx_mgr ctx_mgr; 415 }; 416 417 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 418 419 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 420 unsigned size, struct amdgpu_ib *ib); 421 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 422 struct dma_fence *f); 423 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 424 struct amdgpu_ib *ibs, struct amdgpu_job *job, 425 struct dma_fence **f); 426 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 427 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 428 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 429 430 /* 431 * CS. 432 */ 433 struct amdgpu_cs_chunk { 434 uint32_t chunk_id; 435 uint32_t length_dw; 436 void *kdata; 437 }; 438 439 struct amdgpu_cs_parser { 440 struct amdgpu_device *adev; 441 struct drm_file *filp; 442 struct amdgpu_ctx *ctx; 443 444 /* chunks */ 445 unsigned nchunks; 446 struct amdgpu_cs_chunk *chunks; 447 448 /* scheduler job object */ 449 struct amdgpu_job *job; 450 struct drm_sched_entity *entity; 451 452 /* buffer objects */ 453 struct ww_acquire_ctx ticket; 454 struct amdgpu_bo_list *bo_list; 455 struct amdgpu_mn *mn; 456 struct amdgpu_bo_list_entry vm_pd; 457 struct list_head validated; 458 struct dma_fence *fence; 459 uint64_t bytes_moved_threshold; 460 uint64_t bytes_moved_vis_threshold; 461 uint64_t bytes_moved; 462 uint64_t bytes_moved_vis; 463 struct amdgpu_bo_list_entry *evictable; 464 465 /* user fence */ 466 struct amdgpu_bo_list_entry uf_entry; 467 468 unsigned num_post_dep_syncobjs; 469 struct drm_syncobj **post_dep_syncobjs; 470 }; 471 472 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 473 uint32_t ib_idx, int idx) 474 { 475 return p->job->ibs[ib_idx].ptr[idx]; 476 } 477 478 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 479 uint32_t ib_idx, int idx, 480 uint32_t value) 481 { 482 p->job->ibs[ib_idx].ptr[idx] = value; 483 } 484 485 /* 486 * Writeback 487 */ 488 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 489 490 struct amdgpu_wb { 491 struct amdgpu_bo *wb_obj; 492 volatile uint32_t *wb; 493 uint64_t gpu_addr; 494 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 495 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 496 }; 497 498 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 499 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 500 501 /* 502 * Benchmarking 503 */ 504 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 505 506 507 /* 508 * Testing 509 */ 510 void amdgpu_test_moves(struct amdgpu_device *adev); 511 512 /* 513 * ASIC specific register table accessible by UMD 514 */ 515 struct amdgpu_allowed_register_entry { 516 uint32_t reg_offset; 517 bool grbm_indexed; 518 }; 519 520 /* 521 * ASIC specific functions. 522 */ 523 struct amdgpu_asic_funcs { 524 bool (*read_disabled_bios)(struct amdgpu_device *adev); 525 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 526 u8 *bios, u32 length_bytes); 527 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 528 u32 sh_num, u32 reg_offset, u32 *value); 529 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 530 int (*reset)(struct amdgpu_device *adev); 531 /* get the reference clock */ 532 u32 (*get_xclk)(struct amdgpu_device *adev); 533 /* MM block clocks */ 534 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 535 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 536 /* static power management */ 537 int (*get_pcie_lanes)(struct amdgpu_device *adev); 538 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 539 /* get config memsize register */ 540 u32 (*get_config_memsize)(struct amdgpu_device *adev); 541 /* flush hdp write queue */ 542 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 543 /* invalidate hdp read cache */ 544 void (*invalidate_hdp)(struct amdgpu_device *adev, 545 struct amdgpu_ring *ring); 546 /* check if the asic needs a full reset of if soft reset will work */ 547 bool (*need_full_reset)(struct amdgpu_device *adev); 548 /* initialize doorbell layout for specific asic*/ 549 void (*init_doorbell_index)(struct amdgpu_device *adev); 550 /* PCIe bandwidth usage */ 551 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 552 uint64_t *count1); 553 /* do we need to reset the asic at init time (e.g., kexec) */ 554 bool (*need_reset_on_init)(struct amdgpu_device *adev); 555 }; 556 557 /* 558 * IOCTL. 559 */ 560 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 561 struct drm_file *filp); 562 563 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 564 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 565 struct drm_file *filp); 566 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 567 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 568 struct drm_file *filp); 569 570 /* VRAM scratch page for HDP bug, default vram page */ 571 struct amdgpu_vram_scratch { 572 struct amdgpu_bo *robj; 573 volatile uint32_t *ptr; 574 u64 gpu_addr; 575 }; 576 577 /* 578 * ACPI 579 */ 580 struct amdgpu_atcs_functions { 581 bool get_ext_state; 582 bool pcie_perf_req; 583 bool pcie_dev_rdy; 584 bool pcie_bus_width; 585 }; 586 587 struct amdgpu_atcs { 588 struct amdgpu_atcs_functions functions; 589 }; 590 591 /* 592 * Firmware VRAM reservation 593 */ 594 struct amdgpu_fw_vram_usage { 595 u64 start_offset; 596 u64 size; 597 struct amdgpu_bo *reserved_bo; 598 void *va; 599 }; 600 601 /* 602 * CGS 603 */ 604 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 605 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 606 607 /* 608 * Core structure, functions and helpers. 609 */ 610 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 611 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 612 613 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 614 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 615 616 617 /* 618 * amdgpu nbio functions 619 * 620 */ 621 struct nbio_hdp_flush_reg { 622 u32 ref_and_mask_cp0; 623 u32 ref_and_mask_cp1; 624 u32 ref_and_mask_cp2; 625 u32 ref_and_mask_cp3; 626 u32 ref_and_mask_cp4; 627 u32 ref_and_mask_cp5; 628 u32 ref_and_mask_cp6; 629 u32 ref_and_mask_cp7; 630 u32 ref_and_mask_cp8; 631 u32 ref_and_mask_cp9; 632 u32 ref_and_mask_sdma0; 633 u32 ref_and_mask_sdma1; 634 }; 635 636 struct amdgpu_nbio_funcs { 637 const struct nbio_hdp_flush_reg *hdp_flush_reg; 638 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 639 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 640 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 641 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 642 u32 (*get_rev_id)(struct amdgpu_device *adev); 643 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 644 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 645 u32 (*get_memsize)(struct amdgpu_device *adev); 646 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 647 bool use_doorbell, int doorbell_index, int doorbell_size); 648 void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 649 bool enable); 650 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 651 bool enable); 652 void (*ih_doorbell_range)(struct amdgpu_device *adev, 653 bool use_doorbell, int doorbell_index); 654 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 655 bool enable); 656 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 657 bool enable); 658 void (*get_clockgating_state)(struct amdgpu_device *adev, 659 u32 *flags); 660 void (*ih_control)(struct amdgpu_device *adev); 661 void (*init_registers)(struct amdgpu_device *adev); 662 void (*detect_hw_virt)(struct amdgpu_device *adev); 663 }; 664 665 struct amdgpu_df_funcs { 666 void (*init)(struct amdgpu_device *adev); 667 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 668 bool enable); 669 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 670 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 671 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 672 bool enable); 673 void (*get_clockgating_state)(struct amdgpu_device *adev, 674 u32 *flags); 675 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 676 bool enable); 677 }; 678 /* Define the HW IP blocks will be used in driver , add more if necessary */ 679 enum amd_hw_ip_block_type { 680 GC_HWIP = 1, 681 HDP_HWIP, 682 SDMA0_HWIP, 683 SDMA1_HWIP, 684 MMHUB_HWIP, 685 ATHUB_HWIP, 686 NBIO_HWIP, 687 MP0_HWIP, 688 MP1_HWIP, 689 UVD_HWIP, 690 VCN_HWIP = UVD_HWIP, 691 VCE_HWIP, 692 DF_HWIP, 693 DCE_HWIP, 694 OSSSYS_HWIP, 695 SMUIO_HWIP, 696 PWR_HWIP, 697 NBIF_HWIP, 698 THM_HWIP, 699 CLK_HWIP, 700 MAX_HWIP 701 }; 702 703 #define HWIP_MAX_INSTANCE 6 704 705 struct amd_powerplay { 706 void *pp_handle; 707 const struct amd_pm_funcs *pp_funcs; 708 }; 709 710 #define AMDGPU_RESET_MAGIC_NUM 64 711 struct amdgpu_device { 712 struct device *dev; 713 struct drm_device *ddev; 714 struct pci_dev *pdev; 715 716 #ifdef CONFIG_DRM_AMD_ACP 717 struct amdgpu_acp acp; 718 #endif 719 720 /* ASIC */ 721 enum amd_asic_type asic_type; 722 uint32_t family; 723 uint32_t rev_id; 724 uint32_t external_rev_id; 725 unsigned long flags; 726 int usec_timeout; 727 const struct amdgpu_asic_funcs *asic_funcs; 728 bool shutdown; 729 bool need_dma32; 730 bool need_swiotlb; 731 bool accel_working; 732 struct notifier_block acpi_nb; 733 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 734 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 735 unsigned debugfs_count; 736 #if defined(CONFIG_DEBUG_FS) 737 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 738 #endif 739 struct amdgpu_atif *atif; 740 struct amdgpu_atcs atcs; 741 struct mutex srbm_mutex; 742 /* GRBM index mutex. Protects concurrent access to GRBM index */ 743 struct mutex grbm_idx_mutex; 744 struct dev_pm_domain vga_pm_domain; 745 bool have_disp_power_ref; 746 747 /* BIOS */ 748 bool is_atom_fw; 749 uint8_t *bios; 750 uint32_t bios_size; 751 struct amdgpu_bo *stolen_vga_memory; 752 uint32_t bios_scratch_reg_offset; 753 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 754 755 /* Register/doorbell mmio */ 756 resource_size_t rmmio_base; 757 resource_size_t rmmio_size; 758 void __iomem *rmmio; 759 /* protects concurrent MM_INDEX/DATA based register access */ 760 spinlock_t mmio_idx_lock; 761 /* protects concurrent SMC based register access */ 762 spinlock_t smc_idx_lock; 763 amdgpu_rreg_t smc_rreg; 764 amdgpu_wreg_t smc_wreg; 765 /* protects concurrent PCIE register access */ 766 spinlock_t pcie_idx_lock; 767 amdgpu_rreg_t pcie_rreg; 768 amdgpu_wreg_t pcie_wreg; 769 amdgpu_rreg_t pciep_rreg; 770 amdgpu_wreg_t pciep_wreg; 771 /* protects concurrent UVD register access */ 772 spinlock_t uvd_ctx_idx_lock; 773 amdgpu_rreg_t uvd_ctx_rreg; 774 amdgpu_wreg_t uvd_ctx_wreg; 775 /* protects concurrent DIDT register access */ 776 spinlock_t didt_idx_lock; 777 amdgpu_rreg_t didt_rreg; 778 amdgpu_wreg_t didt_wreg; 779 /* protects concurrent gc_cac register access */ 780 spinlock_t gc_cac_idx_lock; 781 amdgpu_rreg_t gc_cac_rreg; 782 amdgpu_wreg_t gc_cac_wreg; 783 /* protects concurrent se_cac register access */ 784 spinlock_t se_cac_idx_lock; 785 amdgpu_rreg_t se_cac_rreg; 786 amdgpu_wreg_t se_cac_wreg; 787 /* protects concurrent ENDPOINT (audio) register access */ 788 spinlock_t audio_endpt_idx_lock; 789 amdgpu_block_rreg_t audio_endpt_rreg; 790 amdgpu_block_wreg_t audio_endpt_wreg; 791 void __iomem *rio_mem; 792 resource_size_t rio_mem_size; 793 struct amdgpu_doorbell doorbell; 794 795 /* clock/pll info */ 796 struct amdgpu_clock clock; 797 798 /* MC */ 799 struct amdgpu_gmc gmc; 800 struct amdgpu_gart gart; 801 dma_addr_t dummy_page_addr; 802 struct amdgpu_vm_manager vm_manager; 803 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 804 805 /* memory management */ 806 struct amdgpu_mman mman; 807 struct amdgpu_vram_scratch vram_scratch; 808 struct amdgpu_wb wb; 809 atomic64_t num_bytes_moved; 810 atomic64_t num_evictions; 811 atomic64_t num_vram_cpu_page_faults; 812 atomic_t gpu_reset_counter; 813 atomic_t vram_lost_counter; 814 815 /* data for buffer migration throttling */ 816 struct { 817 spinlock_t lock; 818 s64 last_update_us; 819 s64 accum_us; /* accumulated microseconds */ 820 s64 accum_us_vis; /* for visible VRAM */ 821 u32 log2_max_MBps; 822 } mm_stats; 823 824 /* display */ 825 bool enable_virtual_display; 826 struct amdgpu_mode_info mode_info; 827 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 828 struct work_struct hotplug_work; 829 struct amdgpu_irq_src crtc_irq; 830 struct amdgpu_irq_src pageflip_irq; 831 struct amdgpu_irq_src hpd_irq; 832 833 /* rings */ 834 u64 fence_context; 835 unsigned num_rings; 836 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 837 bool ib_pool_ready; 838 struct amdgpu_sa_manager ring_tmp_bo; 839 840 /* interrupts */ 841 struct amdgpu_irq irq; 842 843 /* powerplay */ 844 struct amd_powerplay powerplay; 845 bool pp_force_state_enabled; 846 847 /* smu */ 848 struct smu_context smu; 849 850 /* dpm */ 851 struct amdgpu_pm pm; 852 u32 cg_flags; 853 u32 pg_flags; 854 855 /* gfx */ 856 struct amdgpu_gfx gfx; 857 858 /* sdma */ 859 struct amdgpu_sdma sdma; 860 861 /* uvd */ 862 struct amdgpu_uvd uvd; 863 864 /* vce */ 865 struct amdgpu_vce vce; 866 867 /* vcn */ 868 struct amdgpu_vcn vcn; 869 870 /* firmwares */ 871 struct amdgpu_firmware firmware; 872 873 /* PSP */ 874 struct psp_context psp; 875 876 /* GDS */ 877 struct amdgpu_gds gds; 878 879 /* KFD */ 880 struct amdgpu_kfd_dev kfd; 881 882 /* display related functionality */ 883 struct amdgpu_display_manager dm; 884 885 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 886 int num_ip_blocks; 887 struct mutex mn_lock; 888 DECLARE_HASHTABLE(mn_hash, 7); 889 890 /* tracking pinned memory */ 891 atomic64_t vram_pin_size; 892 atomic64_t visible_pin_size; 893 atomic64_t gart_pin_size; 894 895 /* soc15 register offset based on ip, instance and segment */ 896 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 897 898 const struct amdgpu_nbio_funcs *nbio_funcs; 899 const struct amdgpu_df_funcs *df_funcs; 900 901 /* delayed work_func for deferring clockgating during resume */ 902 struct delayed_work late_init_work; 903 904 struct amdgpu_virt virt; 905 /* firmware VRAM reservation */ 906 struct amdgpu_fw_vram_usage fw_vram_usage; 907 908 /* link all shadow bo */ 909 struct list_head shadow_list; 910 struct mutex shadow_list_lock; 911 /* keep an lru list of rings by HW IP */ 912 struct list_head ring_lru_list; 913 spinlock_t ring_lru_list_lock; 914 915 /* record hw reset is performed */ 916 bool has_hw_reset; 917 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 918 919 /* s3/s4 mask */ 920 bool in_suspend; 921 922 /* record last mm index being written through WREG32*/ 923 unsigned long last_mm_index; 924 bool in_gpu_reset; 925 struct mutex lock_reset; 926 struct amdgpu_doorbell_index doorbell_index; 927 928 int asic_reset_res; 929 struct work_struct xgmi_reset_work; 930 931 bool in_baco_reset; 932 }; 933 934 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 935 { 936 return container_of(bdev, struct amdgpu_device, mman.bdev); 937 } 938 939 int amdgpu_device_init(struct amdgpu_device *adev, 940 struct drm_device *ddev, 941 struct pci_dev *pdev, 942 uint32_t flags); 943 void amdgpu_device_fini(struct amdgpu_device *adev); 944 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 945 946 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 947 uint32_t acc_flags); 948 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 949 uint32_t acc_flags); 950 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 951 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 952 953 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 954 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 955 956 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 957 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 958 959 int emu_soc_asic_init(struct amdgpu_device *adev); 960 961 /* 962 * Registers read & write functions. 963 */ 964 965 #define AMDGPU_REGS_IDX (1<<0) 966 #define AMDGPU_REGS_NO_KIQ (1<<1) 967 968 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 969 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 970 971 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 972 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 973 974 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 975 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 976 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 977 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 978 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 979 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 980 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 981 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 982 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 983 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 984 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 985 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 986 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 987 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 988 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 989 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 990 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 991 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 992 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 993 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 994 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 995 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 996 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 997 #define WREG32_P(reg, val, mask) \ 998 do { \ 999 uint32_t tmp_ = RREG32(reg); \ 1000 tmp_ &= (mask); \ 1001 tmp_ |= ((val) & ~(mask)); \ 1002 WREG32(reg, tmp_); \ 1003 } while (0) 1004 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1005 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1006 #define WREG32_PLL_P(reg, val, mask) \ 1007 do { \ 1008 uint32_t tmp_ = RREG32_PLL(reg); \ 1009 tmp_ &= (mask); \ 1010 tmp_ |= ((val) & ~(mask)); \ 1011 WREG32_PLL(reg, tmp_); \ 1012 } while (0) 1013 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1014 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1015 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1016 1017 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1018 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1019 1020 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1021 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1022 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1023 1024 #define REG_GET_FIELD(value, reg, field) \ 1025 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1026 1027 #define WREG32_FIELD(reg, field, val) \ 1028 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1029 1030 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1031 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1032 1033 /* 1034 * BIOS helpers. 1035 */ 1036 #define RBIOS8(i) (adev->bios[i]) 1037 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1038 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1039 1040 /* 1041 * ASICs macro. 1042 */ 1043 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1044 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1045 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1046 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1047 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1048 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1049 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1050 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1051 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1052 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1053 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1054 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1055 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1056 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1057 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1058 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1059 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1060 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1061 1062 /* Common functions */ 1063 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1064 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1065 struct amdgpu_job* job); 1066 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1067 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1068 1069 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1070 u64 num_vis_bytes); 1071 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1072 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1073 const u32 *registers, 1074 const u32 array_size); 1075 1076 bool amdgpu_device_is_px(struct drm_device *dev); 1077 /* atpx handler */ 1078 #if defined(CONFIG_VGA_SWITCHEROO) 1079 void amdgpu_register_atpx_handler(void); 1080 void amdgpu_unregister_atpx_handler(void); 1081 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1082 bool amdgpu_is_atpx_hybrid(void); 1083 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1084 bool amdgpu_has_atpx(void); 1085 #else 1086 static inline void amdgpu_register_atpx_handler(void) {} 1087 static inline void amdgpu_unregister_atpx_handler(void) {} 1088 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1089 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1090 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1091 static inline bool amdgpu_has_atpx(void) { return false; } 1092 #endif 1093 1094 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1095 void *amdgpu_atpx_get_dhandle(void); 1096 #else 1097 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1098 #endif 1099 1100 /* 1101 * KMS 1102 */ 1103 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1104 extern const int amdgpu_max_kms_ioctl; 1105 1106 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1107 void amdgpu_driver_unload_kms(struct drm_device *dev); 1108 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1109 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1110 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1111 struct drm_file *file_priv); 1112 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1113 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1114 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1115 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1116 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1117 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1118 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1119 unsigned long arg); 1120 1121 /* 1122 * functions used by amdgpu_encoder.c 1123 */ 1124 struct amdgpu_afmt_acr { 1125 u32 clock; 1126 1127 int n_32khz; 1128 int cts_32khz; 1129 1130 int n_44_1khz; 1131 int cts_44_1khz; 1132 1133 int n_48khz; 1134 int cts_48khz; 1135 1136 }; 1137 1138 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1139 1140 /* amdgpu_acpi.c */ 1141 #if defined(CONFIG_ACPI) 1142 int amdgpu_acpi_init(struct amdgpu_device *adev); 1143 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1144 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1145 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1146 u8 perf_req, bool advertise); 1147 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1148 1149 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1150 struct amdgpu_dm_backlight_caps *caps); 1151 #else 1152 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1153 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1154 #endif 1155 1156 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1157 uint64_t addr, struct amdgpu_bo **bo, 1158 struct amdgpu_bo_va_mapping **mapping); 1159 1160 #if defined(CONFIG_DRM_AMD_DC) 1161 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1162 #else 1163 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1164 #endif 1165 1166 #include "amdgpu_object.h" 1167 #endif 1168