1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include "amdgpu_ctx.h" 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/rbtree.h> 38 #include <linux/hashtable.h> 39 #include <linux/dma-fence.h> 40 41 #include <drm/ttm/ttm_bo_api.h> 42 #include <drm/ttm/ttm_bo_driver.h> 43 #include <drm/ttm/ttm_placement.h> 44 #include <drm/ttm/ttm_module.h> 45 #include <drm/ttm/ttm_execbuf_util.h> 46 47 #include <drm/drmP.h> 48 #include <drm/drm_gem.h> 49 #include <drm/amdgpu_drm.h> 50 #include <drm/gpu_scheduler.h> 51 52 #include <kgd_kfd_interface.h> 53 #include "dm_pp_interface.h" 54 #include "kgd_pp_interface.h" 55 56 #include "amd_shared.h" 57 #include "amdgpu_mode.h" 58 #include "amdgpu_ih.h" 59 #include "amdgpu_irq.h" 60 #include "amdgpu_ucode.h" 61 #include "amdgpu_ttm.h" 62 #include "amdgpu_psp.h" 63 #include "amdgpu_gds.h" 64 #include "amdgpu_sync.h" 65 #include "amdgpu_ring.h" 66 #include "amdgpu_vm.h" 67 #include "amdgpu_dpm.h" 68 #include "amdgpu_acp.h" 69 #include "amdgpu_uvd.h" 70 #include "amdgpu_vce.h" 71 #include "amdgpu_vcn.h" 72 #include "amdgpu_mn.h" 73 #include "amdgpu_gmc.h" 74 #include "amdgpu_gfx.h" 75 #include "amdgpu_sdma.h" 76 #include "amdgpu_dm.h" 77 #include "amdgpu_virt.h" 78 #include "amdgpu_csa.h" 79 #include "amdgpu_gart.h" 80 #include "amdgpu_debugfs.h" 81 #include "amdgpu_job.h" 82 #include "amdgpu_bo_list.h" 83 #include "amdgpu_gem.h" 84 #include "amdgpu_doorbell.h" 85 #include "amdgpu_amdkfd.h" 86 #include "amdgpu_smu.h" 87 88 #define MAX_GPU_INSTANCE 16 89 90 struct amdgpu_gpu_instance 91 { 92 struct amdgpu_device *adev; 93 int mgpu_fan_enabled; 94 }; 95 96 struct amdgpu_mgpu_info 97 { 98 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 99 struct mutex mutex; 100 uint32_t num_gpu; 101 uint32_t num_dgpu; 102 uint32_t num_apu; 103 }; 104 105 /* 106 * Modules parameters. 107 */ 108 extern int amdgpu_modeset; 109 extern int amdgpu_vram_limit; 110 extern int amdgpu_vis_vram_limit; 111 extern int amdgpu_gart_size; 112 extern int amdgpu_gtt_size; 113 extern int amdgpu_moverate; 114 extern int amdgpu_benchmarking; 115 extern int amdgpu_testing; 116 extern int amdgpu_audio; 117 extern int amdgpu_disp_priority; 118 extern int amdgpu_hw_i2c; 119 extern int amdgpu_pcie_gen2; 120 extern int amdgpu_msi; 121 extern int amdgpu_dpm; 122 extern int amdgpu_fw_load_type; 123 extern int amdgpu_aspm; 124 extern int amdgpu_runtime_pm; 125 extern uint amdgpu_ip_block_mask; 126 extern int amdgpu_bapm; 127 extern int amdgpu_deep_color; 128 extern int amdgpu_vm_size; 129 extern int amdgpu_vm_block_size; 130 extern int amdgpu_vm_fragment_size; 131 extern int amdgpu_vm_fault_stop; 132 extern int amdgpu_vm_debug; 133 extern int amdgpu_vm_update_mode; 134 extern int amdgpu_dc; 135 extern int amdgpu_sched_jobs; 136 extern int amdgpu_sched_hw_submission; 137 extern uint amdgpu_pcie_gen_cap; 138 extern uint amdgpu_pcie_lane_cap; 139 extern uint amdgpu_cg_mask; 140 extern uint amdgpu_pg_mask; 141 extern uint amdgpu_sdma_phase_quantum; 142 extern char *amdgpu_disable_cu; 143 extern char *amdgpu_virtual_display; 144 extern uint amdgpu_pp_feature_mask; 145 extern int amdgpu_ngg; 146 extern int amdgpu_prim_buf_per_se; 147 extern int amdgpu_pos_buf_per_se; 148 extern int amdgpu_cntl_sb_buf_per_se; 149 extern int amdgpu_param_buf_per_se; 150 extern int amdgpu_job_hang_limit; 151 extern int amdgpu_lbpw; 152 extern int amdgpu_compute_multipipe; 153 extern int amdgpu_gpu_recovery; 154 extern int amdgpu_emu_mode; 155 extern uint amdgpu_smu_memory_pool_size; 156 extern uint amdgpu_dc_feature_mask; 157 extern uint amdgpu_dm_abm_level; 158 extern struct amdgpu_mgpu_info mgpu_info; 159 extern int amdgpu_ras_enable; 160 extern uint amdgpu_ras_mask; 161 extern int amdgpu_async_gfx_ring; 162 163 #ifdef CONFIG_DRM_AMDGPU_SI 164 extern int amdgpu_si_support; 165 #endif 166 #ifdef CONFIG_DRM_AMDGPU_CIK 167 extern int amdgpu_cik_support; 168 #endif 169 170 #define AMDGPU_VM_MAX_NUM_CTX 4096 171 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 172 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 173 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 174 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 175 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 176 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 177 #define AMDGPU_IB_POOL_SIZE 16 178 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 179 #define AMDGPUFB_CONN_LIMIT 4 180 #define AMDGPU_BIOS_NUM_SCRATCH 16 181 182 /* hard reset data */ 183 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 184 185 /* reset flags */ 186 #define AMDGPU_RESET_GFX (1 << 0) 187 #define AMDGPU_RESET_COMPUTE (1 << 1) 188 #define AMDGPU_RESET_DMA (1 << 2) 189 #define AMDGPU_RESET_CP (1 << 3) 190 #define AMDGPU_RESET_GRBM (1 << 4) 191 #define AMDGPU_RESET_DMA1 (1 << 5) 192 #define AMDGPU_RESET_RLC (1 << 6) 193 #define AMDGPU_RESET_SEM (1 << 7) 194 #define AMDGPU_RESET_IH (1 << 8) 195 #define AMDGPU_RESET_VMC (1 << 9) 196 #define AMDGPU_RESET_MC (1 << 10) 197 #define AMDGPU_RESET_DISPLAY (1 << 11) 198 #define AMDGPU_RESET_UVD (1 << 12) 199 #define AMDGPU_RESET_VCE (1 << 13) 200 #define AMDGPU_RESET_VCE1 (1 << 14) 201 202 /* max cursor sizes (in pixels) */ 203 #define CIK_CURSOR_WIDTH 128 204 #define CIK_CURSOR_HEIGHT 128 205 206 struct amdgpu_device; 207 struct amdgpu_ib; 208 struct amdgpu_cs_parser; 209 struct amdgpu_job; 210 struct amdgpu_irq_src; 211 struct amdgpu_fpriv; 212 struct amdgpu_bo_va_mapping; 213 struct amdgpu_atif; 214 struct kfd_vm_fault_info; 215 216 enum amdgpu_cp_irq { 217 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 218 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 219 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 220 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 221 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 222 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 223 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 224 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 225 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 226 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 227 228 AMDGPU_CP_IRQ_LAST 229 }; 230 231 enum amdgpu_thermal_irq { 232 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 233 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 234 235 AMDGPU_THERMAL_IRQ_LAST 236 }; 237 238 enum amdgpu_kiq_irq { 239 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 240 AMDGPU_CP_KIQ_IRQ_LAST 241 }; 242 243 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 244 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 245 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 246 247 int amdgpu_device_ip_set_clockgating_state(void *dev, 248 enum amd_ip_block_type block_type, 249 enum amd_clockgating_state state); 250 int amdgpu_device_ip_set_powergating_state(void *dev, 251 enum amd_ip_block_type block_type, 252 enum amd_powergating_state state); 253 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 254 u32 *flags); 255 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 256 enum amd_ip_block_type block_type); 257 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 258 enum amd_ip_block_type block_type); 259 260 #define AMDGPU_MAX_IP_NUM 16 261 262 struct amdgpu_ip_block_status { 263 bool valid; 264 bool sw; 265 bool hw; 266 bool late_initialized; 267 bool hang; 268 }; 269 270 struct amdgpu_ip_block_version { 271 const enum amd_ip_block_type type; 272 const u32 major; 273 const u32 minor; 274 const u32 rev; 275 const struct amd_ip_funcs *funcs; 276 }; 277 278 struct amdgpu_ip_block { 279 struct amdgpu_ip_block_status status; 280 const struct amdgpu_ip_block_version *version; 281 }; 282 283 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 284 enum amd_ip_block_type type, 285 u32 major, u32 minor); 286 287 struct amdgpu_ip_block * 288 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 289 enum amd_ip_block_type type); 290 291 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 292 const struct amdgpu_ip_block_version *ip_block_version); 293 294 /* 295 * BIOS. 296 */ 297 bool amdgpu_get_bios(struct amdgpu_device *adev); 298 bool amdgpu_read_bios(struct amdgpu_device *adev); 299 300 /* 301 * Clocks 302 */ 303 304 #define AMDGPU_MAX_PPLL 3 305 306 struct amdgpu_clock { 307 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 308 struct amdgpu_pll spll; 309 struct amdgpu_pll mpll; 310 /* 10 Khz units */ 311 uint32_t default_mclk; 312 uint32_t default_sclk; 313 uint32_t default_dispclk; 314 uint32_t current_dispclk; 315 uint32_t dp_extclk; 316 uint32_t max_pixel_clock; 317 }; 318 319 /* sub-allocation manager, it has to be protected by another lock. 320 * By conception this is an helper for other part of the driver 321 * like the indirect buffer or semaphore, which both have their 322 * locking. 323 * 324 * Principe is simple, we keep a list of sub allocation in offset 325 * order (first entry has offset == 0, last entry has the highest 326 * offset). 327 * 328 * When allocating new object we first check if there is room at 329 * the end total_size - (last_object_offset + last_object_size) >= 330 * alloc_size. If so we allocate new object there. 331 * 332 * When there is not enough room at the end, we start waiting for 333 * each sub object until we reach object_offset+object_size >= 334 * alloc_size, this object then become the sub object we return. 335 * 336 * Alignment can't be bigger than page size. 337 * 338 * Hole are not considered for allocation to keep things simple. 339 * Assumption is that there won't be hole (all object on same 340 * alignment). 341 */ 342 343 #define AMDGPU_SA_NUM_FENCE_LISTS 32 344 345 struct amdgpu_sa_manager { 346 wait_queue_head_t wq; 347 struct amdgpu_bo *bo; 348 struct list_head *hole; 349 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 350 struct list_head olist; 351 unsigned size; 352 uint64_t gpu_addr; 353 void *cpu_ptr; 354 uint32_t domain; 355 uint32_t align; 356 }; 357 358 /* sub-allocation buffer */ 359 struct amdgpu_sa_bo { 360 struct list_head olist; 361 struct list_head flist; 362 struct amdgpu_sa_manager *manager; 363 unsigned soffset; 364 unsigned eoffset; 365 struct dma_fence *fence; 366 }; 367 368 int amdgpu_fence_slab_init(void); 369 void amdgpu_fence_slab_fini(void); 370 371 /* 372 * IRQS. 373 */ 374 375 struct amdgpu_flip_work { 376 struct delayed_work flip_work; 377 struct work_struct unpin_work; 378 struct amdgpu_device *adev; 379 int crtc_id; 380 u32 target_vblank; 381 uint64_t base; 382 struct drm_pending_vblank_event *event; 383 struct amdgpu_bo *old_abo; 384 struct dma_fence *excl; 385 unsigned shared_count; 386 struct dma_fence **shared; 387 struct dma_fence_cb cb; 388 bool async; 389 }; 390 391 392 /* 393 * CP & rings. 394 */ 395 396 struct amdgpu_ib { 397 struct amdgpu_sa_bo *sa_bo; 398 uint32_t length_dw; 399 uint64_t gpu_addr; 400 uint32_t *ptr; 401 uint32_t flags; 402 }; 403 404 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 405 406 /* 407 * file private structure 408 */ 409 410 struct amdgpu_fpriv { 411 struct amdgpu_vm vm; 412 struct amdgpu_bo_va *prt_va; 413 struct amdgpu_bo_va *csa_va; 414 struct mutex bo_list_lock; 415 struct idr bo_list_handles; 416 struct amdgpu_ctx_mgr ctx_mgr; 417 }; 418 419 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 420 int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev); 421 422 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 423 unsigned size, struct amdgpu_ib *ib); 424 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 425 struct dma_fence *f); 426 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 427 struct amdgpu_ib *ibs, struct amdgpu_job *job, 428 struct dma_fence **f); 429 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 430 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 431 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 432 433 /* 434 * CS. 435 */ 436 struct amdgpu_cs_chunk { 437 uint32_t chunk_id; 438 uint32_t length_dw; 439 void *kdata; 440 }; 441 442 struct amdgpu_cs_post_dep { 443 struct drm_syncobj *syncobj; 444 struct dma_fence_chain *chain; 445 u64 point; 446 }; 447 448 struct amdgpu_cs_parser { 449 struct amdgpu_device *adev; 450 struct drm_file *filp; 451 struct amdgpu_ctx *ctx; 452 453 /* chunks */ 454 unsigned nchunks; 455 struct amdgpu_cs_chunk *chunks; 456 457 /* scheduler job object */ 458 struct amdgpu_job *job; 459 struct drm_sched_entity *entity; 460 461 /* buffer objects */ 462 struct ww_acquire_ctx ticket; 463 struct amdgpu_bo_list *bo_list; 464 struct amdgpu_mn *mn; 465 struct amdgpu_bo_list_entry vm_pd; 466 struct list_head validated; 467 struct dma_fence *fence; 468 uint64_t bytes_moved_threshold; 469 uint64_t bytes_moved_vis_threshold; 470 uint64_t bytes_moved; 471 uint64_t bytes_moved_vis; 472 struct amdgpu_bo_list_entry *evictable; 473 474 /* user fence */ 475 struct amdgpu_bo_list_entry uf_entry; 476 477 unsigned num_post_deps; 478 struct amdgpu_cs_post_dep *post_deps; 479 }; 480 481 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 482 uint32_t ib_idx, int idx) 483 { 484 return p->job->ibs[ib_idx].ptr[idx]; 485 } 486 487 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 488 uint32_t ib_idx, int idx, 489 uint32_t value) 490 { 491 p->job->ibs[ib_idx].ptr[idx] = value; 492 } 493 494 /* 495 * Writeback 496 */ 497 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 498 499 struct amdgpu_wb { 500 struct amdgpu_bo *wb_obj; 501 volatile uint32_t *wb; 502 uint64_t gpu_addr; 503 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 504 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 505 }; 506 507 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 508 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 509 510 /* 511 * Benchmarking 512 */ 513 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 514 515 516 /* 517 * Testing 518 */ 519 void amdgpu_test_moves(struct amdgpu_device *adev); 520 521 /* 522 * ASIC specific register table accessible by UMD 523 */ 524 struct amdgpu_allowed_register_entry { 525 uint32_t reg_offset; 526 bool grbm_indexed; 527 }; 528 529 /* 530 * ASIC specific functions. 531 */ 532 struct amdgpu_asic_funcs { 533 bool (*read_disabled_bios)(struct amdgpu_device *adev); 534 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 535 u8 *bios, u32 length_bytes); 536 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 537 u32 sh_num, u32 reg_offset, u32 *value); 538 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 539 int (*reset)(struct amdgpu_device *adev); 540 /* get the reference clock */ 541 u32 (*get_xclk)(struct amdgpu_device *adev); 542 /* MM block clocks */ 543 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 544 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 545 /* static power management */ 546 int (*get_pcie_lanes)(struct amdgpu_device *adev); 547 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 548 /* get config memsize register */ 549 u32 (*get_config_memsize)(struct amdgpu_device *adev); 550 /* flush hdp write queue */ 551 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 552 /* invalidate hdp read cache */ 553 void (*invalidate_hdp)(struct amdgpu_device *adev, 554 struct amdgpu_ring *ring); 555 /* check if the asic needs a full reset of if soft reset will work */ 556 bool (*need_full_reset)(struct amdgpu_device *adev); 557 /* initialize doorbell layout for specific asic*/ 558 void (*init_doorbell_index)(struct amdgpu_device *adev); 559 /* PCIe bandwidth usage */ 560 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 561 uint64_t *count1); 562 /* do we need to reset the asic at init time (e.g., kexec) */ 563 bool (*need_reset_on_init)(struct amdgpu_device *adev); 564 /* PCIe replay counter */ 565 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 566 }; 567 568 /* 569 * IOCTL. 570 */ 571 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 572 struct drm_file *filp); 573 574 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 575 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 576 struct drm_file *filp); 577 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 578 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 579 struct drm_file *filp); 580 581 /* VRAM scratch page for HDP bug, default vram page */ 582 struct amdgpu_vram_scratch { 583 struct amdgpu_bo *robj; 584 volatile uint32_t *ptr; 585 u64 gpu_addr; 586 }; 587 588 /* 589 * ACPI 590 */ 591 struct amdgpu_atcs_functions { 592 bool get_ext_state; 593 bool pcie_perf_req; 594 bool pcie_dev_rdy; 595 bool pcie_bus_width; 596 }; 597 598 struct amdgpu_atcs { 599 struct amdgpu_atcs_functions functions; 600 }; 601 602 /* 603 * Firmware VRAM reservation 604 */ 605 struct amdgpu_fw_vram_usage { 606 u64 start_offset; 607 u64 size; 608 struct amdgpu_bo *reserved_bo; 609 void *va; 610 }; 611 612 /* 613 * CGS 614 */ 615 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 616 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 617 618 /* 619 * Core structure, functions and helpers. 620 */ 621 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 622 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 623 624 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 625 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 626 627 628 /* 629 * amdgpu nbio functions 630 * 631 */ 632 struct nbio_hdp_flush_reg { 633 u32 ref_and_mask_cp0; 634 u32 ref_and_mask_cp1; 635 u32 ref_and_mask_cp2; 636 u32 ref_and_mask_cp3; 637 u32 ref_and_mask_cp4; 638 u32 ref_and_mask_cp5; 639 u32 ref_and_mask_cp6; 640 u32 ref_and_mask_cp7; 641 u32 ref_and_mask_cp8; 642 u32 ref_and_mask_cp9; 643 u32 ref_and_mask_sdma0; 644 u32 ref_and_mask_sdma1; 645 }; 646 647 struct amdgpu_mmio_remap { 648 u32 reg_offset; 649 resource_size_t bus_addr; 650 }; 651 652 struct amdgpu_nbio_funcs { 653 const struct nbio_hdp_flush_reg *hdp_flush_reg; 654 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 655 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 656 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 657 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 658 u32 (*get_rev_id)(struct amdgpu_device *adev); 659 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 660 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 661 u32 (*get_memsize)(struct amdgpu_device *adev); 662 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 663 bool use_doorbell, int doorbell_index, int doorbell_size); 664 void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell, 665 int doorbell_index); 666 void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 667 bool enable); 668 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 669 bool enable); 670 void (*ih_doorbell_range)(struct amdgpu_device *adev, 671 bool use_doorbell, int doorbell_index); 672 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 673 bool enable); 674 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 675 bool enable); 676 void (*get_clockgating_state)(struct amdgpu_device *adev, 677 u32 *flags); 678 void (*ih_control)(struct amdgpu_device *adev); 679 void (*init_registers)(struct amdgpu_device *adev); 680 void (*detect_hw_virt)(struct amdgpu_device *adev); 681 void (*remap_hdp_registers)(struct amdgpu_device *adev); 682 }; 683 684 struct amdgpu_df_funcs { 685 void (*init)(struct amdgpu_device *adev); 686 void (*sw_init)(struct amdgpu_device *adev); 687 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 688 bool enable); 689 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 690 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 691 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 692 bool enable); 693 void (*get_clockgating_state)(struct amdgpu_device *adev, 694 u32 *flags); 695 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 696 bool enable); 697 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config, 698 int is_enable); 699 int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config, 700 int is_disable); 701 void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config, 702 uint64_t *count); 703 }; 704 /* Define the HW IP blocks will be used in driver , add more if necessary */ 705 enum amd_hw_ip_block_type { 706 GC_HWIP = 1, 707 HDP_HWIP, 708 SDMA0_HWIP, 709 SDMA1_HWIP, 710 MMHUB_HWIP, 711 ATHUB_HWIP, 712 NBIO_HWIP, 713 MP0_HWIP, 714 MP1_HWIP, 715 UVD_HWIP, 716 VCN_HWIP = UVD_HWIP, 717 VCE_HWIP, 718 DF_HWIP, 719 DCE_HWIP, 720 OSSSYS_HWIP, 721 SMUIO_HWIP, 722 PWR_HWIP, 723 NBIF_HWIP, 724 THM_HWIP, 725 CLK_HWIP, 726 MAX_HWIP 727 }; 728 729 #define HWIP_MAX_INSTANCE 6 730 731 struct amd_powerplay { 732 void *pp_handle; 733 const struct amd_pm_funcs *pp_funcs; 734 }; 735 736 #define AMDGPU_RESET_MAGIC_NUM 64 737 #define AMDGPU_MAX_DF_PERFMONS 4 738 struct amdgpu_device { 739 struct device *dev; 740 struct drm_device *ddev; 741 struct pci_dev *pdev; 742 743 #ifdef CONFIG_DRM_AMD_ACP 744 struct amdgpu_acp acp; 745 #endif 746 747 /* ASIC */ 748 enum amd_asic_type asic_type; 749 uint32_t family; 750 uint32_t rev_id; 751 uint32_t external_rev_id; 752 unsigned long flags; 753 int usec_timeout; 754 const struct amdgpu_asic_funcs *asic_funcs; 755 bool shutdown; 756 bool need_dma32; 757 bool need_swiotlb; 758 bool accel_working; 759 struct notifier_block acpi_nb; 760 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 761 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 762 unsigned debugfs_count; 763 #if defined(CONFIG_DEBUG_FS) 764 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 765 #endif 766 struct amdgpu_atif *atif; 767 struct amdgpu_atcs atcs; 768 struct mutex srbm_mutex; 769 /* GRBM index mutex. Protects concurrent access to GRBM index */ 770 struct mutex grbm_idx_mutex; 771 struct dev_pm_domain vga_pm_domain; 772 bool have_disp_power_ref; 773 774 /* BIOS */ 775 bool is_atom_fw; 776 uint8_t *bios; 777 uint32_t bios_size; 778 struct amdgpu_bo *stolen_vga_memory; 779 uint32_t bios_scratch_reg_offset; 780 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 781 782 /* Register/doorbell mmio */ 783 resource_size_t rmmio_base; 784 resource_size_t rmmio_size; 785 void __iomem *rmmio; 786 /* protects concurrent MM_INDEX/DATA based register access */ 787 spinlock_t mmio_idx_lock; 788 struct amdgpu_mmio_remap rmmio_remap; 789 /* protects concurrent SMC based register access */ 790 spinlock_t smc_idx_lock; 791 amdgpu_rreg_t smc_rreg; 792 amdgpu_wreg_t smc_wreg; 793 /* protects concurrent PCIE register access */ 794 spinlock_t pcie_idx_lock; 795 amdgpu_rreg_t pcie_rreg; 796 amdgpu_wreg_t pcie_wreg; 797 amdgpu_rreg_t pciep_rreg; 798 amdgpu_wreg_t pciep_wreg; 799 /* protects concurrent UVD register access */ 800 spinlock_t uvd_ctx_idx_lock; 801 amdgpu_rreg_t uvd_ctx_rreg; 802 amdgpu_wreg_t uvd_ctx_wreg; 803 /* protects concurrent DIDT register access */ 804 spinlock_t didt_idx_lock; 805 amdgpu_rreg_t didt_rreg; 806 amdgpu_wreg_t didt_wreg; 807 /* protects concurrent gc_cac register access */ 808 spinlock_t gc_cac_idx_lock; 809 amdgpu_rreg_t gc_cac_rreg; 810 amdgpu_wreg_t gc_cac_wreg; 811 /* protects concurrent se_cac register access */ 812 spinlock_t se_cac_idx_lock; 813 amdgpu_rreg_t se_cac_rreg; 814 amdgpu_wreg_t se_cac_wreg; 815 /* protects concurrent ENDPOINT (audio) register access */ 816 spinlock_t audio_endpt_idx_lock; 817 amdgpu_block_rreg_t audio_endpt_rreg; 818 amdgpu_block_wreg_t audio_endpt_wreg; 819 void __iomem *rio_mem; 820 resource_size_t rio_mem_size; 821 struct amdgpu_doorbell doorbell; 822 823 /* clock/pll info */ 824 struct amdgpu_clock clock; 825 826 /* MC */ 827 struct amdgpu_gmc gmc; 828 struct amdgpu_gart gart; 829 dma_addr_t dummy_page_addr; 830 struct amdgpu_vm_manager vm_manager; 831 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 832 833 /* memory management */ 834 struct amdgpu_mman mman; 835 struct amdgpu_vram_scratch vram_scratch; 836 struct amdgpu_wb wb; 837 atomic64_t num_bytes_moved; 838 atomic64_t num_evictions; 839 atomic64_t num_vram_cpu_page_faults; 840 atomic_t gpu_reset_counter; 841 atomic_t vram_lost_counter; 842 843 /* data for buffer migration throttling */ 844 struct { 845 spinlock_t lock; 846 s64 last_update_us; 847 s64 accum_us; /* accumulated microseconds */ 848 s64 accum_us_vis; /* for visible VRAM */ 849 u32 log2_max_MBps; 850 } mm_stats; 851 852 /* display */ 853 bool enable_virtual_display; 854 struct amdgpu_mode_info mode_info; 855 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 856 struct work_struct hotplug_work; 857 struct amdgpu_irq_src crtc_irq; 858 struct amdgpu_irq_src vupdate_irq; 859 struct amdgpu_irq_src pageflip_irq; 860 struct amdgpu_irq_src hpd_irq; 861 862 /* rings */ 863 u64 fence_context; 864 unsigned num_rings; 865 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 866 bool ib_pool_ready; 867 struct amdgpu_sa_manager ring_tmp_bo; 868 869 /* interrupts */ 870 struct amdgpu_irq irq; 871 872 /* powerplay */ 873 struct amd_powerplay powerplay; 874 bool pp_force_state_enabled; 875 876 /* smu */ 877 struct smu_context smu; 878 879 /* dpm */ 880 struct amdgpu_pm pm; 881 u32 cg_flags; 882 u32 pg_flags; 883 884 /* gfx */ 885 struct amdgpu_gfx gfx; 886 887 /* sdma */ 888 struct amdgpu_sdma sdma; 889 890 /* uvd */ 891 struct amdgpu_uvd uvd; 892 893 /* vce */ 894 struct amdgpu_vce vce; 895 896 /* vcn */ 897 struct amdgpu_vcn vcn; 898 899 /* firmwares */ 900 struct amdgpu_firmware firmware; 901 902 /* PSP */ 903 struct psp_context psp; 904 905 /* GDS */ 906 struct amdgpu_gds gds; 907 908 /* KFD */ 909 struct amdgpu_kfd_dev kfd; 910 911 /* display related functionality */ 912 struct amdgpu_display_manager dm; 913 914 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 915 int num_ip_blocks; 916 struct mutex mn_lock; 917 DECLARE_HASHTABLE(mn_hash, 7); 918 919 /* tracking pinned memory */ 920 atomic64_t vram_pin_size; 921 atomic64_t visible_pin_size; 922 atomic64_t gart_pin_size; 923 924 /* soc15 register offset based on ip, instance and segment */ 925 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 926 927 const struct amdgpu_nbio_funcs *nbio_funcs; 928 const struct amdgpu_df_funcs *df_funcs; 929 930 /* delayed work_func for deferring clockgating during resume */ 931 struct delayed_work delayed_init_work; 932 933 struct amdgpu_virt virt; 934 /* firmware VRAM reservation */ 935 struct amdgpu_fw_vram_usage fw_vram_usage; 936 937 /* link all shadow bo */ 938 struct list_head shadow_list; 939 struct mutex shadow_list_lock; 940 /* keep an lru list of rings by HW IP */ 941 struct list_head ring_lru_list; 942 spinlock_t ring_lru_list_lock; 943 944 /* record hw reset is performed */ 945 bool has_hw_reset; 946 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 947 948 /* s3/s4 mask */ 949 bool in_suspend; 950 951 /* record last mm index being written through WREG32*/ 952 unsigned long last_mm_index; 953 bool in_gpu_reset; 954 struct mutex lock_reset; 955 struct amdgpu_doorbell_index doorbell_index; 956 957 int asic_reset_res; 958 struct work_struct xgmi_reset_work; 959 960 bool in_baco_reset; 961 962 long gfx_timeout; 963 long sdma_timeout; 964 long video_timeout; 965 long compute_timeout; 966 967 uint64_t unique_id; 968 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 969 }; 970 971 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 972 { 973 return container_of(bdev, struct amdgpu_device, mman.bdev); 974 } 975 976 int amdgpu_device_init(struct amdgpu_device *adev, 977 struct drm_device *ddev, 978 struct pci_dev *pdev, 979 uint32_t flags); 980 void amdgpu_device_fini(struct amdgpu_device *adev); 981 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 982 983 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 984 uint32_t acc_flags); 985 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 986 uint32_t acc_flags); 987 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 988 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 989 990 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 991 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 992 993 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 994 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 995 996 int emu_soc_asic_init(struct amdgpu_device *adev); 997 998 /* 999 * Registers read & write functions. 1000 */ 1001 1002 #define AMDGPU_REGS_IDX (1<<0) 1003 #define AMDGPU_REGS_NO_KIQ (1<<1) 1004 1005 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1006 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1007 1008 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1009 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1010 1011 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1012 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1013 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1014 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1015 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1016 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1017 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1018 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1019 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1020 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1021 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1022 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1023 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1024 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1025 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1026 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1027 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1028 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1029 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1030 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1031 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1032 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1033 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1034 #define WREG32_P(reg, val, mask) \ 1035 do { \ 1036 uint32_t tmp_ = RREG32(reg); \ 1037 tmp_ &= (mask); \ 1038 tmp_ |= ((val) & ~(mask)); \ 1039 WREG32(reg, tmp_); \ 1040 } while (0) 1041 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1042 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1043 #define WREG32_PLL_P(reg, val, mask) \ 1044 do { \ 1045 uint32_t tmp_ = RREG32_PLL(reg); \ 1046 tmp_ &= (mask); \ 1047 tmp_ |= ((val) & ~(mask)); \ 1048 WREG32_PLL(reg, tmp_); \ 1049 } while (0) 1050 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1051 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1052 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1053 1054 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1055 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1056 1057 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1058 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1059 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1060 1061 #define REG_GET_FIELD(value, reg, field) \ 1062 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1063 1064 #define WREG32_FIELD(reg, field, val) \ 1065 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1066 1067 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1068 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1069 1070 /* 1071 * BIOS helpers. 1072 */ 1073 #define RBIOS8(i) (adev->bios[i]) 1074 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1075 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1076 1077 /* 1078 * ASICs macro. 1079 */ 1080 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1081 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1082 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1083 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1084 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1085 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1086 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1087 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1088 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1089 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1090 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1091 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1092 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1093 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1094 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1095 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1096 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1097 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1098 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1099 1100 /* Common functions */ 1101 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1102 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1103 struct amdgpu_job* job); 1104 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1105 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1106 1107 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1108 u64 num_vis_bytes); 1109 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1110 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1111 const u32 *registers, 1112 const u32 array_size); 1113 1114 bool amdgpu_device_is_px(struct drm_device *dev); 1115 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1116 struct amdgpu_device *peer_adev); 1117 1118 /* atpx handler */ 1119 #if defined(CONFIG_VGA_SWITCHEROO) 1120 void amdgpu_register_atpx_handler(void); 1121 void amdgpu_unregister_atpx_handler(void); 1122 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1123 bool amdgpu_is_atpx_hybrid(void); 1124 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1125 bool amdgpu_has_atpx(void); 1126 #else 1127 static inline void amdgpu_register_atpx_handler(void) {} 1128 static inline void amdgpu_unregister_atpx_handler(void) {} 1129 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1130 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1131 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1132 static inline bool amdgpu_has_atpx(void) { return false; } 1133 #endif 1134 1135 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1136 void *amdgpu_atpx_get_dhandle(void); 1137 #else 1138 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1139 #endif 1140 1141 /* 1142 * KMS 1143 */ 1144 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1145 extern const int amdgpu_max_kms_ioctl; 1146 1147 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1148 void amdgpu_driver_unload_kms(struct drm_device *dev); 1149 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1150 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1151 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1152 struct drm_file *file_priv); 1153 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1154 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1155 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1156 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1157 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1158 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1159 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1160 unsigned long arg); 1161 1162 /* 1163 * functions used by amdgpu_encoder.c 1164 */ 1165 struct amdgpu_afmt_acr { 1166 u32 clock; 1167 1168 int n_32khz; 1169 int cts_32khz; 1170 1171 int n_44_1khz; 1172 int cts_44_1khz; 1173 1174 int n_48khz; 1175 int cts_48khz; 1176 1177 }; 1178 1179 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1180 1181 /* amdgpu_acpi.c */ 1182 #if defined(CONFIG_ACPI) 1183 int amdgpu_acpi_init(struct amdgpu_device *adev); 1184 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1185 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1186 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1187 u8 perf_req, bool advertise); 1188 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1189 1190 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1191 struct amdgpu_dm_backlight_caps *caps); 1192 #else 1193 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1194 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1195 #endif 1196 1197 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1198 uint64_t addr, struct amdgpu_bo **bo, 1199 struct amdgpu_bo_va_mapping **mapping); 1200 1201 #if defined(CONFIG_DRM_AMD_DC) 1202 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1203 #else 1204 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1205 #endif 1206 1207 #include "amdgpu_object.h" 1208 1209 /* used by df_v3_6.c and amdgpu_pmu.c */ 1210 #define AMDGPU_PMU_ATTR(_name, _object) \ 1211 static ssize_t \ 1212 _name##_show(struct device *dev, \ 1213 struct device_attribute *attr, \ 1214 char *page) \ 1215 { \ 1216 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1217 return sprintf(page, _object "\n"); \ 1218 } \ 1219 \ 1220 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1221 1222 #endif 1223 1224