1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_execbuf_util.h> 59 60 #include <drm/amdgpu_drm.h> 61 #include <drm/drm_gem.h> 62 #include <drm/drm_ioctl.h> 63 #include <drm/gpu_scheduler.h> 64 65 #include <kgd_kfd_interface.h> 66 #include "dm_pp_interface.h" 67 #include "kgd_pp_interface.h" 68 69 #include "amd_shared.h" 70 #include "amdgpu_mode.h" 71 #include "amdgpu_ih.h" 72 #include "amdgpu_irq.h" 73 #include "amdgpu_ucode.h" 74 #include "amdgpu_ttm.h" 75 #include "amdgpu_psp.h" 76 #include "amdgpu_gds.h" 77 #include "amdgpu_sync.h" 78 #include "amdgpu_ring.h" 79 #include "amdgpu_vm.h" 80 #include "amdgpu_dpm.h" 81 #include "amdgpu_acp.h" 82 #include "amdgpu_uvd.h" 83 #include "amdgpu_vce.h" 84 #include "amdgpu_vcn.h" 85 #include "amdgpu_jpeg.h" 86 #include "amdgpu_mn.h" 87 #include "amdgpu_gmc.h" 88 #include "amdgpu_gfx.h" 89 #include "amdgpu_sdma.h" 90 #include "amdgpu_nbio.h" 91 #include "amdgpu_hdp.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_smu.h" 103 #include "amdgpu_discovery.h" 104 #include "amdgpu_mes.h" 105 #include "amdgpu_umc.h" 106 #include "amdgpu_mmhub.h" 107 #include "amdgpu_gfxhub.h" 108 #include "amdgpu_df.h" 109 #include "amdgpu_smuio.h" 110 111 #define MAX_GPU_INSTANCE 16 112 113 struct amdgpu_gpu_instance 114 { 115 struct amdgpu_device *adev; 116 int mgpu_fan_enabled; 117 }; 118 119 struct amdgpu_mgpu_info 120 { 121 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 122 struct mutex mutex; 123 uint32_t num_gpu; 124 uint32_t num_dgpu; 125 uint32_t num_apu; 126 127 /* delayed reset_func for XGMI configuration if necessary */ 128 struct delayed_work delayed_reset_work; 129 bool pending_reset; 130 }; 131 132 struct amdgpu_watchdog_timer 133 { 134 bool timeout_fatal_disable; 135 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 136 }; 137 138 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 139 140 /* 141 * Modules parameters. 142 */ 143 extern int amdgpu_modeset; 144 extern int amdgpu_vram_limit; 145 extern int amdgpu_vis_vram_limit; 146 extern int amdgpu_gart_size; 147 extern int amdgpu_gtt_size; 148 extern int amdgpu_moverate; 149 extern int amdgpu_benchmarking; 150 extern int amdgpu_testing; 151 extern int amdgpu_audio; 152 extern int amdgpu_disp_priority; 153 extern int amdgpu_hw_i2c; 154 extern int amdgpu_pcie_gen2; 155 extern int amdgpu_msi; 156 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 157 extern int amdgpu_dpm; 158 extern int amdgpu_fw_load_type; 159 extern int amdgpu_aspm; 160 extern int amdgpu_runtime_pm; 161 extern uint amdgpu_ip_block_mask; 162 extern int amdgpu_bapm; 163 extern int amdgpu_deep_color; 164 extern int amdgpu_vm_size; 165 extern int amdgpu_vm_block_size; 166 extern int amdgpu_vm_fragment_size; 167 extern int amdgpu_vm_fault_stop; 168 extern int amdgpu_vm_debug; 169 extern int amdgpu_vm_update_mode; 170 extern int amdgpu_exp_hw_support; 171 extern int amdgpu_dc; 172 extern int amdgpu_sched_jobs; 173 extern int amdgpu_sched_hw_submission; 174 extern uint amdgpu_pcie_gen_cap; 175 extern uint amdgpu_pcie_lane_cap; 176 extern uint amdgpu_cg_mask; 177 extern uint amdgpu_pg_mask; 178 extern uint amdgpu_sdma_phase_quantum; 179 extern char *amdgpu_disable_cu; 180 extern char *amdgpu_virtual_display; 181 extern uint amdgpu_pp_feature_mask; 182 extern uint amdgpu_force_long_training; 183 extern int amdgpu_job_hang_limit; 184 extern int amdgpu_lbpw; 185 extern int amdgpu_compute_multipipe; 186 extern int amdgpu_gpu_recovery; 187 extern int amdgpu_emu_mode; 188 extern uint amdgpu_smu_memory_pool_size; 189 extern int amdgpu_smu_pptable_id; 190 extern uint amdgpu_dc_feature_mask; 191 extern uint amdgpu_freesync_vid_mode; 192 extern uint amdgpu_dc_debug_mask; 193 extern uint amdgpu_dm_abm_level; 194 extern int amdgpu_backlight; 195 extern struct amdgpu_mgpu_info mgpu_info; 196 extern int amdgpu_ras_enable; 197 extern uint amdgpu_ras_mask; 198 extern int amdgpu_bad_page_threshold; 199 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 200 extern int amdgpu_async_gfx_ring; 201 extern int amdgpu_mcbp; 202 extern int amdgpu_discovery; 203 extern int amdgpu_mes; 204 extern int amdgpu_noretry; 205 extern int amdgpu_force_asic_type; 206 #ifdef CONFIG_HSA_AMD 207 extern int sched_policy; 208 extern bool debug_evictions; 209 extern bool no_system_mem_limit; 210 #else 211 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 212 static const bool __maybe_unused debug_evictions; /* = false */ 213 static const bool __maybe_unused no_system_mem_limit; 214 #endif 215 216 extern int amdgpu_tmz; 217 extern int amdgpu_reset_method; 218 219 #ifdef CONFIG_DRM_AMDGPU_SI 220 extern int amdgpu_si_support; 221 #endif 222 #ifdef CONFIG_DRM_AMDGPU_CIK 223 extern int amdgpu_cik_support; 224 #endif 225 extern int amdgpu_num_kcq; 226 227 #define AMDGPU_VM_MAX_NUM_CTX 4096 228 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 229 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 230 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 231 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 232 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 233 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 234 #define AMDGPUFB_CONN_LIMIT 4 235 #define AMDGPU_BIOS_NUM_SCRATCH 16 236 237 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 238 239 /* hard reset data */ 240 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 241 242 /* reset flags */ 243 #define AMDGPU_RESET_GFX (1 << 0) 244 #define AMDGPU_RESET_COMPUTE (1 << 1) 245 #define AMDGPU_RESET_DMA (1 << 2) 246 #define AMDGPU_RESET_CP (1 << 3) 247 #define AMDGPU_RESET_GRBM (1 << 4) 248 #define AMDGPU_RESET_DMA1 (1 << 5) 249 #define AMDGPU_RESET_RLC (1 << 6) 250 #define AMDGPU_RESET_SEM (1 << 7) 251 #define AMDGPU_RESET_IH (1 << 8) 252 #define AMDGPU_RESET_VMC (1 << 9) 253 #define AMDGPU_RESET_MC (1 << 10) 254 #define AMDGPU_RESET_DISPLAY (1 << 11) 255 #define AMDGPU_RESET_UVD (1 << 12) 256 #define AMDGPU_RESET_VCE (1 << 13) 257 #define AMDGPU_RESET_VCE1 (1 << 14) 258 259 /* max cursor sizes (in pixels) */ 260 #define CIK_CURSOR_WIDTH 128 261 #define CIK_CURSOR_HEIGHT 128 262 263 struct amdgpu_device; 264 struct amdgpu_ib; 265 struct amdgpu_cs_parser; 266 struct amdgpu_job; 267 struct amdgpu_irq_src; 268 struct amdgpu_fpriv; 269 struct amdgpu_bo_va_mapping; 270 struct amdgpu_atif; 271 struct kfd_vm_fault_info; 272 struct amdgpu_hive_info; 273 struct amdgpu_reset_context; 274 struct amdgpu_reset_control; 275 276 enum amdgpu_cp_irq { 277 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 278 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 279 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 280 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 281 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 282 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 283 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 284 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 285 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 286 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 287 288 AMDGPU_CP_IRQ_LAST 289 }; 290 291 enum amdgpu_thermal_irq { 292 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 293 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 294 295 AMDGPU_THERMAL_IRQ_LAST 296 }; 297 298 enum amdgpu_kiq_irq { 299 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 300 AMDGPU_CP_KIQ_IRQ_LAST 301 }; 302 303 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 304 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 305 #define MAX_KIQ_REG_TRY 1000 306 307 int amdgpu_device_ip_set_clockgating_state(void *dev, 308 enum amd_ip_block_type block_type, 309 enum amd_clockgating_state state); 310 int amdgpu_device_ip_set_powergating_state(void *dev, 311 enum amd_ip_block_type block_type, 312 enum amd_powergating_state state); 313 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 314 u32 *flags); 315 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 316 enum amd_ip_block_type block_type); 317 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 318 enum amd_ip_block_type block_type); 319 320 #define AMDGPU_MAX_IP_NUM 16 321 322 struct amdgpu_ip_block_status { 323 bool valid; 324 bool sw; 325 bool hw; 326 bool late_initialized; 327 bool hang; 328 }; 329 330 struct amdgpu_ip_block_version { 331 const enum amd_ip_block_type type; 332 const u32 major; 333 const u32 minor; 334 const u32 rev; 335 const struct amd_ip_funcs *funcs; 336 }; 337 338 #define HW_REV(_Major, _Minor, _Rev) \ 339 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 340 341 struct amdgpu_ip_block { 342 struct amdgpu_ip_block_status status; 343 const struct amdgpu_ip_block_version *version; 344 }; 345 346 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 347 enum amd_ip_block_type type, 348 u32 major, u32 minor); 349 350 struct amdgpu_ip_block * 351 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 352 enum amd_ip_block_type type); 353 354 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 355 const struct amdgpu_ip_block_version *ip_block_version); 356 357 /* 358 * BIOS. 359 */ 360 bool amdgpu_get_bios(struct amdgpu_device *adev); 361 bool amdgpu_read_bios(struct amdgpu_device *adev); 362 363 /* 364 * Clocks 365 */ 366 367 #define AMDGPU_MAX_PPLL 3 368 369 struct amdgpu_clock { 370 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 371 struct amdgpu_pll spll; 372 struct amdgpu_pll mpll; 373 /* 10 Khz units */ 374 uint32_t default_mclk; 375 uint32_t default_sclk; 376 uint32_t default_dispclk; 377 uint32_t current_dispclk; 378 uint32_t dp_extclk; 379 uint32_t max_pixel_clock; 380 }; 381 382 /* sub-allocation manager, it has to be protected by another lock. 383 * By conception this is an helper for other part of the driver 384 * like the indirect buffer or semaphore, which both have their 385 * locking. 386 * 387 * Principe is simple, we keep a list of sub allocation in offset 388 * order (first entry has offset == 0, last entry has the highest 389 * offset). 390 * 391 * When allocating new object we first check if there is room at 392 * the end total_size - (last_object_offset + last_object_size) >= 393 * alloc_size. If so we allocate new object there. 394 * 395 * When there is not enough room at the end, we start waiting for 396 * each sub object until we reach object_offset+object_size >= 397 * alloc_size, this object then become the sub object we return. 398 * 399 * Alignment can't be bigger than page size. 400 * 401 * Hole are not considered for allocation to keep things simple. 402 * Assumption is that there won't be hole (all object on same 403 * alignment). 404 */ 405 406 #define AMDGPU_SA_NUM_FENCE_LISTS 32 407 408 struct amdgpu_sa_manager { 409 wait_queue_head_t wq; 410 struct amdgpu_bo *bo; 411 struct list_head *hole; 412 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 413 struct list_head olist; 414 unsigned size; 415 uint64_t gpu_addr; 416 void *cpu_ptr; 417 uint32_t domain; 418 uint32_t align; 419 }; 420 421 /* sub-allocation buffer */ 422 struct amdgpu_sa_bo { 423 struct list_head olist; 424 struct list_head flist; 425 struct amdgpu_sa_manager *manager; 426 unsigned soffset; 427 unsigned eoffset; 428 struct dma_fence *fence; 429 }; 430 431 int amdgpu_fence_slab_init(void); 432 void amdgpu_fence_slab_fini(void); 433 434 /* 435 * IRQS. 436 */ 437 438 struct amdgpu_flip_work { 439 struct delayed_work flip_work; 440 struct work_struct unpin_work; 441 struct amdgpu_device *adev; 442 int crtc_id; 443 u32 target_vblank; 444 uint64_t base; 445 struct drm_pending_vblank_event *event; 446 struct amdgpu_bo *old_abo; 447 struct dma_fence *excl; 448 unsigned shared_count; 449 struct dma_fence **shared; 450 struct dma_fence_cb cb; 451 bool async; 452 }; 453 454 455 /* 456 * CP & rings. 457 */ 458 459 struct amdgpu_ib { 460 struct amdgpu_sa_bo *sa_bo; 461 uint32_t length_dw; 462 uint64_t gpu_addr; 463 uint32_t *ptr; 464 uint32_t flags; 465 }; 466 467 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 468 469 /* 470 * file private structure 471 */ 472 473 struct amdgpu_fpriv { 474 struct amdgpu_vm vm; 475 struct amdgpu_bo_va *prt_va; 476 struct amdgpu_bo_va *csa_va; 477 struct mutex bo_list_lock; 478 struct idr bo_list_handles; 479 struct amdgpu_ctx_mgr ctx_mgr; 480 }; 481 482 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 483 484 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 485 unsigned size, 486 enum amdgpu_ib_pool_type pool, 487 struct amdgpu_ib *ib); 488 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 489 struct dma_fence *f); 490 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 491 struct amdgpu_ib *ibs, struct amdgpu_job *job, 492 struct dma_fence **f); 493 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 494 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 495 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 496 497 /* 498 * CS. 499 */ 500 struct amdgpu_cs_chunk { 501 uint32_t chunk_id; 502 uint32_t length_dw; 503 void *kdata; 504 }; 505 506 struct amdgpu_cs_post_dep { 507 struct drm_syncobj *syncobj; 508 struct dma_fence_chain *chain; 509 u64 point; 510 }; 511 512 struct amdgpu_cs_parser { 513 struct amdgpu_device *adev; 514 struct drm_file *filp; 515 struct amdgpu_ctx *ctx; 516 517 /* chunks */ 518 unsigned nchunks; 519 struct amdgpu_cs_chunk *chunks; 520 521 /* scheduler job object */ 522 struct amdgpu_job *job; 523 struct drm_sched_entity *entity; 524 525 /* buffer objects */ 526 struct ww_acquire_ctx ticket; 527 struct amdgpu_bo_list *bo_list; 528 struct amdgpu_mn *mn; 529 struct amdgpu_bo_list_entry vm_pd; 530 struct list_head validated; 531 struct dma_fence *fence; 532 uint64_t bytes_moved_threshold; 533 uint64_t bytes_moved_vis_threshold; 534 uint64_t bytes_moved; 535 uint64_t bytes_moved_vis; 536 537 /* user fence */ 538 struct amdgpu_bo_list_entry uf_entry; 539 540 unsigned num_post_deps; 541 struct amdgpu_cs_post_dep *post_deps; 542 }; 543 544 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 545 uint32_t ib_idx, int idx) 546 { 547 return p->job->ibs[ib_idx].ptr[idx]; 548 } 549 550 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 551 uint32_t ib_idx, int idx, 552 uint32_t value) 553 { 554 p->job->ibs[ib_idx].ptr[idx] = value; 555 } 556 557 /* 558 * Writeback 559 */ 560 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 561 562 struct amdgpu_wb { 563 struct amdgpu_bo *wb_obj; 564 volatile uint32_t *wb; 565 uint64_t gpu_addr; 566 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 567 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 568 }; 569 570 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 571 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 572 573 /* 574 * Benchmarking 575 */ 576 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 577 578 579 /* 580 * Testing 581 */ 582 void amdgpu_test_moves(struct amdgpu_device *adev); 583 584 /* 585 * ASIC specific register table accessible by UMD 586 */ 587 struct amdgpu_allowed_register_entry { 588 uint32_t reg_offset; 589 bool grbm_indexed; 590 }; 591 592 enum amd_reset_method { 593 AMD_RESET_METHOD_NONE = -1, 594 AMD_RESET_METHOD_LEGACY = 0, 595 AMD_RESET_METHOD_MODE0, 596 AMD_RESET_METHOD_MODE1, 597 AMD_RESET_METHOD_MODE2, 598 AMD_RESET_METHOD_BACO, 599 AMD_RESET_METHOD_PCI, 600 }; 601 602 struct amdgpu_video_codec_info { 603 u32 codec_type; 604 u32 max_width; 605 u32 max_height; 606 u32 max_pixels_per_frame; 607 u32 max_level; 608 }; 609 610 struct amdgpu_video_codecs { 611 const u32 codec_count; 612 const struct amdgpu_video_codec_info *codec_array; 613 }; 614 615 /* 616 * ASIC specific functions. 617 */ 618 struct amdgpu_asic_funcs { 619 bool (*read_disabled_bios)(struct amdgpu_device *adev); 620 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 621 u8 *bios, u32 length_bytes); 622 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 623 u32 sh_num, u32 reg_offset, u32 *value); 624 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 625 int (*reset)(struct amdgpu_device *adev); 626 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 627 /* get the reference clock */ 628 u32 (*get_xclk)(struct amdgpu_device *adev); 629 /* MM block clocks */ 630 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 631 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 632 /* static power management */ 633 int (*get_pcie_lanes)(struct amdgpu_device *adev); 634 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 635 /* get config memsize register */ 636 u32 (*get_config_memsize)(struct amdgpu_device *adev); 637 /* flush hdp write queue */ 638 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 639 /* invalidate hdp read cache */ 640 void (*invalidate_hdp)(struct amdgpu_device *adev, 641 struct amdgpu_ring *ring); 642 /* check if the asic needs a full reset of if soft reset will work */ 643 bool (*need_full_reset)(struct amdgpu_device *adev); 644 /* initialize doorbell layout for specific asic*/ 645 void (*init_doorbell_index)(struct amdgpu_device *adev); 646 /* PCIe bandwidth usage */ 647 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 648 uint64_t *count1); 649 /* do we need to reset the asic at init time (e.g., kexec) */ 650 bool (*need_reset_on_init)(struct amdgpu_device *adev); 651 /* PCIe replay counter */ 652 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 653 /* device supports BACO */ 654 bool (*supports_baco)(struct amdgpu_device *adev); 655 /* pre asic_init quirks */ 656 void (*pre_asic_init)(struct amdgpu_device *adev); 657 /* enter/exit umd stable pstate */ 658 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 659 /* query video codecs */ 660 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 661 const struct amdgpu_video_codecs **codecs); 662 }; 663 664 /* 665 * IOCTL. 666 */ 667 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 668 struct drm_file *filp); 669 670 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 671 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 672 struct drm_file *filp); 673 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 674 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 675 struct drm_file *filp); 676 677 /* VRAM scratch page for HDP bug, default vram page */ 678 struct amdgpu_vram_scratch { 679 struct amdgpu_bo *robj; 680 volatile uint32_t *ptr; 681 u64 gpu_addr; 682 }; 683 684 /* 685 * ACPI 686 */ 687 struct amdgpu_atcs_functions { 688 bool get_ext_state; 689 bool pcie_perf_req; 690 bool pcie_dev_rdy; 691 bool pcie_bus_width; 692 }; 693 694 struct amdgpu_atcs { 695 struct amdgpu_atcs_functions functions; 696 }; 697 698 /* 699 * CGS 700 */ 701 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 702 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 703 704 /* 705 * Core structure, functions and helpers. 706 */ 707 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 708 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 709 710 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 711 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 712 713 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 714 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 715 716 struct amdgpu_mmio_remap { 717 u32 reg_offset; 718 resource_size_t bus_addr; 719 }; 720 721 /* Define the HW IP blocks will be used in driver , add more if necessary */ 722 enum amd_hw_ip_block_type { 723 GC_HWIP = 1, 724 HDP_HWIP, 725 SDMA0_HWIP, 726 SDMA1_HWIP, 727 SDMA2_HWIP, 728 SDMA3_HWIP, 729 SDMA4_HWIP, 730 SDMA5_HWIP, 731 SDMA6_HWIP, 732 SDMA7_HWIP, 733 MMHUB_HWIP, 734 ATHUB_HWIP, 735 NBIO_HWIP, 736 MP0_HWIP, 737 MP1_HWIP, 738 UVD_HWIP, 739 VCN_HWIP = UVD_HWIP, 740 JPEG_HWIP = VCN_HWIP, 741 VCE_HWIP, 742 DF_HWIP, 743 DCE_HWIP, 744 OSSSYS_HWIP, 745 SMUIO_HWIP, 746 PWR_HWIP, 747 NBIF_HWIP, 748 THM_HWIP, 749 CLK_HWIP, 750 UMC_HWIP, 751 RSMU_HWIP, 752 MAX_HWIP 753 }; 754 755 #define HWIP_MAX_INSTANCE 8 756 757 struct amd_powerplay { 758 void *pp_handle; 759 const struct amd_pm_funcs *pp_funcs; 760 }; 761 762 /* polaris10 kickers */ 763 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 764 ((rid == 0xE3) || \ 765 (rid == 0xE4) || \ 766 (rid == 0xE5) || \ 767 (rid == 0xE7) || \ 768 (rid == 0xEF))) || \ 769 ((did == 0x6FDF) && \ 770 ((rid == 0xE7) || \ 771 (rid == 0xEF) || \ 772 (rid == 0xFF)))) 773 774 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 775 ((rid == 0xE1) || \ 776 (rid == 0xF7))) 777 778 /* polaris11 kickers */ 779 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 780 ((rid == 0xE0) || \ 781 (rid == 0xE5))) || \ 782 ((did == 0x67FF) && \ 783 ((rid == 0xCF) || \ 784 (rid == 0xEF) || \ 785 (rid == 0xFF)))) 786 787 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 788 ((rid == 0xE2))) 789 790 /* polaris12 kickers */ 791 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 792 ((rid == 0xC0) || \ 793 (rid == 0xC1) || \ 794 (rid == 0xC3) || \ 795 (rid == 0xC7))) || \ 796 ((did == 0x6981) && \ 797 ((rid == 0x00) || \ 798 (rid == 0x01) || \ 799 (rid == 0x10)))) 800 801 #define AMDGPU_RESET_MAGIC_NUM 64 802 #define AMDGPU_MAX_DF_PERFMONS 4 803 struct amdgpu_device { 804 struct device *dev; 805 struct pci_dev *pdev; 806 struct drm_device ddev; 807 808 #ifdef CONFIG_DRM_AMD_ACP 809 struct amdgpu_acp acp; 810 #endif 811 struct amdgpu_hive_info *hive; 812 /* ASIC */ 813 enum amd_asic_type asic_type; 814 uint32_t family; 815 uint32_t rev_id; 816 uint32_t external_rev_id; 817 unsigned long flags; 818 unsigned long apu_flags; 819 int usec_timeout; 820 const struct amdgpu_asic_funcs *asic_funcs; 821 bool shutdown; 822 bool need_swiotlb; 823 bool accel_working; 824 struct notifier_block acpi_nb; 825 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 826 struct debugfs_blob_wrapper debugfs_vbios_blob; 827 struct amdgpu_atif *atif; 828 struct amdgpu_atcs atcs; 829 struct mutex srbm_mutex; 830 /* GRBM index mutex. Protects concurrent access to GRBM index */ 831 struct mutex grbm_idx_mutex; 832 struct dev_pm_domain vga_pm_domain; 833 bool have_disp_power_ref; 834 bool have_atomics_support; 835 836 /* BIOS */ 837 bool is_atom_fw; 838 uint8_t *bios; 839 uint32_t bios_size; 840 uint32_t bios_scratch_reg_offset; 841 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 842 843 /* Register/doorbell mmio */ 844 resource_size_t rmmio_base; 845 resource_size_t rmmio_size; 846 void __iomem *rmmio; 847 /* protects concurrent MM_INDEX/DATA based register access */ 848 spinlock_t mmio_idx_lock; 849 struct amdgpu_mmio_remap rmmio_remap; 850 /* protects concurrent SMC based register access */ 851 spinlock_t smc_idx_lock; 852 amdgpu_rreg_t smc_rreg; 853 amdgpu_wreg_t smc_wreg; 854 /* protects concurrent PCIE register access */ 855 spinlock_t pcie_idx_lock; 856 amdgpu_rreg_t pcie_rreg; 857 amdgpu_wreg_t pcie_wreg; 858 amdgpu_rreg_t pciep_rreg; 859 amdgpu_wreg_t pciep_wreg; 860 amdgpu_rreg64_t pcie_rreg64; 861 amdgpu_wreg64_t pcie_wreg64; 862 /* protects concurrent UVD register access */ 863 spinlock_t uvd_ctx_idx_lock; 864 amdgpu_rreg_t uvd_ctx_rreg; 865 amdgpu_wreg_t uvd_ctx_wreg; 866 /* protects concurrent DIDT register access */ 867 spinlock_t didt_idx_lock; 868 amdgpu_rreg_t didt_rreg; 869 amdgpu_wreg_t didt_wreg; 870 /* protects concurrent gc_cac register access */ 871 spinlock_t gc_cac_idx_lock; 872 amdgpu_rreg_t gc_cac_rreg; 873 amdgpu_wreg_t gc_cac_wreg; 874 /* protects concurrent se_cac register access */ 875 spinlock_t se_cac_idx_lock; 876 amdgpu_rreg_t se_cac_rreg; 877 amdgpu_wreg_t se_cac_wreg; 878 /* protects concurrent ENDPOINT (audio) register access */ 879 spinlock_t audio_endpt_idx_lock; 880 amdgpu_block_rreg_t audio_endpt_rreg; 881 amdgpu_block_wreg_t audio_endpt_wreg; 882 struct amdgpu_doorbell doorbell; 883 884 /* clock/pll info */ 885 struct amdgpu_clock clock; 886 887 /* MC */ 888 struct amdgpu_gmc gmc; 889 struct amdgpu_gart gart; 890 dma_addr_t dummy_page_addr; 891 struct amdgpu_vm_manager vm_manager; 892 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 893 unsigned num_vmhubs; 894 895 /* memory management */ 896 struct amdgpu_mman mman; 897 struct amdgpu_vram_scratch vram_scratch; 898 struct amdgpu_wb wb; 899 atomic64_t num_bytes_moved; 900 atomic64_t num_evictions; 901 atomic64_t num_vram_cpu_page_faults; 902 atomic_t gpu_reset_counter; 903 atomic_t vram_lost_counter; 904 905 /* data for buffer migration throttling */ 906 struct { 907 spinlock_t lock; 908 s64 last_update_us; 909 s64 accum_us; /* accumulated microseconds */ 910 s64 accum_us_vis; /* for visible VRAM */ 911 u32 log2_max_MBps; 912 } mm_stats; 913 914 /* display */ 915 bool enable_virtual_display; 916 struct amdgpu_mode_info mode_info; 917 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 918 struct work_struct hotplug_work; 919 struct amdgpu_irq_src crtc_irq; 920 struct amdgpu_irq_src vline0_irq; 921 struct amdgpu_irq_src vupdate_irq; 922 struct amdgpu_irq_src pageflip_irq; 923 struct amdgpu_irq_src hpd_irq; 924 struct amdgpu_irq_src dmub_trace_irq; 925 struct amdgpu_irq_src dmub_outbox_irq; 926 927 /* rings */ 928 u64 fence_context; 929 unsigned num_rings; 930 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 931 bool ib_pool_ready; 932 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 933 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 934 935 /* interrupts */ 936 struct amdgpu_irq irq; 937 938 /* powerplay */ 939 struct amd_powerplay powerplay; 940 bool pp_force_state_enabled; 941 942 /* smu */ 943 struct smu_context smu; 944 945 /* dpm */ 946 struct amdgpu_pm pm; 947 u32 cg_flags; 948 u32 pg_flags; 949 950 /* nbio */ 951 struct amdgpu_nbio nbio; 952 953 /* hdp */ 954 struct amdgpu_hdp hdp; 955 956 /* smuio */ 957 struct amdgpu_smuio smuio; 958 959 /* mmhub */ 960 struct amdgpu_mmhub mmhub; 961 962 /* gfxhub */ 963 struct amdgpu_gfxhub gfxhub; 964 965 /* gfx */ 966 struct amdgpu_gfx gfx; 967 968 /* sdma */ 969 struct amdgpu_sdma sdma; 970 971 /* uvd */ 972 struct amdgpu_uvd uvd; 973 974 /* vce */ 975 struct amdgpu_vce vce; 976 977 /* vcn */ 978 struct amdgpu_vcn vcn; 979 980 /* jpeg */ 981 struct amdgpu_jpeg jpeg; 982 983 /* firmwares */ 984 struct amdgpu_firmware firmware; 985 986 /* PSP */ 987 struct psp_context psp; 988 989 /* GDS */ 990 struct amdgpu_gds gds; 991 992 /* KFD */ 993 struct amdgpu_kfd_dev kfd; 994 995 /* UMC */ 996 struct amdgpu_umc umc; 997 998 /* display related functionality */ 999 struct amdgpu_display_manager dm; 1000 1001 /* mes */ 1002 bool enable_mes; 1003 struct amdgpu_mes mes; 1004 1005 /* df */ 1006 struct amdgpu_df df; 1007 1008 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1009 int num_ip_blocks; 1010 struct mutex mn_lock; 1011 DECLARE_HASHTABLE(mn_hash, 7); 1012 1013 /* tracking pinned memory */ 1014 atomic64_t vram_pin_size; 1015 atomic64_t visible_pin_size; 1016 atomic64_t gart_pin_size; 1017 1018 /* soc15 register offset based on ip, instance and segment */ 1019 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1020 1021 /* delayed work_func for deferring clockgating during resume */ 1022 struct delayed_work delayed_init_work; 1023 1024 struct amdgpu_virt virt; 1025 1026 /* link all shadow bo */ 1027 struct list_head shadow_list; 1028 struct mutex shadow_list_lock; 1029 1030 /* record hw reset is performed */ 1031 bool has_hw_reset; 1032 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1033 1034 /* s3/s4 mask */ 1035 bool in_suspend; 1036 bool in_s3; 1037 bool in_s4; 1038 bool in_s0ix; 1039 1040 atomic_t in_gpu_reset; 1041 enum pp_mp1_state mp1_state; 1042 struct rw_semaphore reset_sem; 1043 struct amdgpu_doorbell_index doorbell_index; 1044 1045 struct mutex notifier_lock; 1046 1047 int asic_reset_res; 1048 struct work_struct xgmi_reset_work; 1049 struct list_head reset_list; 1050 1051 long gfx_timeout; 1052 long sdma_timeout; 1053 long video_timeout; 1054 long compute_timeout; 1055 1056 uint64_t unique_id; 1057 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1058 1059 /* enable runtime pm on the device */ 1060 bool runpm; 1061 bool in_runpm; 1062 bool has_pr3; 1063 1064 bool pm_sysfs_en; 1065 bool ucode_sysfs_en; 1066 1067 /* Chip product information */ 1068 char product_number[16]; 1069 char product_name[32]; 1070 char serial[20]; 1071 1072 struct amdgpu_autodump autodump; 1073 1074 atomic_t throttling_logging_enabled; 1075 struct ratelimit_state throttling_logging_rs; 1076 uint32_t ras_features; 1077 1078 bool in_pci_err_recovery; 1079 struct pci_saved_state *pci_state; 1080 1081 struct amdgpu_reset_control *reset_cntl; 1082 }; 1083 1084 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1085 { 1086 return container_of(ddev, struct amdgpu_device, ddev); 1087 } 1088 1089 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1090 { 1091 return &adev->ddev; 1092 } 1093 1094 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1095 { 1096 return container_of(bdev, struct amdgpu_device, mman.bdev); 1097 } 1098 1099 int amdgpu_device_init(struct amdgpu_device *adev, 1100 uint32_t flags); 1101 void amdgpu_device_fini(struct amdgpu_device *adev); 1102 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1103 1104 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1105 uint32_t *buf, size_t size, bool write); 1106 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1107 uint32_t reg, uint32_t acc_flags); 1108 void amdgpu_device_wreg(struct amdgpu_device *adev, 1109 uint32_t reg, uint32_t v, 1110 uint32_t acc_flags); 1111 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1112 uint32_t reg, uint32_t v); 1113 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1114 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1115 1116 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1117 u32 pcie_index, u32 pcie_data, 1118 u32 reg_addr); 1119 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1120 u32 pcie_index, u32 pcie_data, 1121 u32 reg_addr); 1122 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1123 u32 pcie_index, u32 pcie_data, 1124 u32 reg_addr, u32 reg_data); 1125 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1126 u32 pcie_index, u32 pcie_data, 1127 u32 reg_addr, u64 reg_data); 1128 1129 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1130 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1131 1132 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1133 struct amdgpu_reset_context *reset_context); 1134 1135 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1136 struct amdgpu_reset_context *reset_context); 1137 1138 int emu_soc_asic_init(struct amdgpu_device *adev); 1139 1140 /* 1141 * Registers read & write functions. 1142 */ 1143 #define AMDGPU_REGS_NO_KIQ (1<<1) 1144 1145 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1146 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1147 1148 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1149 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1150 1151 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1152 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1153 1154 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1155 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1156 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1157 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1158 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1159 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1160 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1161 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1162 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1163 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1164 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1165 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1166 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1167 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1168 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1169 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1170 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1171 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1172 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1173 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1174 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1175 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1176 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1177 #define WREG32_P(reg, val, mask) \ 1178 do { \ 1179 uint32_t tmp_ = RREG32(reg); \ 1180 tmp_ &= (mask); \ 1181 tmp_ |= ((val) & ~(mask)); \ 1182 WREG32(reg, tmp_); \ 1183 } while (0) 1184 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1185 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1186 #define WREG32_PLL_P(reg, val, mask) \ 1187 do { \ 1188 uint32_t tmp_ = RREG32_PLL(reg); \ 1189 tmp_ &= (mask); \ 1190 tmp_ |= ((val) & ~(mask)); \ 1191 WREG32_PLL(reg, tmp_); \ 1192 } while (0) 1193 1194 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1195 do { \ 1196 u32 tmp = RREG32_SMC(_Reg); \ 1197 tmp &= (_Mask); \ 1198 tmp |= ((_Val) & ~(_Mask)); \ 1199 WREG32_SMC(_Reg, tmp); \ 1200 } while (0) 1201 1202 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1203 1204 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1205 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1206 1207 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1208 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1209 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1210 1211 #define REG_GET_FIELD(value, reg, field) \ 1212 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1213 1214 #define WREG32_FIELD(reg, field, val) \ 1215 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1216 1217 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1218 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1219 1220 /* 1221 * BIOS helpers. 1222 */ 1223 #define RBIOS8(i) (adev->bios[i]) 1224 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1225 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1226 1227 /* 1228 * ASICs macro. 1229 */ 1230 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1231 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1232 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1233 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1234 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1235 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1236 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1237 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1238 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1239 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1240 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1241 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1242 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1243 #define amdgpu_asic_flush_hdp(adev, r) \ 1244 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1245 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1246 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r))) 1247 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1248 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1249 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1250 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1251 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1252 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1253 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1254 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1255 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1256 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1257 1258 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1259 1260 /* Common functions */ 1261 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1262 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1263 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1264 struct amdgpu_job* job); 1265 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1266 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1267 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1268 1269 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1270 u64 num_vis_bytes); 1271 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1272 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1273 const u32 *registers, 1274 const u32 array_size); 1275 1276 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1277 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1278 bool amdgpu_device_supports_px(struct drm_device *dev); 1279 bool amdgpu_device_supports_boco(struct drm_device *dev); 1280 bool amdgpu_device_supports_baco(struct drm_device *dev); 1281 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1282 struct amdgpu_device *peer_adev); 1283 int amdgpu_device_baco_enter(struct drm_device *dev); 1284 int amdgpu_device_baco_exit(struct drm_device *dev); 1285 1286 /* atpx handler */ 1287 #if defined(CONFIG_VGA_SWITCHEROO) 1288 void amdgpu_register_atpx_handler(void); 1289 void amdgpu_unregister_atpx_handler(void); 1290 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1291 bool amdgpu_is_atpx_hybrid(void); 1292 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1293 bool amdgpu_has_atpx(void); 1294 #else 1295 static inline void amdgpu_register_atpx_handler(void) {} 1296 static inline void amdgpu_unregister_atpx_handler(void) {} 1297 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1298 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1299 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1300 static inline bool amdgpu_has_atpx(void) { return false; } 1301 #endif 1302 1303 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1304 void *amdgpu_atpx_get_dhandle(void); 1305 #else 1306 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1307 #endif 1308 1309 /* 1310 * KMS 1311 */ 1312 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1313 extern const int amdgpu_max_kms_ioctl; 1314 1315 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1316 void amdgpu_driver_unload_kms(struct drm_device *dev); 1317 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1318 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1319 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1320 struct drm_file *file_priv); 1321 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1322 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1323 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1324 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1325 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1326 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1327 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1328 unsigned long arg); 1329 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1330 struct drm_file *filp); 1331 1332 /* 1333 * functions used by amdgpu_encoder.c 1334 */ 1335 struct amdgpu_afmt_acr { 1336 u32 clock; 1337 1338 int n_32khz; 1339 int cts_32khz; 1340 1341 int n_44_1khz; 1342 int cts_44_1khz; 1343 1344 int n_48khz; 1345 int cts_48khz; 1346 1347 }; 1348 1349 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1350 1351 /* amdgpu_acpi.c */ 1352 #if defined(CONFIG_ACPI) 1353 int amdgpu_acpi_init(struct amdgpu_device *adev); 1354 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1355 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1356 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1357 u8 perf_req, bool advertise); 1358 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1359 1360 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1361 struct amdgpu_dm_backlight_caps *caps); 1362 bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev); 1363 #else 1364 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1365 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1366 static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; } 1367 #endif 1368 1369 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1370 uint64_t addr, struct amdgpu_bo **bo, 1371 struct amdgpu_bo_va_mapping **mapping); 1372 1373 #if defined(CONFIG_DRM_AMD_DC) 1374 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1375 #else 1376 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1377 #endif 1378 1379 1380 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1381 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1382 1383 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1384 pci_channel_state_t state); 1385 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1386 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1387 void amdgpu_pci_resume(struct pci_dev *pdev); 1388 1389 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1390 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1391 1392 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1393 1394 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1395 enum amd_clockgating_state state); 1396 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1397 enum amd_powergating_state state); 1398 1399 #include "amdgpu_object.h" 1400 1401 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1402 { 1403 return adev->gmc.tmz_enabled; 1404 } 1405 1406 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1407 { 1408 return atomic_read(&adev->in_gpu_reset); 1409 } 1410 #endif 1411