1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_execbuf_util.h> 59 60 #include <drm/amdgpu_drm.h> 61 #include <drm/drm_gem.h> 62 #include <drm/drm_ioctl.h> 63 #include <drm/gpu_scheduler.h> 64 65 #include <kgd_kfd_interface.h> 66 #include "dm_pp_interface.h" 67 #include "kgd_pp_interface.h" 68 69 #include "amd_shared.h" 70 #include "amdgpu_mode.h" 71 #include "amdgpu_ih.h" 72 #include "amdgpu_irq.h" 73 #include "amdgpu_ucode.h" 74 #include "amdgpu_ttm.h" 75 #include "amdgpu_psp.h" 76 #include "amdgpu_gds.h" 77 #include "amdgpu_sync.h" 78 #include "amdgpu_ring.h" 79 #include "amdgpu_vm.h" 80 #include "amdgpu_dpm.h" 81 #include "amdgpu_acp.h" 82 #include "amdgpu_uvd.h" 83 #include "amdgpu_vce.h" 84 #include "amdgpu_vcn.h" 85 #include "amdgpu_jpeg.h" 86 #include "amdgpu_mn.h" 87 #include "amdgpu_gmc.h" 88 #include "amdgpu_gfx.h" 89 #include "amdgpu_sdma.h" 90 #include "amdgpu_nbio.h" 91 #include "amdgpu_hdp.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_discovery.h" 103 #include "amdgpu_mes.h" 104 #include "amdgpu_umc.h" 105 #include "amdgpu_mmhub.h" 106 #include "amdgpu_gfxhub.h" 107 #include "amdgpu_df.h" 108 #include "amdgpu_smuio.h" 109 #include "amdgpu_fdinfo.h" 110 #include "amdgpu_mca.h" 111 #include "amdgpu_ras.h" 112 113 #define MAX_GPU_INSTANCE 16 114 115 struct amdgpu_gpu_instance 116 { 117 struct amdgpu_device *adev; 118 int mgpu_fan_enabled; 119 }; 120 121 struct amdgpu_mgpu_info 122 { 123 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 124 struct mutex mutex; 125 uint32_t num_gpu; 126 uint32_t num_dgpu; 127 uint32_t num_apu; 128 129 /* delayed reset_func for XGMI configuration if necessary */ 130 struct delayed_work delayed_reset_work; 131 bool pending_reset; 132 }; 133 134 enum amdgpu_ss { 135 AMDGPU_SS_DRV_LOAD, 136 AMDGPU_SS_DEV_D0, 137 AMDGPU_SS_DEV_D3, 138 AMDGPU_SS_DRV_UNLOAD 139 }; 140 141 struct amdgpu_watchdog_timer 142 { 143 bool timeout_fatal_disable; 144 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 145 }; 146 147 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 148 149 /* 150 * Modules parameters. 151 */ 152 extern int amdgpu_modeset; 153 extern int amdgpu_vram_limit; 154 extern int amdgpu_vis_vram_limit; 155 extern int amdgpu_gart_size; 156 extern int amdgpu_gtt_size; 157 extern int amdgpu_moverate; 158 extern int amdgpu_audio; 159 extern int amdgpu_disp_priority; 160 extern int amdgpu_hw_i2c; 161 extern int amdgpu_pcie_gen2; 162 extern int amdgpu_msi; 163 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 164 extern int amdgpu_dpm; 165 extern int amdgpu_fw_load_type; 166 extern int amdgpu_aspm; 167 extern int amdgpu_runtime_pm; 168 extern uint amdgpu_ip_block_mask; 169 extern int amdgpu_bapm; 170 extern int amdgpu_deep_color; 171 extern int amdgpu_vm_size; 172 extern int amdgpu_vm_block_size; 173 extern int amdgpu_vm_fragment_size; 174 extern int amdgpu_vm_fault_stop; 175 extern int amdgpu_vm_debug; 176 extern int amdgpu_vm_update_mode; 177 extern int amdgpu_exp_hw_support; 178 extern int amdgpu_dc; 179 extern int amdgpu_sched_jobs; 180 extern int amdgpu_sched_hw_submission; 181 extern uint amdgpu_pcie_gen_cap; 182 extern uint amdgpu_pcie_lane_cap; 183 extern uint amdgpu_cg_mask; 184 extern uint amdgpu_pg_mask; 185 extern uint amdgpu_sdma_phase_quantum; 186 extern char *amdgpu_disable_cu; 187 extern char *amdgpu_virtual_display; 188 extern uint amdgpu_pp_feature_mask; 189 extern uint amdgpu_force_long_training; 190 extern int amdgpu_job_hang_limit; 191 extern int amdgpu_lbpw; 192 extern int amdgpu_compute_multipipe; 193 extern int amdgpu_gpu_recovery; 194 extern int amdgpu_emu_mode; 195 extern uint amdgpu_smu_memory_pool_size; 196 extern int amdgpu_smu_pptable_id; 197 extern uint amdgpu_dc_feature_mask; 198 extern uint amdgpu_dc_debug_mask; 199 extern uint amdgpu_dm_abm_level; 200 extern int amdgpu_backlight; 201 extern struct amdgpu_mgpu_info mgpu_info; 202 extern int amdgpu_ras_enable; 203 extern uint amdgpu_ras_mask; 204 extern int amdgpu_bad_page_threshold; 205 extern bool amdgpu_ignore_bad_page_threshold; 206 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 207 extern int amdgpu_async_gfx_ring; 208 extern int amdgpu_mcbp; 209 extern int amdgpu_discovery; 210 extern int amdgpu_mes; 211 extern int amdgpu_noretry; 212 extern int amdgpu_force_asic_type; 213 extern int amdgpu_smartshift_bias; 214 extern int amdgpu_use_xgmi_p2p; 215 #ifdef CONFIG_HSA_AMD 216 extern int sched_policy; 217 extern bool debug_evictions; 218 extern bool no_system_mem_limit; 219 #else 220 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 221 static const bool __maybe_unused debug_evictions; /* = false */ 222 static const bool __maybe_unused no_system_mem_limit; 223 #endif 224 225 extern int amdgpu_tmz; 226 extern int amdgpu_reset_method; 227 228 #ifdef CONFIG_DRM_AMDGPU_SI 229 extern int amdgpu_si_support; 230 #endif 231 #ifdef CONFIG_DRM_AMDGPU_CIK 232 extern int amdgpu_cik_support; 233 #endif 234 extern int amdgpu_num_kcq; 235 236 #define AMDGPU_VM_MAX_NUM_CTX 4096 237 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 238 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 239 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 240 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 241 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 242 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 243 #define AMDGPUFB_CONN_LIMIT 4 244 #define AMDGPU_BIOS_NUM_SCRATCH 16 245 246 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 247 248 /* hard reset data */ 249 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 250 251 /* reset flags */ 252 #define AMDGPU_RESET_GFX (1 << 0) 253 #define AMDGPU_RESET_COMPUTE (1 << 1) 254 #define AMDGPU_RESET_DMA (1 << 2) 255 #define AMDGPU_RESET_CP (1 << 3) 256 #define AMDGPU_RESET_GRBM (1 << 4) 257 #define AMDGPU_RESET_DMA1 (1 << 5) 258 #define AMDGPU_RESET_RLC (1 << 6) 259 #define AMDGPU_RESET_SEM (1 << 7) 260 #define AMDGPU_RESET_IH (1 << 8) 261 #define AMDGPU_RESET_VMC (1 << 9) 262 #define AMDGPU_RESET_MC (1 << 10) 263 #define AMDGPU_RESET_DISPLAY (1 << 11) 264 #define AMDGPU_RESET_UVD (1 << 12) 265 #define AMDGPU_RESET_VCE (1 << 13) 266 #define AMDGPU_RESET_VCE1 (1 << 14) 267 268 /* max cursor sizes (in pixels) */ 269 #define CIK_CURSOR_WIDTH 128 270 #define CIK_CURSOR_HEIGHT 128 271 272 /* smasrt shift bias level limits */ 273 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 274 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 275 276 struct amdgpu_device; 277 struct amdgpu_ib; 278 struct amdgpu_cs_parser; 279 struct amdgpu_job; 280 struct amdgpu_irq_src; 281 struct amdgpu_fpriv; 282 struct amdgpu_bo_va_mapping; 283 struct kfd_vm_fault_info; 284 struct amdgpu_hive_info; 285 struct amdgpu_reset_context; 286 struct amdgpu_reset_control; 287 288 enum amdgpu_cp_irq { 289 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 290 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 291 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 292 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 293 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 294 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 295 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 296 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 297 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 298 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 299 300 AMDGPU_CP_IRQ_LAST 301 }; 302 303 enum amdgpu_thermal_irq { 304 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 305 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 306 307 AMDGPU_THERMAL_IRQ_LAST 308 }; 309 310 enum amdgpu_kiq_irq { 311 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 312 AMDGPU_CP_KIQ_IRQ_LAST 313 }; 314 315 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 316 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 317 #define MAX_KIQ_REG_TRY 1000 318 319 int amdgpu_device_ip_set_clockgating_state(void *dev, 320 enum amd_ip_block_type block_type, 321 enum amd_clockgating_state state); 322 int amdgpu_device_ip_set_powergating_state(void *dev, 323 enum amd_ip_block_type block_type, 324 enum amd_powergating_state state); 325 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 326 u32 *flags); 327 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 328 enum amd_ip_block_type block_type); 329 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 330 enum amd_ip_block_type block_type); 331 332 #define AMDGPU_MAX_IP_NUM 16 333 334 struct amdgpu_ip_block_status { 335 bool valid; 336 bool sw; 337 bool hw; 338 bool late_initialized; 339 bool hang; 340 }; 341 342 struct amdgpu_ip_block_version { 343 const enum amd_ip_block_type type; 344 const u32 major; 345 const u32 minor; 346 const u32 rev; 347 const struct amd_ip_funcs *funcs; 348 }; 349 350 #define HW_REV(_Major, _Minor, _Rev) \ 351 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 352 353 struct amdgpu_ip_block { 354 struct amdgpu_ip_block_status status; 355 const struct amdgpu_ip_block_version *version; 356 }; 357 358 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 359 enum amd_ip_block_type type, 360 u32 major, u32 minor); 361 362 struct amdgpu_ip_block * 363 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 364 enum amd_ip_block_type type); 365 366 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 367 const struct amdgpu_ip_block_version *ip_block_version); 368 369 /* 370 * BIOS. 371 */ 372 bool amdgpu_get_bios(struct amdgpu_device *adev); 373 bool amdgpu_read_bios(struct amdgpu_device *adev); 374 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 375 u8 *bios, u32 length_bytes); 376 /* 377 * Clocks 378 */ 379 380 #define AMDGPU_MAX_PPLL 3 381 382 struct amdgpu_clock { 383 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 384 struct amdgpu_pll spll; 385 struct amdgpu_pll mpll; 386 /* 10 Khz units */ 387 uint32_t default_mclk; 388 uint32_t default_sclk; 389 uint32_t default_dispclk; 390 uint32_t current_dispclk; 391 uint32_t dp_extclk; 392 uint32_t max_pixel_clock; 393 }; 394 395 /* sub-allocation manager, it has to be protected by another lock. 396 * By conception this is an helper for other part of the driver 397 * like the indirect buffer or semaphore, which both have their 398 * locking. 399 * 400 * Principe is simple, we keep a list of sub allocation in offset 401 * order (first entry has offset == 0, last entry has the highest 402 * offset). 403 * 404 * When allocating new object we first check if there is room at 405 * the end total_size - (last_object_offset + last_object_size) >= 406 * alloc_size. If so we allocate new object there. 407 * 408 * When there is not enough room at the end, we start waiting for 409 * each sub object until we reach object_offset+object_size >= 410 * alloc_size, this object then become the sub object we return. 411 * 412 * Alignment can't be bigger than page size. 413 * 414 * Hole are not considered for allocation to keep things simple. 415 * Assumption is that there won't be hole (all object on same 416 * alignment). 417 */ 418 419 #define AMDGPU_SA_NUM_FENCE_LISTS 32 420 421 struct amdgpu_sa_manager { 422 wait_queue_head_t wq; 423 struct amdgpu_bo *bo; 424 struct list_head *hole; 425 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 426 struct list_head olist; 427 unsigned size; 428 uint64_t gpu_addr; 429 void *cpu_ptr; 430 uint32_t domain; 431 uint32_t align; 432 }; 433 434 /* sub-allocation buffer */ 435 struct amdgpu_sa_bo { 436 struct list_head olist; 437 struct list_head flist; 438 struct amdgpu_sa_manager *manager; 439 unsigned soffset; 440 unsigned eoffset; 441 struct dma_fence *fence; 442 }; 443 444 int amdgpu_fence_slab_init(void); 445 void amdgpu_fence_slab_fini(void); 446 447 /* 448 * IRQS. 449 */ 450 451 struct amdgpu_flip_work { 452 struct delayed_work flip_work; 453 struct work_struct unpin_work; 454 struct amdgpu_device *adev; 455 int crtc_id; 456 u32 target_vblank; 457 uint64_t base; 458 struct drm_pending_vblank_event *event; 459 struct amdgpu_bo *old_abo; 460 unsigned shared_count; 461 struct dma_fence **shared; 462 struct dma_fence_cb cb; 463 bool async; 464 }; 465 466 467 /* 468 * CP & rings. 469 */ 470 471 struct amdgpu_ib { 472 struct amdgpu_sa_bo *sa_bo; 473 uint32_t length_dw; 474 uint64_t gpu_addr; 475 uint32_t *ptr; 476 uint32_t flags; 477 }; 478 479 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 480 481 /* 482 * file private structure 483 */ 484 485 struct amdgpu_fpriv { 486 struct amdgpu_vm vm; 487 struct amdgpu_bo_va *prt_va; 488 struct amdgpu_bo_va *csa_va; 489 struct mutex bo_list_lock; 490 struct idr bo_list_handles; 491 struct amdgpu_ctx_mgr ctx_mgr; 492 }; 493 494 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 495 496 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 497 unsigned size, 498 enum amdgpu_ib_pool_type pool, 499 struct amdgpu_ib *ib); 500 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 501 struct dma_fence *f); 502 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 503 struct amdgpu_ib *ibs, struct amdgpu_job *job, 504 struct dma_fence **f); 505 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 506 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 507 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 508 509 /* 510 * CS. 511 */ 512 struct amdgpu_cs_chunk { 513 uint32_t chunk_id; 514 uint32_t length_dw; 515 void *kdata; 516 }; 517 518 struct amdgpu_cs_post_dep { 519 struct drm_syncobj *syncobj; 520 struct dma_fence_chain *chain; 521 u64 point; 522 }; 523 524 struct amdgpu_cs_parser { 525 struct amdgpu_device *adev; 526 struct drm_file *filp; 527 struct amdgpu_ctx *ctx; 528 529 /* chunks */ 530 unsigned nchunks; 531 struct amdgpu_cs_chunk *chunks; 532 533 /* scheduler job object */ 534 struct amdgpu_job *job; 535 struct drm_sched_entity *entity; 536 537 /* buffer objects */ 538 struct ww_acquire_ctx ticket; 539 struct amdgpu_bo_list *bo_list; 540 struct amdgpu_mn *mn; 541 struct amdgpu_bo_list_entry vm_pd; 542 struct list_head validated; 543 struct dma_fence *fence; 544 uint64_t bytes_moved_threshold; 545 uint64_t bytes_moved_vis_threshold; 546 uint64_t bytes_moved; 547 uint64_t bytes_moved_vis; 548 549 /* user fence */ 550 struct amdgpu_bo_list_entry uf_entry; 551 552 unsigned num_post_deps; 553 struct amdgpu_cs_post_dep *post_deps; 554 }; 555 556 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 557 uint32_t ib_idx, int idx) 558 { 559 return p->job->ibs[ib_idx].ptr[idx]; 560 } 561 562 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 563 uint32_t ib_idx, int idx, 564 uint32_t value) 565 { 566 p->job->ibs[ib_idx].ptr[idx] = value; 567 } 568 569 /* 570 * Writeback 571 */ 572 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 573 574 struct amdgpu_wb { 575 struct amdgpu_bo *wb_obj; 576 volatile uint32_t *wb; 577 uint64_t gpu_addr; 578 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 579 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 580 }; 581 582 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 583 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 584 585 /* 586 * Benchmarking 587 */ 588 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 589 590 /* 591 * ASIC specific register table accessible by UMD 592 */ 593 struct amdgpu_allowed_register_entry { 594 uint32_t reg_offset; 595 bool grbm_indexed; 596 }; 597 598 enum amd_reset_method { 599 AMD_RESET_METHOD_NONE = -1, 600 AMD_RESET_METHOD_LEGACY = 0, 601 AMD_RESET_METHOD_MODE0, 602 AMD_RESET_METHOD_MODE1, 603 AMD_RESET_METHOD_MODE2, 604 AMD_RESET_METHOD_BACO, 605 AMD_RESET_METHOD_PCI, 606 }; 607 608 struct amdgpu_video_codec_info { 609 u32 codec_type; 610 u32 max_width; 611 u32 max_height; 612 u32 max_pixels_per_frame; 613 u32 max_level; 614 }; 615 616 #define codec_info_build(type, width, height, level) \ 617 .codec_type = type,\ 618 .max_width = width,\ 619 .max_height = height,\ 620 .max_pixels_per_frame = height * width,\ 621 .max_level = level, 622 623 struct amdgpu_video_codecs { 624 const u32 codec_count; 625 const struct amdgpu_video_codec_info *codec_array; 626 }; 627 628 /* 629 * ASIC specific functions. 630 */ 631 struct amdgpu_asic_funcs { 632 bool (*read_disabled_bios)(struct amdgpu_device *adev); 633 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 634 u8 *bios, u32 length_bytes); 635 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 636 u32 sh_num, u32 reg_offset, u32 *value); 637 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 638 int (*reset)(struct amdgpu_device *adev); 639 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 640 /* get the reference clock */ 641 u32 (*get_xclk)(struct amdgpu_device *adev); 642 /* MM block clocks */ 643 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 644 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 645 /* static power management */ 646 int (*get_pcie_lanes)(struct amdgpu_device *adev); 647 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 648 /* get config memsize register */ 649 u32 (*get_config_memsize)(struct amdgpu_device *adev); 650 /* flush hdp write queue */ 651 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 652 /* invalidate hdp read cache */ 653 void (*invalidate_hdp)(struct amdgpu_device *adev, 654 struct amdgpu_ring *ring); 655 /* check if the asic needs a full reset of if soft reset will work */ 656 bool (*need_full_reset)(struct amdgpu_device *adev); 657 /* initialize doorbell layout for specific asic*/ 658 void (*init_doorbell_index)(struct amdgpu_device *adev); 659 /* PCIe bandwidth usage */ 660 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 661 uint64_t *count1); 662 /* do we need to reset the asic at init time (e.g., kexec) */ 663 bool (*need_reset_on_init)(struct amdgpu_device *adev); 664 /* PCIe replay counter */ 665 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 666 /* device supports BACO */ 667 bool (*supports_baco)(struct amdgpu_device *adev); 668 /* pre asic_init quirks */ 669 void (*pre_asic_init)(struct amdgpu_device *adev); 670 /* enter/exit umd stable pstate */ 671 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 672 /* query video codecs */ 673 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 674 const struct amdgpu_video_codecs **codecs); 675 }; 676 677 /* 678 * IOCTL. 679 */ 680 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 681 struct drm_file *filp); 682 683 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 684 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 685 struct drm_file *filp); 686 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 687 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 688 struct drm_file *filp); 689 690 /* VRAM scratch page for HDP bug, default vram page */ 691 struct amdgpu_vram_scratch { 692 struct amdgpu_bo *robj; 693 volatile uint32_t *ptr; 694 u64 gpu_addr; 695 }; 696 697 /* 698 * CGS 699 */ 700 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 701 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 702 703 /* 704 * Core structure, functions and helpers. 705 */ 706 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 707 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 708 709 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 710 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 711 712 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 713 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 714 715 struct amdgpu_mmio_remap { 716 u32 reg_offset; 717 resource_size_t bus_addr; 718 }; 719 720 /* Define the HW IP blocks will be used in driver , add more if necessary */ 721 enum amd_hw_ip_block_type { 722 GC_HWIP = 1, 723 HDP_HWIP, 724 SDMA0_HWIP, 725 SDMA1_HWIP, 726 SDMA2_HWIP, 727 SDMA3_HWIP, 728 SDMA4_HWIP, 729 SDMA5_HWIP, 730 SDMA6_HWIP, 731 SDMA7_HWIP, 732 MMHUB_HWIP, 733 ATHUB_HWIP, 734 NBIO_HWIP, 735 MP0_HWIP, 736 MP1_HWIP, 737 UVD_HWIP, 738 VCN_HWIP = UVD_HWIP, 739 JPEG_HWIP = VCN_HWIP, 740 VCN1_HWIP, 741 VCE_HWIP, 742 DF_HWIP, 743 DCE_HWIP, 744 OSSSYS_HWIP, 745 SMUIO_HWIP, 746 PWR_HWIP, 747 NBIF_HWIP, 748 THM_HWIP, 749 CLK_HWIP, 750 UMC_HWIP, 751 RSMU_HWIP, 752 XGMI_HWIP, 753 DCI_HWIP, 754 MAX_HWIP 755 }; 756 757 #define HWIP_MAX_INSTANCE 10 758 759 #define HW_ID_MAX 300 760 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 761 762 struct amd_powerplay { 763 void *pp_handle; 764 const struct amd_pm_funcs *pp_funcs; 765 }; 766 767 struct ip_discovery_top; 768 769 /* polaris10 kickers */ 770 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 771 ((rid == 0xE3) || \ 772 (rid == 0xE4) || \ 773 (rid == 0xE5) || \ 774 (rid == 0xE7) || \ 775 (rid == 0xEF))) || \ 776 ((did == 0x6FDF) && \ 777 ((rid == 0xE7) || \ 778 (rid == 0xEF) || \ 779 (rid == 0xFF)))) 780 781 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 782 ((rid == 0xE1) || \ 783 (rid == 0xF7))) 784 785 /* polaris11 kickers */ 786 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 787 ((rid == 0xE0) || \ 788 (rid == 0xE5))) || \ 789 ((did == 0x67FF) && \ 790 ((rid == 0xCF) || \ 791 (rid == 0xEF) || \ 792 (rid == 0xFF)))) 793 794 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 795 ((rid == 0xE2))) 796 797 /* polaris12 kickers */ 798 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 799 ((rid == 0xC0) || \ 800 (rid == 0xC1) || \ 801 (rid == 0xC3) || \ 802 (rid == 0xC7))) || \ 803 ((did == 0x6981) && \ 804 ((rid == 0x00) || \ 805 (rid == 0x01) || \ 806 (rid == 0x10)))) 807 808 #define AMDGPU_RESET_MAGIC_NUM 64 809 #define AMDGPU_MAX_DF_PERFMONS 4 810 #define AMDGPU_PRODUCT_NAME_LEN 64 811 struct amdgpu_reset_domain; 812 813 struct amdgpu_device { 814 struct device *dev; 815 struct pci_dev *pdev; 816 struct drm_device ddev; 817 818 #ifdef CONFIG_DRM_AMD_ACP 819 struct amdgpu_acp acp; 820 #endif 821 struct amdgpu_hive_info *hive; 822 /* ASIC */ 823 enum amd_asic_type asic_type; 824 uint32_t family; 825 uint32_t rev_id; 826 uint32_t external_rev_id; 827 unsigned long flags; 828 unsigned long apu_flags; 829 int usec_timeout; 830 const struct amdgpu_asic_funcs *asic_funcs; 831 bool shutdown; 832 bool need_swiotlb; 833 bool accel_working; 834 struct notifier_block acpi_nb; 835 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 836 struct debugfs_blob_wrapper debugfs_vbios_blob; 837 struct debugfs_blob_wrapper debugfs_discovery_blob; 838 struct mutex srbm_mutex; 839 /* GRBM index mutex. Protects concurrent access to GRBM index */ 840 struct mutex grbm_idx_mutex; 841 struct dev_pm_domain vga_pm_domain; 842 bool have_disp_power_ref; 843 bool have_atomics_support; 844 845 /* BIOS */ 846 bool is_atom_fw; 847 uint8_t *bios; 848 uint32_t bios_size; 849 uint32_t bios_scratch_reg_offset; 850 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 851 852 /* Register/doorbell mmio */ 853 resource_size_t rmmio_base; 854 resource_size_t rmmio_size; 855 void __iomem *rmmio; 856 /* protects concurrent MM_INDEX/DATA based register access */ 857 spinlock_t mmio_idx_lock; 858 struct amdgpu_mmio_remap rmmio_remap; 859 /* protects concurrent SMC based register access */ 860 spinlock_t smc_idx_lock; 861 amdgpu_rreg_t smc_rreg; 862 amdgpu_wreg_t smc_wreg; 863 /* protects concurrent PCIE register access */ 864 spinlock_t pcie_idx_lock; 865 amdgpu_rreg_t pcie_rreg; 866 amdgpu_wreg_t pcie_wreg; 867 amdgpu_rreg_t pciep_rreg; 868 amdgpu_wreg_t pciep_wreg; 869 amdgpu_rreg64_t pcie_rreg64; 870 amdgpu_wreg64_t pcie_wreg64; 871 /* protects concurrent UVD register access */ 872 spinlock_t uvd_ctx_idx_lock; 873 amdgpu_rreg_t uvd_ctx_rreg; 874 amdgpu_wreg_t uvd_ctx_wreg; 875 /* protects concurrent DIDT register access */ 876 spinlock_t didt_idx_lock; 877 amdgpu_rreg_t didt_rreg; 878 amdgpu_wreg_t didt_wreg; 879 /* protects concurrent gc_cac register access */ 880 spinlock_t gc_cac_idx_lock; 881 amdgpu_rreg_t gc_cac_rreg; 882 amdgpu_wreg_t gc_cac_wreg; 883 /* protects concurrent se_cac register access */ 884 spinlock_t se_cac_idx_lock; 885 amdgpu_rreg_t se_cac_rreg; 886 amdgpu_wreg_t se_cac_wreg; 887 /* protects concurrent ENDPOINT (audio) register access */ 888 spinlock_t audio_endpt_idx_lock; 889 amdgpu_block_rreg_t audio_endpt_rreg; 890 amdgpu_block_wreg_t audio_endpt_wreg; 891 struct amdgpu_doorbell doorbell; 892 893 /* clock/pll info */ 894 struct amdgpu_clock clock; 895 896 /* MC */ 897 struct amdgpu_gmc gmc; 898 struct amdgpu_gart gart; 899 dma_addr_t dummy_page_addr; 900 struct amdgpu_vm_manager vm_manager; 901 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 902 unsigned num_vmhubs; 903 904 /* memory management */ 905 struct amdgpu_mman mman; 906 struct amdgpu_vram_scratch vram_scratch; 907 struct amdgpu_wb wb; 908 atomic64_t num_bytes_moved; 909 atomic64_t num_evictions; 910 atomic64_t num_vram_cpu_page_faults; 911 atomic_t gpu_reset_counter; 912 atomic_t vram_lost_counter; 913 914 /* data for buffer migration throttling */ 915 struct { 916 spinlock_t lock; 917 s64 last_update_us; 918 s64 accum_us; /* accumulated microseconds */ 919 s64 accum_us_vis; /* for visible VRAM */ 920 u32 log2_max_MBps; 921 } mm_stats; 922 923 /* display */ 924 bool enable_virtual_display; 925 struct amdgpu_vkms_output *amdgpu_vkms_output; 926 struct amdgpu_mode_info mode_info; 927 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 928 struct work_struct hotplug_work; 929 struct amdgpu_irq_src crtc_irq; 930 struct amdgpu_irq_src vline0_irq; 931 struct amdgpu_irq_src vupdate_irq; 932 struct amdgpu_irq_src pageflip_irq; 933 struct amdgpu_irq_src hpd_irq; 934 struct amdgpu_irq_src dmub_trace_irq; 935 struct amdgpu_irq_src dmub_outbox_irq; 936 937 /* rings */ 938 u64 fence_context; 939 unsigned num_rings; 940 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 941 bool ib_pool_ready; 942 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 943 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 944 945 /* interrupts */ 946 struct amdgpu_irq irq; 947 948 /* powerplay */ 949 struct amd_powerplay powerplay; 950 struct amdgpu_pm pm; 951 u32 cg_flags; 952 u32 pg_flags; 953 954 /* nbio */ 955 struct amdgpu_nbio nbio; 956 957 /* hdp */ 958 struct amdgpu_hdp hdp; 959 960 /* smuio */ 961 struct amdgpu_smuio smuio; 962 963 /* mmhub */ 964 struct amdgpu_mmhub mmhub; 965 966 /* gfxhub */ 967 struct amdgpu_gfxhub gfxhub; 968 969 /* gfx */ 970 struct amdgpu_gfx gfx; 971 972 /* sdma */ 973 struct amdgpu_sdma sdma; 974 975 /* uvd */ 976 struct amdgpu_uvd uvd; 977 978 /* vce */ 979 struct amdgpu_vce vce; 980 981 /* vcn */ 982 struct amdgpu_vcn vcn; 983 984 /* jpeg */ 985 struct amdgpu_jpeg jpeg; 986 987 /* firmwares */ 988 struct amdgpu_firmware firmware; 989 990 /* PSP */ 991 struct psp_context psp; 992 993 /* GDS */ 994 struct amdgpu_gds gds; 995 996 /* KFD */ 997 struct amdgpu_kfd_dev kfd; 998 999 /* UMC */ 1000 struct amdgpu_umc umc; 1001 1002 /* display related functionality */ 1003 struct amdgpu_display_manager dm; 1004 1005 /* mes */ 1006 bool enable_mes; 1007 struct amdgpu_mes mes; 1008 1009 /* df */ 1010 struct amdgpu_df df; 1011 1012 /* MCA */ 1013 struct amdgpu_mca mca; 1014 1015 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1016 uint32_t harvest_ip_mask; 1017 int num_ip_blocks; 1018 struct mutex mn_lock; 1019 DECLARE_HASHTABLE(mn_hash, 7); 1020 1021 /* tracking pinned memory */ 1022 atomic64_t vram_pin_size; 1023 atomic64_t visible_pin_size; 1024 atomic64_t gart_pin_size; 1025 1026 /* soc15 register offset based on ip, instance and segment */ 1027 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1028 1029 /* delayed work_func for deferring clockgating during resume */ 1030 struct delayed_work delayed_init_work; 1031 1032 struct amdgpu_virt virt; 1033 1034 /* link all shadow bo */ 1035 struct list_head shadow_list; 1036 struct mutex shadow_list_lock; 1037 1038 /* record hw reset is performed */ 1039 bool has_hw_reset; 1040 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1041 1042 /* s3/s4 mask */ 1043 bool in_suspend; 1044 bool in_s3; 1045 bool in_s4; 1046 bool in_s0ix; 1047 1048 enum pp_mp1_state mp1_state; 1049 struct amdgpu_doorbell_index doorbell_index; 1050 1051 struct mutex notifier_lock; 1052 1053 int asic_reset_res; 1054 struct work_struct xgmi_reset_work; 1055 struct list_head reset_list; 1056 1057 long gfx_timeout; 1058 long sdma_timeout; 1059 long video_timeout; 1060 long compute_timeout; 1061 1062 uint64_t unique_id; 1063 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1064 1065 /* enable runtime pm on the device */ 1066 bool runpm; 1067 bool in_runpm; 1068 bool has_pr3; 1069 bool is_fw_fb; 1070 1071 bool pm_sysfs_en; 1072 bool ucode_sysfs_en; 1073 1074 /* Chip product information */ 1075 char product_number[16]; 1076 char product_name[AMDGPU_PRODUCT_NAME_LEN]; 1077 char serial[20]; 1078 1079 atomic_t throttling_logging_enabled; 1080 struct ratelimit_state throttling_logging_rs; 1081 uint32_t ras_hw_enabled; 1082 uint32_t ras_enabled; 1083 1084 bool no_hw_access; 1085 struct pci_saved_state *pci_state; 1086 pci_channel_state_t pci_channel_state; 1087 1088 struct amdgpu_reset_control *reset_cntl; 1089 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1090 1091 bool ram_is_direct_mapped; 1092 1093 struct list_head ras_list; 1094 1095 struct ip_discovery_top *ip_top; 1096 1097 struct amdgpu_reset_domain *reset_domain; 1098 1099 struct mutex benchmark_mutex; 1100 1101 /* reset dump register */ 1102 uint32_t *reset_dump_reg_list; 1103 int num_regs; 1104 }; 1105 1106 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1107 { 1108 return container_of(ddev, struct amdgpu_device, ddev); 1109 } 1110 1111 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1112 { 1113 return &adev->ddev; 1114 } 1115 1116 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1117 { 1118 return container_of(bdev, struct amdgpu_device, mman.bdev); 1119 } 1120 1121 int amdgpu_device_init(struct amdgpu_device *adev, 1122 uint32_t flags); 1123 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1124 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1125 1126 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1127 1128 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1129 void *buf, size_t size, bool write); 1130 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1131 void *buf, size_t size, bool write); 1132 1133 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1134 void *buf, size_t size, bool write); 1135 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1136 uint32_t reg, uint32_t acc_flags); 1137 void amdgpu_device_wreg(struct amdgpu_device *adev, 1138 uint32_t reg, uint32_t v, 1139 uint32_t acc_flags); 1140 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1141 uint32_t reg, uint32_t v); 1142 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1143 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1144 1145 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1146 u32 pcie_index, u32 pcie_data, 1147 u32 reg_addr); 1148 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1149 u32 pcie_index, u32 pcie_data, 1150 u32 reg_addr); 1151 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1152 u32 pcie_index, u32 pcie_data, 1153 u32 reg_addr, u32 reg_data); 1154 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1155 u32 pcie_index, u32 pcie_data, 1156 u32 reg_addr, u64 reg_data); 1157 1158 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1159 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1160 1161 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1162 struct amdgpu_reset_context *reset_context); 1163 1164 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1165 struct amdgpu_reset_context *reset_context); 1166 1167 int emu_soc_asic_init(struct amdgpu_device *adev); 1168 1169 /* 1170 * Registers read & write functions. 1171 */ 1172 #define AMDGPU_REGS_NO_KIQ (1<<1) 1173 #define AMDGPU_REGS_RLC (1<<2) 1174 1175 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1176 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1177 1178 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1179 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1180 1181 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1182 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1183 1184 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1185 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1186 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1187 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1188 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1189 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1190 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1191 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1192 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1193 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1194 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1195 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1196 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1197 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1198 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1199 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1200 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1201 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1202 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1203 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1204 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1205 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1206 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1207 #define WREG32_P(reg, val, mask) \ 1208 do { \ 1209 uint32_t tmp_ = RREG32(reg); \ 1210 tmp_ &= (mask); \ 1211 tmp_ |= ((val) & ~(mask)); \ 1212 WREG32(reg, tmp_); \ 1213 } while (0) 1214 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1215 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1216 #define WREG32_PLL_P(reg, val, mask) \ 1217 do { \ 1218 uint32_t tmp_ = RREG32_PLL(reg); \ 1219 tmp_ &= (mask); \ 1220 tmp_ |= ((val) & ~(mask)); \ 1221 WREG32_PLL(reg, tmp_); \ 1222 } while (0) 1223 1224 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1225 do { \ 1226 u32 tmp = RREG32_SMC(_Reg); \ 1227 tmp &= (_Mask); \ 1228 tmp |= ((_Val) & ~(_Mask)); \ 1229 WREG32_SMC(_Reg, tmp); \ 1230 } while (0) 1231 1232 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1233 1234 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1235 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1236 1237 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1238 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1239 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1240 1241 #define REG_GET_FIELD(value, reg, field) \ 1242 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1243 1244 #define WREG32_FIELD(reg, field, val) \ 1245 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1246 1247 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1248 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1249 1250 /* 1251 * BIOS helpers. 1252 */ 1253 #define RBIOS8(i) (adev->bios[i]) 1254 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1255 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1256 1257 /* 1258 * ASICs macro. 1259 */ 1260 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1261 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1262 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1263 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1264 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1265 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1266 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1267 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1268 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1269 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1270 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1271 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1272 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1273 #define amdgpu_asic_flush_hdp(adev, r) \ 1274 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1275 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1276 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r))) 1277 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1278 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1279 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1280 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1281 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1282 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1283 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1284 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1285 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1286 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1287 1288 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1289 1290 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 1291 1292 /* Common functions */ 1293 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1294 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1295 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1296 struct amdgpu_job* job); 1297 int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev, 1298 struct amdgpu_job *job); 1299 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1300 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1301 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1302 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1303 1304 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1305 u64 num_vis_bytes); 1306 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1307 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1308 const u32 *registers, 1309 const u32 array_size); 1310 1311 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1312 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1313 bool amdgpu_device_supports_px(struct drm_device *dev); 1314 bool amdgpu_device_supports_boco(struct drm_device *dev); 1315 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1316 bool amdgpu_device_supports_baco(struct drm_device *dev); 1317 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1318 struct amdgpu_device *peer_adev); 1319 int amdgpu_device_baco_enter(struct drm_device *dev); 1320 int amdgpu_device_baco_exit(struct drm_device *dev); 1321 1322 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1323 struct amdgpu_ring *ring); 1324 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1325 struct amdgpu_ring *ring); 1326 1327 void amdgpu_device_halt(struct amdgpu_device *adev); 1328 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1329 u32 reg); 1330 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1331 u32 reg, u32 v); 1332 1333 /* atpx handler */ 1334 #if defined(CONFIG_VGA_SWITCHEROO) 1335 void amdgpu_register_atpx_handler(void); 1336 void amdgpu_unregister_atpx_handler(void); 1337 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1338 bool amdgpu_is_atpx_hybrid(void); 1339 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1340 bool amdgpu_has_atpx(void); 1341 #else 1342 static inline void amdgpu_register_atpx_handler(void) {} 1343 static inline void amdgpu_unregister_atpx_handler(void) {} 1344 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1345 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1346 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1347 static inline bool amdgpu_has_atpx(void) { return false; } 1348 #endif 1349 1350 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1351 void *amdgpu_atpx_get_dhandle(void); 1352 #else 1353 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1354 #endif 1355 1356 /* 1357 * KMS 1358 */ 1359 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1360 extern const int amdgpu_max_kms_ioctl; 1361 1362 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1363 void amdgpu_driver_unload_kms(struct drm_device *dev); 1364 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1365 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1366 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1367 struct drm_file *file_priv); 1368 void amdgpu_driver_release_kms(struct drm_device *dev); 1369 1370 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1371 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1372 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1373 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1374 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1375 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1376 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1377 struct drm_file *filp); 1378 1379 /* 1380 * functions used by amdgpu_encoder.c 1381 */ 1382 struct amdgpu_afmt_acr { 1383 u32 clock; 1384 1385 int n_32khz; 1386 int cts_32khz; 1387 1388 int n_44_1khz; 1389 int cts_44_1khz; 1390 1391 int n_48khz; 1392 int cts_48khz; 1393 1394 }; 1395 1396 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1397 1398 /* amdgpu_acpi.c */ 1399 1400 /* ATCS Device/Driver State */ 1401 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1402 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1403 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1404 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1405 1406 #if defined(CONFIG_ACPI) 1407 int amdgpu_acpi_init(struct amdgpu_device *adev); 1408 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1409 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1410 bool amdgpu_acpi_is_power_shift_control_supported(void); 1411 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1412 u8 perf_req, bool advertise); 1413 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1414 u8 dev_state, bool drv_state); 1415 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1416 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1417 1418 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1419 void amdgpu_acpi_detect(void); 1420 #else 1421 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1422 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1423 static inline void amdgpu_acpi_detect(void) { } 1424 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1425 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1426 u8 dev_state, bool drv_state) { return 0; } 1427 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1428 enum amdgpu_ss ss_state) { return 0; } 1429 #endif 1430 1431 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1432 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1433 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1434 #else 1435 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1436 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1437 #endif 1438 1439 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1440 uint64_t addr, struct amdgpu_bo **bo, 1441 struct amdgpu_bo_va_mapping **mapping); 1442 1443 #if defined(CONFIG_DRM_AMD_DC) 1444 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1445 #else 1446 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1447 #endif 1448 1449 1450 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1451 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1452 1453 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1454 pci_channel_state_t state); 1455 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1456 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1457 void amdgpu_pci_resume(struct pci_dev *pdev); 1458 1459 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1460 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1461 1462 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1463 1464 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1465 enum amd_clockgating_state state); 1466 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1467 enum amd_powergating_state state); 1468 1469 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1470 { 1471 return amdgpu_gpu_recovery != 0 && 1472 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1473 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1474 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1475 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1476 } 1477 1478 #include "amdgpu_object.h" 1479 1480 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1481 { 1482 return adev->gmc.tmz_enabled; 1483 } 1484 1485 int amdgpu_in_reset(struct amdgpu_device *adev); 1486 1487 #endif 1488