1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_execbuf_util.h> 59 60 #include <drm/amdgpu_drm.h> 61 #include <drm/drm_gem.h> 62 #include <drm/drm_ioctl.h> 63 #include <drm/gpu_scheduler.h> 64 65 #include <kgd_kfd_interface.h> 66 #include "dm_pp_interface.h" 67 #include "kgd_pp_interface.h" 68 69 #include "amd_shared.h" 70 #include "amdgpu_mode.h" 71 #include "amdgpu_ih.h" 72 #include "amdgpu_irq.h" 73 #include "amdgpu_ucode.h" 74 #include "amdgpu_ttm.h" 75 #include "amdgpu_psp.h" 76 #include "amdgpu_gds.h" 77 #include "amdgpu_sync.h" 78 #include "amdgpu_ring.h" 79 #include "amdgpu_vm.h" 80 #include "amdgpu_dpm.h" 81 #include "amdgpu_acp.h" 82 #include "amdgpu_uvd.h" 83 #include "amdgpu_vce.h" 84 #include "amdgpu_vcn.h" 85 #include "amdgpu_jpeg.h" 86 #include "amdgpu_mn.h" 87 #include "amdgpu_gmc.h" 88 #include "amdgpu_gfx.h" 89 #include "amdgpu_sdma.h" 90 #include "amdgpu_nbio.h" 91 #include "amdgpu_hdp.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_discovery.h" 103 #include "amdgpu_mes.h" 104 #include "amdgpu_umc.h" 105 #include "amdgpu_mmhub.h" 106 #include "amdgpu_gfxhub.h" 107 #include "amdgpu_df.h" 108 #include "amdgpu_smuio.h" 109 #include "amdgpu_fdinfo.h" 110 #include "amdgpu_mca.h" 111 #include "amdgpu_ras.h" 112 113 #define MAX_GPU_INSTANCE 16 114 115 struct amdgpu_gpu_instance 116 { 117 struct amdgpu_device *adev; 118 int mgpu_fan_enabled; 119 }; 120 121 struct amdgpu_mgpu_info 122 { 123 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 124 struct mutex mutex; 125 uint32_t num_gpu; 126 uint32_t num_dgpu; 127 uint32_t num_apu; 128 129 /* delayed reset_func for XGMI configuration if necessary */ 130 struct delayed_work delayed_reset_work; 131 bool pending_reset; 132 }; 133 134 enum amdgpu_ss { 135 AMDGPU_SS_DRV_LOAD, 136 AMDGPU_SS_DEV_D0, 137 AMDGPU_SS_DEV_D3, 138 AMDGPU_SS_DRV_UNLOAD 139 }; 140 141 struct amdgpu_watchdog_timer 142 { 143 bool timeout_fatal_disable; 144 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 145 }; 146 147 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 148 149 /* 150 * Modules parameters. 151 */ 152 extern int amdgpu_modeset; 153 extern int amdgpu_vram_limit; 154 extern int amdgpu_vis_vram_limit; 155 extern int amdgpu_gart_size; 156 extern int amdgpu_gtt_size; 157 extern int amdgpu_moverate; 158 extern int amdgpu_audio; 159 extern int amdgpu_disp_priority; 160 extern int amdgpu_hw_i2c; 161 extern int amdgpu_pcie_gen2; 162 extern int amdgpu_msi; 163 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 164 extern int amdgpu_dpm; 165 extern int amdgpu_fw_load_type; 166 extern int amdgpu_aspm; 167 extern int amdgpu_runtime_pm; 168 extern uint amdgpu_ip_block_mask; 169 extern int amdgpu_bapm; 170 extern int amdgpu_deep_color; 171 extern int amdgpu_vm_size; 172 extern int amdgpu_vm_block_size; 173 extern int amdgpu_vm_fragment_size; 174 extern int amdgpu_vm_fault_stop; 175 extern int amdgpu_vm_debug; 176 extern int amdgpu_vm_update_mode; 177 extern int amdgpu_exp_hw_support; 178 extern int amdgpu_dc; 179 extern int amdgpu_sched_jobs; 180 extern int amdgpu_sched_hw_submission; 181 extern uint amdgpu_pcie_gen_cap; 182 extern uint amdgpu_pcie_lane_cap; 183 extern uint amdgpu_cg_mask; 184 extern uint amdgpu_pg_mask; 185 extern uint amdgpu_sdma_phase_quantum; 186 extern char *amdgpu_disable_cu; 187 extern char *amdgpu_virtual_display; 188 extern uint amdgpu_pp_feature_mask; 189 extern uint amdgpu_force_long_training; 190 extern int amdgpu_job_hang_limit; 191 extern int amdgpu_lbpw; 192 extern int amdgpu_compute_multipipe; 193 extern int amdgpu_gpu_recovery; 194 extern int amdgpu_emu_mode; 195 extern uint amdgpu_smu_memory_pool_size; 196 extern int amdgpu_smu_pptable_id; 197 extern uint amdgpu_dc_feature_mask; 198 extern uint amdgpu_dc_debug_mask; 199 extern uint amdgpu_dm_abm_level; 200 extern int amdgpu_backlight; 201 extern struct amdgpu_mgpu_info mgpu_info; 202 extern int amdgpu_ras_enable; 203 extern uint amdgpu_ras_mask; 204 extern int amdgpu_bad_page_threshold; 205 extern bool amdgpu_ignore_bad_page_threshold; 206 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 207 extern int amdgpu_async_gfx_ring; 208 extern int amdgpu_mcbp; 209 extern int amdgpu_discovery; 210 extern int amdgpu_mes; 211 extern int amdgpu_noretry; 212 extern int amdgpu_force_asic_type; 213 extern int amdgpu_smartshift_bias; 214 #ifdef CONFIG_HSA_AMD 215 extern int sched_policy; 216 extern bool debug_evictions; 217 extern bool no_system_mem_limit; 218 #else 219 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 220 static const bool __maybe_unused debug_evictions; /* = false */ 221 static const bool __maybe_unused no_system_mem_limit; 222 #endif 223 224 extern int amdgpu_tmz; 225 extern int amdgpu_reset_method; 226 227 #ifdef CONFIG_DRM_AMDGPU_SI 228 extern int amdgpu_si_support; 229 #endif 230 #ifdef CONFIG_DRM_AMDGPU_CIK 231 extern int amdgpu_cik_support; 232 #endif 233 extern int amdgpu_num_kcq; 234 235 #define AMDGPU_VM_MAX_NUM_CTX 4096 236 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 237 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 238 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 239 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 240 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 241 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 242 #define AMDGPUFB_CONN_LIMIT 4 243 #define AMDGPU_BIOS_NUM_SCRATCH 16 244 245 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 246 247 /* hard reset data */ 248 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 249 250 /* reset flags */ 251 #define AMDGPU_RESET_GFX (1 << 0) 252 #define AMDGPU_RESET_COMPUTE (1 << 1) 253 #define AMDGPU_RESET_DMA (1 << 2) 254 #define AMDGPU_RESET_CP (1 << 3) 255 #define AMDGPU_RESET_GRBM (1 << 4) 256 #define AMDGPU_RESET_DMA1 (1 << 5) 257 #define AMDGPU_RESET_RLC (1 << 6) 258 #define AMDGPU_RESET_SEM (1 << 7) 259 #define AMDGPU_RESET_IH (1 << 8) 260 #define AMDGPU_RESET_VMC (1 << 9) 261 #define AMDGPU_RESET_MC (1 << 10) 262 #define AMDGPU_RESET_DISPLAY (1 << 11) 263 #define AMDGPU_RESET_UVD (1 << 12) 264 #define AMDGPU_RESET_VCE (1 << 13) 265 #define AMDGPU_RESET_VCE1 (1 << 14) 266 267 /* max cursor sizes (in pixels) */ 268 #define CIK_CURSOR_WIDTH 128 269 #define CIK_CURSOR_HEIGHT 128 270 271 /* smasrt shift bias level limits */ 272 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 273 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 274 275 struct amdgpu_device; 276 struct amdgpu_ib; 277 struct amdgpu_cs_parser; 278 struct amdgpu_job; 279 struct amdgpu_irq_src; 280 struct amdgpu_fpriv; 281 struct amdgpu_bo_va_mapping; 282 struct kfd_vm_fault_info; 283 struct amdgpu_hive_info; 284 struct amdgpu_reset_context; 285 struct amdgpu_reset_control; 286 287 enum amdgpu_cp_irq { 288 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 289 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 290 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 291 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 292 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 293 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 294 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 295 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 296 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 297 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 298 299 AMDGPU_CP_IRQ_LAST 300 }; 301 302 enum amdgpu_thermal_irq { 303 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 304 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 305 306 AMDGPU_THERMAL_IRQ_LAST 307 }; 308 309 enum amdgpu_kiq_irq { 310 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 311 AMDGPU_CP_KIQ_IRQ_LAST 312 }; 313 314 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 315 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 316 #define MAX_KIQ_REG_TRY 1000 317 318 int amdgpu_device_ip_set_clockgating_state(void *dev, 319 enum amd_ip_block_type block_type, 320 enum amd_clockgating_state state); 321 int amdgpu_device_ip_set_powergating_state(void *dev, 322 enum amd_ip_block_type block_type, 323 enum amd_powergating_state state); 324 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 325 u32 *flags); 326 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 327 enum amd_ip_block_type block_type); 328 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 329 enum amd_ip_block_type block_type); 330 331 #define AMDGPU_MAX_IP_NUM 16 332 333 struct amdgpu_ip_block_status { 334 bool valid; 335 bool sw; 336 bool hw; 337 bool late_initialized; 338 bool hang; 339 }; 340 341 struct amdgpu_ip_block_version { 342 const enum amd_ip_block_type type; 343 const u32 major; 344 const u32 minor; 345 const u32 rev; 346 const struct amd_ip_funcs *funcs; 347 }; 348 349 #define HW_REV(_Major, _Minor, _Rev) \ 350 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 351 352 struct amdgpu_ip_block { 353 struct amdgpu_ip_block_status status; 354 const struct amdgpu_ip_block_version *version; 355 }; 356 357 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 358 enum amd_ip_block_type type, 359 u32 major, u32 minor); 360 361 struct amdgpu_ip_block * 362 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 363 enum amd_ip_block_type type); 364 365 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 366 const struct amdgpu_ip_block_version *ip_block_version); 367 368 /* 369 * BIOS. 370 */ 371 bool amdgpu_get_bios(struct amdgpu_device *adev); 372 bool amdgpu_read_bios(struct amdgpu_device *adev); 373 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 374 u8 *bios, u32 length_bytes); 375 /* 376 * Clocks 377 */ 378 379 #define AMDGPU_MAX_PPLL 3 380 381 struct amdgpu_clock { 382 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 383 struct amdgpu_pll spll; 384 struct amdgpu_pll mpll; 385 /* 10 Khz units */ 386 uint32_t default_mclk; 387 uint32_t default_sclk; 388 uint32_t default_dispclk; 389 uint32_t current_dispclk; 390 uint32_t dp_extclk; 391 uint32_t max_pixel_clock; 392 }; 393 394 /* sub-allocation manager, it has to be protected by another lock. 395 * By conception this is an helper for other part of the driver 396 * like the indirect buffer or semaphore, which both have their 397 * locking. 398 * 399 * Principe is simple, we keep a list of sub allocation in offset 400 * order (first entry has offset == 0, last entry has the highest 401 * offset). 402 * 403 * When allocating new object we first check if there is room at 404 * the end total_size - (last_object_offset + last_object_size) >= 405 * alloc_size. If so we allocate new object there. 406 * 407 * When there is not enough room at the end, we start waiting for 408 * each sub object until we reach object_offset+object_size >= 409 * alloc_size, this object then become the sub object we return. 410 * 411 * Alignment can't be bigger than page size. 412 * 413 * Hole are not considered for allocation to keep things simple. 414 * Assumption is that there won't be hole (all object on same 415 * alignment). 416 */ 417 418 #define AMDGPU_SA_NUM_FENCE_LISTS 32 419 420 struct amdgpu_sa_manager { 421 wait_queue_head_t wq; 422 struct amdgpu_bo *bo; 423 struct list_head *hole; 424 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 425 struct list_head olist; 426 unsigned size; 427 uint64_t gpu_addr; 428 void *cpu_ptr; 429 uint32_t domain; 430 uint32_t align; 431 }; 432 433 /* sub-allocation buffer */ 434 struct amdgpu_sa_bo { 435 struct list_head olist; 436 struct list_head flist; 437 struct amdgpu_sa_manager *manager; 438 unsigned soffset; 439 unsigned eoffset; 440 struct dma_fence *fence; 441 }; 442 443 int amdgpu_fence_slab_init(void); 444 void amdgpu_fence_slab_fini(void); 445 446 /* 447 * IRQS. 448 */ 449 450 struct amdgpu_flip_work { 451 struct delayed_work flip_work; 452 struct work_struct unpin_work; 453 struct amdgpu_device *adev; 454 int crtc_id; 455 u32 target_vblank; 456 uint64_t base; 457 struct drm_pending_vblank_event *event; 458 struct amdgpu_bo *old_abo; 459 unsigned shared_count; 460 struct dma_fence **shared; 461 struct dma_fence_cb cb; 462 bool async; 463 }; 464 465 466 /* 467 * CP & rings. 468 */ 469 470 struct amdgpu_ib { 471 struct amdgpu_sa_bo *sa_bo; 472 uint32_t length_dw; 473 uint64_t gpu_addr; 474 uint32_t *ptr; 475 uint32_t flags; 476 }; 477 478 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 479 480 /* 481 * file private structure 482 */ 483 484 struct amdgpu_fpriv { 485 struct amdgpu_vm vm; 486 struct amdgpu_bo_va *prt_va; 487 struct amdgpu_bo_va *csa_va; 488 struct mutex bo_list_lock; 489 struct idr bo_list_handles; 490 struct amdgpu_ctx_mgr ctx_mgr; 491 }; 492 493 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 494 495 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 496 unsigned size, 497 enum amdgpu_ib_pool_type pool, 498 struct amdgpu_ib *ib); 499 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 500 struct dma_fence *f); 501 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 502 struct amdgpu_ib *ibs, struct amdgpu_job *job, 503 struct dma_fence **f); 504 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 505 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 506 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 507 508 /* 509 * CS. 510 */ 511 struct amdgpu_cs_chunk { 512 uint32_t chunk_id; 513 uint32_t length_dw; 514 void *kdata; 515 }; 516 517 struct amdgpu_cs_post_dep { 518 struct drm_syncobj *syncobj; 519 struct dma_fence_chain *chain; 520 u64 point; 521 }; 522 523 struct amdgpu_cs_parser { 524 struct amdgpu_device *adev; 525 struct drm_file *filp; 526 struct amdgpu_ctx *ctx; 527 528 /* chunks */ 529 unsigned nchunks; 530 struct amdgpu_cs_chunk *chunks; 531 532 /* scheduler job object */ 533 struct amdgpu_job *job; 534 struct drm_sched_entity *entity; 535 536 /* buffer objects */ 537 struct ww_acquire_ctx ticket; 538 struct amdgpu_bo_list *bo_list; 539 struct amdgpu_mn *mn; 540 struct amdgpu_bo_list_entry vm_pd; 541 struct list_head validated; 542 struct dma_fence *fence; 543 uint64_t bytes_moved_threshold; 544 uint64_t bytes_moved_vis_threshold; 545 uint64_t bytes_moved; 546 uint64_t bytes_moved_vis; 547 548 /* user fence */ 549 struct amdgpu_bo_list_entry uf_entry; 550 551 unsigned num_post_deps; 552 struct amdgpu_cs_post_dep *post_deps; 553 }; 554 555 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 556 uint32_t ib_idx, int idx) 557 { 558 return p->job->ibs[ib_idx].ptr[idx]; 559 } 560 561 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 562 uint32_t ib_idx, int idx, 563 uint32_t value) 564 { 565 p->job->ibs[ib_idx].ptr[idx] = value; 566 } 567 568 /* 569 * Writeback 570 */ 571 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 572 573 struct amdgpu_wb { 574 struct amdgpu_bo *wb_obj; 575 volatile uint32_t *wb; 576 uint64_t gpu_addr; 577 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 578 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 579 }; 580 581 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 582 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 583 584 /* 585 * Benchmarking 586 */ 587 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 588 589 /* 590 * ASIC specific register table accessible by UMD 591 */ 592 struct amdgpu_allowed_register_entry { 593 uint32_t reg_offset; 594 bool grbm_indexed; 595 }; 596 597 enum amd_reset_method { 598 AMD_RESET_METHOD_NONE = -1, 599 AMD_RESET_METHOD_LEGACY = 0, 600 AMD_RESET_METHOD_MODE0, 601 AMD_RESET_METHOD_MODE1, 602 AMD_RESET_METHOD_MODE2, 603 AMD_RESET_METHOD_BACO, 604 AMD_RESET_METHOD_PCI, 605 }; 606 607 struct amdgpu_video_codec_info { 608 u32 codec_type; 609 u32 max_width; 610 u32 max_height; 611 u32 max_pixels_per_frame; 612 u32 max_level; 613 }; 614 615 #define codec_info_build(type, width, height, level) \ 616 .codec_type = type,\ 617 .max_width = width,\ 618 .max_height = height,\ 619 .max_pixels_per_frame = height * width,\ 620 .max_level = level, 621 622 struct amdgpu_video_codecs { 623 const u32 codec_count; 624 const struct amdgpu_video_codec_info *codec_array; 625 }; 626 627 /* 628 * ASIC specific functions. 629 */ 630 struct amdgpu_asic_funcs { 631 bool (*read_disabled_bios)(struct amdgpu_device *adev); 632 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 633 u8 *bios, u32 length_bytes); 634 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 635 u32 sh_num, u32 reg_offset, u32 *value); 636 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 637 int (*reset)(struct amdgpu_device *adev); 638 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 639 /* get the reference clock */ 640 u32 (*get_xclk)(struct amdgpu_device *adev); 641 /* MM block clocks */ 642 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 643 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 644 /* static power management */ 645 int (*get_pcie_lanes)(struct amdgpu_device *adev); 646 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 647 /* get config memsize register */ 648 u32 (*get_config_memsize)(struct amdgpu_device *adev); 649 /* flush hdp write queue */ 650 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 651 /* invalidate hdp read cache */ 652 void (*invalidate_hdp)(struct amdgpu_device *adev, 653 struct amdgpu_ring *ring); 654 /* check if the asic needs a full reset of if soft reset will work */ 655 bool (*need_full_reset)(struct amdgpu_device *adev); 656 /* initialize doorbell layout for specific asic*/ 657 void (*init_doorbell_index)(struct amdgpu_device *adev); 658 /* PCIe bandwidth usage */ 659 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 660 uint64_t *count1); 661 /* do we need to reset the asic at init time (e.g., kexec) */ 662 bool (*need_reset_on_init)(struct amdgpu_device *adev); 663 /* PCIe replay counter */ 664 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 665 /* device supports BACO */ 666 bool (*supports_baco)(struct amdgpu_device *adev); 667 /* pre asic_init quirks */ 668 void (*pre_asic_init)(struct amdgpu_device *adev); 669 /* enter/exit umd stable pstate */ 670 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 671 /* query video codecs */ 672 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 673 const struct amdgpu_video_codecs **codecs); 674 }; 675 676 /* 677 * IOCTL. 678 */ 679 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 680 struct drm_file *filp); 681 682 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 683 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 684 struct drm_file *filp); 685 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 686 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 687 struct drm_file *filp); 688 689 /* VRAM scratch page for HDP bug, default vram page */ 690 struct amdgpu_vram_scratch { 691 struct amdgpu_bo *robj; 692 volatile uint32_t *ptr; 693 u64 gpu_addr; 694 }; 695 696 /* 697 * CGS 698 */ 699 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 700 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 701 702 /* 703 * Core structure, functions and helpers. 704 */ 705 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 706 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 707 708 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 709 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 710 711 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 712 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 713 714 struct amdgpu_mmio_remap { 715 u32 reg_offset; 716 resource_size_t bus_addr; 717 }; 718 719 /* Define the HW IP blocks will be used in driver , add more if necessary */ 720 enum amd_hw_ip_block_type { 721 GC_HWIP = 1, 722 HDP_HWIP, 723 SDMA0_HWIP, 724 SDMA1_HWIP, 725 SDMA2_HWIP, 726 SDMA3_HWIP, 727 SDMA4_HWIP, 728 SDMA5_HWIP, 729 SDMA6_HWIP, 730 SDMA7_HWIP, 731 MMHUB_HWIP, 732 ATHUB_HWIP, 733 NBIO_HWIP, 734 MP0_HWIP, 735 MP1_HWIP, 736 UVD_HWIP, 737 VCN_HWIP = UVD_HWIP, 738 JPEG_HWIP = VCN_HWIP, 739 VCN1_HWIP, 740 VCE_HWIP, 741 DF_HWIP, 742 DCE_HWIP, 743 OSSSYS_HWIP, 744 SMUIO_HWIP, 745 PWR_HWIP, 746 NBIF_HWIP, 747 THM_HWIP, 748 CLK_HWIP, 749 UMC_HWIP, 750 RSMU_HWIP, 751 XGMI_HWIP, 752 DCI_HWIP, 753 MAX_HWIP 754 }; 755 756 #define HWIP_MAX_INSTANCE 10 757 758 #define HW_ID_MAX 300 759 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 760 761 struct amd_powerplay { 762 void *pp_handle; 763 const struct amd_pm_funcs *pp_funcs; 764 }; 765 766 struct ip_discovery_top; 767 768 /* polaris10 kickers */ 769 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 770 ((rid == 0xE3) || \ 771 (rid == 0xE4) || \ 772 (rid == 0xE5) || \ 773 (rid == 0xE7) || \ 774 (rid == 0xEF))) || \ 775 ((did == 0x6FDF) && \ 776 ((rid == 0xE7) || \ 777 (rid == 0xEF) || \ 778 (rid == 0xFF)))) 779 780 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 781 ((rid == 0xE1) || \ 782 (rid == 0xF7))) 783 784 /* polaris11 kickers */ 785 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 786 ((rid == 0xE0) || \ 787 (rid == 0xE5))) || \ 788 ((did == 0x67FF) && \ 789 ((rid == 0xCF) || \ 790 (rid == 0xEF) || \ 791 (rid == 0xFF)))) 792 793 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 794 ((rid == 0xE2))) 795 796 /* polaris12 kickers */ 797 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 798 ((rid == 0xC0) || \ 799 (rid == 0xC1) || \ 800 (rid == 0xC3) || \ 801 (rid == 0xC7))) || \ 802 ((did == 0x6981) && \ 803 ((rid == 0x00) || \ 804 (rid == 0x01) || \ 805 (rid == 0x10)))) 806 807 #define AMDGPU_RESET_MAGIC_NUM 64 808 #define AMDGPU_MAX_DF_PERFMONS 4 809 #define AMDGPU_PRODUCT_NAME_LEN 64 810 struct amdgpu_device { 811 struct device *dev; 812 struct pci_dev *pdev; 813 struct drm_device ddev; 814 815 #ifdef CONFIG_DRM_AMD_ACP 816 struct amdgpu_acp acp; 817 #endif 818 struct amdgpu_hive_info *hive; 819 /* ASIC */ 820 enum amd_asic_type asic_type; 821 uint32_t family; 822 uint32_t rev_id; 823 uint32_t external_rev_id; 824 unsigned long flags; 825 unsigned long apu_flags; 826 int usec_timeout; 827 const struct amdgpu_asic_funcs *asic_funcs; 828 bool shutdown; 829 bool need_swiotlb; 830 bool accel_working; 831 struct notifier_block acpi_nb; 832 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 833 struct debugfs_blob_wrapper debugfs_vbios_blob; 834 struct debugfs_blob_wrapper debugfs_discovery_blob; 835 struct mutex srbm_mutex; 836 /* GRBM index mutex. Protects concurrent access to GRBM index */ 837 struct mutex grbm_idx_mutex; 838 struct dev_pm_domain vga_pm_domain; 839 bool have_disp_power_ref; 840 bool have_atomics_support; 841 842 /* BIOS */ 843 bool is_atom_fw; 844 uint8_t *bios; 845 uint32_t bios_size; 846 uint32_t bios_scratch_reg_offset; 847 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 848 849 /* Register/doorbell mmio */ 850 resource_size_t rmmio_base; 851 resource_size_t rmmio_size; 852 void __iomem *rmmio; 853 /* protects concurrent MM_INDEX/DATA based register access */ 854 spinlock_t mmio_idx_lock; 855 struct amdgpu_mmio_remap rmmio_remap; 856 /* protects concurrent SMC based register access */ 857 spinlock_t smc_idx_lock; 858 amdgpu_rreg_t smc_rreg; 859 amdgpu_wreg_t smc_wreg; 860 /* protects concurrent PCIE register access */ 861 spinlock_t pcie_idx_lock; 862 amdgpu_rreg_t pcie_rreg; 863 amdgpu_wreg_t pcie_wreg; 864 amdgpu_rreg_t pciep_rreg; 865 amdgpu_wreg_t pciep_wreg; 866 amdgpu_rreg64_t pcie_rreg64; 867 amdgpu_wreg64_t pcie_wreg64; 868 /* protects concurrent UVD register access */ 869 spinlock_t uvd_ctx_idx_lock; 870 amdgpu_rreg_t uvd_ctx_rreg; 871 amdgpu_wreg_t uvd_ctx_wreg; 872 /* protects concurrent DIDT register access */ 873 spinlock_t didt_idx_lock; 874 amdgpu_rreg_t didt_rreg; 875 amdgpu_wreg_t didt_wreg; 876 /* protects concurrent gc_cac register access */ 877 spinlock_t gc_cac_idx_lock; 878 amdgpu_rreg_t gc_cac_rreg; 879 amdgpu_wreg_t gc_cac_wreg; 880 /* protects concurrent se_cac register access */ 881 spinlock_t se_cac_idx_lock; 882 amdgpu_rreg_t se_cac_rreg; 883 amdgpu_wreg_t se_cac_wreg; 884 /* protects concurrent ENDPOINT (audio) register access */ 885 spinlock_t audio_endpt_idx_lock; 886 amdgpu_block_rreg_t audio_endpt_rreg; 887 amdgpu_block_wreg_t audio_endpt_wreg; 888 struct amdgpu_doorbell doorbell; 889 890 /* clock/pll info */ 891 struct amdgpu_clock clock; 892 893 /* MC */ 894 struct amdgpu_gmc gmc; 895 struct amdgpu_gart gart; 896 dma_addr_t dummy_page_addr; 897 struct amdgpu_vm_manager vm_manager; 898 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 899 unsigned num_vmhubs; 900 901 /* memory management */ 902 struct amdgpu_mman mman; 903 struct amdgpu_vram_scratch vram_scratch; 904 struct amdgpu_wb wb; 905 atomic64_t num_bytes_moved; 906 atomic64_t num_evictions; 907 atomic64_t num_vram_cpu_page_faults; 908 atomic_t gpu_reset_counter; 909 atomic_t vram_lost_counter; 910 911 /* data for buffer migration throttling */ 912 struct { 913 spinlock_t lock; 914 s64 last_update_us; 915 s64 accum_us; /* accumulated microseconds */ 916 s64 accum_us_vis; /* for visible VRAM */ 917 u32 log2_max_MBps; 918 } mm_stats; 919 920 /* display */ 921 bool enable_virtual_display; 922 struct amdgpu_vkms_output *amdgpu_vkms_output; 923 struct amdgpu_mode_info mode_info; 924 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 925 struct work_struct hotplug_work; 926 struct amdgpu_irq_src crtc_irq; 927 struct amdgpu_irq_src vline0_irq; 928 struct amdgpu_irq_src vupdate_irq; 929 struct amdgpu_irq_src pageflip_irq; 930 struct amdgpu_irq_src hpd_irq; 931 struct amdgpu_irq_src dmub_trace_irq; 932 struct amdgpu_irq_src dmub_outbox_irq; 933 934 /* rings */ 935 u64 fence_context; 936 unsigned num_rings; 937 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 938 bool ib_pool_ready; 939 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 940 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 941 942 /* interrupts */ 943 struct amdgpu_irq irq; 944 945 /* powerplay */ 946 struct amd_powerplay powerplay; 947 struct amdgpu_pm pm; 948 u32 cg_flags; 949 u32 pg_flags; 950 951 /* nbio */ 952 struct amdgpu_nbio nbio; 953 954 /* hdp */ 955 struct amdgpu_hdp hdp; 956 957 /* smuio */ 958 struct amdgpu_smuio smuio; 959 960 /* mmhub */ 961 struct amdgpu_mmhub mmhub; 962 963 /* gfxhub */ 964 struct amdgpu_gfxhub gfxhub; 965 966 /* gfx */ 967 struct amdgpu_gfx gfx; 968 969 /* sdma */ 970 struct amdgpu_sdma sdma; 971 972 /* uvd */ 973 struct amdgpu_uvd uvd; 974 975 /* vce */ 976 struct amdgpu_vce vce; 977 978 /* vcn */ 979 struct amdgpu_vcn vcn; 980 981 /* jpeg */ 982 struct amdgpu_jpeg jpeg; 983 984 /* firmwares */ 985 struct amdgpu_firmware firmware; 986 987 /* PSP */ 988 struct psp_context psp; 989 990 /* GDS */ 991 struct amdgpu_gds gds; 992 993 /* KFD */ 994 struct amdgpu_kfd_dev kfd; 995 996 /* UMC */ 997 struct amdgpu_umc umc; 998 999 /* display related functionality */ 1000 struct amdgpu_display_manager dm; 1001 1002 /* mes */ 1003 bool enable_mes; 1004 struct amdgpu_mes mes; 1005 1006 /* df */ 1007 struct amdgpu_df df; 1008 1009 /* MCA */ 1010 struct amdgpu_mca mca; 1011 1012 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1013 uint32_t harvest_ip_mask; 1014 int num_ip_blocks; 1015 struct mutex mn_lock; 1016 DECLARE_HASHTABLE(mn_hash, 7); 1017 1018 /* tracking pinned memory */ 1019 atomic64_t vram_pin_size; 1020 atomic64_t visible_pin_size; 1021 atomic64_t gart_pin_size; 1022 1023 /* soc15 register offset based on ip, instance and segment */ 1024 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1025 1026 /* delayed work_func for deferring clockgating during resume */ 1027 struct delayed_work delayed_init_work; 1028 1029 struct amdgpu_virt virt; 1030 1031 /* link all shadow bo */ 1032 struct list_head shadow_list; 1033 struct mutex shadow_list_lock; 1034 1035 /* record hw reset is performed */ 1036 bool has_hw_reset; 1037 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1038 1039 /* s3/s4 mask */ 1040 bool in_suspend; 1041 bool in_s3; 1042 bool in_s4; 1043 bool in_s0ix; 1044 1045 atomic_t in_gpu_reset; 1046 enum pp_mp1_state mp1_state; 1047 struct rw_semaphore reset_sem; 1048 struct amdgpu_doorbell_index doorbell_index; 1049 1050 struct mutex notifier_lock; 1051 1052 int asic_reset_res; 1053 struct work_struct xgmi_reset_work; 1054 struct list_head reset_list; 1055 1056 long gfx_timeout; 1057 long sdma_timeout; 1058 long video_timeout; 1059 long compute_timeout; 1060 1061 uint64_t unique_id; 1062 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1063 1064 /* enable runtime pm on the device */ 1065 bool runpm; 1066 bool in_runpm; 1067 bool has_pr3; 1068 bool is_fw_fb; 1069 1070 bool pm_sysfs_en; 1071 bool ucode_sysfs_en; 1072 1073 /* Chip product information */ 1074 char product_number[16]; 1075 char product_name[AMDGPU_PRODUCT_NAME_LEN]; 1076 char serial[20]; 1077 1078 atomic_t throttling_logging_enabled; 1079 struct ratelimit_state throttling_logging_rs; 1080 uint32_t ras_hw_enabled; 1081 uint32_t ras_enabled; 1082 1083 bool no_hw_access; 1084 struct pci_saved_state *pci_state; 1085 pci_channel_state_t pci_channel_state; 1086 1087 struct amdgpu_reset_control *reset_cntl; 1088 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1089 1090 bool ram_is_direct_mapped; 1091 1092 struct list_head ras_list; 1093 1094 struct ip_discovery_top *ip_top; 1095 1096 struct mutex benchmark_mutex; 1097 }; 1098 1099 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1100 { 1101 return container_of(ddev, struct amdgpu_device, ddev); 1102 } 1103 1104 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1105 { 1106 return &adev->ddev; 1107 } 1108 1109 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1110 { 1111 return container_of(bdev, struct amdgpu_device, mman.bdev); 1112 } 1113 1114 int amdgpu_device_init(struct amdgpu_device *adev, 1115 uint32_t flags); 1116 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1117 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1118 1119 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1120 1121 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1122 void *buf, size_t size, bool write); 1123 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1124 void *buf, size_t size, bool write); 1125 1126 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1127 void *buf, size_t size, bool write); 1128 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1129 uint32_t reg, uint32_t acc_flags); 1130 void amdgpu_device_wreg(struct amdgpu_device *adev, 1131 uint32_t reg, uint32_t v, 1132 uint32_t acc_flags); 1133 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1134 uint32_t reg, uint32_t v); 1135 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1136 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1137 1138 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1139 u32 pcie_index, u32 pcie_data, 1140 u32 reg_addr); 1141 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1142 u32 pcie_index, u32 pcie_data, 1143 u32 reg_addr); 1144 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1145 u32 pcie_index, u32 pcie_data, 1146 u32 reg_addr, u32 reg_data); 1147 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1148 u32 pcie_index, u32 pcie_data, 1149 u32 reg_addr, u64 reg_data); 1150 1151 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1152 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1153 1154 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1155 struct amdgpu_reset_context *reset_context); 1156 1157 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1158 struct amdgpu_reset_context *reset_context); 1159 1160 int emu_soc_asic_init(struct amdgpu_device *adev); 1161 1162 /* 1163 * Registers read & write functions. 1164 */ 1165 #define AMDGPU_REGS_NO_KIQ (1<<1) 1166 #define AMDGPU_REGS_RLC (1<<2) 1167 1168 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1169 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1170 1171 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1172 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1173 1174 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1175 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1176 1177 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1178 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1179 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1180 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1181 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1182 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1183 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1184 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1185 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1186 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1187 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1188 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1189 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1190 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1191 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1192 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1193 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1194 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1195 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1196 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1197 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1198 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1199 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1200 #define WREG32_P(reg, val, mask) \ 1201 do { \ 1202 uint32_t tmp_ = RREG32(reg); \ 1203 tmp_ &= (mask); \ 1204 tmp_ |= ((val) & ~(mask)); \ 1205 WREG32(reg, tmp_); \ 1206 } while (0) 1207 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1208 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1209 #define WREG32_PLL_P(reg, val, mask) \ 1210 do { \ 1211 uint32_t tmp_ = RREG32_PLL(reg); \ 1212 tmp_ &= (mask); \ 1213 tmp_ |= ((val) & ~(mask)); \ 1214 WREG32_PLL(reg, tmp_); \ 1215 } while (0) 1216 1217 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1218 do { \ 1219 u32 tmp = RREG32_SMC(_Reg); \ 1220 tmp &= (_Mask); \ 1221 tmp |= ((_Val) & ~(_Mask)); \ 1222 WREG32_SMC(_Reg, tmp); \ 1223 } while (0) 1224 1225 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1226 1227 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1228 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1229 1230 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1231 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1232 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1233 1234 #define REG_GET_FIELD(value, reg, field) \ 1235 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1236 1237 #define WREG32_FIELD(reg, field, val) \ 1238 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1239 1240 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1241 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1242 1243 /* 1244 * BIOS helpers. 1245 */ 1246 #define RBIOS8(i) (adev->bios[i]) 1247 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1248 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1249 1250 /* 1251 * ASICs macro. 1252 */ 1253 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1254 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1255 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1256 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1257 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1258 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1259 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1260 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1261 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1262 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1263 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1264 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1265 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1266 #define amdgpu_asic_flush_hdp(adev, r) \ 1267 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1268 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1269 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r))) 1270 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1271 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1272 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1273 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1274 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1275 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1276 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1277 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1278 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1279 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1280 1281 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1282 1283 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 1284 1285 /* Common functions */ 1286 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1287 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1288 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1289 struct amdgpu_job* job); 1290 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1291 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1292 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1293 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1294 1295 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1296 u64 num_vis_bytes); 1297 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1298 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1299 const u32 *registers, 1300 const u32 array_size); 1301 1302 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1303 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1304 bool amdgpu_device_supports_px(struct drm_device *dev); 1305 bool amdgpu_device_supports_boco(struct drm_device *dev); 1306 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1307 bool amdgpu_device_supports_baco(struct drm_device *dev); 1308 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1309 struct amdgpu_device *peer_adev); 1310 int amdgpu_device_baco_enter(struct drm_device *dev); 1311 int amdgpu_device_baco_exit(struct drm_device *dev); 1312 1313 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1314 struct amdgpu_ring *ring); 1315 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1316 struct amdgpu_ring *ring); 1317 1318 void amdgpu_device_halt(struct amdgpu_device *adev); 1319 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1320 u32 reg); 1321 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1322 u32 reg, u32 v); 1323 1324 /* atpx handler */ 1325 #if defined(CONFIG_VGA_SWITCHEROO) 1326 void amdgpu_register_atpx_handler(void); 1327 void amdgpu_unregister_atpx_handler(void); 1328 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1329 bool amdgpu_is_atpx_hybrid(void); 1330 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1331 bool amdgpu_has_atpx(void); 1332 #else 1333 static inline void amdgpu_register_atpx_handler(void) {} 1334 static inline void amdgpu_unregister_atpx_handler(void) {} 1335 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1336 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1337 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1338 static inline bool amdgpu_has_atpx(void) { return false; } 1339 #endif 1340 1341 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1342 void *amdgpu_atpx_get_dhandle(void); 1343 #else 1344 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1345 #endif 1346 1347 /* 1348 * KMS 1349 */ 1350 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1351 extern const int amdgpu_max_kms_ioctl; 1352 1353 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1354 void amdgpu_driver_unload_kms(struct drm_device *dev); 1355 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1356 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1357 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1358 struct drm_file *file_priv); 1359 void amdgpu_driver_release_kms(struct drm_device *dev); 1360 1361 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1362 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1363 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1364 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1365 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1366 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1367 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1368 struct drm_file *filp); 1369 1370 /* 1371 * functions used by amdgpu_encoder.c 1372 */ 1373 struct amdgpu_afmt_acr { 1374 u32 clock; 1375 1376 int n_32khz; 1377 int cts_32khz; 1378 1379 int n_44_1khz; 1380 int cts_44_1khz; 1381 1382 int n_48khz; 1383 int cts_48khz; 1384 1385 }; 1386 1387 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1388 1389 /* amdgpu_acpi.c */ 1390 1391 /* ATCS Device/Driver State */ 1392 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1393 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1394 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1395 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1396 1397 #if defined(CONFIG_ACPI) 1398 int amdgpu_acpi_init(struct amdgpu_device *adev); 1399 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1400 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1401 bool amdgpu_acpi_is_power_shift_control_supported(void); 1402 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1403 u8 perf_req, bool advertise); 1404 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1405 u8 dev_state, bool drv_state); 1406 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1407 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1408 1409 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1410 void amdgpu_acpi_detect(void); 1411 #else 1412 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1413 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1414 static inline void amdgpu_acpi_detect(void) { } 1415 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1416 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1417 u8 dev_state, bool drv_state) { return 0; } 1418 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1419 enum amdgpu_ss ss_state) { return 0; } 1420 #endif 1421 1422 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1423 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1424 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1425 #else 1426 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1427 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1428 #endif 1429 1430 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1431 uint64_t addr, struct amdgpu_bo **bo, 1432 struct amdgpu_bo_va_mapping **mapping); 1433 1434 #if defined(CONFIG_DRM_AMD_DC) 1435 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1436 #else 1437 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1438 #endif 1439 1440 1441 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1442 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1443 1444 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1445 pci_channel_state_t state); 1446 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1447 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1448 void amdgpu_pci_resume(struct pci_dev *pdev); 1449 1450 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1451 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1452 1453 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1454 1455 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1456 enum amd_clockgating_state state); 1457 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1458 enum amd_powergating_state state); 1459 1460 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1461 { 1462 return amdgpu_gpu_recovery != 0 && 1463 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1464 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1465 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1466 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1467 } 1468 1469 #include "amdgpu_object.h" 1470 1471 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1472 { 1473 return adev->gmc.tmz_enabled; 1474 } 1475 1476 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1477 { 1478 return atomic_read(&adev->in_gpu_reset); 1479 } 1480 #endif 1481