1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 53 #include <drm/ttm/ttm_bo_api.h> 54 #include <drm/ttm/ttm_bo_driver.h> 55 #include <drm/ttm/ttm_placement.h> 56 #include <drm/ttm/ttm_module.h> 57 #include <drm/ttm/ttm_execbuf_util.h> 58 59 #include <drm/amdgpu_drm.h> 60 #include <drm/drm_gem.h> 61 #include <drm/drm_ioctl.h> 62 #include <drm/gpu_scheduler.h> 63 64 #include <kgd_kfd_interface.h> 65 #include "dm_pp_interface.h" 66 #include "kgd_pp_interface.h" 67 68 #include "amd_shared.h" 69 #include "amdgpu_mode.h" 70 #include "amdgpu_ih.h" 71 #include "amdgpu_irq.h" 72 #include "amdgpu_ucode.h" 73 #include "amdgpu_ttm.h" 74 #include "amdgpu_psp.h" 75 #include "amdgpu_gds.h" 76 #include "amdgpu_sync.h" 77 #include "amdgpu_ring.h" 78 #include "amdgpu_vm.h" 79 #include "amdgpu_dpm.h" 80 #include "amdgpu_acp.h" 81 #include "amdgpu_uvd.h" 82 #include "amdgpu_vce.h" 83 #include "amdgpu_vcn.h" 84 #include "amdgpu_jpeg.h" 85 #include "amdgpu_mn.h" 86 #include "amdgpu_gmc.h" 87 #include "amdgpu_gfx.h" 88 #include "amdgpu_sdma.h" 89 #include "amdgpu_nbio.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_gart.h" 94 #include "amdgpu_debugfs.h" 95 #include "amdgpu_job.h" 96 #include "amdgpu_bo_list.h" 97 #include "amdgpu_gem.h" 98 #include "amdgpu_doorbell.h" 99 #include "amdgpu_amdkfd.h" 100 #include "amdgpu_smu.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_df.h" 106 107 #define MAX_GPU_INSTANCE 16 108 109 struct amdgpu_gpu_instance 110 { 111 struct amdgpu_device *adev; 112 int mgpu_fan_enabled; 113 }; 114 115 struct amdgpu_mgpu_info 116 { 117 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 118 struct mutex mutex; 119 uint32_t num_gpu; 120 uint32_t num_dgpu; 121 uint32_t num_apu; 122 }; 123 124 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 125 126 /* 127 * Modules parameters. 128 */ 129 extern int amdgpu_modeset; 130 extern int amdgpu_vram_limit; 131 extern int amdgpu_vis_vram_limit; 132 extern int amdgpu_gart_size; 133 extern int amdgpu_gtt_size; 134 extern int amdgpu_moverate; 135 extern int amdgpu_benchmarking; 136 extern int amdgpu_testing; 137 extern int amdgpu_audio; 138 extern int amdgpu_disp_priority; 139 extern int amdgpu_hw_i2c; 140 extern int amdgpu_pcie_gen2; 141 extern int amdgpu_msi; 142 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 143 extern int amdgpu_dpm; 144 extern int amdgpu_fw_load_type; 145 extern int amdgpu_aspm; 146 extern int amdgpu_runtime_pm; 147 extern uint amdgpu_ip_block_mask; 148 extern int amdgpu_bapm; 149 extern int amdgpu_deep_color; 150 extern int amdgpu_vm_size; 151 extern int amdgpu_vm_block_size; 152 extern int amdgpu_vm_fragment_size; 153 extern int amdgpu_vm_fault_stop; 154 extern int amdgpu_vm_debug; 155 extern int amdgpu_vm_update_mode; 156 extern int amdgpu_exp_hw_support; 157 extern int amdgpu_dc; 158 extern int amdgpu_sched_jobs; 159 extern int amdgpu_sched_hw_submission; 160 extern uint amdgpu_pcie_gen_cap; 161 extern uint amdgpu_pcie_lane_cap; 162 extern uint amdgpu_cg_mask; 163 extern uint amdgpu_pg_mask; 164 extern uint amdgpu_sdma_phase_quantum; 165 extern char *amdgpu_disable_cu; 166 extern char *amdgpu_virtual_display; 167 extern uint amdgpu_pp_feature_mask; 168 extern uint amdgpu_force_long_training; 169 extern int amdgpu_job_hang_limit; 170 extern int amdgpu_lbpw; 171 extern int amdgpu_compute_multipipe; 172 extern int amdgpu_gpu_recovery; 173 extern int amdgpu_emu_mode; 174 extern uint amdgpu_smu_memory_pool_size; 175 extern uint amdgpu_dc_feature_mask; 176 extern uint amdgpu_dc_debug_mask; 177 extern uint amdgpu_dm_abm_level; 178 extern struct amdgpu_mgpu_info mgpu_info; 179 extern int amdgpu_ras_enable; 180 extern uint amdgpu_ras_mask; 181 extern int amdgpu_bad_page_threshold; 182 extern int amdgpu_async_gfx_ring; 183 extern int amdgpu_mcbp; 184 extern int amdgpu_discovery; 185 extern int amdgpu_mes; 186 extern int amdgpu_noretry; 187 extern int amdgpu_force_asic_type; 188 #ifdef CONFIG_HSA_AMD 189 extern int sched_policy; 190 extern bool debug_evictions; 191 extern bool no_system_mem_limit; 192 #else 193 static const int sched_policy = KFD_SCHED_POLICY_HWS; 194 static const bool debug_evictions; /* = false */ 195 static const bool no_system_mem_limit; 196 #endif 197 198 extern int amdgpu_tmz; 199 extern int amdgpu_reset_method; 200 201 #ifdef CONFIG_DRM_AMDGPU_SI 202 extern int amdgpu_si_support; 203 #endif 204 #ifdef CONFIG_DRM_AMDGPU_CIK 205 extern int amdgpu_cik_support; 206 #endif 207 extern int amdgpu_num_kcq; 208 209 #define AMDGPU_VM_MAX_NUM_CTX 4096 210 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 211 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 212 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 213 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 214 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 215 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 216 #define AMDGPUFB_CONN_LIMIT 4 217 #define AMDGPU_BIOS_NUM_SCRATCH 16 218 219 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 220 221 /* hard reset data */ 222 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 223 224 /* reset flags */ 225 #define AMDGPU_RESET_GFX (1 << 0) 226 #define AMDGPU_RESET_COMPUTE (1 << 1) 227 #define AMDGPU_RESET_DMA (1 << 2) 228 #define AMDGPU_RESET_CP (1 << 3) 229 #define AMDGPU_RESET_GRBM (1 << 4) 230 #define AMDGPU_RESET_DMA1 (1 << 5) 231 #define AMDGPU_RESET_RLC (1 << 6) 232 #define AMDGPU_RESET_SEM (1 << 7) 233 #define AMDGPU_RESET_IH (1 << 8) 234 #define AMDGPU_RESET_VMC (1 << 9) 235 #define AMDGPU_RESET_MC (1 << 10) 236 #define AMDGPU_RESET_DISPLAY (1 << 11) 237 #define AMDGPU_RESET_UVD (1 << 12) 238 #define AMDGPU_RESET_VCE (1 << 13) 239 #define AMDGPU_RESET_VCE1 (1 << 14) 240 241 /* max cursor sizes (in pixels) */ 242 #define CIK_CURSOR_WIDTH 128 243 #define CIK_CURSOR_HEIGHT 128 244 245 struct amdgpu_device; 246 struct amdgpu_ib; 247 struct amdgpu_cs_parser; 248 struct amdgpu_job; 249 struct amdgpu_irq_src; 250 struct amdgpu_fpriv; 251 struct amdgpu_bo_va_mapping; 252 struct amdgpu_atif; 253 struct kfd_vm_fault_info; 254 struct amdgpu_hive_info; 255 256 enum amdgpu_cp_irq { 257 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 258 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 259 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 260 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 261 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 262 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 263 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 264 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 265 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 266 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 267 268 AMDGPU_CP_IRQ_LAST 269 }; 270 271 enum amdgpu_thermal_irq { 272 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 273 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 274 275 AMDGPU_THERMAL_IRQ_LAST 276 }; 277 278 enum amdgpu_kiq_irq { 279 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 280 AMDGPU_CP_KIQ_IRQ_LAST 281 }; 282 283 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 284 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 285 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 286 287 int amdgpu_device_ip_set_clockgating_state(void *dev, 288 enum amd_ip_block_type block_type, 289 enum amd_clockgating_state state); 290 int amdgpu_device_ip_set_powergating_state(void *dev, 291 enum amd_ip_block_type block_type, 292 enum amd_powergating_state state); 293 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 294 u32 *flags); 295 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 296 enum amd_ip_block_type block_type); 297 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 298 enum amd_ip_block_type block_type); 299 300 #define AMDGPU_MAX_IP_NUM 16 301 302 struct amdgpu_ip_block_status { 303 bool valid; 304 bool sw; 305 bool hw; 306 bool late_initialized; 307 bool hang; 308 }; 309 310 struct amdgpu_ip_block_version { 311 const enum amd_ip_block_type type; 312 const u32 major; 313 const u32 minor; 314 const u32 rev; 315 const struct amd_ip_funcs *funcs; 316 }; 317 318 #define HW_REV(_Major, _Minor, _Rev) \ 319 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 320 321 struct amdgpu_ip_block { 322 struct amdgpu_ip_block_status status; 323 const struct amdgpu_ip_block_version *version; 324 }; 325 326 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 327 enum amd_ip_block_type type, 328 u32 major, u32 minor); 329 330 struct amdgpu_ip_block * 331 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 332 enum amd_ip_block_type type); 333 334 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 335 const struct amdgpu_ip_block_version *ip_block_version); 336 337 /* 338 * BIOS. 339 */ 340 bool amdgpu_get_bios(struct amdgpu_device *adev); 341 bool amdgpu_read_bios(struct amdgpu_device *adev); 342 343 /* 344 * Clocks 345 */ 346 347 #define AMDGPU_MAX_PPLL 3 348 349 struct amdgpu_clock { 350 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 351 struct amdgpu_pll spll; 352 struct amdgpu_pll mpll; 353 /* 10 Khz units */ 354 uint32_t default_mclk; 355 uint32_t default_sclk; 356 uint32_t default_dispclk; 357 uint32_t current_dispclk; 358 uint32_t dp_extclk; 359 uint32_t max_pixel_clock; 360 }; 361 362 /* sub-allocation manager, it has to be protected by another lock. 363 * By conception this is an helper for other part of the driver 364 * like the indirect buffer or semaphore, which both have their 365 * locking. 366 * 367 * Principe is simple, we keep a list of sub allocation in offset 368 * order (first entry has offset == 0, last entry has the highest 369 * offset). 370 * 371 * When allocating new object we first check if there is room at 372 * the end total_size - (last_object_offset + last_object_size) >= 373 * alloc_size. If so we allocate new object there. 374 * 375 * When there is not enough room at the end, we start waiting for 376 * each sub object until we reach object_offset+object_size >= 377 * alloc_size, this object then become the sub object we return. 378 * 379 * Alignment can't be bigger than page size. 380 * 381 * Hole are not considered for allocation to keep things simple. 382 * Assumption is that there won't be hole (all object on same 383 * alignment). 384 */ 385 386 #define AMDGPU_SA_NUM_FENCE_LISTS 32 387 388 struct amdgpu_sa_manager { 389 wait_queue_head_t wq; 390 struct amdgpu_bo *bo; 391 struct list_head *hole; 392 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 393 struct list_head olist; 394 unsigned size; 395 uint64_t gpu_addr; 396 void *cpu_ptr; 397 uint32_t domain; 398 uint32_t align; 399 }; 400 401 /* sub-allocation buffer */ 402 struct amdgpu_sa_bo { 403 struct list_head olist; 404 struct list_head flist; 405 struct amdgpu_sa_manager *manager; 406 unsigned soffset; 407 unsigned eoffset; 408 struct dma_fence *fence; 409 }; 410 411 int amdgpu_fence_slab_init(void); 412 void amdgpu_fence_slab_fini(void); 413 414 /* 415 * IRQS. 416 */ 417 418 struct amdgpu_flip_work { 419 struct delayed_work flip_work; 420 struct work_struct unpin_work; 421 struct amdgpu_device *adev; 422 int crtc_id; 423 u32 target_vblank; 424 uint64_t base; 425 struct drm_pending_vblank_event *event; 426 struct amdgpu_bo *old_abo; 427 struct dma_fence *excl; 428 unsigned shared_count; 429 struct dma_fence **shared; 430 struct dma_fence_cb cb; 431 bool async; 432 }; 433 434 435 /* 436 * CP & rings. 437 */ 438 439 struct amdgpu_ib { 440 struct amdgpu_sa_bo *sa_bo; 441 uint32_t length_dw; 442 uint64_t gpu_addr; 443 uint32_t *ptr; 444 uint32_t flags; 445 }; 446 447 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 448 449 /* 450 * file private structure 451 */ 452 453 struct amdgpu_fpriv { 454 struct amdgpu_vm vm; 455 struct amdgpu_bo_va *prt_va; 456 struct amdgpu_bo_va *csa_va; 457 struct mutex bo_list_lock; 458 struct idr bo_list_handles; 459 struct amdgpu_ctx_mgr ctx_mgr; 460 }; 461 462 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 463 464 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 465 unsigned size, 466 enum amdgpu_ib_pool_type pool, 467 struct amdgpu_ib *ib); 468 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 469 struct dma_fence *f); 470 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 471 struct amdgpu_ib *ibs, struct amdgpu_job *job, 472 struct dma_fence **f); 473 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 474 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 475 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 476 477 /* 478 * CS. 479 */ 480 struct amdgpu_cs_chunk { 481 uint32_t chunk_id; 482 uint32_t length_dw; 483 void *kdata; 484 }; 485 486 struct amdgpu_cs_post_dep { 487 struct drm_syncobj *syncobj; 488 struct dma_fence_chain *chain; 489 u64 point; 490 }; 491 492 struct amdgpu_cs_parser { 493 struct amdgpu_device *adev; 494 struct drm_file *filp; 495 struct amdgpu_ctx *ctx; 496 497 /* chunks */ 498 unsigned nchunks; 499 struct amdgpu_cs_chunk *chunks; 500 501 /* scheduler job object */ 502 struct amdgpu_job *job; 503 struct drm_sched_entity *entity; 504 505 /* buffer objects */ 506 struct ww_acquire_ctx ticket; 507 struct amdgpu_bo_list *bo_list; 508 struct amdgpu_mn *mn; 509 struct amdgpu_bo_list_entry vm_pd; 510 struct list_head validated; 511 struct dma_fence *fence; 512 uint64_t bytes_moved_threshold; 513 uint64_t bytes_moved_vis_threshold; 514 uint64_t bytes_moved; 515 uint64_t bytes_moved_vis; 516 517 /* user fence */ 518 struct amdgpu_bo_list_entry uf_entry; 519 520 unsigned num_post_deps; 521 struct amdgpu_cs_post_dep *post_deps; 522 }; 523 524 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 525 uint32_t ib_idx, int idx) 526 { 527 return p->job->ibs[ib_idx].ptr[idx]; 528 } 529 530 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 531 uint32_t ib_idx, int idx, 532 uint32_t value) 533 { 534 p->job->ibs[ib_idx].ptr[idx] = value; 535 } 536 537 /* 538 * Writeback 539 */ 540 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 541 542 struct amdgpu_wb { 543 struct amdgpu_bo *wb_obj; 544 volatile uint32_t *wb; 545 uint64_t gpu_addr; 546 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 547 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 548 }; 549 550 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 551 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 552 553 /* 554 * Benchmarking 555 */ 556 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 557 558 559 /* 560 * Testing 561 */ 562 void amdgpu_test_moves(struct amdgpu_device *adev); 563 564 /* 565 * ASIC specific register table accessible by UMD 566 */ 567 struct amdgpu_allowed_register_entry { 568 uint32_t reg_offset; 569 bool grbm_indexed; 570 }; 571 572 enum amd_reset_method { 573 AMD_RESET_METHOD_LEGACY = 0, 574 AMD_RESET_METHOD_MODE0, 575 AMD_RESET_METHOD_MODE1, 576 AMD_RESET_METHOD_MODE2, 577 AMD_RESET_METHOD_BACO 578 }; 579 580 /* 581 * ASIC specific functions. 582 */ 583 struct amdgpu_asic_funcs { 584 bool (*read_disabled_bios)(struct amdgpu_device *adev); 585 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 586 u8 *bios, u32 length_bytes); 587 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 588 u32 sh_num, u32 reg_offset, u32 *value); 589 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 590 int (*reset)(struct amdgpu_device *adev); 591 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 592 /* get the reference clock */ 593 u32 (*get_xclk)(struct amdgpu_device *adev); 594 /* MM block clocks */ 595 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 596 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 597 /* static power management */ 598 int (*get_pcie_lanes)(struct amdgpu_device *adev); 599 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 600 /* get config memsize register */ 601 u32 (*get_config_memsize)(struct amdgpu_device *adev); 602 /* flush hdp write queue */ 603 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 604 /* invalidate hdp read cache */ 605 void (*invalidate_hdp)(struct amdgpu_device *adev, 606 struct amdgpu_ring *ring); 607 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev); 608 /* check if the asic needs a full reset of if soft reset will work */ 609 bool (*need_full_reset)(struct amdgpu_device *adev); 610 /* initialize doorbell layout for specific asic*/ 611 void (*init_doorbell_index)(struct amdgpu_device *adev); 612 /* PCIe bandwidth usage */ 613 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 614 uint64_t *count1); 615 /* do we need to reset the asic at init time (e.g., kexec) */ 616 bool (*need_reset_on_init)(struct amdgpu_device *adev); 617 /* PCIe replay counter */ 618 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 619 /* device supports BACO */ 620 bool (*supports_baco)(struct amdgpu_device *adev); 621 /* pre asic_init quirks */ 622 void (*pre_asic_init)(struct amdgpu_device *adev); 623 }; 624 625 /* 626 * IOCTL. 627 */ 628 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 629 struct drm_file *filp); 630 631 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 632 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 633 struct drm_file *filp); 634 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 635 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 636 struct drm_file *filp); 637 638 /* VRAM scratch page for HDP bug, default vram page */ 639 struct amdgpu_vram_scratch { 640 struct amdgpu_bo *robj; 641 volatile uint32_t *ptr; 642 u64 gpu_addr; 643 }; 644 645 /* 646 * ACPI 647 */ 648 struct amdgpu_atcs_functions { 649 bool get_ext_state; 650 bool pcie_perf_req; 651 bool pcie_dev_rdy; 652 bool pcie_bus_width; 653 }; 654 655 struct amdgpu_atcs { 656 struct amdgpu_atcs_functions functions; 657 }; 658 659 /* 660 * CGS 661 */ 662 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 663 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 664 665 /* 666 * Core structure, functions and helpers. 667 */ 668 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 669 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 670 671 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 672 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 673 674 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 675 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 676 677 struct amdgpu_mmio_remap { 678 u32 reg_offset; 679 resource_size_t bus_addr; 680 }; 681 682 /* Define the HW IP blocks will be used in driver , add more if necessary */ 683 enum amd_hw_ip_block_type { 684 GC_HWIP = 1, 685 HDP_HWIP, 686 SDMA0_HWIP, 687 SDMA1_HWIP, 688 SDMA2_HWIP, 689 SDMA3_HWIP, 690 SDMA4_HWIP, 691 SDMA5_HWIP, 692 SDMA6_HWIP, 693 SDMA7_HWIP, 694 MMHUB_HWIP, 695 ATHUB_HWIP, 696 NBIO_HWIP, 697 MP0_HWIP, 698 MP1_HWIP, 699 UVD_HWIP, 700 VCN_HWIP = UVD_HWIP, 701 JPEG_HWIP = VCN_HWIP, 702 VCE_HWIP, 703 DF_HWIP, 704 DCE_HWIP, 705 OSSSYS_HWIP, 706 SMUIO_HWIP, 707 PWR_HWIP, 708 NBIF_HWIP, 709 THM_HWIP, 710 CLK_HWIP, 711 UMC_HWIP, 712 RSMU_HWIP, 713 MAX_HWIP 714 }; 715 716 #define HWIP_MAX_INSTANCE 8 717 718 struct amd_powerplay { 719 void *pp_handle; 720 const struct amd_pm_funcs *pp_funcs; 721 }; 722 723 #define AMDGPU_RESET_MAGIC_NUM 64 724 #define AMDGPU_MAX_DF_PERFMONS 4 725 struct amdgpu_device { 726 struct device *dev; 727 struct pci_dev *pdev; 728 struct drm_device ddev; 729 730 #ifdef CONFIG_DRM_AMD_ACP 731 struct amdgpu_acp acp; 732 #endif 733 struct amdgpu_hive_info *hive; 734 /* ASIC */ 735 enum amd_asic_type asic_type; 736 uint32_t family; 737 uint32_t rev_id; 738 uint32_t external_rev_id; 739 unsigned long flags; 740 unsigned long apu_flags; 741 int usec_timeout; 742 const struct amdgpu_asic_funcs *asic_funcs; 743 bool shutdown; 744 bool need_swiotlb; 745 bool accel_working; 746 struct notifier_block acpi_nb; 747 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 748 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 749 unsigned debugfs_count; 750 #if defined(CONFIG_DEBUG_FS) 751 struct dentry *debugfs_preempt; 752 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 753 #endif 754 struct amdgpu_atif *atif; 755 struct amdgpu_atcs atcs; 756 struct mutex srbm_mutex; 757 /* GRBM index mutex. Protects concurrent access to GRBM index */ 758 struct mutex grbm_idx_mutex; 759 struct dev_pm_domain vga_pm_domain; 760 bool have_disp_power_ref; 761 bool have_atomics_support; 762 763 /* BIOS */ 764 bool is_atom_fw; 765 uint8_t *bios; 766 uint32_t bios_size; 767 uint32_t bios_scratch_reg_offset; 768 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 769 770 /* Register/doorbell mmio */ 771 resource_size_t rmmio_base; 772 resource_size_t rmmio_size; 773 void __iomem *rmmio; 774 /* protects concurrent MM_INDEX/DATA based register access */ 775 spinlock_t mmio_idx_lock; 776 struct amdgpu_mmio_remap rmmio_remap; 777 /* protects concurrent SMC based register access */ 778 spinlock_t smc_idx_lock; 779 amdgpu_rreg_t smc_rreg; 780 amdgpu_wreg_t smc_wreg; 781 /* protects concurrent PCIE register access */ 782 spinlock_t pcie_idx_lock; 783 amdgpu_rreg_t pcie_rreg; 784 amdgpu_wreg_t pcie_wreg; 785 amdgpu_rreg_t pciep_rreg; 786 amdgpu_wreg_t pciep_wreg; 787 amdgpu_rreg64_t pcie_rreg64; 788 amdgpu_wreg64_t pcie_wreg64; 789 /* protects concurrent UVD register access */ 790 spinlock_t uvd_ctx_idx_lock; 791 amdgpu_rreg_t uvd_ctx_rreg; 792 amdgpu_wreg_t uvd_ctx_wreg; 793 /* protects concurrent DIDT register access */ 794 spinlock_t didt_idx_lock; 795 amdgpu_rreg_t didt_rreg; 796 amdgpu_wreg_t didt_wreg; 797 /* protects concurrent gc_cac register access */ 798 spinlock_t gc_cac_idx_lock; 799 amdgpu_rreg_t gc_cac_rreg; 800 amdgpu_wreg_t gc_cac_wreg; 801 /* protects concurrent se_cac register access */ 802 spinlock_t se_cac_idx_lock; 803 amdgpu_rreg_t se_cac_rreg; 804 amdgpu_wreg_t se_cac_wreg; 805 /* protects concurrent ENDPOINT (audio) register access */ 806 spinlock_t audio_endpt_idx_lock; 807 amdgpu_block_rreg_t audio_endpt_rreg; 808 amdgpu_block_wreg_t audio_endpt_wreg; 809 void __iomem *rio_mem; 810 resource_size_t rio_mem_size; 811 struct amdgpu_doorbell doorbell; 812 813 /* clock/pll info */ 814 struct amdgpu_clock clock; 815 816 /* MC */ 817 struct amdgpu_gmc gmc; 818 struct amdgpu_gart gart; 819 dma_addr_t dummy_page_addr; 820 struct amdgpu_vm_manager vm_manager; 821 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 822 unsigned num_vmhubs; 823 824 /* memory management */ 825 struct amdgpu_mman mman; 826 struct amdgpu_vram_scratch vram_scratch; 827 struct amdgpu_wb wb; 828 atomic64_t num_bytes_moved; 829 atomic64_t num_evictions; 830 atomic64_t num_vram_cpu_page_faults; 831 atomic_t gpu_reset_counter; 832 atomic_t vram_lost_counter; 833 834 /* data for buffer migration throttling */ 835 struct { 836 spinlock_t lock; 837 s64 last_update_us; 838 s64 accum_us; /* accumulated microseconds */ 839 s64 accum_us_vis; /* for visible VRAM */ 840 u32 log2_max_MBps; 841 } mm_stats; 842 843 /* display */ 844 bool enable_virtual_display; 845 struct amdgpu_mode_info mode_info; 846 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 847 struct work_struct hotplug_work; 848 struct amdgpu_irq_src crtc_irq; 849 struct amdgpu_irq_src vupdate_irq; 850 struct amdgpu_irq_src pageflip_irq; 851 struct amdgpu_irq_src hpd_irq; 852 853 /* rings */ 854 u64 fence_context; 855 unsigned num_rings; 856 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 857 bool ib_pool_ready; 858 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 859 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 860 861 /* interrupts */ 862 struct amdgpu_irq irq; 863 864 /* powerplay */ 865 struct amd_powerplay powerplay; 866 bool pp_force_state_enabled; 867 868 /* smu */ 869 struct smu_context smu; 870 871 /* dpm */ 872 struct amdgpu_pm pm; 873 u32 cg_flags; 874 u32 pg_flags; 875 876 /* nbio */ 877 struct amdgpu_nbio nbio; 878 879 /* mmhub */ 880 struct amdgpu_mmhub mmhub; 881 882 /* gfx */ 883 struct amdgpu_gfx gfx; 884 885 /* sdma */ 886 struct amdgpu_sdma sdma; 887 888 /* uvd */ 889 struct amdgpu_uvd uvd; 890 891 /* vce */ 892 struct amdgpu_vce vce; 893 894 /* vcn */ 895 struct amdgpu_vcn vcn; 896 897 /* jpeg */ 898 struct amdgpu_jpeg jpeg; 899 900 /* firmwares */ 901 struct amdgpu_firmware firmware; 902 903 /* PSP */ 904 struct psp_context psp; 905 906 /* GDS */ 907 struct amdgpu_gds gds; 908 909 /* KFD */ 910 struct amdgpu_kfd_dev kfd; 911 912 /* UMC */ 913 struct amdgpu_umc umc; 914 915 /* display related functionality */ 916 struct amdgpu_display_manager dm; 917 918 /* mes */ 919 bool enable_mes; 920 struct amdgpu_mes mes; 921 922 /* df */ 923 struct amdgpu_df df; 924 925 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 926 int num_ip_blocks; 927 struct mutex mn_lock; 928 DECLARE_HASHTABLE(mn_hash, 7); 929 930 /* tracking pinned memory */ 931 atomic64_t vram_pin_size; 932 atomic64_t visible_pin_size; 933 atomic64_t gart_pin_size; 934 935 /* soc15 register offset based on ip, instance and segment */ 936 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 937 938 /* delayed work_func for deferring clockgating during resume */ 939 struct delayed_work delayed_init_work; 940 941 struct amdgpu_virt virt; 942 943 /* link all shadow bo */ 944 struct list_head shadow_list; 945 struct mutex shadow_list_lock; 946 947 /* record hw reset is performed */ 948 bool has_hw_reset; 949 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 950 951 /* s3/s4 mask */ 952 bool in_suspend; 953 bool in_hibernate; 954 955 atomic_t in_gpu_reset; 956 enum pp_mp1_state mp1_state; 957 struct rw_semaphore reset_sem; 958 struct amdgpu_doorbell_index doorbell_index; 959 960 struct mutex notifier_lock; 961 962 int asic_reset_res; 963 struct work_struct xgmi_reset_work; 964 965 long gfx_timeout; 966 long sdma_timeout; 967 long video_timeout; 968 long compute_timeout; 969 970 uint64_t unique_id; 971 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 972 973 /* enable runtime pm on the device */ 974 bool runpm; 975 bool in_runpm; 976 977 bool pm_sysfs_en; 978 bool ucode_sysfs_en; 979 980 /* Chip product information */ 981 char product_number[16]; 982 char product_name[32]; 983 char serial[20]; 984 985 struct amdgpu_autodump autodump; 986 987 atomic_t throttling_logging_enabled; 988 struct ratelimit_state throttling_logging_rs; 989 uint32_t ras_features; 990 }; 991 992 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 993 { 994 return container_of(ddev, struct amdgpu_device, ddev); 995 } 996 997 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 998 { 999 return &adev->ddev; 1000 } 1001 1002 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1003 { 1004 return container_of(bdev, struct amdgpu_device, mman.bdev); 1005 } 1006 1007 int amdgpu_device_init(struct amdgpu_device *adev, 1008 uint32_t flags); 1009 void amdgpu_device_fini(struct amdgpu_device *adev); 1010 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1011 1012 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1013 uint32_t *buf, size_t size, bool write); 1014 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1015 uint32_t acc_flags); 1016 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1017 uint32_t acc_flags); 1018 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1019 uint32_t acc_flags); 1020 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1021 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1022 1023 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1024 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1025 1026 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1027 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1028 1029 int emu_soc_asic_init(struct amdgpu_device *adev); 1030 1031 /* 1032 * Registers read & write functions. 1033 */ 1034 #define AMDGPU_REGS_NO_KIQ (1<<1) 1035 1036 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1037 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1038 1039 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1040 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1041 1042 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1043 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1044 1045 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1046 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1047 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1048 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1049 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1050 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1051 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1052 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1053 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1054 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1055 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1056 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1057 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1058 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1059 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1060 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1061 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1062 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1063 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1064 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1065 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1066 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1067 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1068 #define WREG32_P(reg, val, mask) \ 1069 do { \ 1070 uint32_t tmp_ = RREG32(reg); \ 1071 tmp_ &= (mask); \ 1072 tmp_ |= ((val) & ~(mask)); \ 1073 WREG32(reg, tmp_); \ 1074 } while (0) 1075 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1076 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1077 #define WREG32_PLL_P(reg, val, mask) \ 1078 do { \ 1079 uint32_t tmp_ = RREG32_PLL(reg); \ 1080 tmp_ &= (mask); \ 1081 tmp_ |= ((val) & ~(mask)); \ 1082 WREG32_PLL(reg, tmp_); \ 1083 } while (0) 1084 1085 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1086 do { \ 1087 u32 tmp = RREG32_SMC(_Reg); \ 1088 tmp &= (_Mask); \ 1089 tmp |= ((_Val) & ~(_Mask)); \ 1090 WREG32_SMC(_Reg, tmp); \ 1091 } while (0) 1092 1093 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1094 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1095 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1096 1097 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1098 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1099 1100 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1101 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1102 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1103 1104 #define REG_GET_FIELD(value, reg, field) \ 1105 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1106 1107 #define WREG32_FIELD(reg, field, val) \ 1108 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1109 1110 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1111 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1112 1113 /* 1114 * BIOS helpers. 1115 */ 1116 #define RBIOS8(i) (adev->bios[i]) 1117 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1118 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1119 1120 /* 1121 * ASICs macro. 1122 */ 1123 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1124 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1125 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1126 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1127 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1128 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1129 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1130 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1131 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1132 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1133 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1134 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1135 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1136 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1137 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1138 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1139 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1140 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1141 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1142 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1143 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1144 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1145 1146 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1147 1148 /* Common functions */ 1149 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1150 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1151 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1152 struct amdgpu_job* job); 1153 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1154 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1155 1156 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1157 u64 num_vis_bytes); 1158 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1159 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1160 const u32 *registers, 1161 const u32 array_size); 1162 1163 bool amdgpu_device_supports_boco(struct drm_device *dev); 1164 bool amdgpu_device_supports_baco(struct drm_device *dev); 1165 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1166 struct amdgpu_device *peer_adev); 1167 int amdgpu_device_baco_enter(struct drm_device *dev); 1168 int amdgpu_device_baco_exit(struct drm_device *dev); 1169 1170 /* atpx handler */ 1171 #if defined(CONFIG_VGA_SWITCHEROO) 1172 void amdgpu_register_atpx_handler(void); 1173 void amdgpu_unregister_atpx_handler(void); 1174 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1175 bool amdgpu_is_atpx_hybrid(void); 1176 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1177 bool amdgpu_has_atpx(void); 1178 #else 1179 static inline void amdgpu_register_atpx_handler(void) {} 1180 static inline void amdgpu_unregister_atpx_handler(void) {} 1181 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1182 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1183 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1184 static inline bool amdgpu_has_atpx(void) { return false; } 1185 #endif 1186 1187 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1188 void *amdgpu_atpx_get_dhandle(void); 1189 #else 1190 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1191 #endif 1192 1193 /* 1194 * KMS 1195 */ 1196 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1197 extern const int amdgpu_max_kms_ioctl; 1198 1199 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1200 void amdgpu_driver_unload_kms(struct drm_device *dev); 1201 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1202 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1203 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1204 struct drm_file *file_priv); 1205 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1206 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1207 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1208 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1209 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1210 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1211 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1212 unsigned long arg); 1213 1214 /* 1215 * functions used by amdgpu_encoder.c 1216 */ 1217 struct amdgpu_afmt_acr { 1218 u32 clock; 1219 1220 int n_32khz; 1221 int cts_32khz; 1222 1223 int n_44_1khz; 1224 int cts_44_1khz; 1225 1226 int n_48khz; 1227 int cts_48khz; 1228 1229 }; 1230 1231 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1232 1233 /* amdgpu_acpi.c */ 1234 #if defined(CONFIG_ACPI) 1235 int amdgpu_acpi_init(struct amdgpu_device *adev); 1236 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1237 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1238 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1239 u8 perf_req, bool advertise); 1240 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1241 1242 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1243 struct amdgpu_dm_backlight_caps *caps); 1244 #else 1245 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1246 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1247 #endif 1248 1249 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1250 uint64_t addr, struct amdgpu_bo **bo, 1251 struct amdgpu_bo_va_mapping **mapping); 1252 1253 #if defined(CONFIG_DRM_AMD_DC) 1254 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1255 #else 1256 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1257 #endif 1258 1259 1260 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1261 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1262 1263 #include "amdgpu_object.h" 1264 1265 /* used by df_v3_6.c and amdgpu_pmu.c */ 1266 #define AMDGPU_PMU_ATTR(_name, _object) \ 1267 static ssize_t \ 1268 _name##_show(struct device *dev, \ 1269 struct device_attribute *attr, \ 1270 char *page) \ 1271 { \ 1272 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1273 return sprintf(page, _object "\n"); \ 1274 } \ 1275 \ 1276 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1277 1278 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1279 { 1280 return adev->gmc.tmz_enabled; 1281 } 1282 1283 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1284 { 1285 return atomic_read(&adev->in_gpu_reset); 1286 } 1287 #endif 1288