1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_module.h> 59 #include <drm/ttm/ttm_execbuf_util.h> 60 61 #include <drm/amdgpu_drm.h> 62 #include <drm/drm_gem.h> 63 #include <drm/drm_ioctl.h> 64 #include <drm/gpu_scheduler.h> 65 66 #include <kgd_kfd_interface.h> 67 #include "dm_pp_interface.h" 68 #include "kgd_pp_interface.h" 69 70 #include "amd_shared.h" 71 #include "amdgpu_mode.h" 72 #include "amdgpu_ih.h" 73 #include "amdgpu_irq.h" 74 #include "amdgpu_ucode.h" 75 #include "amdgpu_ttm.h" 76 #include "amdgpu_psp.h" 77 #include "amdgpu_gds.h" 78 #include "amdgpu_sync.h" 79 #include "amdgpu_ring.h" 80 #include "amdgpu_vm.h" 81 #include "amdgpu_dpm.h" 82 #include "amdgpu_acp.h" 83 #include "amdgpu_uvd.h" 84 #include "amdgpu_vce.h" 85 #include "amdgpu_vcn.h" 86 #include "amdgpu_jpeg.h" 87 #include "amdgpu_mn.h" 88 #include "amdgpu_gmc.h" 89 #include "amdgpu_gfx.h" 90 #include "amdgpu_sdma.h" 91 #include "amdgpu_nbio.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_smu.h" 103 #include "amdgpu_discovery.h" 104 #include "amdgpu_mes.h" 105 #include "amdgpu_umc.h" 106 #include "amdgpu_mmhub.h" 107 #include "amdgpu_df.h" 108 109 #define MAX_GPU_INSTANCE 16 110 111 struct amdgpu_gpu_instance 112 { 113 struct amdgpu_device *adev; 114 int mgpu_fan_enabled; 115 }; 116 117 struct amdgpu_mgpu_info 118 { 119 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 120 struct mutex mutex; 121 uint32_t num_gpu; 122 uint32_t num_dgpu; 123 uint32_t num_apu; 124 }; 125 126 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 127 128 /* 129 * Modules parameters. 130 */ 131 extern int amdgpu_modeset; 132 extern int amdgpu_vram_limit; 133 extern int amdgpu_vis_vram_limit; 134 extern int amdgpu_gart_size; 135 extern int amdgpu_gtt_size; 136 extern int amdgpu_moverate; 137 extern int amdgpu_benchmarking; 138 extern int amdgpu_testing; 139 extern int amdgpu_audio; 140 extern int amdgpu_disp_priority; 141 extern int amdgpu_hw_i2c; 142 extern int amdgpu_pcie_gen2; 143 extern int amdgpu_msi; 144 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 145 extern int amdgpu_dpm; 146 extern int amdgpu_fw_load_type; 147 extern int amdgpu_aspm; 148 extern int amdgpu_runtime_pm; 149 extern uint amdgpu_ip_block_mask; 150 extern int amdgpu_bapm; 151 extern int amdgpu_deep_color; 152 extern int amdgpu_vm_size; 153 extern int amdgpu_vm_block_size; 154 extern int amdgpu_vm_fragment_size; 155 extern int amdgpu_vm_fault_stop; 156 extern int amdgpu_vm_debug; 157 extern int amdgpu_vm_update_mode; 158 extern int amdgpu_exp_hw_support; 159 extern int amdgpu_dc; 160 extern int amdgpu_sched_jobs; 161 extern int amdgpu_sched_hw_submission; 162 extern uint amdgpu_pcie_gen_cap; 163 extern uint amdgpu_pcie_lane_cap; 164 extern uint amdgpu_cg_mask; 165 extern uint amdgpu_pg_mask; 166 extern uint amdgpu_sdma_phase_quantum; 167 extern char *amdgpu_disable_cu; 168 extern char *amdgpu_virtual_display; 169 extern uint amdgpu_pp_feature_mask; 170 extern uint amdgpu_force_long_training; 171 extern int amdgpu_job_hang_limit; 172 extern int amdgpu_lbpw; 173 extern int amdgpu_compute_multipipe; 174 extern int amdgpu_gpu_recovery; 175 extern int amdgpu_emu_mode; 176 extern uint amdgpu_smu_memory_pool_size; 177 extern uint amdgpu_dc_feature_mask; 178 extern uint amdgpu_dc_debug_mask; 179 extern uint amdgpu_dm_abm_level; 180 extern struct amdgpu_mgpu_info mgpu_info; 181 extern int amdgpu_ras_enable; 182 extern uint amdgpu_ras_mask; 183 extern int amdgpu_bad_page_threshold; 184 extern int amdgpu_async_gfx_ring; 185 extern int amdgpu_mcbp; 186 extern int amdgpu_discovery; 187 extern int amdgpu_mes; 188 extern int amdgpu_noretry; 189 extern int amdgpu_force_asic_type; 190 #ifdef CONFIG_HSA_AMD 191 extern int sched_policy; 192 extern bool debug_evictions; 193 extern bool no_system_mem_limit; 194 #else 195 static const int sched_policy = KFD_SCHED_POLICY_HWS; 196 static const bool debug_evictions; /* = false */ 197 static const bool no_system_mem_limit; 198 #endif 199 200 extern int amdgpu_tmz; 201 extern int amdgpu_reset_method; 202 203 #ifdef CONFIG_DRM_AMDGPU_SI 204 extern int amdgpu_si_support; 205 #endif 206 #ifdef CONFIG_DRM_AMDGPU_CIK 207 extern int amdgpu_cik_support; 208 #endif 209 extern int amdgpu_num_kcq; 210 211 #define AMDGPU_VM_MAX_NUM_CTX 4096 212 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 213 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 214 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 215 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 216 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 217 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 218 #define AMDGPUFB_CONN_LIMIT 4 219 #define AMDGPU_BIOS_NUM_SCRATCH 16 220 221 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 222 223 /* hard reset data */ 224 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 225 226 /* reset flags */ 227 #define AMDGPU_RESET_GFX (1 << 0) 228 #define AMDGPU_RESET_COMPUTE (1 << 1) 229 #define AMDGPU_RESET_DMA (1 << 2) 230 #define AMDGPU_RESET_CP (1 << 3) 231 #define AMDGPU_RESET_GRBM (1 << 4) 232 #define AMDGPU_RESET_DMA1 (1 << 5) 233 #define AMDGPU_RESET_RLC (1 << 6) 234 #define AMDGPU_RESET_SEM (1 << 7) 235 #define AMDGPU_RESET_IH (1 << 8) 236 #define AMDGPU_RESET_VMC (1 << 9) 237 #define AMDGPU_RESET_MC (1 << 10) 238 #define AMDGPU_RESET_DISPLAY (1 << 11) 239 #define AMDGPU_RESET_UVD (1 << 12) 240 #define AMDGPU_RESET_VCE (1 << 13) 241 #define AMDGPU_RESET_VCE1 (1 << 14) 242 243 /* max cursor sizes (in pixels) */ 244 #define CIK_CURSOR_WIDTH 128 245 #define CIK_CURSOR_HEIGHT 128 246 247 struct amdgpu_device; 248 struct amdgpu_ib; 249 struct amdgpu_cs_parser; 250 struct amdgpu_job; 251 struct amdgpu_irq_src; 252 struct amdgpu_fpriv; 253 struct amdgpu_bo_va_mapping; 254 struct amdgpu_atif; 255 struct kfd_vm_fault_info; 256 struct amdgpu_hive_info; 257 258 enum amdgpu_cp_irq { 259 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 260 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 261 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 262 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 263 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 264 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 265 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 266 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 267 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 268 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 269 270 AMDGPU_CP_IRQ_LAST 271 }; 272 273 enum amdgpu_thermal_irq { 274 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 275 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 276 277 AMDGPU_THERMAL_IRQ_LAST 278 }; 279 280 enum amdgpu_kiq_irq { 281 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 282 AMDGPU_CP_KIQ_IRQ_LAST 283 }; 284 285 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 286 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 287 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 288 289 int amdgpu_device_ip_set_clockgating_state(void *dev, 290 enum amd_ip_block_type block_type, 291 enum amd_clockgating_state state); 292 int amdgpu_device_ip_set_powergating_state(void *dev, 293 enum amd_ip_block_type block_type, 294 enum amd_powergating_state state); 295 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 296 u32 *flags); 297 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 298 enum amd_ip_block_type block_type); 299 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 300 enum amd_ip_block_type block_type); 301 302 #define AMDGPU_MAX_IP_NUM 16 303 304 struct amdgpu_ip_block_status { 305 bool valid; 306 bool sw; 307 bool hw; 308 bool late_initialized; 309 bool hang; 310 }; 311 312 struct amdgpu_ip_block_version { 313 const enum amd_ip_block_type type; 314 const u32 major; 315 const u32 minor; 316 const u32 rev; 317 const struct amd_ip_funcs *funcs; 318 }; 319 320 #define HW_REV(_Major, _Minor, _Rev) \ 321 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 322 323 struct amdgpu_ip_block { 324 struct amdgpu_ip_block_status status; 325 const struct amdgpu_ip_block_version *version; 326 }; 327 328 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 329 enum amd_ip_block_type type, 330 u32 major, u32 minor); 331 332 struct amdgpu_ip_block * 333 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 334 enum amd_ip_block_type type); 335 336 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 337 const struct amdgpu_ip_block_version *ip_block_version); 338 339 /* 340 * BIOS. 341 */ 342 bool amdgpu_get_bios(struct amdgpu_device *adev); 343 bool amdgpu_read_bios(struct amdgpu_device *adev); 344 345 /* 346 * Clocks 347 */ 348 349 #define AMDGPU_MAX_PPLL 3 350 351 struct amdgpu_clock { 352 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 353 struct amdgpu_pll spll; 354 struct amdgpu_pll mpll; 355 /* 10 Khz units */ 356 uint32_t default_mclk; 357 uint32_t default_sclk; 358 uint32_t default_dispclk; 359 uint32_t current_dispclk; 360 uint32_t dp_extclk; 361 uint32_t max_pixel_clock; 362 }; 363 364 /* sub-allocation manager, it has to be protected by another lock. 365 * By conception this is an helper for other part of the driver 366 * like the indirect buffer or semaphore, which both have their 367 * locking. 368 * 369 * Principe is simple, we keep a list of sub allocation in offset 370 * order (first entry has offset == 0, last entry has the highest 371 * offset). 372 * 373 * When allocating new object we first check if there is room at 374 * the end total_size - (last_object_offset + last_object_size) >= 375 * alloc_size. If so we allocate new object there. 376 * 377 * When there is not enough room at the end, we start waiting for 378 * each sub object until we reach object_offset+object_size >= 379 * alloc_size, this object then become the sub object we return. 380 * 381 * Alignment can't be bigger than page size. 382 * 383 * Hole are not considered for allocation to keep things simple. 384 * Assumption is that there won't be hole (all object on same 385 * alignment). 386 */ 387 388 #define AMDGPU_SA_NUM_FENCE_LISTS 32 389 390 struct amdgpu_sa_manager { 391 wait_queue_head_t wq; 392 struct amdgpu_bo *bo; 393 struct list_head *hole; 394 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 395 struct list_head olist; 396 unsigned size; 397 uint64_t gpu_addr; 398 void *cpu_ptr; 399 uint32_t domain; 400 uint32_t align; 401 }; 402 403 /* sub-allocation buffer */ 404 struct amdgpu_sa_bo { 405 struct list_head olist; 406 struct list_head flist; 407 struct amdgpu_sa_manager *manager; 408 unsigned soffset; 409 unsigned eoffset; 410 struct dma_fence *fence; 411 }; 412 413 int amdgpu_fence_slab_init(void); 414 void amdgpu_fence_slab_fini(void); 415 416 /* 417 * IRQS. 418 */ 419 420 struct amdgpu_flip_work { 421 struct delayed_work flip_work; 422 struct work_struct unpin_work; 423 struct amdgpu_device *adev; 424 int crtc_id; 425 u32 target_vblank; 426 uint64_t base; 427 struct drm_pending_vblank_event *event; 428 struct amdgpu_bo *old_abo; 429 struct dma_fence *excl; 430 unsigned shared_count; 431 struct dma_fence **shared; 432 struct dma_fence_cb cb; 433 bool async; 434 }; 435 436 437 /* 438 * CP & rings. 439 */ 440 441 struct amdgpu_ib { 442 struct amdgpu_sa_bo *sa_bo; 443 uint32_t length_dw; 444 uint64_t gpu_addr; 445 uint32_t *ptr; 446 uint32_t flags; 447 }; 448 449 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 450 451 /* 452 * file private structure 453 */ 454 455 struct amdgpu_fpriv { 456 struct amdgpu_vm vm; 457 struct amdgpu_bo_va *prt_va; 458 struct amdgpu_bo_va *csa_va; 459 struct mutex bo_list_lock; 460 struct idr bo_list_handles; 461 struct amdgpu_ctx_mgr ctx_mgr; 462 }; 463 464 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 465 466 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 467 unsigned size, 468 enum amdgpu_ib_pool_type pool, 469 struct amdgpu_ib *ib); 470 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 471 struct dma_fence *f); 472 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 473 struct amdgpu_ib *ibs, struct amdgpu_job *job, 474 struct dma_fence **f); 475 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 476 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 477 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 478 479 /* 480 * CS. 481 */ 482 struct amdgpu_cs_chunk { 483 uint32_t chunk_id; 484 uint32_t length_dw; 485 void *kdata; 486 }; 487 488 struct amdgpu_cs_post_dep { 489 struct drm_syncobj *syncobj; 490 struct dma_fence_chain *chain; 491 u64 point; 492 }; 493 494 struct amdgpu_cs_parser { 495 struct amdgpu_device *adev; 496 struct drm_file *filp; 497 struct amdgpu_ctx *ctx; 498 499 /* chunks */ 500 unsigned nchunks; 501 struct amdgpu_cs_chunk *chunks; 502 503 /* scheduler job object */ 504 struct amdgpu_job *job; 505 struct drm_sched_entity *entity; 506 507 /* buffer objects */ 508 struct ww_acquire_ctx ticket; 509 struct amdgpu_bo_list *bo_list; 510 struct amdgpu_mn *mn; 511 struct amdgpu_bo_list_entry vm_pd; 512 struct list_head validated; 513 struct dma_fence *fence; 514 uint64_t bytes_moved_threshold; 515 uint64_t bytes_moved_vis_threshold; 516 uint64_t bytes_moved; 517 uint64_t bytes_moved_vis; 518 519 /* user fence */ 520 struct amdgpu_bo_list_entry uf_entry; 521 522 unsigned num_post_deps; 523 struct amdgpu_cs_post_dep *post_deps; 524 }; 525 526 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 527 uint32_t ib_idx, int idx) 528 { 529 return p->job->ibs[ib_idx].ptr[idx]; 530 } 531 532 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 533 uint32_t ib_idx, int idx, 534 uint32_t value) 535 { 536 p->job->ibs[ib_idx].ptr[idx] = value; 537 } 538 539 /* 540 * Writeback 541 */ 542 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 543 544 struct amdgpu_wb { 545 struct amdgpu_bo *wb_obj; 546 volatile uint32_t *wb; 547 uint64_t gpu_addr; 548 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 549 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 550 }; 551 552 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 553 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 554 555 /* 556 * Benchmarking 557 */ 558 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 559 560 561 /* 562 * Testing 563 */ 564 void amdgpu_test_moves(struct amdgpu_device *adev); 565 566 /* 567 * ASIC specific register table accessible by UMD 568 */ 569 struct amdgpu_allowed_register_entry { 570 uint32_t reg_offset; 571 bool grbm_indexed; 572 }; 573 574 enum amd_reset_method { 575 AMD_RESET_METHOD_LEGACY = 0, 576 AMD_RESET_METHOD_MODE0, 577 AMD_RESET_METHOD_MODE1, 578 AMD_RESET_METHOD_MODE2, 579 AMD_RESET_METHOD_BACO 580 }; 581 582 /* 583 * ASIC specific functions. 584 */ 585 struct amdgpu_asic_funcs { 586 bool (*read_disabled_bios)(struct amdgpu_device *adev); 587 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 588 u8 *bios, u32 length_bytes); 589 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 590 u32 sh_num, u32 reg_offset, u32 *value); 591 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 592 int (*reset)(struct amdgpu_device *adev); 593 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 594 /* get the reference clock */ 595 u32 (*get_xclk)(struct amdgpu_device *adev); 596 /* MM block clocks */ 597 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 598 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 599 /* static power management */ 600 int (*get_pcie_lanes)(struct amdgpu_device *adev); 601 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 602 /* get config memsize register */ 603 u32 (*get_config_memsize)(struct amdgpu_device *adev); 604 /* flush hdp write queue */ 605 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 606 /* invalidate hdp read cache */ 607 void (*invalidate_hdp)(struct amdgpu_device *adev, 608 struct amdgpu_ring *ring); 609 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev); 610 /* check if the asic needs a full reset of if soft reset will work */ 611 bool (*need_full_reset)(struct amdgpu_device *adev); 612 /* initialize doorbell layout for specific asic*/ 613 void (*init_doorbell_index)(struct amdgpu_device *adev); 614 /* PCIe bandwidth usage */ 615 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 616 uint64_t *count1); 617 /* do we need to reset the asic at init time (e.g., kexec) */ 618 bool (*need_reset_on_init)(struct amdgpu_device *adev); 619 /* PCIe replay counter */ 620 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 621 /* device supports BACO */ 622 bool (*supports_baco)(struct amdgpu_device *adev); 623 /* pre asic_init quirks */ 624 void (*pre_asic_init)(struct amdgpu_device *adev); 625 }; 626 627 /* 628 * IOCTL. 629 */ 630 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 631 struct drm_file *filp); 632 633 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 634 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 635 struct drm_file *filp); 636 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 637 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 638 struct drm_file *filp); 639 640 /* VRAM scratch page for HDP bug, default vram page */ 641 struct amdgpu_vram_scratch { 642 struct amdgpu_bo *robj; 643 volatile uint32_t *ptr; 644 u64 gpu_addr; 645 }; 646 647 /* 648 * ACPI 649 */ 650 struct amdgpu_atcs_functions { 651 bool get_ext_state; 652 bool pcie_perf_req; 653 bool pcie_dev_rdy; 654 bool pcie_bus_width; 655 }; 656 657 struct amdgpu_atcs { 658 struct amdgpu_atcs_functions functions; 659 }; 660 661 /* 662 * CGS 663 */ 664 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 665 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 666 667 /* 668 * Core structure, functions and helpers. 669 */ 670 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 671 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 672 673 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 674 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 675 676 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 677 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 678 679 struct amdgpu_mmio_remap { 680 u32 reg_offset; 681 resource_size_t bus_addr; 682 }; 683 684 /* Define the HW IP blocks will be used in driver , add more if necessary */ 685 enum amd_hw_ip_block_type { 686 GC_HWIP = 1, 687 HDP_HWIP, 688 SDMA0_HWIP, 689 SDMA1_HWIP, 690 SDMA2_HWIP, 691 SDMA3_HWIP, 692 SDMA4_HWIP, 693 SDMA5_HWIP, 694 SDMA6_HWIP, 695 SDMA7_HWIP, 696 MMHUB_HWIP, 697 ATHUB_HWIP, 698 NBIO_HWIP, 699 MP0_HWIP, 700 MP1_HWIP, 701 UVD_HWIP, 702 VCN_HWIP = UVD_HWIP, 703 JPEG_HWIP = VCN_HWIP, 704 VCE_HWIP, 705 DF_HWIP, 706 DCE_HWIP, 707 OSSSYS_HWIP, 708 SMUIO_HWIP, 709 PWR_HWIP, 710 NBIF_HWIP, 711 THM_HWIP, 712 CLK_HWIP, 713 UMC_HWIP, 714 RSMU_HWIP, 715 MAX_HWIP 716 }; 717 718 #define HWIP_MAX_INSTANCE 8 719 720 struct amd_powerplay { 721 void *pp_handle; 722 const struct amd_pm_funcs *pp_funcs; 723 }; 724 725 #define AMDGPU_RESET_MAGIC_NUM 64 726 #define AMDGPU_MAX_DF_PERFMONS 4 727 struct amdgpu_device { 728 struct device *dev; 729 struct pci_dev *pdev; 730 struct drm_device ddev; 731 732 #ifdef CONFIG_DRM_AMD_ACP 733 struct amdgpu_acp acp; 734 #endif 735 struct amdgpu_hive_info *hive; 736 /* ASIC */ 737 enum amd_asic_type asic_type; 738 uint32_t family; 739 uint32_t rev_id; 740 uint32_t external_rev_id; 741 unsigned long flags; 742 unsigned long apu_flags; 743 int usec_timeout; 744 const struct amdgpu_asic_funcs *asic_funcs; 745 bool shutdown; 746 bool need_swiotlb; 747 bool accel_working; 748 struct notifier_block acpi_nb; 749 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 750 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 751 unsigned debugfs_count; 752 #if defined(CONFIG_DEBUG_FS) 753 struct dentry *debugfs_preempt; 754 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 755 #endif 756 struct amdgpu_atif *atif; 757 struct amdgpu_atcs atcs; 758 struct mutex srbm_mutex; 759 /* GRBM index mutex. Protects concurrent access to GRBM index */ 760 struct mutex grbm_idx_mutex; 761 struct dev_pm_domain vga_pm_domain; 762 bool have_disp_power_ref; 763 bool have_atomics_support; 764 765 /* BIOS */ 766 bool is_atom_fw; 767 uint8_t *bios; 768 uint32_t bios_size; 769 uint32_t bios_scratch_reg_offset; 770 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 771 772 /* Register/doorbell mmio */ 773 resource_size_t rmmio_base; 774 resource_size_t rmmio_size; 775 void __iomem *rmmio; 776 /* protects concurrent MM_INDEX/DATA based register access */ 777 spinlock_t mmio_idx_lock; 778 struct amdgpu_mmio_remap rmmio_remap; 779 /* protects concurrent SMC based register access */ 780 spinlock_t smc_idx_lock; 781 amdgpu_rreg_t smc_rreg; 782 amdgpu_wreg_t smc_wreg; 783 /* protects concurrent PCIE register access */ 784 spinlock_t pcie_idx_lock; 785 amdgpu_rreg_t pcie_rreg; 786 amdgpu_wreg_t pcie_wreg; 787 amdgpu_rreg_t pciep_rreg; 788 amdgpu_wreg_t pciep_wreg; 789 amdgpu_rreg64_t pcie_rreg64; 790 amdgpu_wreg64_t pcie_wreg64; 791 /* protects concurrent UVD register access */ 792 spinlock_t uvd_ctx_idx_lock; 793 amdgpu_rreg_t uvd_ctx_rreg; 794 amdgpu_wreg_t uvd_ctx_wreg; 795 /* protects concurrent DIDT register access */ 796 spinlock_t didt_idx_lock; 797 amdgpu_rreg_t didt_rreg; 798 amdgpu_wreg_t didt_wreg; 799 /* protects concurrent gc_cac register access */ 800 spinlock_t gc_cac_idx_lock; 801 amdgpu_rreg_t gc_cac_rreg; 802 amdgpu_wreg_t gc_cac_wreg; 803 /* protects concurrent se_cac register access */ 804 spinlock_t se_cac_idx_lock; 805 amdgpu_rreg_t se_cac_rreg; 806 amdgpu_wreg_t se_cac_wreg; 807 /* protects concurrent ENDPOINT (audio) register access */ 808 spinlock_t audio_endpt_idx_lock; 809 amdgpu_block_rreg_t audio_endpt_rreg; 810 amdgpu_block_wreg_t audio_endpt_wreg; 811 void __iomem *rio_mem; 812 resource_size_t rio_mem_size; 813 struct amdgpu_doorbell doorbell; 814 815 /* clock/pll info */ 816 struct amdgpu_clock clock; 817 818 /* MC */ 819 struct amdgpu_gmc gmc; 820 struct amdgpu_gart gart; 821 dma_addr_t dummy_page_addr; 822 struct amdgpu_vm_manager vm_manager; 823 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 824 unsigned num_vmhubs; 825 826 /* memory management */ 827 struct amdgpu_mman mman; 828 struct amdgpu_vram_scratch vram_scratch; 829 struct amdgpu_wb wb; 830 atomic64_t num_bytes_moved; 831 atomic64_t num_evictions; 832 atomic64_t num_vram_cpu_page_faults; 833 atomic_t gpu_reset_counter; 834 atomic_t vram_lost_counter; 835 836 /* data for buffer migration throttling */ 837 struct { 838 spinlock_t lock; 839 s64 last_update_us; 840 s64 accum_us; /* accumulated microseconds */ 841 s64 accum_us_vis; /* for visible VRAM */ 842 u32 log2_max_MBps; 843 } mm_stats; 844 845 /* display */ 846 bool enable_virtual_display; 847 struct amdgpu_mode_info mode_info; 848 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 849 struct work_struct hotplug_work; 850 struct amdgpu_irq_src crtc_irq; 851 struct amdgpu_irq_src vupdate_irq; 852 struct amdgpu_irq_src pageflip_irq; 853 struct amdgpu_irq_src hpd_irq; 854 855 /* rings */ 856 u64 fence_context; 857 unsigned num_rings; 858 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 859 bool ib_pool_ready; 860 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 861 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 862 863 /* interrupts */ 864 struct amdgpu_irq irq; 865 866 /* powerplay */ 867 struct amd_powerplay powerplay; 868 bool pp_force_state_enabled; 869 870 /* smu */ 871 struct smu_context smu; 872 873 /* dpm */ 874 struct amdgpu_pm pm; 875 u32 cg_flags; 876 u32 pg_flags; 877 878 /* nbio */ 879 struct amdgpu_nbio nbio; 880 881 /* mmhub */ 882 struct amdgpu_mmhub mmhub; 883 884 /* gfx */ 885 struct amdgpu_gfx gfx; 886 887 /* sdma */ 888 struct amdgpu_sdma sdma; 889 890 /* uvd */ 891 struct amdgpu_uvd uvd; 892 893 /* vce */ 894 struct amdgpu_vce vce; 895 896 /* vcn */ 897 struct amdgpu_vcn vcn; 898 899 /* jpeg */ 900 struct amdgpu_jpeg jpeg; 901 902 /* firmwares */ 903 struct amdgpu_firmware firmware; 904 905 /* PSP */ 906 struct psp_context psp; 907 908 /* GDS */ 909 struct amdgpu_gds gds; 910 911 /* KFD */ 912 struct amdgpu_kfd_dev kfd; 913 914 /* UMC */ 915 struct amdgpu_umc umc; 916 917 /* display related functionality */ 918 struct amdgpu_display_manager dm; 919 920 /* mes */ 921 bool enable_mes; 922 struct amdgpu_mes mes; 923 924 /* df */ 925 struct amdgpu_df df; 926 927 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 928 int num_ip_blocks; 929 struct mutex mn_lock; 930 DECLARE_HASHTABLE(mn_hash, 7); 931 932 /* tracking pinned memory */ 933 atomic64_t vram_pin_size; 934 atomic64_t visible_pin_size; 935 atomic64_t gart_pin_size; 936 937 /* soc15 register offset based on ip, instance and segment */ 938 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 939 940 /* delayed work_func for deferring clockgating during resume */ 941 struct delayed_work delayed_init_work; 942 943 struct amdgpu_virt virt; 944 945 /* link all shadow bo */ 946 struct list_head shadow_list; 947 struct mutex shadow_list_lock; 948 949 /* record hw reset is performed */ 950 bool has_hw_reset; 951 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 952 953 /* s3/s4 mask */ 954 bool in_suspend; 955 bool in_hibernate; 956 957 atomic_t in_gpu_reset; 958 enum pp_mp1_state mp1_state; 959 struct rw_semaphore reset_sem; 960 struct amdgpu_doorbell_index doorbell_index; 961 962 struct mutex notifier_lock; 963 964 int asic_reset_res; 965 struct work_struct xgmi_reset_work; 966 967 long gfx_timeout; 968 long sdma_timeout; 969 long video_timeout; 970 long compute_timeout; 971 972 uint64_t unique_id; 973 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 974 975 /* enable runtime pm on the device */ 976 bool runpm; 977 bool in_runpm; 978 979 bool pm_sysfs_en; 980 bool ucode_sysfs_en; 981 982 /* Chip product information */ 983 char product_number[16]; 984 char product_name[32]; 985 char serial[20]; 986 987 struct amdgpu_autodump autodump; 988 989 atomic_t throttling_logging_enabled; 990 struct ratelimit_state throttling_logging_rs; 991 uint32_t ras_features; 992 993 bool in_pci_err_recovery; 994 struct pci_saved_state *pci_state; 995 }; 996 997 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 998 { 999 return container_of(ddev, struct amdgpu_device, ddev); 1000 } 1001 1002 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1003 { 1004 return &adev->ddev; 1005 } 1006 1007 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1008 { 1009 return container_of(bdev, struct amdgpu_device, mman.bdev); 1010 } 1011 1012 int amdgpu_device_init(struct amdgpu_device *adev, 1013 uint32_t flags); 1014 void amdgpu_device_fini(struct amdgpu_device *adev); 1015 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1016 1017 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1018 uint32_t *buf, size_t size, bool write); 1019 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1020 uint32_t acc_flags); 1021 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1022 uint32_t acc_flags); 1023 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1024 uint32_t acc_flags); 1025 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1026 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1027 1028 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1029 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1030 1031 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1032 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1033 1034 int emu_soc_asic_init(struct amdgpu_device *adev); 1035 1036 /* 1037 * Registers read & write functions. 1038 */ 1039 #define AMDGPU_REGS_NO_KIQ (1<<1) 1040 1041 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1042 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1043 1044 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1045 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1046 1047 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1048 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1049 1050 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1051 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1052 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1053 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1054 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1055 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1056 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1057 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1058 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1059 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1060 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1061 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1062 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1063 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1064 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1065 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1066 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1067 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1068 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1069 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1070 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1071 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1072 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1073 #define WREG32_P(reg, val, mask) \ 1074 do { \ 1075 uint32_t tmp_ = RREG32(reg); \ 1076 tmp_ &= (mask); \ 1077 tmp_ |= ((val) & ~(mask)); \ 1078 WREG32(reg, tmp_); \ 1079 } while (0) 1080 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1081 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1082 #define WREG32_PLL_P(reg, val, mask) \ 1083 do { \ 1084 uint32_t tmp_ = RREG32_PLL(reg); \ 1085 tmp_ &= (mask); \ 1086 tmp_ |= ((val) & ~(mask)); \ 1087 WREG32_PLL(reg, tmp_); \ 1088 } while (0) 1089 1090 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1091 do { \ 1092 u32 tmp = RREG32_SMC(_Reg); \ 1093 tmp &= (_Mask); \ 1094 tmp |= ((_Val) & ~(_Mask)); \ 1095 WREG32_SMC(_Reg, tmp); \ 1096 } while (0) 1097 1098 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1099 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1100 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1101 1102 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1103 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1104 1105 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1106 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1107 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1108 1109 #define REG_GET_FIELD(value, reg, field) \ 1110 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1111 1112 #define WREG32_FIELD(reg, field, val) \ 1113 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1114 1115 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1116 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1117 1118 /* 1119 * BIOS helpers. 1120 */ 1121 #define RBIOS8(i) (adev->bios[i]) 1122 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1123 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1124 1125 /* 1126 * ASICs macro. 1127 */ 1128 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1129 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1130 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1131 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1132 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1133 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1134 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1135 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1136 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1137 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1138 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1139 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1140 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1141 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1142 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1143 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1144 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1145 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1146 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1147 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1148 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1149 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1150 1151 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1152 1153 /* Common functions */ 1154 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1155 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1156 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1157 struct amdgpu_job* job); 1158 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1159 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1160 1161 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1162 u64 num_vis_bytes); 1163 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1164 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1165 const u32 *registers, 1166 const u32 array_size); 1167 1168 bool amdgpu_device_supports_boco(struct drm_device *dev); 1169 bool amdgpu_device_supports_baco(struct drm_device *dev); 1170 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1171 struct amdgpu_device *peer_adev); 1172 int amdgpu_device_baco_enter(struct drm_device *dev); 1173 int amdgpu_device_baco_exit(struct drm_device *dev); 1174 1175 /* atpx handler */ 1176 #if defined(CONFIG_VGA_SWITCHEROO) 1177 void amdgpu_register_atpx_handler(void); 1178 void amdgpu_unregister_atpx_handler(void); 1179 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1180 bool amdgpu_is_atpx_hybrid(void); 1181 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1182 bool amdgpu_has_atpx(void); 1183 #else 1184 static inline void amdgpu_register_atpx_handler(void) {} 1185 static inline void amdgpu_unregister_atpx_handler(void) {} 1186 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1187 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1188 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1189 static inline bool amdgpu_has_atpx(void) { return false; } 1190 #endif 1191 1192 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1193 void *amdgpu_atpx_get_dhandle(void); 1194 #else 1195 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1196 #endif 1197 1198 /* 1199 * KMS 1200 */ 1201 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1202 extern const int amdgpu_max_kms_ioctl; 1203 1204 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1205 void amdgpu_driver_unload_kms(struct drm_device *dev); 1206 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1207 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1208 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1209 struct drm_file *file_priv); 1210 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1211 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1212 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1213 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1214 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1215 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1216 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1217 unsigned long arg); 1218 1219 /* 1220 * functions used by amdgpu_encoder.c 1221 */ 1222 struct amdgpu_afmt_acr { 1223 u32 clock; 1224 1225 int n_32khz; 1226 int cts_32khz; 1227 1228 int n_44_1khz; 1229 int cts_44_1khz; 1230 1231 int n_48khz; 1232 int cts_48khz; 1233 1234 }; 1235 1236 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1237 1238 /* amdgpu_acpi.c */ 1239 #if defined(CONFIG_ACPI) 1240 int amdgpu_acpi_init(struct amdgpu_device *adev); 1241 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1242 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1243 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1244 u8 perf_req, bool advertise); 1245 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1246 1247 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1248 struct amdgpu_dm_backlight_caps *caps); 1249 #else 1250 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1251 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1252 #endif 1253 1254 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1255 uint64_t addr, struct amdgpu_bo **bo, 1256 struct amdgpu_bo_va_mapping **mapping); 1257 1258 #if defined(CONFIG_DRM_AMD_DC) 1259 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1260 #else 1261 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1262 #endif 1263 1264 1265 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1266 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1267 1268 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1269 pci_channel_state_t state); 1270 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1271 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1272 void amdgpu_pci_resume(struct pci_dev *pdev); 1273 1274 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1275 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1276 1277 #include "amdgpu_object.h" 1278 1279 /* used by df_v3_6.c and amdgpu_pmu.c */ 1280 #define AMDGPU_PMU_ATTR(_name, _object) \ 1281 static ssize_t \ 1282 _name##_show(struct device *dev, \ 1283 struct device_attribute *attr, \ 1284 char *page) \ 1285 { \ 1286 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1287 return sprintf(page, _object "\n"); \ 1288 } \ 1289 \ 1290 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1291 1292 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1293 { 1294 return adev->gmc.tmz_enabled; 1295 } 1296 1297 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1298 { 1299 return atomic_read(&adev->in_gpu_reset); 1300 } 1301 #endif 1302