1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo.h> 56 #include <drm/ttm/ttm_placement.h> 57 #include <drm/ttm/ttm_execbuf_util.h> 58 59 #include <drm/amdgpu_drm.h> 60 #include <drm/drm_gem.h> 61 #include <drm/drm_ioctl.h> 62 63 #include <kgd_kfd_interface.h> 64 #include "dm_pp_interface.h" 65 #include "kgd_pp_interface.h" 66 67 #include "amd_shared.h" 68 #include "amdgpu_mode.h" 69 #include "amdgpu_ih.h" 70 #include "amdgpu_irq.h" 71 #include "amdgpu_ucode.h" 72 #include "amdgpu_ttm.h" 73 #include "amdgpu_psp.h" 74 #include "amdgpu_gds.h" 75 #include "amdgpu_sync.h" 76 #include "amdgpu_ring.h" 77 #include "amdgpu_vm.h" 78 #include "amdgpu_dpm.h" 79 #include "amdgpu_acp.h" 80 #include "amdgpu_uvd.h" 81 #include "amdgpu_vce.h" 82 #include "amdgpu_vcn.h" 83 #include "amdgpu_jpeg.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_lsdma.h" 88 #include "amdgpu_nbio.h" 89 #include "amdgpu_hdp.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_mes_ctx.h" 94 #include "amdgpu_gart.h" 95 #include "amdgpu_debugfs.h" 96 #include "amdgpu_job.h" 97 #include "amdgpu_bo_list.h" 98 #include "amdgpu_gem.h" 99 #include "amdgpu_doorbell.h" 100 #include "amdgpu_amdkfd.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_gfxhub.h" 106 #include "amdgpu_df.h" 107 #include "amdgpu_smuio.h" 108 #include "amdgpu_fdinfo.h" 109 #include "amdgpu_mca.h" 110 #include "amdgpu_ras.h" 111 112 #define MAX_GPU_INSTANCE 16 113 114 struct amdgpu_gpu_instance 115 { 116 struct amdgpu_device *adev; 117 int mgpu_fan_enabled; 118 }; 119 120 struct amdgpu_mgpu_info 121 { 122 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 123 struct mutex mutex; 124 uint32_t num_gpu; 125 uint32_t num_dgpu; 126 uint32_t num_apu; 127 128 /* delayed reset_func for XGMI configuration if necessary */ 129 struct delayed_work delayed_reset_work; 130 bool pending_reset; 131 }; 132 133 enum amdgpu_ss { 134 AMDGPU_SS_DRV_LOAD, 135 AMDGPU_SS_DEV_D0, 136 AMDGPU_SS_DEV_D3, 137 AMDGPU_SS_DRV_UNLOAD 138 }; 139 140 struct amdgpu_watchdog_timer 141 { 142 bool timeout_fatal_disable; 143 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 144 }; 145 146 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 147 148 /* 149 * Modules parameters. 150 */ 151 extern int amdgpu_modeset; 152 extern unsigned int amdgpu_vram_limit; 153 extern int amdgpu_vis_vram_limit; 154 extern int amdgpu_gart_size; 155 extern int amdgpu_gtt_size; 156 extern int amdgpu_moverate; 157 extern int amdgpu_audio; 158 extern int amdgpu_disp_priority; 159 extern int amdgpu_hw_i2c; 160 extern int amdgpu_pcie_gen2; 161 extern int amdgpu_msi; 162 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 163 extern int amdgpu_dpm; 164 extern int amdgpu_fw_load_type; 165 extern int amdgpu_aspm; 166 extern int amdgpu_runtime_pm; 167 extern uint amdgpu_ip_block_mask; 168 extern int amdgpu_bapm; 169 extern int amdgpu_deep_color; 170 extern int amdgpu_vm_size; 171 extern int amdgpu_vm_block_size; 172 extern int amdgpu_vm_fragment_size; 173 extern int amdgpu_vm_fault_stop; 174 extern int amdgpu_vm_debug; 175 extern int amdgpu_vm_update_mode; 176 extern int amdgpu_exp_hw_support; 177 extern int amdgpu_dc; 178 extern int amdgpu_sched_jobs; 179 extern int amdgpu_sched_hw_submission; 180 extern uint amdgpu_pcie_gen_cap; 181 extern uint amdgpu_pcie_lane_cap; 182 extern u64 amdgpu_cg_mask; 183 extern uint amdgpu_pg_mask; 184 extern uint amdgpu_sdma_phase_quantum; 185 extern char *amdgpu_disable_cu; 186 extern char *amdgpu_virtual_display; 187 extern uint amdgpu_pp_feature_mask; 188 extern uint amdgpu_force_long_training; 189 extern int amdgpu_job_hang_limit; 190 extern int amdgpu_lbpw; 191 extern int amdgpu_compute_multipipe; 192 extern int amdgpu_gpu_recovery; 193 extern int amdgpu_emu_mode; 194 extern uint amdgpu_smu_memory_pool_size; 195 extern int amdgpu_smu_pptable_id; 196 extern uint amdgpu_dc_feature_mask; 197 extern uint amdgpu_freesync_vid_mode; 198 extern uint amdgpu_dc_debug_mask; 199 extern uint amdgpu_dc_visual_confirm; 200 extern uint amdgpu_dm_abm_level; 201 extern int amdgpu_backlight; 202 extern struct amdgpu_mgpu_info mgpu_info; 203 extern int amdgpu_ras_enable; 204 extern uint amdgpu_ras_mask; 205 extern int amdgpu_bad_page_threshold; 206 extern bool amdgpu_ignore_bad_page_threshold; 207 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 208 extern int amdgpu_async_gfx_ring; 209 extern int amdgpu_mcbp; 210 extern int amdgpu_discovery; 211 extern int amdgpu_mes; 212 extern int amdgpu_mes_kiq; 213 extern int amdgpu_noretry; 214 extern int amdgpu_force_asic_type; 215 extern int amdgpu_smartshift_bias; 216 extern int amdgpu_use_xgmi_p2p; 217 #ifdef CONFIG_HSA_AMD 218 extern int sched_policy; 219 extern bool debug_evictions; 220 extern bool no_system_mem_limit; 221 extern int halt_if_hws_hang; 222 #else 223 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 224 static const bool __maybe_unused debug_evictions; /* = false */ 225 static const bool __maybe_unused no_system_mem_limit; 226 static const int __maybe_unused halt_if_hws_hang; 227 #endif 228 #ifdef CONFIG_HSA_AMD_P2P 229 extern bool pcie_p2p; 230 #endif 231 232 extern int amdgpu_tmz; 233 extern int amdgpu_reset_method; 234 235 #ifdef CONFIG_DRM_AMDGPU_SI 236 extern int amdgpu_si_support; 237 #endif 238 #ifdef CONFIG_DRM_AMDGPU_CIK 239 extern int amdgpu_cik_support; 240 #endif 241 extern int amdgpu_num_kcq; 242 243 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 244 extern int amdgpu_vcnfw_log; 245 extern int amdgpu_sg_display; 246 247 #define AMDGPU_VM_MAX_NUM_CTX 4096 248 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 249 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 250 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 251 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 252 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 253 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 254 #define AMDGPUFB_CONN_LIMIT 4 255 #define AMDGPU_BIOS_NUM_SCRATCH 16 256 257 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 258 259 /* hard reset data */ 260 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 261 262 /* reset flags */ 263 #define AMDGPU_RESET_GFX (1 << 0) 264 #define AMDGPU_RESET_COMPUTE (1 << 1) 265 #define AMDGPU_RESET_DMA (1 << 2) 266 #define AMDGPU_RESET_CP (1 << 3) 267 #define AMDGPU_RESET_GRBM (1 << 4) 268 #define AMDGPU_RESET_DMA1 (1 << 5) 269 #define AMDGPU_RESET_RLC (1 << 6) 270 #define AMDGPU_RESET_SEM (1 << 7) 271 #define AMDGPU_RESET_IH (1 << 8) 272 #define AMDGPU_RESET_VMC (1 << 9) 273 #define AMDGPU_RESET_MC (1 << 10) 274 #define AMDGPU_RESET_DISPLAY (1 << 11) 275 #define AMDGPU_RESET_UVD (1 << 12) 276 #define AMDGPU_RESET_VCE (1 << 13) 277 #define AMDGPU_RESET_VCE1 (1 << 14) 278 279 /* max cursor sizes (in pixels) */ 280 #define CIK_CURSOR_WIDTH 128 281 #define CIK_CURSOR_HEIGHT 128 282 283 /* smart shift bias level limits */ 284 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 285 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 286 287 struct amdgpu_device; 288 struct amdgpu_irq_src; 289 struct amdgpu_fpriv; 290 struct amdgpu_bo_va_mapping; 291 struct kfd_vm_fault_info; 292 struct amdgpu_hive_info; 293 struct amdgpu_reset_context; 294 struct amdgpu_reset_control; 295 296 enum amdgpu_cp_irq { 297 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 298 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 299 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 300 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 301 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 302 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 303 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 304 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 305 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 306 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 307 308 AMDGPU_CP_IRQ_LAST 309 }; 310 311 enum amdgpu_thermal_irq { 312 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 313 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 314 315 AMDGPU_THERMAL_IRQ_LAST 316 }; 317 318 enum amdgpu_kiq_irq { 319 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 320 AMDGPU_CP_KIQ_IRQ_LAST 321 }; 322 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 323 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 324 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 325 #define MAX_KIQ_REG_TRY 1000 326 327 int amdgpu_device_ip_set_clockgating_state(void *dev, 328 enum amd_ip_block_type block_type, 329 enum amd_clockgating_state state); 330 int amdgpu_device_ip_set_powergating_state(void *dev, 331 enum amd_ip_block_type block_type, 332 enum amd_powergating_state state); 333 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 334 u64 *flags); 335 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 336 enum amd_ip_block_type block_type); 337 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 338 enum amd_ip_block_type block_type); 339 340 #define AMDGPU_MAX_IP_NUM 16 341 342 struct amdgpu_ip_block_status { 343 bool valid; 344 bool sw; 345 bool hw; 346 bool late_initialized; 347 bool hang; 348 }; 349 350 struct amdgpu_ip_block_version { 351 const enum amd_ip_block_type type; 352 const u32 major; 353 const u32 minor; 354 const u32 rev; 355 const struct amd_ip_funcs *funcs; 356 }; 357 358 #define HW_REV(_Major, _Minor, _Rev) \ 359 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 360 361 struct amdgpu_ip_block { 362 struct amdgpu_ip_block_status status; 363 const struct amdgpu_ip_block_version *version; 364 }; 365 366 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 367 enum amd_ip_block_type type, 368 u32 major, u32 minor); 369 370 struct amdgpu_ip_block * 371 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 372 enum amd_ip_block_type type); 373 374 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 375 const struct amdgpu_ip_block_version *ip_block_version); 376 377 /* 378 * BIOS. 379 */ 380 bool amdgpu_get_bios(struct amdgpu_device *adev); 381 bool amdgpu_read_bios(struct amdgpu_device *adev); 382 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 383 u8 *bios, u32 length_bytes); 384 /* 385 * Clocks 386 */ 387 388 #define AMDGPU_MAX_PPLL 3 389 390 struct amdgpu_clock { 391 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 392 struct amdgpu_pll spll; 393 struct amdgpu_pll mpll; 394 /* 10 Khz units */ 395 uint32_t default_mclk; 396 uint32_t default_sclk; 397 uint32_t default_dispclk; 398 uint32_t current_dispclk; 399 uint32_t dp_extclk; 400 uint32_t max_pixel_clock; 401 }; 402 403 /* sub-allocation manager, it has to be protected by another lock. 404 * By conception this is an helper for other part of the driver 405 * like the indirect buffer or semaphore, which both have their 406 * locking. 407 * 408 * Principe is simple, we keep a list of sub allocation in offset 409 * order (first entry has offset == 0, last entry has the highest 410 * offset). 411 * 412 * When allocating new object we first check if there is room at 413 * the end total_size - (last_object_offset + last_object_size) >= 414 * alloc_size. If so we allocate new object there. 415 * 416 * When there is not enough room at the end, we start waiting for 417 * each sub object until we reach object_offset+object_size >= 418 * alloc_size, this object then become the sub object we return. 419 * 420 * Alignment can't be bigger than page size. 421 * 422 * Hole are not considered for allocation to keep things simple. 423 * Assumption is that there won't be hole (all object on same 424 * alignment). 425 */ 426 427 struct amdgpu_sa_manager { 428 struct drm_suballoc_manager base; 429 struct amdgpu_bo *bo; 430 uint64_t gpu_addr; 431 void *cpu_ptr; 432 }; 433 434 int amdgpu_fence_slab_init(void); 435 void amdgpu_fence_slab_fini(void); 436 437 /* 438 * IRQS. 439 */ 440 441 struct amdgpu_flip_work { 442 struct delayed_work flip_work; 443 struct work_struct unpin_work; 444 struct amdgpu_device *adev; 445 int crtc_id; 446 u32 target_vblank; 447 uint64_t base; 448 struct drm_pending_vblank_event *event; 449 struct amdgpu_bo *old_abo; 450 unsigned shared_count; 451 struct dma_fence **shared; 452 struct dma_fence_cb cb; 453 bool async; 454 }; 455 456 457 /* 458 * file private structure 459 */ 460 461 struct amdgpu_fpriv { 462 struct amdgpu_vm vm; 463 struct amdgpu_bo_va *prt_va; 464 struct amdgpu_bo_va *csa_va; 465 struct mutex bo_list_lock; 466 struct idr bo_list_handles; 467 struct amdgpu_ctx_mgr ctx_mgr; 468 }; 469 470 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 471 472 /* 473 * Writeback 474 */ 475 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 476 477 struct amdgpu_wb { 478 struct amdgpu_bo *wb_obj; 479 volatile uint32_t *wb; 480 uint64_t gpu_addr; 481 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 482 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 483 }; 484 485 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 486 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 487 488 /* 489 * Benchmarking 490 */ 491 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 492 493 /* 494 * ASIC specific register table accessible by UMD 495 */ 496 struct amdgpu_allowed_register_entry { 497 uint32_t reg_offset; 498 bool grbm_indexed; 499 }; 500 501 enum amd_reset_method { 502 AMD_RESET_METHOD_NONE = -1, 503 AMD_RESET_METHOD_LEGACY = 0, 504 AMD_RESET_METHOD_MODE0, 505 AMD_RESET_METHOD_MODE1, 506 AMD_RESET_METHOD_MODE2, 507 AMD_RESET_METHOD_BACO, 508 AMD_RESET_METHOD_PCI, 509 }; 510 511 struct amdgpu_video_codec_info { 512 u32 codec_type; 513 u32 max_width; 514 u32 max_height; 515 u32 max_pixels_per_frame; 516 u32 max_level; 517 }; 518 519 #define codec_info_build(type, width, height, level) \ 520 .codec_type = type,\ 521 .max_width = width,\ 522 .max_height = height,\ 523 .max_pixels_per_frame = height * width,\ 524 .max_level = level, 525 526 struct amdgpu_video_codecs { 527 const u32 codec_count; 528 const struct amdgpu_video_codec_info *codec_array; 529 }; 530 531 /* 532 * ASIC specific functions. 533 */ 534 struct amdgpu_asic_funcs { 535 bool (*read_disabled_bios)(struct amdgpu_device *adev); 536 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 537 u8 *bios, u32 length_bytes); 538 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 539 u32 sh_num, u32 reg_offset, u32 *value); 540 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 541 int (*reset)(struct amdgpu_device *adev); 542 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 543 /* get the reference clock */ 544 u32 (*get_xclk)(struct amdgpu_device *adev); 545 /* MM block clocks */ 546 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 547 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 548 /* static power management */ 549 int (*get_pcie_lanes)(struct amdgpu_device *adev); 550 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 551 /* get config memsize register */ 552 u32 (*get_config_memsize)(struct amdgpu_device *adev); 553 /* flush hdp write queue */ 554 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 555 /* invalidate hdp read cache */ 556 void (*invalidate_hdp)(struct amdgpu_device *adev, 557 struct amdgpu_ring *ring); 558 /* check if the asic needs a full reset of if soft reset will work */ 559 bool (*need_full_reset)(struct amdgpu_device *adev); 560 /* initialize doorbell layout for specific asic*/ 561 void (*init_doorbell_index)(struct amdgpu_device *adev); 562 /* PCIe bandwidth usage */ 563 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 564 uint64_t *count1); 565 /* do we need to reset the asic at init time (e.g., kexec) */ 566 bool (*need_reset_on_init)(struct amdgpu_device *adev); 567 /* PCIe replay counter */ 568 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 569 /* device supports BACO */ 570 bool (*supports_baco)(struct amdgpu_device *adev); 571 /* pre asic_init quirks */ 572 void (*pre_asic_init)(struct amdgpu_device *adev); 573 /* enter/exit umd stable pstate */ 574 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 575 /* query video codecs */ 576 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 577 const struct amdgpu_video_codecs **codecs); 578 }; 579 580 /* 581 * IOCTL. 582 */ 583 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 584 struct drm_file *filp); 585 586 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 587 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 588 struct drm_file *filp); 589 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 590 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 591 struct drm_file *filp); 592 593 /* VRAM scratch page for HDP bug, default vram page */ 594 struct amdgpu_mem_scratch { 595 struct amdgpu_bo *robj; 596 volatile uint32_t *ptr; 597 u64 gpu_addr; 598 }; 599 600 /* 601 * CGS 602 */ 603 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 604 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 605 606 /* 607 * Core structure, functions and helpers. 608 */ 609 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 610 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 611 612 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 613 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 614 615 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 616 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 617 618 struct amdgpu_mmio_remap { 619 u32 reg_offset; 620 resource_size_t bus_addr; 621 }; 622 623 /* Define the HW IP blocks will be used in driver , add more if necessary */ 624 enum amd_hw_ip_block_type { 625 GC_HWIP = 1, 626 HDP_HWIP, 627 SDMA0_HWIP, 628 SDMA1_HWIP, 629 SDMA2_HWIP, 630 SDMA3_HWIP, 631 SDMA4_HWIP, 632 SDMA5_HWIP, 633 SDMA6_HWIP, 634 SDMA7_HWIP, 635 LSDMA_HWIP, 636 MMHUB_HWIP, 637 ATHUB_HWIP, 638 NBIO_HWIP, 639 MP0_HWIP, 640 MP1_HWIP, 641 UVD_HWIP, 642 VCN_HWIP = UVD_HWIP, 643 JPEG_HWIP = VCN_HWIP, 644 VCN1_HWIP, 645 VCE_HWIP, 646 DF_HWIP, 647 DCE_HWIP, 648 OSSSYS_HWIP, 649 SMUIO_HWIP, 650 PWR_HWIP, 651 NBIF_HWIP, 652 THM_HWIP, 653 CLK_HWIP, 654 UMC_HWIP, 655 RSMU_HWIP, 656 XGMI_HWIP, 657 DCI_HWIP, 658 PCIE_HWIP, 659 MAX_HWIP 660 }; 661 662 #define HWIP_MAX_INSTANCE 28 663 664 #define HW_ID_MAX 300 665 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 666 #define IP_VERSION_MAJ(ver) ((ver) >> 16) 667 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF) 668 #define IP_VERSION_REV(ver) ((ver) & 0xFF) 669 670 struct amd_powerplay { 671 void *pp_handle; 672 const struct amd_pm_funcs *pp_funcs; 673 }; 674 675 struct ip_discovery_top; 676 677 /* polaris10 kickers */ 678 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 679 ((rid == 0xE3) || \ 680 (rid == 0xE4) || \ 681 (rid == 0xE5) || \ 682 (rid == 0xE7) || \ 683 (rid == 0xEF))) || \ 684 ((did == 0x6FDF) && \ 685 ((rid == 0xE7) || \ 686 (rid == 0xEF) || \ 687 (rid == 0xFF)))) 688 689 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 690 ((rid == 0xE1) || \ 691 (rid == 0xF7))) 692 693 /* polaris11 kickers */ 694 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 695 ((rid == 0xE0) || \ 696 (rid == 0xE5))) || \ 697 ((did == 0x67FF) && \ 698 ((rid == 0xCF) || \ 699 (rid == 0xEF) || \ 700 (rid == 0xFF)))) 701 702 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 703 ((rid == 0xE2))) 704 705 /* polaris12 kickers */ 706 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 707 ((rid == 0xC0) || \ 708 (rid == 0xC1) || \ 709 (rid == 0xC3) || \ 710 (rid == 0xC7))) || \ 711 ((did == 0x6981) && \ 712 ((rid == 0x00) || \ 713 (rid == 0x01) || \ 714 (rid == 0x10)))) 715 716 struct amdgpu_mqd_prop { 717 uint64_t mqd_gpu_addr; 718 uint64_t hqd_base_gpu_addr; 719 uint64_t rptr_gpu_addr; 720 uint64_t wptr_gpu_addr; 721 uint32_t queue_size; 722 bool use_doorbell; 723 uint32_t doorbell_index; 724 uint64_t eop_gpu_addr; 725 uint32_t hqd_pipe_priority; 726 uint32_t hqd_queue_priority; 727 bool hqd_active; 728 }; 729 730 struct amdgpu_mqd { 731 unsigned mqd_size; 732 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 733 struct amdgpu_mqd_prop *p); 734 }; 735 736 #define AMDGPU_RESET_MAGIC_NUM 64 737 #define AMDGPU_MAX_DF_PERFMONS 4 738 #define AMDGPU_PRODUCT_NAME_LEN 64 739 struct amdgpu_reset_domain; 740 741 /* 742 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 743 */ 744 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 745 746 struct amdgpu_device { 747 struct device *dev; 748 struct pci_dev *pdev; 749 struct drm_device ddev; 750 751 #ifdef CONFIG_DRM_AMD_ACP 752 struct amdgpu_acp acp; 753 #endif 754 struct amdgpu_hive_info *hive; 755 /* ASIC */ 756 enum amd_asic_type asic_type; 757 uint32_t family; 758 uint32_t rev_id; 759 uint32_t external_rev_id; 760 unsigned long flags; 761 unsigned long apu_flags; 762 int usec_timeout; 763 const struct amdgpu_asic_funcs *asic_funcs; 764 bool shutdown; 765 bool need_swiotlb; 766 bool accel_working; 767 struct notifier_block acpi_nb; 768 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 769 struct debugfs_blob_wrapper debugfs_vbios_blob; 770 struct debugfs_blob_wrapper debugfs_discovery_blob; 771 struct mutex srbm_mutex; 772 /* GRBM index mutex. Protects concurrent access to GRBM index */ 773 struct mutex grbm_idx_mutex; 774 struct dev_pm_domain vga_pm_domain; 775 bool have_disp_power_ref; 776 bool have_atomics_support; 777 778 /* BIOS */ 779 bool is_atom_fw; 780 uint8_t *bios; 781 uint32_t bios_size; 782 uint32_t bios_scratch_reg_offset; 783 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 784 785 /* Register/doorbell mmio */ 786 resource_size_t rmmio_base; 787 resource_size_t rmmio_size; 788 void __iomem *rmmio; 789 /* protects concurrent MM_INDEX/DATA based register access */ 790 spinlock_t mmio_idx_lock; 791 struct amdgpu_mmio_remap rmmio_remap; 792 /* protects concurrent SMC based register access */ 793 spinlock_t smc_idx_lock; 794 amdgpu_rreg_t smc_rreg; 795 amdgpu_wreg_t smc_wreg; 796 /* protects concurrent PCIE register access */ 797 spinlock_t pcie_idx_lock; 798 amdgpu_rreg_t pcie_rreg; 799 amdgpu_wreg_t pcie_wreg; 800 amdgpu_rreg_t pciep_rreg; 801 amdgpu_wreg_t pciep_wreg; 802 amdgpu_rreg64_t pcie_rreg64; 803 amdgpu_wreg64_t pcie_wreg64; 804 /* protects concurrent UVD register access */ 805 spinlock_t uvd_ctx_idx_lock; 806 amdgpu_rreg_t uvd_ctx_rreg; 807 amdgpu_wreg_t uvd_ctx_wreg; 808 /* protects concurrent DIDT register access */ 809 spinlock_t didt_idx_lock; 810 amdgpu_rreg_t didt_rreg; 811 amdgpu_wreg_t didt_wreg; 812 /* protects concurrent gc_cac register access */ 813 spinlock_t gc_cac_idx_lock; 814 amdgpu_rreg_t gc_cac_rreg; 815 amdgpu_wreg_t gc_cac_wreg; 816 /* protects concurrent se_cac register access */ 817 spinlock_t se_cac_idx_lock; 818 amdgpu_rreg_t se_cac_rreg; 819 amdgpu_wreg_t se_cac_wreg; 820 /* protects concurrent ENDPOINT (audio) register access */ 821 spinlock_t audio_endpt_idx_lock; 822 amdgpu_block_rreg_t audio_endpt_rreg; 823 amdgpu_block_wreg_t audio_endpt_wreg; 824 struct amdgpu_doorbell doorbell; 825 826 /* clock/pll info */ 827 struct amdgpu_clock clock; 828 829 /* MC */ 830 struct amdgpu_gmc gmc; 831 struct amdgpu_gart gart; 832 dma_addr_t dummy_page_addr; 833 struct amdgpu_vm_manager vm_manager; 834 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 835 unsigned num_vmhubs; 836 837 /* memory management */ 838 struct amdgpu_mman mman; 839 struct amdgpu_mem_scratch mem_scratch; 840 struct amdgpu_wb wb; 841 atomic64_t num_bytes_moved; 842 atomic64_t num_evictions; 843 atomic64_t num_vram_cpu_page_faults; 844 atomic_t gpu_reset_counter; 845 atomic_t vram_lost_counter; 846 847 /* data for buffer migration throttling */ 848 struct { 849 spinlock_t lock; 850 s64 last_update_us; 851 s64 accum_us; /* accumulated microseconds */ 852 s64 accum_us_vis; /* for visible VRAM */ 853 u32 log2_max_MBps; 854 } mm_stats; 855 856 /* display */ 857 bool enable_virtual_display; 858 struct amdgpu_vkms_output *amdgpu_vkms_output; 859 struct amdgpu_mode_info mode_info; 860 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 861 struct delayed_work hotplug_work; 862 struct amdgpu_irq_src crtc_irq; 863 struct amdgpu_irq_src vline0_irq; 864 struct amdgpu_irq_src vupdate_irq; 865 struct amdgpu_irq_src pageflip_irq; 866 struct amdgpu_irq_src hpd_irq; 867 struct amdgpu_irq_src dmub_trace_irq; 868 struct amdgpu_irq_src dmub_outbox_irq; 869 870 /* rings */ 871 u64 fence_context; 872 unsigned num_rings; 873 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 874 struct dma_fence __rcu *gang_submit; 875 bool ib_pool_ready; 876 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 877 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 878 879 /* interrupts */ 880 struct amdgpu_irq irq; 881 882 /* powerplay */ 883 struct amd_powerplay powerplay; 884 struct amdgpu_pm pm; 885 u64 cg_flags; 886 u32 pg_flags; 887 888 /* nbio */ 889 struct amdgpu_nbio nbio; 890 891 /* hdp */ 892 struct amdgpu_hdp hdp; 893 894 /* smuio */ 895 struct amdgpu_smuio smuio; 896 897 /* mmhub */ 898 struct amdgpu_mmhub mmhub; 899 900 /* gfxhub */ 901 struct amdgpu_gfxhub gfxhub; 902 903 /* gfx */ 904 struct amdgpu_gfx gfx; 905 906 /* sdma */ 907 struct amdgpu_sdma sdma; 908 909 /* lsdma */ 910 struct amdgpu_lsdma lsdma; 911 912 /* uvd */ 913 struct amdgpu_uvd uvd; 914 915 /* vce */ 916 struct amdgpu_vce vce; 917 918 /* vcn */ 919 struct amdgpu_vcn vcn; 920 921 /* jpeg */ 922 struct amdgpu_jpeg jpeg; 923 924 /* firmwares */ 925 struct amdgpu_firmware firmware; 926 927 /* PSP */ 928 struct psp_context psp; 929 930 /* GDS */ 931 struct amdgpu_gds gds; 932 933 /* KFD */ 934 struct amdgpu_kfd_dev kfd; 935 936 /* UMC */ 937 struct amdgpu_umc umc; 938 939 /* display related functionality */ 940 struct amdgpu_display_manager dm; 941 942 /* mes */ 943 bool enable_mes; 944 bool enable_mes_kiq; 945 struct amdgpu_mes mes; 946 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 947 948 /* df */ 949 struct amdgpu_df df; 950 951 /* MCA */ 952 struct amdgpu_mca mca; 953 954 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 955 uint32_t harvest_ip_mask; 956 int num_ip_blocks; 957 struct mutex mn_lock; 958 DECLARE_HASHTABLE(mn_hash, 7); 959 960 /* tracking pinned memory */ 961 atomic64_t vram_pin_size; 962 atomic64_t visible_pin_size; 963 atomic64_t gart_pin_size; 964 965 /* soc15 register offset based on ip, instance and segment */ 966 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 967 968 /* delayed work_func for deferring clockgating during resume */ 969 struct delayed_work delayed_init_work; 970 971 struct amdgpu_virt virt; 972 973 /* link all shadow bo */ 974 struct list_head shadow_list; 975 struct mutex shadow_list_lock; 976 977 /* record hw reset is performed */ 978 bool has_hw_reset; 979 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 980 981 /* s3/s4 mask */ 982 bool in_suspend; 983 bool in_s3; 984 bool in_s4; 985 bool in_s0ix; 986 987 enum pp_mp1_state mp1_state; 988 struct amdgpu_doorbell_index doorbell_index; 989 990 struct mutex notifier_lock; 991 992 int asic_reset_res; 993 struct work_struct xgmi_reset_work; 994 struct list_head reset_list; 995 996 long gfx_timeout; 997 long sdma_timeout; 998 long video_timeout; 999 long compute_timeout; 1000 1001 uint64_t unique_id; 1002 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1003 1004 /* enable runtime pm on the device */ 1005 bool in_runpm; 1006 bool has_pr3; 1007 1008 bool pm_sysfs_en; 1009 bool ucode_sysfs_en; 1010 bool psp_sysfs_en; 1011 1012 /* Chip product information */ 1013 char product_number[20]; 1014 char product_name[AMDGPU_PRODUCT_NAME_LEN]; 1015 char serial[20]; 1016 1017 atomic_t throttling_logging_enabled; 1018 struct ratelimit_state throttling_logging_rs; 1019 uint32_t ras_hw_enabled; 1020 uint32_t ras_enabled; 1021 1022 bool no_hw_access; 1023 struct pci_saved_state *pci_state; 1024 pci_channel_state_t pci_channel_state; 1025 1026 struct amdgpu_reset_control *reset_cntl; 1027 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1028 1029 bool ram_is_direct_mapped; 1030 1031 struct list_head ras_list; 1032 1033 struct ip_discovery_top *ip_top; 1034 1035 struct amdgpu_reset_domain *reset_domain; 1036 1037 struct mutex benchmark_mutex; 1038 1039 /* reset dump register */ 1040 uint32_t *reset_dump_reg_list; 1041 uint32_t *reset_dump_reg_value; 1042 int num_regs; 1043 #ifdef CONFIG_DEV_COREDUMP 1044 struct amdgpu_task_info reset_task_info; 1045 bool reset_vram_lost; 1046 struct timespec64 reset_time; 1047 #endif 1048 1049 bool scpm_enabled; 1050 uint32_t scpm_status; 1051 1052 struct work_struct reset_work; 1053 1054 bool job_hang; 1055 bool dc_enabled; 1056 }; 1057 1058 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1059 { 1060 return container_of(ddev, struct amdgpu_device, ddev); 1061 } 1062 1063 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1064 { 1065 return &adev->ddev; 1066 } 1067 1068 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1069 { 1070 return container_of(bdev, struct amdgpu_device, mman.bdev); 1071 } 1072 1073 int amdgpu_device_init(struct amdgpu_device *adev, 1074 uint32_t flags); 1075 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1076 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1077 1078 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1079 1080 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1081 void *buf, size_t size, bool write); 1082 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1083 void *buf, size_t size, bool write); 1084 1085 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1086 void *buf, size_t size, bool write); 1087 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1088 uint32_t reg, uint32_t acc_flags); 1089 void amdgpu_device_wreg(struct amdgpu_device *adev, 1090 uint32_t reg, uint32_t v, 1091 uint32_t acc_flags); 1092 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1093 uint32_t reg, uint32_t v); 1094 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1095 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1096 1097 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1098 u32 pcie_index, u32 pcie_data, 1099 u32 reg_addr); 1100 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1101 u32 pcie_index, u32 pcie_data, 1102 u32 reg_addr); 1103 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1104 u32 pcie_index, u32 pcie_data, 1105 u32 reg_addr, u32 reg_data); 1106 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1107 u32 pcie_index, u32 pcie_data, 1108 u32 reg_addr, u64 reg_data); 1109 1110 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1111 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1112 1113 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1114 1115 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1116 struct amdgpu_reset_context *reset_context); 1117 1118 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1119 struct amdgpu_reset_context *reset_context); 1120 1121 int emu_soc_asic_init(struct amdgpu_device *adev); 1122 1123 /* 1124 * Registers read & write functions. 1125 */ 1126 #define AMDGPU_REGS_NO_KIQ (1<<1) 1127 #define AMDGPU_REGS_RLC (1<<2) 1128 1129 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1130 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1131 1132 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1133 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1134 1135 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1136 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1137 1138 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1139 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1140 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1141 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1142 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1143 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1144 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1145 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1146 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1147 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1148 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1149 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1150 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1151 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1152 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1153 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1154 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1155 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1156 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1157 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1158 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1159 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1160 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1161 #define WREG32_P(reg, val, mask) \ 1162 do { \ 1163 uint32_t tmp_ = RREG32(reg); \ 1164 tmp_ &= (mask); \ 1165 tmp_ |= ((val) & ~(mask)); \ 1166 WREG32(reg, tmp_); \ 1167 } while (0) 1168 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1169 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1170 #define WREG32_PLL_P(reg, val, mask) \ 1171 do { \ 1172 uint32_t tmp_ = RREG32_PLL(reg); \ 1173 tmp_ &= (mask); \ 1174 tmp_ |= ((val) & ~(mask)); \ 1175 WREG32_PLL(reg, tmp_); \ 1176 } while (0) 1177 1178 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1179 do { \ 1180 u32 tmp = RREG32_SMC(_Reg); \ 1181 tmp &= (_Mask); \ 1182 tmp |= ((_Val) & ~(_Mask)); \ 1183 WREG32_SMC(_Reg, tmp); \ 1184 } while (0) 1185 1186 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1187 1188 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1189 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1190 1191 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1192 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1193 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1194 1195 #define REG_GET_FIELD(value, reg, field) \ 1196 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1197 1198 #define WREG32_FIELD(reg, field, val) \ 1199 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1200 1201 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1202 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1203 1204 /* 1205 * BIOS helpers. 1206 */ 1207 #define RBIOS8(i) (adev->bios[i]) 1208 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1209 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1210 1211 /* 1212 * ASICs macro. 1213 */ 1214 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1215 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1216 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1217 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1218 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1219 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1220 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1221 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1222 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1223 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1224 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1225 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1226 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1227 #define amdgpu_asic_flush_hdp(adev, r) \ 1228 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1229 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1230 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1231 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0)) 1232 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1233 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1234 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1235 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1236 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1237 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1238 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1239 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1240 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1241 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1242 1243 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1244 1245 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 1246 1247 /* Common functions */ 1248 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1249 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1250 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1251 struct amdgpu_job *job, 1252 struct amdgpu_reset_context *reset_context); 1253 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1254 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1255 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1256 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1257 1258 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1259 u64 num_vis_bytes); 1260 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1261 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1262 const u32 *registers, 1263 const u32 array_size); 1264 1265 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1266 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1267 bool amdgpu_device_supports_px(struct drm_device *dev); 1268 bool amdgpu_device_supports_boco(struct drm_device *dev); 1269 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1270 bool amdgpu_device_supports_baco(struct drm_device *dev); 1271 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1272 struct amdgpu_device *peer_adev); 1273 int amdgpu_device_baco_enter(struct drm_device *dev); 1274 int amdgpu_device_baco_exit(struct drm_device *dev); 1275 1276 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1277 struct amdgpu_ring *ring); 1278 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1279 struct amdgpu_ring *ring); 1280 1281 void amdgpu_device_halt(struct amdgpu_device *adev); 1282 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1283 u32 reg); 1284 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1285 u32 reg, u32 v); 1286 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1287 struct dma_fence *gang); 1288 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1289 1290 /* atpx handler */ 1291 #if defined(CONFIG_VGA_SWITCHEROO) 1292 void amdgpu_register_atpx_handler(void); 1293 void amdgpu_unregister_atpx_handler(void); 1294 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1295 bool amdgpu_is_atpx_hybrid(void); 1296 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1297 bool amdgpu_has_atpx(void); 1298 #else 1299 static inline void amdgpu_register_atpx_handler(void) {} 1300 static inline void amdgpu_unregister_atpx_handler(void) {} 1301 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1302 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1303 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1304 static inline bool amdgpu_has_atpx(void) { return false; } 1305 #endif 1306 1307 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1308 void *amdgpu_atpx_get_dhandle(void); 1309 #else 1310 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1311 #endif 1312 1313 /* 1314 * KMS 1315 */ 1316 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1317 extern const int amdgpu_max_kms_ioctl; 1318 1319 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1320 void amdgpu_driver_unload_kms(struct drm_device *dev); 1321 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1322 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1323 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1324 struct drm_file *file_priv); 1325 void amdgpu_driver_release_kms(struct drm_device *dev); 1326 1327 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1328 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1329 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1330 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1331 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1332 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1333 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1334 struct drm_file *filp); 1335 1336 /* 1337 * functions used by amdgpu_encoder.c 1338 */ 1339 struct amdgpu_afmt_acr { 1340 u32 clock; 1341 1342 int n_32khz; 1343 int cts_32khz; 1344 1345 int n_44_1khz; 1346 int cts_44_1khz; 1347 1348 int n_48khz; 1349 int cts_48khz; 1350 1351 }; 1352 1353 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1354 1355 /* amdgpu_acpi.c */ 1356 1357 /* ATCS Device/Driver State */ 1358 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1359 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1360 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1361 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1362 1363 #if defined(CONFIG_ACPI) 1364 int amdgpu_acpi_init(struct amdgpu_device *adev); 1365 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1366 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1367 bool amdgpu_acpi_is_power_shift_control_supported(void); 1368 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1369 u8 perf_req, bool advertise); 1370 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1371 u8 dev_state, bool drv_state); 1372 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1373 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1374 1375 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1376 void amdgpu_acpi_detect(void); 1377 #else 1378 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1379 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1380 static inline void amdgpu_acpi_detect(void) { } 1381 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1382 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1383 u8 dev_state, bool drv_state) { return 0; } 1384 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1385 enum amdgpu_ss ss_state) { return 0; } 1386 #endif 1387 1388 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1389 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1390 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1391 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1392 #else 1393 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1394 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1395 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1396 #endif 1397 1398 #if defined(CONFIG_DRM_AMD_DC) 1399 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1400 #else 1401 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1402 #endif 1403 1404 1405 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1406 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1407 1408 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1409 pci_channel_state_t state); 1410 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1411 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1412 void amdgpu_pci_resume(struct pci_dev *pdev); 1413 1414 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1415 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1416 1417 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1418 1419 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1420 enum amd_clockgating_state state); 1421 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1422 enum amd_powergating_state state); 1423 1424 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1425 { 1426 return amdgpu_gpu_recovery != 0 && 1427 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1428 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1429 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1430 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1431 } 1432 1433 #include "amdgpu_object.h" 1434 1435 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1436 { 1437 return adev->gmc.tmz_enabled; 1438 } 1439 1440 int amdgpu_in_reset(struct amdgpu_device *adev); 1441 1442 #endif 1443