1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 #include <drm/ttm/ttm_execbuf_util.h> 57 58 #include <drm/amdgpu_drm.h> 59 #include <drm/drm_gem.h> 60 #include <drm/drm_ioctl.h> 61 62 #include <kgd_kfd_interface.h> 63 #include "dm_pp_interface.h" 64 #include "kgd_pp_interface.h" 65 66 #include "amd_shared.h" 67 #include "amdgpu_mode.h" 68 #include "amdgpu_ih.h" 69 #include "amdgpu_irq.h" 70 #include "amdgpu_ucode.h" 71 #include "amdgpu_ttm.h" 72 #include "amdgpu_psp.h" 73 #include "amdgpu_gds.h" 74 #include "amdgpu_sync.h" 75 #include "amdgpu_ring.h" 76 #include "amdgpu_vm.h" 77 #include "amdgpu_dpm.h" 78 #include "amdgpu_acp.h" 79 #include "amdgpu_uvd.h" 80 #include "amdgpu_vce.h" 81 #include "amdgpu_vcn.h" 82 #include "amdgpu_jpeg.h" 83 #include "amdgpu_gmc.h" 84 #include "amdgpu_gfx.h" 85 #include "amdgpu_sdma.h" 86 #include "amdgpu_lsdma.h" 87 #include "amdgpu_nbio.h" 88 #include "amdgpu_hdp.h" 89 #include "amdgpu_dm.h" 90 #include "amdgpu_virt.h" 91 #include "amdgpu_csa.h" 92 #include "amdgpu_mes_ctx.h" 93 #include "amdgpu_gart.h" 94 #include "amdgpu_debugfs.h" 95 #include "amdgpu_job.h" 96 #include "amdgpu_bo_list.h" 97 #include "amdgpu_gem.h" 98 #include "amdgpu_doorbell.h" 99 #include "amdgpu_amdkfd.h" 100 #include "amdgpu_discovery.h" 101 #include "amdgpu_mes.h" 102 #include "amdgpu_umc.h" 103 #include "amdgpu_mmhub.h" 104 #include "amdgpu_gfxhub.h" 105 #include "amdgpu_df.h" 106 #include "amdgpu_smuio.h" 107 #include "amdgpu_fdinfo.h" 108 #include "amdgpu_mca.h" 109 #include "amdgpu_ras.h" 110 #include "amdgpu_xcp.h" 111 112 #define MAX_GPU_INSTANCE 64 113 114 struct amdgpu_gpu_instance 115 { 116 struct amdgpu_device *adev; 117 int mgpu_fan_enabled; 118 }; 119 120 struct amdgpu_mgpu_info 121 { 122 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 123 struct mutex mutex; 124 uint32_t num_gpu; 125 uint32_t num_dgpu; 126 uint32_t num_apu; 127 128 /* delayed reset_func for XGMI configuration if necessary */ 129 struct delayed_work delayed_reset_work; 130 bool pending_reset; 131 }; 132 133 enum amdgpu_ss { 134 AMDGPU_SS_DRV_LOAD, 135 AMDGPU_SS_DEV_D0, 136 AMDGPU_SS_DEV_D3, 137 AMDGPU_SS_DRV_UNLOAD 138 }; 139 140 struct amdgpu_watchdog_timer 141 { 142 bool timeout_fatal_disable; 143 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 144 }; 145 146 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 147 148 /* 149 * Modules parameters. 150 */ 151 extern int amdgpu_modeset; 152 extern unsigned int amdgpu_vram_limit; 153 extern int amdgpu_vis_vram_limit; 154 extern int amdgpu_gart_size; 155 extern int amdgpu_gtt_size; 156 extern int amdgpu_moverate; 157 extern int amdgpu_audio; 158 extern int amdgpu_disp_priority; 159 extern int amdgpu_hw_i2c; 160 extern int amdgpu_pcie_gen2; 161 extern int amdgpu_msi; 162 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 163 extern int amdgpu_dpm; 164 extern int amdgpu_fw_load_type; 165 extern int amdgpu_aspm; 166 extern int amdgpu_runtime_pm; 167 extern uint amdgpu_ip_block_mask; 168 extern int amdgpu_bapm; 169 extern int amdgpu_deep_color; 170 extern int amdgpu_vm_size; 171 extern int amdgpu_vm_block_size; 172 extern int amdgpu_vm_fragment_size; 173 extern int amdgpu_vm_fault_stop; 174 extern int amdgpu_vm_debug; 175 extern int amdgpu_vm_update_mode; 176 extern int amdgpu_exp_hw_support; 177 extern int amdgpu_dc; 178 extern int amdgpu_sched_jobs; 179 extern int amdgpu_sched_hw_submission; 180 extern uint amdgpu_pcie_gen_cap; 181 extern uint amdgpu_pcie_lane_cap; 182 extern u64 amdgpu_cg_mask; 183 extern uint amdgpu_pg_mask; 184 extern uint amdgpu_sdma_phase_quantum; 185 extern char *amdgpu_disable_cu; 186 extern char *amdgpu_virtual_display; 187 extern uint amdgpu_pp_feature_mask; 188 extern uint amdgpu_force_long_training; 189 extern int amdgpu_lbpw; 190 extern int amdgpu_compute_multipipe; 191 extern int amdgpu_gpu_recovery; 192 extern int amdgpu_emu_mode; 193 extern uint amdgpu_smu_memory_pool_size; 194 extern int amdgpu_smu_pptable_id; 195 extern uint amdgpu_dc_feature_mask; 196 extern uint amdgpu_freesync_vid_mode; 197 extern uint amdgpu_dc_debug_mask; 198 extern uint amdgpu_dc_visual_confirm; 199 extern uint amdgpu_dm_abm_level; 200 extern int amdgpu_backlight; 201 extern struct amdgpu_mgpu_info mgpu_info; 202 extern int amdgpu_ras_enable; 203 extern uint amdgpu_ras_mask; 204 extern int amdgpu_bad_page_threshold; 205 extern bool amdgpu_ignore_bad_page_threshold; 206 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 207 extern int amdgpu_async_gfx_ring; 208 extern int amdgpu_mcbp; 209 extern int amdgpu_discovery; 210 extern int amdgpu_mes; 211 extern int amdgpu_mes_kiq; 212 extern int amdgpu_noretry; 213 extern int amdgpu_force_asic_type; 214 extern int amdgpu_smartshift_bias; 215 extern int amdgpu_use_xgmi_p2p; 216 extern int amdgpu_mtype_local; 217 #ifdef CONFIG_HSA_AMD 218 extern int sched_policy; 219 extern bool debug_evictions; 220 extern bool no_system_mem_limit; 221 extern int halt_if_hws_hang; 222 #else 223 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 224 static const bool __maybe_unused debug_evictions; /* = false */ 225 static const bool __maybe_unused no_system_mem_limit; 226 static const int __maybe_unused halt_if_hws_hang; 227 #endif 228 #ifdef CONFIG_HSA_AMD_P2P 229 extern bool pcie_p2p; 230 #endif 231 232 extern int amdgpu_tmz; 233 extern int amdgpu_reset_method; 234 235 #ifdef CONFIG_DRM_AMDGPU_SI 236 extern int amdgpu_si_support; 237 #endif 238 #ifdef CONFIG_DRM_AMDGPU_CIK 239 extern int amdgpu_cik_support; 240 #endif 241 extern int amdgpu_num_kcq; 242 243 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 244 extern int amdgpu_vcnfw_log; 245 extern int amdgpu_sg_display; 246 247 extern int amdgpu_user_partt_mode; 248 249 #define AMDGPU_VM_MAX_NUM_CTX 4096 250 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 251 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 252 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 253 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 254 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 255 #define AMDGPUFB_CONN_LIMIT 4 256 #define AMDGPU_BIOS_NUM_SCRATCH 16 257 258 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 259 260 /* hard reset data */ 261 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 262 263 /* reset flags */ 264 #define AMDGPU_RESET_GFX (1 << 0) 265 #define AMDGPU_RESET_COMPUTE (1 << 1) 266 #define AMDGPU_RESET_DMA (1 << 2) 267 #define AMDGPU_RESET_CP (1 << 3) 268 #define AMDGPU_RESET_GRBM (1 << 4) 269 #define AMDGPU_RESET_DMA1 (1 << 5) 270 #define AMDGPU_RESET_RLC (1 << 6) 271 #define AMDGPU_RESET_SEM (1 << 7) 272 #define AMDGPU_RESET_IH (1 << 8) 273 #define AMDGPU_RESET_VMC (1 << 9) 274 #define AMDGPU_RESET_MC (1 << 10) 275 #define AMDGPU_RESET_DISPLAY (1 << 11) 276 #define AMDGPU_RESET_UVD (1 << 12) 277 #define AMDGPU_RESET_VCE (1 << 13) 278 #define AMDGPU_RESET_VCE1 (1 << 14) 279 280 /* max cursor sizes (in pixels) */ 281 #define CIK_CURSOR_WIDTH 128 282 #define CIK_CURSOR_HEIGHT 128 283 284 /* smart shift bias level limits */ 285 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 286 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 287 288 struct amdgpu_xcp_mgr; 289 struct amdgpu_device; 290 struct amdgpu_irq_src; 291 struct amdgpu_fpriv; 292 struct amdgpu_bo_va_mapping; 293 struct kfd_vm_fault_info; 294 struct amdgpu_hive_info; 295 struct amdgpu_reset_context; 296 struct amdgpu_reset_control; 297 298 enum amdgpu_cp_irq { 299 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 300 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 301 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 302 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 303 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 304 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 305 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 306 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 307 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 308 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 309 310 AMDGPU_CP_IRQ_LAST 311 }; 312 313 enum amdgpu_thermal_irq { 314 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 315 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 316 317 AMDGPU_THERMAL_IRQ_LAST 318 }; 319 320 enum amdgpu_kiq_irq { 321 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 322 AMDGPU_CP_KIQ_IRQ_LAST 323 }; 324 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 325 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 326 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 327 #define MAX_KIQ_REG_TRY 1000 328 329 int amdgpu_device_ip_set_clockgating_state(void *dev, 330 enum amd_ip_block_type block_type, 331 enum amd_clockgating_state state); 332 int amdgpu_device_ip_set_powergating_state(void *dev, 333 enum amd_ip_block_type block_type, 334 enum amd_powergating_state state); 335 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 336 u64 *flags); 337 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 338 enum amd_ip_block_type block_type); 339 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 340 enum amd_ip_block_type block_type); 341 342 #define AMDGPU_MAX_IP_NUM 16 343 344 struct amdgpu_ip_block_status { 345 bool valid; 346 bool sw; 347 bool hw; 348 bool late_initialized; 349 bool hang; 350 }; 351 352 struct amdgpu_ip_block_version { 353 const enum amd_ip_block_type type; 354 const u32 major; 355 const u32 minor; 356 const u32 rev; 357 const struct amd_ip_funcs *funcs; 358 }; 359 360 #define HW_REV(_Major, _Minor, _Rev) \ 361 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 362 363 struct amdgpu_ip_block { 364 struct amdgpu_ip_block_status status; 365 const struct amdgpu_ip_block_version *version; 366 }; 367 368 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 369 enum amd_ip_block_type type, 370 u32 major, u32 minor); 371 372 struct amdgpu_ip_block * 373 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 374 enum amd_ip_block_type type); 375 376 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 377 const struct amdgpu_ip_block_version *ip_block_version); 378 379 /* 380 * BIOS. 381 */ 382 bool amdgpu_get_bios(struct amdgpu_device *adev); 383 bool amdgpu_read_bios(struct amdgpu_device *adev); 384 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 385 u8 *bios, u32 length_bytes); 386 /* 387 * Clocks 388 */ 389 390 #define AMDGPU_MAX_PPLL 3 391 392 struct amdgpu_clock { 393 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 394 struct amdgpu_pll spll; 395 struct amdgpu_pll mpll; 396 /* 10 Khz units */ 397 uint32_t default_mclk; 398 uint32_t default_sclk; 399 uint32_t default_dispclk; 400 uint32_t current_dispclk; 401 uint32_t dp_extclk; 402 uint32_t max_pixel_clock; 403 }; 404 405 /* sub-allocation manager, it has to be protected by another lock. 406 * By conception this is an helper for other part of the driver 407 * like the indirect buffer or semaphore, which both have their 408 * locking. 409 * 410 * Principe is simple, we keep a list of sub allocation in offset 411 * order (first entry has offset == 0, last entry has the highest 412 * offset). 413 * 414 * When allocating new object we first check if there is room at 415 * the end total_size - (last_object_offset + last_object_size) >= 416 * alloc_size. If so we allocate new object there. 417 * 418 * When there is not enough room at the end, we start waiting for 419 * each sub object until we reach object_offset+object_size >= 420 * alloc_size, this object then become the sub object we return. 421 * 422 * Alignment can't be bigger than page size. 423 * 424 * Hole are not considered for allocation to keep things simple. 425 * Assumption is that there won't be hole (all object on same 426 * alignment). 427 */ 428 429 struct amdgpu_sa_manager { 430 struct drm_suballoc_manager base; 431 struct amdgpu_bo *bo; 432 uint64_t gpu_addr; 433 void *cpu_ptr; 434 }; 435 436 int amdgpu_fence_slab_init(void); 437 void amdgpu_fence_slab_fini(void); 438 439 /* 440 * IRQS. 441 */ 442 443 struct amdgpu_flip_work { 444 struct delayed_work flip_work; 445 struct work_struct unpin_work; 446 struct amdgpu_device *adev; 447 int crtc_id; 448 u32 target_vblank; 449 uint64_t base; 450 struct drm_pending_vblank_event *event; 451 struct amdgpu_bo *old_abo; 452 unsigned shared_count; 453 struct dma_fence **shared; 454 struct dma_fence_cb cb; 455 bool async; 456 }; 457 458 459 /* 460 * file private structure 461 */ 462 463 struct amdgpu_fpriv { 464 struct amdgpu_vm vm; 465 struct amdgpu_bo_va *prt_va; 466 struct amdgpu_bo_va *csa_va; 467 struct mutex bo_list_lock; 468 struct idr bo_list_handles; 469 struct amdgpu_ctx_mgr ctx_mgr; 470 /** GPU partition selection */ 471 uint32_t xcp_id; 472 }; 473 474 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 475 476 /* 477 * Writeback 478 */ 479 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 480 481 struct amdgpu_wb { 482 struct amdgpu_bo *wb_obj; 483 volatile uint32_t *wb; 484 uint64_t gpu_addr; 485 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 486 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 487 }; 488 489 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 490 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 491 492 /* 493 * Benchmarking 494 */ 495 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 496 497 /* 498 * ASIC specific register table accessible by UMD 499 */ 500 struct amdgpu_allowed_register_entry { 501 uint32_t reg_offset; 502 bool grbm_indexed; 503 }; 504 505 enum amd_reset_method { 506 AMD_RESET_METHOD_NONE = -1, 507 AMD_RESET_METHOD_LEGACY = 0, 508 AMD_RESET_METHOD_MODE0, 509 AMD_RESET_METHOD_MODE1, 510 AMD_RESET_METHOD_MODE2, 511 AMD_RESET_METHOD_BACO, 512 AMD_RESET_METHOD_PCI, 513 }; 514 515 struct amdgpu_video_codec_info { 516 u32 codec_type; 517 u32 max_width; 518 u32 max_height; 519 u32 max_pixels_per_frame; 520 u32 max_level; 521 }; 522 523 #define codec_info_build(type, width, height, level) \ 524 .codec_type = type,\ 525 .max_width = width,\ 526 .max_height = height,\ 527 .max_pixels_per_frame = height * width,\ 528 .max_level = level, 529 530 struct amdgpu_video_codecs { 531 const u32 codec_count; 532 const struct amdgpu_video_codec_info *codec_array; 533 }; 534 535 /* 536 * ASIC specific functions. 537 */ 538 struct amdgpu_asic_funcs { 539 bool (*read_disabled_bios)(struct amdgpu_device *adev); 540 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 541 u8 *bios, u32 length_bytes); 542 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 543 u32 sh_num, u32 reg_offset, u32 *value); 544 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 545 int (*reset)(struct amdgpu_device *adev); 546 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 547 /* get the reference clock */ 548 u32 (*get_xclk)(struct amdgpu_device *adev); 549 /* MM block clocks */ 550 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 551 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 552 /* static power management */ 553 int (*get_pcie_lanes)(struct amdgpu_device *adev); 554 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 555 /* get config memsize register */ 556 u32 (*get_config_memsize)(struct amdgpu_device *adev); 557 /* flush hdp write queue */ 558 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 559 /* invalidate hdp read cache */ 560 void (*invalidate_hdp)(struct amdgpu_device *adev, 561 struct amdgpu_ring *ring); 562 /* check if the asic needs a full reset of if soft reset will work */ 563 bool (*need_full_reset)(struct amdgpu_device *adev); 564 /* initialize doorbell layout for specific asic*/ 565 void (*init_doorbell_index)(struct amdgpu_device *adev); 566 /* PCIe bandwidth usage */ 567 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 568 uint64_t *count1); 569 /* do we need to reset the asic at init time (e.g., kexec) */ 570 bool (*need_reset_on_init)(struct amdgpu_device *adev); 571 /* PCIe replay counter */ 572 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 573 /* device supports BACO */ 574 bool (*supports_baco)(struct amdgpu_device *adev); 575 /* pre asic_init quirks */ 576 void (*pre_asic_init)(struct amdgpu_device *adev); 577 /* enter/exit umd stable pstate */ 578 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 579 /* query video codecs */ 580 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 581 const struct amdgpu_video_codecs **codecs); 582 /* encode "> 32bits" smn addressing */ 583 u64 (*encode_ext_smn_addressing)(int ext_id); 584 }; 585 586 /* 587 * IOCTL. 588 */ 589 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 590 struct drm_file *filp); 591 592 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 593 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 594 struct drm_file *filp); 595 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 596 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 597 struct drm_file *filp); 598 599 /* VRAM scratch page for HDP bug, default vram page */ 600 struct amdgpu_mem_scratch { 601 struct amdgpu_bo *robj; 602 volatile uint32_t *ptr; 603 u64 gpu_addr; 604 }; 605 606 /* 607 * CGS 608 */ 609 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 610 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 611 612 /* 613 * Core structure, functions and helpers. 614 */ 615 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 616 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 617 618 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 619 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 620 621 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 622 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 623 624 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 625 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 626 627 struct amdgpu_mmio_remap { 628 u32 reg_offset; 629 resource_size_t bus_addr; 630 }; 631 632 /* Define the HW IP blocks will be used in driver , add more if necessary */ 633 enum amd_hw_ip_block_type { 634 GC_HWIP = 1, 635 HDP_HWIP, 636 SDMA0_HWIP, 637 SDMA1_HWIP, 638 SDMA2_HWIP, 639 SDMA3_HWIP, 640 SDMA4_HWIP, 641 SDMA5_HWIP, 642 SDMA6_HWIP, 643 SDMA7_HWIP, 644 LSDMA_HWIP, 645 MMHUB_HWIP, 646 ATHUB_HWIP, 647 NBIO_HWIP, 648 MP0_HWIP, 649 MP1_HWIP, 650 UVD_HWIP, 651 VCN_HWIP = UVD_HWIP, 652 JPEG_HWIP = VCN_HWIP, 653 VCN1_HWIP, 654 VCE_HWIP, 655 DF_HWIP, 656 DCE_HWIP, 657 OSSSYS_HWIP, 658 SMUIO_HWIP, 659 PWR_HWIP, 660 NBIF_HWIP, 661 THM_HWIP, 662 CLK_HWIP, 663 UMC_HWIP, 664 RSMU_HWIP, 665 XGMI_HWIP, 666 DCI_HWIP, 667 PCIE_HWIP, 668 MAX_HWIP 669 }; 670 671 #define HWIP_MAX_INSTANCE 44 672 673 #define HW_ID_MAX 300 674 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 675 #define IP_VERSION_MAJ(ver) ((ver) >> 16) 676 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF) 677 #define IP_VERSION_REV(ver) ((ver) & 0xFF) 678 679 struct amdgpu_ip_map_info { 680 /* Map of logical to actual dev instances/mask */ 681 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 682 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 683 enum amd_hw_ip_block_type block, 684 int8_t inst); 685 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 686 enum amd_hw_ip_block_type block, 687 uint32_t mask); 688 }; 689 690 struct amd_powerplay { 691 void *pp_handle; 692 const struct amd_pm_funcs *pp_funcs; 693 }; 694 695 struct ip_discovery_top; 696 697 /* polaris10 kickers */ 698 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 699 ((rid == 0xE3) || \ 700 (rid == 0xE4) || \ 701 (rid == 0xE5) || \ 702 (rid == 0xE7) || \ 703 (rid == 0xEF))) || \ 704 ((did == 0x6FDF) && \ 705 ((rid == 0xE7) || \ 706 (rid == 0xEF) || \ 707 (rid == 0xFF)))) 708 709 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 710 ((rid == 0xE1) || \ 711 (rid == 0xF7))) 712 713 /* polaris11 kickers */ 714 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 715 ((rid == 0xE0) || \ 716 (rid == 0xE5))) || \ 717 ((did == 0x67FF) && \ 718 ((rid == 0xCF) || \ 719 (rid == 0xEF) || \ 720 (rid == 0xFF)))) 721 722 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 723 ((rid == 0xE2))) 724 725 /* polaris12 kickers */ 726 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 727 ((rid == 0xC0) || \ 728 (rid == 0xC1) || \ 729 (rid == 0xC3) || \ 730 (rid == 0xC7))) || \ 731 ((did == 0x6981) && \ 732 ((rid == 0x00) || \ 733 (rid == 0x01) || \ 734 (rid == 0x10)))) 735 736 struct amdgpu_mqd_prop { 737 uint64_t mqd_gpu_addr; 738 uint64_t hqd_base_gpu_addr; 739 uint64_t rptr_gpu_addr; 740 uint64_t wptr_gpu_addr; 741 uint32_t queue_size; 742 bool use_doorbell; 743 uint32_t doorbell_index; 744 uint64_t eop_gpu_addr; 745 uint32_t hqd_pipe_priority; 746 uint32_t hqd_queue_priority; 747 bool hqd_active; 748 }; 749 750 struct amdgpu_mqd { 751 unsigned mqd_size; 752 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 753 struct amdgpu_mqd_prop *p); 754 }; 755 756 #define AMDGPU_RESET_MAGIC_NUM 64 757 #define AMDGPU_MAX_DF_PERFMONS 4 758 #define AMDGPU_PRODUCT_NAME_LEN 64 759 struct amdgpu_reset_domain; 760 761 /* 762 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 763 */ 764 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 765 766 struct amdgpu_device { 767 struct device *dev; 768 struct pci_dev *pdev; 769 struct drm_device ddev; 770 771 #ifdef CONFIG_DRM_AMD_ACP 772 struct amdgpu_acp acp; 773 #endif 774 struct amdgpu_hive_info *hive; 775 struct amdgpu_xcp_mgr *xcp_mgr; 776 /* ASIC */ 777 enum amd_asic_type asic_type; 778 uint32_t family; 779 uint32_t rev_id; 780 uint32_t external_rev_id; 781 unsigned long flags; 782 unsigned long apu_flags; 783 int usec_timeout; 784 const struct amdgpu_asic_funcs *asic_funcs; 785 bool shutdown; 786 bool need_swiotlb; 787 bool accel_working; 788 struct notifier_block acpi_nb; 789 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 790 struct debugfs_blob_wrapper debugfs_vbios_blob; 791 struct debugfs_blob_wrapper debugfs_discovery_blob; 792 struct mutex srbm_mutex; 793 /* GRBM index mutex. Protects concurrent access to GRBM index */ 794 struct mutex grbm_idx_mutex; 795 struct dev_pm_domain vga_pm_domain; 796 bool have_disp_power_ref; 797 bool have_atomics_support; 798 799 /* BIOS */ 800 bool is_atom_fw; 801 uint8_t *bios; 802 uint32_t bios_size; 803 uint32_t bios_scratch_reg_offset; 804 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 805 806 /* Register/doorbell mmio */ 807 resource_size_t rmmio_base; 808 resource_size_t rmmio_size; 809 void __iomem *rmmio; 810 /* protects concurrent MM_INDEX/DATA based register access */ 811 spinlock_t mmio_idx_lock; 812 struct amdgpu_mmio_remap rmmio_remap; 813 /* protects concurrent SMC based register access */ 814 spinlock_t smc_idx_lock; 815 amdgpu_rreg_t smc_rreg; 816 amdgpu_wreg_t smc_wreg; 817 /* protects concurrent PCIE register access */ 818 spinlock_t pcie_idx_lock; 819 amdgpu_rreg_t pcie_rreg; 820 amdgpu_wreg_t pcie_wreg; 821 amdgpu_rreg_t pciep_rreg; 822 amdgpu_wreg_t pciep_wreg; 823 amdgpu_rreg_ext_t pcie_rreg_ext; 824 amdgpu_wreg_ext_t pcie_wreg_ext; 825 amdgpu_rreg64_t pcie_rreg64; 826 amdgpu_wreg64_t pcie_wreg64; 827 /* protects concurrent UVD register access */ 828 spinlock_t uvd_ctx_idx_lock; 829 amdgpu_rreg_t uvd_ctx_rreg; 830 amdgpu_wreg_t uvd_ctx_wreg; 831 /* protects concurrent DIDT register access */ 832 spinlock_t didt_idx_lock; 833 amdgpu_rreg_t didt_rreg; 834 amdgpu_wreg_t didt_wreg; 835 /* protects concurrent gc_cac register access */ 836 spinlock_t gc_cac_idx_lock; 837 amdgpu_rreg_t gc_cac_rreg; 838 amdgpu_wreg_t gc_cac_wreg; 839 /* protects concurrent se_cac register access */ 840 spinlock_t se_cac_idx_lock; 841 amdgpu_rreg_t se_cac_rreg; 842 amdgpu_wreg_t se_cac_wreg; 843 /* protects concurrent ENDPOINT (audio) register access */ 844 spinlock_t audio_endpt_idx_lock; 845 amdgpu_block_rreg_t audio_endpt_rreg; 846 amdgpu_block_wreg_t audio_endpt_wreg; 847 struct amdgpu_doorbell doorbell; 848 849 /* clock/pll info */ 850 struct amdgpu_clock clock; 851 852 /* MC */ 853 struct amdgpu_gmc gmc; 854 struct amdgpu_gart gart; 855 dma_addr_t dummy_page_addr; 856 struct amdgpu_vm_manager vm_manager; 857 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 858 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 859 860 /* memory management */ 861 struct amdgpu_mman mman; 862 struct amdgpu_mem_scratch mem_scratch; 863 struct amdgpu_wb wb; 864 atomic64_t num_bytes_moved; 865 atomic64_t num_evictions; 866 atomic64_t num_vram_cpu_page_faults; 867 atomic_t gpu_reset_counter; 868 atomic_t vram_lost_counter; 869 870 /* data for buffer migration throttling */ 871 struct { 872 spinlock_t lock; 873 s64 last_update_us; 874 s64 accum_us; /* accumulated microseconds */ 875 s64 accum_us_vis; /* for visible VRAM */ 876 u32 log2_max_MBps; 877 } mm_stats; 878 879 /* display */ 880 bool enable_virtual_display; 881 struct amdgpu_vkms_output *amdgpu_vkms_output; 882 struct amdgpu_mode_info mode_info; 883 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 884 struct delayed_work hotplug_work; 885 struct amdgpu_irq_src crtc_irq; 886 struct amdgpu_irq_src vline0_irq; 887 struct amdgpu_irq_src vupdate_irq; 888 struct amdgpu_irq_src pageflip_irq; 889 struct amdgpu_irq_src hpd_irq; 890 struct amdgpu_irq_src dmub_trace_irq; 891 struct amdgpu_irq_src dmub_outbox_irq; 892 893 /* rings */ 894 u64 fence_context; 895 unsigned num_rings; 896 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 897 struct dma_fence __rcu *gang_submit; 898 bool ib_pool_ready; 899 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 900 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 901 902 /* interrupts */ 903 struct amdgpu_irq irq; 904 905 /* powerplay */ 906 struct amd_powerplay powerplay; 907 struct amdgpu_pm pm; 908 u64 cg_flags; 909 u32 pg_flags; 910 911 /* nbio */ 912 struct amdgpu_nbio nbio; 913 914 /* hdp */ 915 struct amdgpu_hdp hdp; 916 917 /* smuio */ 918 struct amdgpu_smuio smuio; 919 920 /* mmhub */ 921 struct amdgpu_mmhub mmhub; 922 923 /* gfxhub */ 924 struct amdgpu_gfxhub gfxhub; 925 926 /* gfx */ 927 struct amdgpu_gfx gfx; 928 929 /* sdma */ 930 struct amdgpu_sdma sdma; 931 932 /* lsdma */ 933 struct amdgpu_lsdma lsdma; 934 935 /* uvd */ 936 struct amdgpu_uvd uvd; 937 938 /* vce */ 939 struct amdgpu_vce vce; 940 941 /* vcn */ 942 struct amdgpu_vcn vcn; 943 944 /* jpeg */ 945 struct amdgpu_jpeg jpeg; 946 947 /* firmwares */ 948 struct amdgpu_firmware firmware; 949 950 /* PSP */ 951 struct psp_context psp; 952 953 /* GDS */ 954 struct amdgpu_gds gds; 955 956 /* KFD */ 957 struct amdgpu_kfd_dev kfd; 958 959 /* UMC */ 960 struct amdgpu_umc umc; 961 962 /* display related functionality */ 963 struct amdgpu_display_manager dm; 964 965 /* mes */ 966 bool enable_mes; 967 bool enable_mes_kiq; 968 struct amdgpu_mes mes; 969 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 970 971 /* df */ 972 struct amdgpu_df df; 973 974 /* MCA */ 975 struct amdgpu_mca mca; 976 977 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 978 uint32_t harvest_ip_mask; 979 int num_ip_blocks; 980 struct mutex mn_lock; 981 DECLARE_HASHTABLE(mn_hash, 7); 982 983 /* tracking pinned memory */ 984 atomic64_t vram_pin_size; 985 atomic64_t visible_pin_size; 986 atomic64_t gart_pin_size; 987 988 /* soc15 register offset based on ip, instance and segment */ 989 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 990 struct amdgpu_ip_map_info ip_map; 991 992 /* delayed work_func for deferring clockgating during resume */ 993 struct delayed_work delayed_init_work; 994 995 struct amdgpu_virt virt; 996 997 /* link all shadow bo */ 998 struct list_head shadow_list; 999 struct mutex shadow_list_lock; 1000 1001 /* record hw reset is performed */ 1002 bool has_hw_reset; 1003 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1004 1005 /* s3/s4 mask */ 1006 bool in_suspend; 1007 bool in_s3; 1008 bool in_s4; 1009 bool in_s0ix; 1010 1011 enum pp_mp1_state mp1_state; 1012 struct amdgpu_doorbell_index doorbell_index; 1013 1014 struct mutex notifier_lock; 1015 1016 int asic_reset_res; 1017 struct work_struct xgmi_reset_work; 1018 struct list_head reset_list; 1019 1020 long gfx_timeout; 1021 long sdma_timeout; 1022 long video_timeout; 1023 long compute_timeout; 1024 1025 uint64_t unique_id; 1026 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1027 1028 /* enable runtime pm on the device */ 1029 bool in_runpm; 1030 bool has_pr3; 1031 1032 bool ucode_sysfs_en; 1033 bool psp_sysfs_en; 1034 1035 /* Chip product information */ 1036 char product_number[20]; 1037 char product_name[AMDGPU_PRODUCT_NAME_LEN]; 1038 char serial[20]; 1039 1040 atomic_t throttling_logging_enabled; 1041 struct ratelimit_state throttling_logging_rs; 1042 uint32_t ras_hw_enabled; 1043 uint32_t ras_enabled; 1044 1045 bool no_hw_access; 1046 struct pci_saved_state *pci_state; 1047 pci_channel_state_t pci_channel_state; 1048 1049 struct amdgpu_reset_control *reset_cntl; 1050 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1051 1052 bool ram_is_direct_mapped; 1053 1054 struct list_head ras_list; 1055 1056 struct ip_discovery_top *ip_top; 1057 1058 struct amdgpu_reset_domain *reset_domain; 1059 1060 struct mutex benchmark_mutex; 1061 1062 /* reset dump register */ 1063 uint32_t *reset_dump_reg_list; 1064 uint32_t *reset_dump_reg_value; 1065 int num_regs; 1066 #ifdef CONFIG_DEV_COREDUMP 1067 struct amdgpu_task_info reset_task_info; 1068 bool reset_vram_lost; 1069 struct timespec64 reset_time; 1070 #endif 1071 1072 bool scpm_enabled; 1073 uint32_t scpm_status; 1074 1075 struct work_struct reset_work; 1076 1077 bool job_hang; 1078 bool dc_enabled; 1079 /* Mask of active clusters */ 1080 uint32_t aid_mask; 1081 }; 1082 1083 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1084 { 1085 return container_of(ddev, struct amdgpu_device, ddev); 1086 } 1087 1088 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1089 { 1090 return &adev->ddev; 1091 } 1092 1093 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1094 { 1095 return container_of(bdev, struct amdgpu_device, mman.bdev); 1096 } 1097 1098 int amdgpu_device_init(struct amdgpu_device *adev, 1099 uint32_t flags); 1100 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1101 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1102 1103 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1104 1105 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1106 void *buf, size_t size, bool write); 1107 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1108 void *buf, size_t size, bool write); 1109 1110 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1111 void *buf, size_t size, bool write); 1112 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1113 uint32_t inst, uint32_t reg_addr, char reg_name[], 1114 uint32_t expected_value, uint32_t mask); 1115 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1116 uint32_t reg, uint32_t acc_flags); 1117 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1118 u64 reg_addr); 1119 void amdgpu_device_wreg(struct amdgpu_device *adev, 1120 uint32_t reg, uint32_t v, 1121 uint32_t acc_flags); 1122 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1123 u64 reg_addr, u32 reg_data); 1124 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1125 uint32_t reg, uint32_t v); 1126 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1127 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1128 1129 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1130 u32 reg_addr); 1131 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1132 u32 reg_addr); 1133 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1134 u32 reg_addr, u32 reg_data); 1135 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1136 u32 reg_addr, u64 reg_data); 1137 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1138 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1139 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1140 1141 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1142 1143 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1144 struct amdgpu_reset_context *reset_context); 1145 1146 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1147 struct amdgpu_reset_context *reset_context); 1148 1149 int emu_soc_asic_init(struct amdgpu_device *adev); 1150 1151 /* 1152 * Registers read & write functions. 1153 */ 1154 #define AMDGPU_REGS_NO_KIQ (1<<1) 1155 #define AMDGPU_REGS_RLC (1<<2) 1156 1157 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1158 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1159 1160 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1161 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1162 1163 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1164 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1165 1166 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1167 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1168 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1169 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1170 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1171 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1172 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1173 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1174 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1175 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1176 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1177 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1178 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1179 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1180 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1181 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1182 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1183 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1184 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1185 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1186 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1187 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1188 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1189 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1190 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1191 #define WREG32_P(reg, val, mask) \ 1192 do { \ 1193 uint32_t tmp_ = RREG32(reg); \ 1194 tmp_ &= (mask); \ 1195 tmp_ |= ((val) & ~(mask)); \ 1196 WREG32(reg, tmp_); \ 1197 } while (0) 1198 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1199 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1200 #define WREG32_PLL_P(reg, val, mask) \ 1201 do { \ 1202 uint32_t tmp_ = RREG32_PLL(reg); \ 1203 tmp_ &= (mask); \ 1204 tmp_ |= ((val) & ~(mask)); \ 1205 WREG32_PLL(reg, tmp_); \ 1206 } while (0) 1207 1208 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1209 do { \ 1210 u32 tmp = RREG32_SMC(_Reg); \ 1211 tmp &= (_Mask); \ 1212 tmp |= ((_Val) & ~(_Mask)); \ 1213 WREG32_SMC(_Reg, tmp); \ 1214 } while (0) 1215 1216 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1217 1218 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1219 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1220 1221 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1222 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1223 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1224 1225 #define REG_GET_FIELD(value, reg, field) \ 1226 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1227 1228 #define WREG32_FIELD(reg, field, val) \ 1229 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1230 1231 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1232 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1233 1234 /* 1235 * BIOS helpers. 1236 */ 1237 #define RBIOS8(i) (adev->bios[i]) 1238 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1239 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1240 1241 /* 1242 * ASICs macro. 1243 */ 1244 #define amdgpu_asic_set_vga_state(adev, state) \ 1245 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1246 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1247 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1248 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1249 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1250 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1251 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1252 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1253 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1254 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1255 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1256 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1257 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1258 #define amdgpu_asic_flush_hdp(adev, r) \ 1259 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1260 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1261 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1262 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1263 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1264 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1265 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1266 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1267 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1268 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1269 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1270 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1271 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1272 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1273 1274 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1275 1276 #define for_each_inst(i, inst_mask) \ 1277 for (i = ffs(inst_mask) - 1; inst_mask; \ 1278 inst_mask &= ~(1U << i), i = ffs(inst_mask) - 1) 1279 1280 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 1281 1282 /* Common functions */ 1283 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1284 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1285 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1286 struct amdgpu_job *job, 1287 struct amdgpu_reset_context *reset_context); 1288 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1289 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1290 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1291 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1292 bool amdgpu_device_aspm_support_quirk(void); 1293 1294 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1295 u64 num_vis_bytes); 1296 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1297 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1298 const u32 *registers, 1299 const u32 array_size); 1300 1301 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1302 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1303 bool amdgpu_device_supports_px(struct drm_device *dev); 1304 bool amdgpu_device_supports_boco(struct drm_device *dev); 1305 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1306 bool amdgpu_device_supports_baco(struct drm_device *dev); 1307 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1308 struct amdgpu_device *peer_adev); 1309 int amdgpu_device_baco_enter(struct drm_device *dev); 1310 int amdgpu_device_baco_exit(struct drm_device *dev); 1311 1312 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1313 struct amdgpu_ring *ring); 1314 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1315 struct amdgpu_ring *ring); 1316 1317 void amdgpu_device_halt(struct amdgpu_device *adev); 1318 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1319 u32 reg); 1320 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1321 u32 reg, u32 v); 1322 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1323 struct dma_fence *gang); 1324 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1325 1326 /* atpx handler */ 1327 #if defined(CONFIG_VGA_SWITCHEROO) 1328 void amdgpu_register_atpx_handler(void); 1329 void amdgpu_unregister_atpx_handler(void); 1330 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1331 bool amdgpu_is_atpx_hybrid(void); 1332 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1333 bool amdgpu_has_atpx(void); 1334 #else 1335 static inline void amdgpu_register_atpx_handler(void) {} 1336 static inline void amdgpu_unregister_atpx_handler(void) {} 1337 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1338 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1339 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1340 static inline bool amdgpu_has_atpx(void) { return false; } 1341 #endif 1342 1343 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1344 void *amdgpu_atpx_get_dhandle(void); 1345 #else 1346 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1347 #endif 1348 1349 /* 1350 * KMS 1351 */ 1352 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1353 extern const int amdgpu_max_kms_ioctl; 1354 1355 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1356 void amdgpu_driver_unload_kms(struct drm_device *dev); 1357 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1358 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1359 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1360 struct drm_file *file_priv); 1361 void amdgpu_driver_release_kms(struct drm_device *dev); 1362 1363 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1364 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1365 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1366 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1367 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1368 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1369 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1370 struct drm_file *filp); 1371 1372 /* 1373 * functions used by amdgpu_encoder.c 1374 */ 1375 struct amdgpu_afmt_acr { 1376 u32 clock; 1377 1378 int n_32khz; 1379 int cts_32khz; 1380 1381 int n_44_1khz; 1382 int cts_44_1khz; 1383 1384 int n_48khz; 1385 int cts_48khz; 1386 1387 }; 1388 1389 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1390 1391 /* amdgpu_acpi.c */ 1392 1393 struct amdgpu_numa_info { 1394 uint64_t size; 1395 int pxm; 1396 int nid; 1397 }; 1398 1399 /* ATCS Device/Driver State */ 1400 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1401 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1402 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1403 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1404 1405 #if defined(CONFIG_ACPI) 1406 int amdgpu_acpi_init(struct amdgpu_device *adev); 1407 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1408 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1409 bool amdgpu_acpi_is_power_shift_control_supported(void); 1410 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1411 u8 perf_req, bool advertise); 1412 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1413 u8 dev_state, bool drv_state); 1414 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1415 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1416 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1417 u64 *tmr_size); 1418 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1419 struct amdgpu_numa_info *numa_info); 1420 1421 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1422 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1423 void amdgpu_acpi_detect(void); 1424 void amdgpu_acpi_release(void); 1425 #else 1426 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1427 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1428 u64 *tmr_offset, u64 *tmr_size) 1429 { 1430 return -EINVAL; 1431 } 1432 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1433 int xcc_id, 1434 struct amdgpu_numa_info *numa_info) 1435 { 1436 return -EINVAL; 1437 } 1438 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1439 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1440 static inline void amdgpu_acpi_detect(void) { } 1441 static inline void amdgpu_acpi_release(void) { } 1442 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1443 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1444 u8 dev_state, bool drv_state) { return 0; } 1445 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1446 enum amdgpu_ss ss_state) { return 0; } 1447 #endif 1448 1449 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1450 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1451 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1452 #else 1453 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1454 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1455 #endif 1456 1457 #if defined(CONFIG_DRM_AMD_DC) 1458 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1459 #else 1460 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1461 #endif 1462 1463 1464 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1465 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1466 1467 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1468 pci_channel_state_t state); 1469 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1470 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1471 void amdgpu_pci_resume(struct pci_dev *pdev); 1472 1473 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1474 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1475 1476 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1477 1478 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1479 enum amd_clockgating_state state); 1480 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1481 enum amd_powergating_state state); 1482 1483 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1484 { 1485 return amdgpu_gpu_recovery != 0 && 1486 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1487 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1488 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1489 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1490 } 1491 1492 #include "amdgpu_object.h" 1493 1494 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1495 { 1496 return adev->gmc.tmz_enabled; 1497 } 1498 1499 int amdgpu_in_reset(struct amdgpu_device *adev); 1500 1501 #endif 1502