1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 #include <drm/ttm/ttm_execbuf_util.h> 57 58 #include <drm/amdgpu_drm.h> 59 #include <drm/drm_gem.h> 60 #include <drm/drm_ioctl.h> 61 62 #include <kgd_kfd_interface.h> 63 #include "dm_pp_interface.h" 64 #include "kgd_pp_interface.h" 65 66 #include "amd_shared.h" 67 #include "amdgpu_mode.h" 68 #include "amdgpu_ih.h" 69 #include "amdgpu_irq.h" 70 #include "amdgpu_ucode.h" 71 #include "amdgpu_ttm.h" 72 #include "amdgpu_psp.h" 73 #include "amdgpu_gds.h" 74 #include "amdgpu_sync.h" 75 #include "amdgpu_ring.h" 76 #include "amdgpu_vm.h" 77 #include "amdgpu_dpm.h" 78 #include "amdgpu_acp.h" 79 #include "amdgpu_uvd.h" 80 #include "amdgpu_vce.h" 81 #include "amdgpu_vcn.h" 82 #include "amdgpu_jpeg.h" 83 #include "amdgpu_gmc.h" 84 #include "amdgpu_gfx.h" 85 #include "amdgpu_sdma.h" 86 #include "amdgpu_lsdma.h" 87 #include "amdgpu_nbio.h" 88 #include "amdgpu_hdp.h" 89 #include "amdgpu_dm.h" 90 #include "amdgpu_virt.h" 91 #include "amdgpu_csa.h" 92 #include "amdgpu_mes_ctx.h" 93 #include "amdgpu_gart.h" 94 #include "amdgpu_debugfs.h" 95 #include "amdgpu_job.h" 96 #include "amdgpu_bo_list.h" 97 #include "amdgpu_gem.h" 98 #include "amdgpu_doorbell.h" 99 #include "amdgpu_amdkfd.h" 100 #include "amdgpu_discovery.h" 101 #include "amdgpu_mes.h" 102 #include "amdgpu_umc.h" 103 #include "amdgpu_mmhub.h" 104 #include "amdgpu_gfxhub.h" 105 #include "amdgpu_df.h" 106 #include "amdgpu_smuio.h" 107 #include "amdgpu_fdinfo.h" 108 #include "amdgpu_mca.h" 109 #include "amdgpu_ras.h" 110 111 #define MAX_GPU_INSTANCE 16 112 113 struct amdgpu_gpu_instance 114 { 115 struct amdgpu_device *adev; 116 int mgpu_fan_enabled; 117 }; 118 119 struct amdgpu_mgpu_info 120 { 121 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 122 struct mutex mutex; 123 uint32_t num_gpu; 124 uint32_t num_dgpu; 125 uint32_t num_apu; 126 127 /* delayed reset_func for XGMI configuration if necessary */ 128 struct delayed_work delayed_reset_work; 129 bool pending_reset; 130 }; 131 132 enum amdgpu_ss { 133 AMDGPU_SS_DRV_LOAD, 134 AMDGPU_SS_DEV_D0, 135 AMDGPU_SS_DEV_D3, 136 AMDGPU_SS_DRV_UNLOAD 137 }; 138 139 struct amdgpu_watchdog_timer 140 { 141 bool timeout_fatal_disable; 142 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 143 }; 144 145 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 146 147 /* 148 * Modules parameters. 149 */ 150 extern int amdgpu_modeset; 151 extern unsigned int amdgpu_vram_limit; 152 extern int amdgpu_vis_vram_limit; 153 extern int amdgpu_gart_size; 154 extern int amdgpu_gtt_size; 155 extern int amdgpu_moverate; 156 extern int amdgpu_audio; 157 extern int amdgpu_disp_priority; 158 extern int amdgpu_hw_i2c; 159 extern int amdgpu_pcie_gen2; 160 extern int amdgpu_msi; 161 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 162 extern int amdgpu_dpm; 163 extern int amdgpu_fw_load_type; 164 extern int amdgpu_aspm; 165 extern int amdgpu_runtime_pm; 166 extern uint amdgpu_ip_block_mask; 167 extern int amdgpu_bapm; 168 extern int amdgpu_deep_color; 169 extern int amdgpu_vm_size; 170 extern int amdgpu_vm_block_size; 171 extern int amdgpu_vm_fragment_size; 172 extern int amdgpu_vm_fault_stop; 173 extern int amdgpu_vm_debug; 174 extern int amdgpu_vm_update_mode; 175 extern int amdgpu_exp_hw_support; 176 extern int amdgpu_dc; 177 extern int amdgpu_sched_jobs; 178 extern int amdgpu_sched_hw_submission; 179 extern uint amdgpu_pcie_gen_cap; 180 extern uint amdgpu_pcie_lane_cap; 181 extern u64 amdgpu_cg_mask; 182 extern uint amdgpu_pg_mask; 183 extern uint amdgpu_sdma_phase_quantum; 184 extern char *amdgpu_disable_cu; 185 extern char *amdgpu_virtual_display; 186 extern uint amdgpu_pp_feature_mask; 187 extern uint amdgpu_force_long_training; 188 extern int amdgpu_lbpw; 189 extern int amdgpu_compute_multipipe; 190 extern int amdgpu_gpu_recovery; 191 extern int amdgpu_emu_mode; 192 extern uint amdgpu_smu_memory_pool_size; 193 extern int amdgpu_smu_pptable_id; 194 extern uint amdgpu_dc_feature_mask; 195 extern uint amdgpu_freesync_vid_mode; 196 extern uint amdgpu_dc_debug_mask; 197 extern uint amdgpu_dc_visual_confirm; 198 extern uint amdgpu_dm_abm_level; 199 extern int amdgpu_backlight; 200 extern struct amdgpu_mgpu_info mgpu_info; 201 extern int amdgpu_ras_enable; 202 extern uint amdgpu_ras_mask; 203 extern int amdgpu_bad_page_threshold; 204 extern bool amdgpu_ignore_bad_page_threshold; 205 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 206 extern int amdgpu_async_gfx_ring; 207 extern int amdgpu_mcbp; 208 extern int amdgpu_discovery; 209 extern int amdgpu_mes; 210 extern int amdgpu_mes_kiq; 211 extern int amdgpu_noretry; 212 extern int amdgpu_force_asic_type; 213 extern int amdgpu_smartshift_bias; 214 extern int amdgpu_use_xgmi_p2p; 215 #ifdef CONFIG_HSA_AMD 216 extern int sched_policy; 217 extern bool debug_evictions; 218 extern bool no_system_mem_limit; 219 extern int halt_if_hws_hang; 220 #else 221 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 222 static const bool __maybe_unused debug_evictions; /* = false */ 223 static const bool __maybe_unused no_system_mem_limit; 224 static const int __maybe_unused halt_if_hws_hang; 225 #endif 226 #ifdef CONFIG_HSA_AMD_P2P 227 extern bool pcie_p2p; 228 #endif 229 230 extern int amdgpu_tmz; 231 extern int amdgpu_reset_method; 232 233 #ifdef CONFIG_DRM_AMDGPU_SI 234 extern int amdgpu_si_support; 235 #endif 236 #ifdef CONFIG_DRM_AMDGPU_CIK 237 extern int amdgpu_cik_support; 238 #endif 239 extern int amdgpu_num_kcq; 240 241 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 242 extern int amdgpu_vcnfw_log; 243 extern int amdgpu_sg_display; 244 245 #define AMDGPU_VM_MAX_NUM_CTX 4096 246 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 247 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 248 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 249 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 250 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 251 #define AMDGPUFB_CONN_LIMIT 4 252 #define AMDGPU_BIOS_NUM_SCRATCH 16 253 254 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 255 256 /* hard reset data */ 257 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 258 259 /* reset flags */ 260 #define AMDGPU_RESET_GFX (1 << 0) 261 #define AMDGPU_RESET_COMPUTE (1 << 1) 262 #define AMDGPU_RESET_DMA (1 << 2) 263 #define AMDGPU_RESET_CP (1 << 3) 264 #define AMDGPU_RESET_GRBM (1 << 4) 265 #define AMDGPU_RESET_DMA1 (1 << 5) 266 #define AMDGPU_RESET_RLC (1 << 6) 267 #define AMDGPU_RESET_SEM (1 << 7) 268 #define AMDGPU_RESET_IH (1 << 8) 269 #define AMDGPU_RESET_VMC (1 << 9) 270 #define AMDGPU_RESET_MC (1 << 10) 271 #define AMDGPU_RESET_DISPLAY (1 << 11) 272 #define AMDGPU_RESET_UVD (1 << 12) 273 #define AMDGPU_RESET_VCE (1 << 13) 274 #define AMDGPU_RESET_VCE1 (1 << 14) 275 276 /* max cursor sizes (in pixels) */ 277 #define CIK_CURSOR_WIDTH 128 278 #define CIK_CURSOR_HEIGHT 128 279 280 /* smart shift bias level limits */ 281 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 282 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 283 284 struct amdgpu_device; 285 struct amdgpu_irq_src; 286 struct amdgpu_fpriv; 287 struct amdgpu_bo_va_mapping; 288 struct kfd_vm_fault_info; 289 struct amdgpu_hive_info; 290 struct amdgpu_reset_context; 291 struct amdgpu_reset_control; 292 293 enum amdgpu_cp_irq { 294 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 295 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 296 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 297 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 298 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 299 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 300 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 301 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 302 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 303 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 304 305 AMDGPU_CP_IRQ_LAST 306 }; 307 308 enum amdgpu_thermal_irq { 309 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 310 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 311 312 AMDGPU_THERMAL_IRQ_LAST 313 }; 314 315 enum amdgpu_kiq_irq { 316 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 317 AMDGPU_CP_KIQ_IRQ_LAST 318 }; 319 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 320 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 321 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 322 #define MAX_KIQ_REG_TRY 1000 323 324 int amdgpu_device_ip_set_clockgating_state(void *dev, 325 enum amd_ip_block_type block_type, 326 enum amd_clockgating_state state); 327 int amdgpu_device_ip_set_powergating_state(void *dev, 328 enum amd_ip_block_type block_type, 329 enum amd_powergating_state state); 330 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 331 u64 *flags); 332 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 333 enum amd_ip_block_type block_type); 334 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 335 enum amd_ip_block_type block_type); 336 337 #define AMDGPU_MAX_IP_NUM 16 338 339 struct amdgpu_ip_block_status { 340 bool valid; 341 bool sw; 342 bool hw; 343 bool late_initialized; 344 bool hang; 345 }; 346 347 struct amdgpu_ip_block_version { 348 const enum amd_ip_block_type type; 349 const u32 major; 350 const u32 minor; 351 const u32 rev; 352 const struct amd_ip_funcs *funcs; 353 }; 354 355 #define HW_REV(_Major, _Minor, _Rev) \ 356 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 357 358 struct amdgpu_ip_block { 359 struct amdgpu_ip_block_status status; 360 const struct amdgpu_ip_block_version *version; 361 }; 362 363 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 364 enum amd_ip_block_type type, 365 u32 major, u32 minor); 366 367 struct amdgpu_ip_block * 368 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 369 enum amd_ip_block_type type); 370 371 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 372 const struct amdgpu_ip_block_version *ip_block_version); 373 374 /* 375 * BIOS. 376 */ 377 bool amdgpu_get_bios(struct amdgpu_device *adev); 378 bool amdgpu_read_bios(struct amdgpu_device *adev); 379 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 380 u8 *bios, u32 length_bytes); 381 /* 382 * Clocks 383 */ 384 385 #define AMDGPU_MAX_PPLL 3 386 387 struct amdgpu_clock { 388 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 389 struct amdgpu_pll spll; 390 struct amdgpu_pll mpll; 391 /* 10 Khz units */ 392 uint32_t default_mclk; 393 uint32_t default_sclk; 394 uint32_t default_dispclk; 395 uint32_t current_dispclk; 396 uint32_t dp_extclk; 397 uint32_t max_pixel_clock; 398 }; 399 400 /* sub-allocation manager, it has to be protected by another lock. 401 * By conception this is an helper for other part of the driver 402 * like the indirect buffer or semaphore, which both have their 403 * locking. 404 * 405 * Principe is simple, we keep a list of sub allocation in offset 406 * order (first entry has offset == 0, last entry has the highest 407 * offset). 408 * 409 * When allocating new object we first check if there is room at 410 * the end total_size - (last_object_offset + last_object_size) >= 411 * alloc_size. If so we allocate new object there. 412 * 413 * When there is not enough room at the end, we start waiting for 414 * each sub object until we reach object_offset+object_size >= 415 * alloc_size, this object then become the sub object we return. 416 * 417 * Alignment can't be bigger than page size. 418 * 419 * Hole are not considered for allocation to keep things simple. 420 * Assumption is that there won't be hole (all object on same 421 * alignment). 422 */ 423 424 struct amdgpu_sa_manager { 425 struct drm_suballoc_manager base; 426 struct amdgpu_bo *bo; 427 uint64_t gpu_addr; 428 void *cpu_ptr; 429 }; 430 431 int amdgpu_fence_slab_init(void); 432 void amdgpu_fence_slab_fini(void); 433 434 /* 435 * IRQS. 436 */ 437 438 struct amdgpu_flip_work { 439 struct delayed_work flip_work; 440 struct work_struct unpin_work; 441 struct amdgpu_device *adev; 442 int crtc_id; 443 u32 target_vblank; 444 uint64_t base; 445 struct drm_pending_vblank_event *event; 446 struct amdgpu_bo *old_abo; 447 unsigned shared_count; 448 struct dma_fence **shared; 449 struct dma_fence_cb cb; 450 bool async; 451 }; 452 453 454 /* 455 * file private structure 456 */ 457 458 struct amdgpu_fpriv { 459 struct amdgpu_vm vm; 460 struct amdgpu_bo_va *prt_va; 461 struct amdgpu_bo_va *csa_va; 462 struct mutex bo_list_lock; 463 struct idr bo_list_handles; 464 struct amdgpu_ctx_mgr ctx_mgr; 465 }; 466 467 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 468 469 /* 470 * Writeback 471 */ 472 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 473 474 struct amdgpu_wb { 475 struct amdgpu_bo *wb_obj; 476 volatile uint32_t *wb; 477 uint64_t gpu_addr; 478 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 479 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 480 }; 481 482 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 483 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 484 485 /* 486 * Benchmarking 487 */ 488 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 489 490 /* 491 * ASIC specific register table accessible by UMD 492 */ 493 struct amdgpu_allowed_register_entry { 494 uint32_t reg_offset; 495 bool grbm_indexed; 496 }; 497 498 enum amd_reset_method { 499 AMD_RESET_METHOD_NONE = -1, 500 AMD_RESET_METHOD_LEGACY = 0, 501 AMD_RESET_METHOD_MODE0, 502 AMD_RESET_METHOD_MODE1, 503 AMD_RESET_METHOD_MODE2, 504 AMD_RESET_METHOD_BACO, 505 AMD_RESET_METHOD_PCI, 506 }; 507 508 struct amdgpu_video_codec_info { 509 u32 codec_type; 510 u32 max_width; 511 u32 max_height; 512 u32 max_pixels_per_frame; 513 u32 max_level; 514 }; 515 516 #define codec_info_build(type, width, height, level) \ 517 .codec_type = type,\ 518 .max_width = width,\ 519 .max_height = height,\ 520 .max_pixels_per_frame = height * width,\ 521 .max_level = level, 522 523 struct amdgpu_video_codecs { 524 const u32 codec_count; 525 const struct amdgpu_video_codec_info *codec_array; 526 }; 527 528 /* 529 * ASIC specific functions. 530 */ 531 struct amdgpu_asic_funcs { 532 bool (*read_disabled_bios)(struct amdgpu_device *adev); 533 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 534 u8 *bios, u32 length_bytes); 535 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 536 u32 sh_num, u32 reg_offset, u32 *value); 537 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 538 int (*reset)(struct amdgpu_device *adev); 539 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 540 /* get the reference clock */ 541 u32 (*get_xclk)(struct amdgpu_device *adev); 542 /* MM block clocks */ 543 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 544 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 545 /* static power management */ 546 int (*get_pcie_lanes)(struct amdgpu_device *adev); 547 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 548 /* get config memsize register */ 549 u32 (*get_config_memsize)(struct amdgpu_device *adev); 550 /* flush hdp write queue */ 551 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 552 /* invalidate hdp read cache */ 553 void (*invalidate_hdp)(struct amdgpu_device *adev, 554 struct amdgpu_ring *ring); 555 /* check if the asic needs a full reset of if soft reset will work */ 556 bool (*need_full_reset)(struct amdgpu_device *adev); 557 /* initialize doorbell layout for specific asic*/ 558 void (*init_doorbell_index)(struct amdgpu_device *adev); 559 /* PCIe bandwidth usage */ 560 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 561 uint64_t *count1); 562 /* do we need to reset the asic at init time (e.g., kexec) */ 563 bool (*need_reset_on_init)(struct amdgpu_device *adev); 564 /* PCIe replay counter */ 565 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 566 /* device supports BACO */ 567 bool (*supports_baco)(struct amdgpu_device *adev); 568 /* pre asic_init quirks */ 569 void (*pre_asic_init)(struct amdgpu_device *adev); 570 /* enter/exit umd stable pstate */ 571 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 572 /* query video codecs */ 573 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 574 const struct amdgpu_video_codecs **codecs); 575 }; 576 577 /* 578 * IOCTL. 579 */ 580 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 581 struct drm_file *filp); 582 583 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 584 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 585 struct drm_file *filp); 586 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 587 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 588 struct drm_file *filp); 589 590 /* VRAM scratch page for HDP bug, default vram page */ 591 struct amdgpu_mem_scratch { 592 struct amdgpu_bo *robj; 593 volatile uint32_t *ptr; 594 u64 gpu_addr; 595 }; 596 597 /* 598 * CGS 599 */ 600 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 601 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 602 603 /* 604 * Core structure, functions and helpers. 605 */ 606 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 607 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 608 609 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 610 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 611 612 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 613 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 614 615 struct amdgpu_mmio_remap { 616 u32 reg_offset; 617 resource_size_t bus_addr; 618 }; 619 620 /* Define the HW IP blocks will be used in driver , add more if necessary */ 621 enum amd_hw_ip_block_type { 622 GC_HWIP = 1, 623 HDP_HWIP, 624 SDMA0_HWIP, 625 SDMA1_HWIP, 626 SDMA2_HWIP, 627 SDMA3_HWIP, 628 SDMA4_HWIP, 629 SDMA5_HWIP, 630 SDMA6_HWIP, 631 SDMA7_HWIP, 632 LSDMA_HWIP, 633 MMHUB_HWIP, 634 ATHUB_HWIP, 635 NBIO_HWIP, 636 MP0_HWIP, 637 MP1_HWIP, 638 UVD_HWIP, 639 VCN_HWIP = UVD_HWIP, 640 JPEG_HWIP = VCN_HWIP, 641 VCN1_HWIP, 642 VCE_HWIP, 643 DF_HWIP, 644 DCE_HWIP, 645 OSSSYS_HWIP, 646 SMUIO_HWIP, 647 PWR_HWIP, 648 NBIF_HWIP, 649 THM_HWIP, 650 CLK_HWIP, 651 UMC_HWIP, 652 RSMU_HWIP, 653 XGMI_HWIP, 654 DCI_HWIP, 655 PCIE_HWIP, 656 MAX_HWIP 657 }; 658 659 #define HWIP_MAX_INSTANCE 28 660 661 #define HW_ID_MAX 300 662 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 663 #define IP_VERSION_MAJ(ver) ((ver) >> 16) 664 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF) 665 #define IP_VERSION_REV(ver) ((ver) & 0xFF) 666 667 struct amd_powerplay { 668 void *pp_handle; 669 const struct amd_pm_funcs *pp_funcs; 670 }; 671 672 struct ip_discovery_top; 673 674 /* polaris10 kickers */ 675 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 676 ((rid == 0xE3) || \ 677 (rid == 0xE4) || \ 678 (rid == 0xE5) || \ 679 (rid == 0xE7) || \ 680 (rid == 0xEF))) || \ 681 ((did == 0x6FDF) && \ 682 ((rid == 0xE7) || \ 683 (rid == 0xEF) || \ 684 (rid == 0xFF)))) 685 686 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 687 ((rid == 0xE1) || \ 688 (rid == 0xF7))) 689 690 /* polaris11 kickers */ 691 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 692 ((rid == 0xE0) || \ 693 (rid == 0xE5))) || \ 694 ((did == 0x67FF) && \ 695 ((rid == 0xCF) || \ 696 (rid == 0xEF) || \ 697 (rid == 0xFF)))) 698 699 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 700 ((rid == 0xE2))) 701 702 /* polaris12 kickers */ 703 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 704 ((rid == 0xC0) || \ 705 (rid == 0xC1) || \ 706 (rid == 0xC3) || \ 707 (rid == 0xC7))) || \ 708 ((did == 0x6981) && \ 709 ((rid == 0x00) || \ 710 (rid == 0x01) || \ 711 (rid == 0x10)))) 712 713 struct amdgpu_mqd_prop { 714 uint64_t mqd_gpu_addr; 715 uint64_t hqd_base_gpu_addr; 716 uint64_t rptr_gpu_addr; 717 uint64_t wptr_gpu_addr; 718 uint32_t queue_size; 719 bool use_doorbell; 720 uint32_t doorbell_index; 721 uint64_t eop_gpu_addr; 722 uint32_t hqd_pipe_priority; 723 uint32_t hqd_queue_priority; 724 bool hqd_active; 725 }; 726 727 struct amdgpu_mqd { 728 unsigned mqd_size; 729 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 730 struct amdgpu_mqd_prop *p); 731 }; 732 733 #define AMDGPU_RESET_MAGIC_NUM 64 734 #define AMDGPU_MAX_DF_PERFMONS 4 735 #define AMDGPU_PRODUCT_NAME_LEN 64 736 struct amdgpu_reset_domain; 737 738 /* 739 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 740 */ 741 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 742 743 struct amdgpu_device { 744 struct device *dev; 745 struct pci_dev *pdev; 746 struct drm_device ddev; 747 748 #ifdef CONFIG_DRM_AMD_ACP 749 struct amdgpu_acp acp; 750 #endif 751 struct amdgpu_hive_info *hive; 752 /* ASIC */ 753 enum amd_asic_type asic_type; 754 uint32_t family; 755 uint32_t rev_id; 756 uint32_t external_rev_id; 757 unsigned long flags; 758 unsigned long apu_flags; 759 int usec_timeout; 760 const struct amdgpu_asic_funcs *asic_funcs; 761 bool shutdown; 762 bool need_swiotlb; 763 bool accel_working; 764 struct notifier_block acpi_nb; 765 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 766 struct debugfs_blob_wrapper debugfs_vbios_blob; 767 struct debugfs_blob_wrapper debugfs_discovery_blob; 768 struct mutex srbm_mutex; 769 /* GRBM index mutex. Protects concurrent access to GRBM index */ 770 struct mutex grbm_idx_mutex; 771 struct dev_pm_domain vga_pm_domain; 772 bool have_disp_power_ref; 773 bool have_atomics_support; 774 775 /* BIOS */ 776 bool is_atom_fw; 777 uint8_t *bios; 778 uint32_t bios_size; 779 uint32_t bios_scratch_reg_offset; 780 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 781 782 /* Register/doorbell mmio */ 783 resource_size_t rmmio_base; 784 resource_size_t rmmio_size; 785 void __iomem *rmmio; 786 /* protects concurrent MM_INDEX/DATA based register access */ 787 spinlock_t mmio_idx_lock; 788 struct amdgpu_mmio_remap rmmio_remap; 789 /* protects concurrent SMC based register access */ 790 spinlock_t smc_idx_lock; 791 amdgpu_rreg_t smc_rreg; 792 amdgpu_wreg_t smc_wreg; 793 /* protects concurrent PCIE register access */ 794 spinlock_t pcie_idx_lock; 795 amdgpu_rreg_t pcie_rreg; 796 amdgpu_wreg_t pcie_wreg; 797 amdgpu_rreg_t pciep_rreg; 798 amdgpu_wreg_t pciep_wreg; 799 amdgpu_rreg64_t pcie_rreg64; 800 amdgpu_wreg64_t pcie_wreg64; 801 /* protects concurrent UVD register access */ 802 spinlock_t uvd_ctx_idx_lock; 803 amdgpu_rreg_t uvd_ctx_rreg; 804 amdgpu_wreg_t uvd_ctx_wreg; 805 /* protects concurrent DIDT register access */ 806 spinlock_t didt_idx_lock; 807 amdgpu_rreg_t didt_rreg; 808 amdgpu_wreg_t didt_wreg; 809 /* protects concurrent gc_cac register access */ 810 spinlock_t gc_cac_idx_lock; 811 amdgpu_rreg_t gc_cac_rreg; 812 amdgpu_wreg_t gc_cac_wreg; 813 /* protects concurrent se_cac register access */ 814 spinlock_t se_cac_idx_lock; 815 amdgpu_rreg_t se_cac_rreg; 816 amdgpu_wreg_t se_cac_wreg; 817 /* protects concurrent ENDPOINT (audio) register access */ 818 spinlock_t audio_endpt_idx_lock; 819 amdgpu_block_rreg_t audio_endpt_rreg; 820 amdgpu_block_wreg_t audio_endpt_wreg; 821 struct amdgpu_doorbell doorbell; 822 823 /* clock/pll info */ 824 struct amdgpu_clock clock; 825 826 /* MC */ 827 struct amdgpu_gmc gmc; 828 struct amdgpu_gart gart; 829 dma_addr_t dummy_page_addr; 830 struct amdgpu_vm_manager vm_manager; 831 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 832 unsigned num_vmhubs; 833 834 /* memory management */ 835 struct amdgpu_mman mman; 836 struct amdgpu_mem_scratch mem_scratch; 837 struct amdgpu_wb wb; 838 atomic64_t num_bytes_moved; 839 atomic64_t num_evictions; 840 atomic64_t num_vram_cpu_page_faults; 841 atomic_t gpu_reset_counter; 842 atomic_t vram_lost_counter; 843 844 /* data for buffer migration throttling */ 845 struct { 846 spinlock_t lock; 847 s64 last_update_us; 848 s64 accum_us; /* accumulated microseconds */ 849 s64 accum_us_vis; /* for visible VRAM */ 850 u32 log2_max_MBps; 851 } mm_stats; 852 853 /* display */ 854 bool enable_virtual_display; 855 struct amdgpu_vkms_output *amdgpu_vkms_output; 856 struct amdgpu_mode_info mode_info; 857 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 858 struct delayed_work hotplug_work; 859 struct amdgpu_irq_src crtc_irq; 860 struct amdgpu_irq_src vline0_irq; 861 struct amdgpu_irq_src vupdate_irq; 862 struct amdgpu_irq_src pageflip_irq; 863 struct amdgpu_irq_src hpd_irq; 864 struct amdgpu_irq_src dmub_trace_irq; 865 struct amdgpu_irq_src dmub_outbox_irq; 866 867 /* rings */ 868 u64 fence_context; 869 unsigned num_rings; 870 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 871 struct dma_fence __rcu *gang_submit; 872 bool ib_pool_ready; 873 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 874 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 875 876 /* interrupts */ 877 struct amdgpu_irq irq; 878 879 /* powerplay */ 880 struct amd_powerplay powerplay; 881 struct amdgpu_pm pm; 882 u64 cg_flags; 883 u32 pg_flags; 884 885 /* nbio */ 886 struct amdgpu_nbio nbio; 887 888 /* hdp */ 889 struct amdgpu_hdp hdp; 890 891 /* smuio */ 892 struct amdgpu_smuio smuio; 893 894 /* mmhub */ 895 struct amdgpu_mmhub mmhub; 896 897 /* gfxhub */ 898 struct amdgpu_gfxhub gfxhub; 899 900 /* gfx */ 901 struct amdgpu_gfx gfx; 902 903 /* sdma */ 904 struct amdgpu_sdma sdma; 905 906 /* lsdma */ 907 struct amdgpu_lsdma lsdma; 908 909 /* uvd */ 910 struct amdgpu_uvd uvd; 911 912 /* vce */ 913 struct amdgpu_vce vce; 914 915 /* vcn */ 916 struct amdgpu_vcn vcn; 917 918 /* jpeg */ 919 struct amdgpu_jpeg jpeg; 920 921 /* firmwares */ 922 struct amdgpu_firmware firmware; 923 924 /* PSP */ 925 struct psp_context psp; 926 927 /* GDS */ 928 struct amdgpu_gds gds; 929 930 /* KFD */ 931 struct amdgpu_kfd_dev kfd; 932 933 /* UMC */ 934 struct amdgpu_umc umc; 935 936 /* display related functionality */ 937 struct amdgpu_display_manager dm; 938 939 /* mes */ 940 bool enable_mes; 941 bool enable_mes_kiq; 942 struct amdgpu_mes mes; 943 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 944 945 /* df */ 946 struct amdgpu_df df; 947 948 /* MCA */ 949 struct amdgpu_mca mca; 950 951 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 952 uint32_t harvest_ip_mask; 953 int num_ip_blocks; 954 struct mutex mn_lock; 955 DECLARE_HASHTABLE(mn_hash, 7); 956 957 /* tracking pinned memory */ 958 atomic64_t vram_pin_size; 959 atomic64_t visible_pin_size; 960 atomic64_t gart_pin_size; 961 962 /* soc15 register offset based on ip, instance and segment */ 963 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 964 965 /* delayed work_func for deferring clockgating during resume */ 966 struct delayed_work delayed_init_work; 967 968 struct amdgpu_virt virt; 969 970 /* link all shadow bo */ 971 struct list_head shadow_list; 972 struct mutex shadow_list_lock; 973 974 /* record hw reset is performed */ 975 bool has_hw_reset; 976 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 977 978 /* s3/s4 mask */ 979 bool in_suspend; 980 bool in_s3; 981 bool in_s4; 982 bool in_s0ix; 983 984 enum pp_mp1_state mp1_state; 985 struct amdgpu_doorbell_index doorbell_index; 986 987 struct mutex notifier_lock; 988 989 int asic_reset_res; 990 struct work_struct xgmi_reset_work; 991 struct list_head reset_list; 992 993 long gfx_timeout; 994 long sdma_timeout; 995 long video_timeout; 996 long compute_timeout; 997 998 uint64_t unique_id; 999 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1000 1001 /* enable runtime pm on the device */ 1002 bool in_runpm; 1003 bool has_pr3; 1004 1005 bool ucode_sysfs_en; 1006 bool psp_sysfs_en; 1007 1008 /* Chip product information */ 1009 char product_number[20]; 1010 char product_name[AMDGPU_PRODUCT_NAME_LEN]; 1011 char serial[20]; 1012 1013 atomic_t throttling_logging_enabled; 1014 struct ratelimit_state throttling_logging_rs; 1015 uint32_t ras_hw_enabled; 1016 uint32_t ras_enabled; 1017 1018 bool no_hw_access; 1019 struct pci_saved_state *pci_state; 1020 pci_channel_state_t pci_channel_state; 1021 1022 struct amdgpu_reset_control *reset_cntl; 1023 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1024 1025 bool ram_is_direct_mapped; 1026 1027 struct list_head ras_list; 1028 1029 struct ip_discovery_top *ip_top; 1030 1031 struct amdgpu_reset_domain *reset_domain; 1032 1033 struct mutex benchmark_mutex; 1034 1035 /* reset dump register */ 1036 uint32_t *reset_dump_reg_list; 1037 uint32_t *reset_dump_reg_value; 1038 int num_regs; 1039 #ifdef CONFIG_DEV_COREDUMP 1040 struct amdgpu_task_info reset_task_info; 1041 bool reset_vram_lost; 1042 struct timespec64 reset_time; 1043 #endif 1044 1045 bool scpm_enabled; 1046 uint32_t scpm_status; 1047 1048 struct work_struct reset_work; 1049 1050 bool job_hang; 1051 bool dc_enabled; 1052 }; 1053 1054 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1055 { 1056 return container_of(ddev, struct amdgpu_device, ddev); 1057 } 1058 1059 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1060 { 1061 return &adev->ddev; 1062 } 1063 1064 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1065 { 1066 return container_of(bdev, struct amdgpu_device, mman.bdev); 1067 } 1068 1069 int amdgpu_device_init(struct amdgpu_device *adev, 1070 uint32_t flags); 1071 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1072 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1073 1074 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1075 1076 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1077 void *buf, size_t size, bool write); 1078 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1079 void *buf, size_t size, bool write); 1080 1081 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1082 void *buf, size_t size, bool write); 1083 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1084 uint32_t reg, uint32_t acc_flags); 1085 void amdgpu_device_wreg(struct amdgpu_device *adev, 1086 uint32_t reg, uint32_t v, 1087 uint32_t acc_flags); 1088 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1089 uint32_t reg, uint32_t v); 1090 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1091 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1092 1093 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1094 u32 reg_addr); 1095 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1096 u32 reg_addr); 1097 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1098 u32 reg_addr, u32 reg_data); 1099 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1100 u32 reg_addr, u64 reg_data); 1101 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1102 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1103 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1104 1105 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1106 1107 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1108 struct amdgpu_reset_context *reset_context); 1109 1110 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1111 struct amdgpu_reset_context *reset_context); 1112 1113 int emu_soc_asic_init(struct amdgpu_device *adev); 1114 1115 /* 1116 * Registers read & write functions. 1117 */ 1118 #define AMDGPU_REGS_NO_KIQ (1<<1) 1119 #define AMDGPU_REGS_RLC (1<<2) 1120 1121 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1122 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1123 1124 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1125 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1126 1127 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1128 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1129 1130 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1131 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1132 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1133 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1134 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1135 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1136 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1137 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1138 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1139 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1140 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1141 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1142 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1143 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1144 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1145 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1146 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1147 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1148 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1149 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1150 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1151 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1152 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1153 #define WREG32_P(reg, val, mask) \ 1154 do { \ 1155 uint32_t tmp_ = RREG32(reg); \ 1156 tmp_ &= (mask); \ 1157 tmp_ |= ((val) & ~(mask)); \ 1158 WREG32(reg, tmp_); \ 1159 } while (0) 1160 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1161 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1162 #define WREG32_PLL_P(reg, val, mask) \ 1163 do { \ 1164 uint32_t tmp_ = RREG32_PLL(reg); \ 1165 tmp_ &= (mask); \ 1166 tmp_ |= ((val) & ~(mask)); \ 1167 WREG32_PLL(reg, tmp_); \ 1168 } while (0) 1169 1170 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1171 do { \ 1172 u32 tmp = RREG32_SMC(_Reg); \ 1173 tmp &= (_Mask); \ 1174 tmp |= ((_Val) & ~(_Mask)); \ 1175 WREG32_SMC(_Reg, tmp); \ 1176 } while (0) 1177 1178 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1179 1180 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1181 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1182 1183 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1184 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1185 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1186 1187 #define REG_GET_FIELD(value, reg, field) \ 1188 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1189 1190 #define WREG32_FIELD(reg, field, val) \ 1191 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1192 1193 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1194 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1195 1196 /* 1197 * BIOS helpers. 1198 */ 1199 #define RBIOS8(i) (adev->bios[i]) 1200 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1201 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1202 1203 /* 1204 * ASICs macro. 1205 */ 1206 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1207 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1208 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1209 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1210 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1211 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1212 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1213 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1214 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1215 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1216 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1217 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1218 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1219 #define amdgpu_asic_flush_hdp(adev, r) \ 1220 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1221 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1222 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1223 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1224 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1225 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1226 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1227 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1228 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1229 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1230 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1231 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1232 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1233 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1234 1235 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1236 1237 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 1238 1239 /* Common functions */ 1240 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1241 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1242 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1243 struct amdgpu_job *job, 1244 struct amdgpu_reset_context *reset_context); 1245 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1246 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1247 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1248 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1249 bool amdgpu_device_aspm_support_quirk(void); 1250 1251 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1252 u64 num_vis_bytes); 1253 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1254 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1255 const u32 *registers, 1256 const u32 array_size); 1257 1258 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1259 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1260 bool amdgpu_device_supports_px(struct drm_device *dev); 1261 bool amdgpu_device_supports_boco(struct drm_device *dev); 1262 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1263 bool amdgpu_device_supports_baco(struct drm_device *dev); 1264 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1265 struct amdgpu_device *peer_adev); 1266 int amdgpu_device_baco_enter(struct drm_device *dev); 1267 int amdgpu_device_baco_exit(struct drm_device *dev); 1268 1269 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1270 struct amdgpu_ring *ring); 1271 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1272 struct amdgpu_ring *ring); 1273 1274 void amdgpu_device_halt(struct amdgpu_device *adev); 1275 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1276 u32 reg); 1277 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1278 u32 reg, u32 v); 1279 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1280 struct dma_fence *gang); 1281 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1282 1283 /* atpx handler */ 1284 #if defined(CONFIG_VGA_SWITCHEROO) 1285 void amdgpu_register_atpx_handler(void); 1286 void amdgpu_unregister_atpx_handler(void); 1287 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1288 bool amdgpu_is_atpx_hybrid(void); 1289 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1290 bool amdgpu_has_atpx(void); 1291 #else 1292 static inline void amdgpu_register_atpx_handler(void) {} 1293 static inline void amdgpu_unregister_atpx_handler(void) {} 1294 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1295 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1296 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1297 static inline bool amdgpu_has_atpx(void) { return false; } 1298 #endif 1299 1300 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1301 void *amdgpu_atpx_get_dhandle(void); 1302 #else 1303 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1304 #endif 1305 1306 /* 1307 * KMS 1308 */ 1309 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1310 extern const int amdgpu_max_kms_ioctl; 1311 1312 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1313 void amdgpu_driver_unload_kms(struct drm_device *dev); 1314 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1315 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1316 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1317 struct drm_file *file_priv); 1318 void amdgpu_driver_release_kms(struct drm_device *dev); 1319 1320 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1321 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1322 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1323 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1324 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1325 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1326 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1327 struct drm_file *filp); 1328 1329 /* 1330 * functions used by amdgpu_encoder.c 1331 */ 1332 struct amdgpu_afmt_acr { 1333 u32 clock; 1334 1335 int n_32khz; 1336 int cts_32khz; 1337 1338 int n_44_1khz; 1339 int cts_44_1khz; 1340 1341 int n_48khz; 1342 int cts_48khz; 1343 1344 }; 1345 1346 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1347 1348 /* amdgpu_acpi.c */ 1349 1350 /* ATCS Device/Driver State */ 1351 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1352 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1353 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1354 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1355 1356 #if defined(CONFIG_ACPI) 1357 int amdgpu_acpi_init(struct amdgpu_device *adev); 1358 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1359 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1360 bool amdgpu_acpi_is_power_shift_control_supported(void); 1361 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1362 u8 perf_req, bool advertise); 1363 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1364 u8 dev_state, bool drv_state); 1365 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1366 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1367 1368 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1369 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1370 void amdgpu_acpi_detect(void); 1371 #else 1372 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1373 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1374 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1375 static inline void amdgpu_acpi_detect(void) { } 1376 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1377 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1378 u8 dev_state, bool drv_state) { return 0; } 1379 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1380 enum amdgpu_ss ss_state) { return 0; } 1381 #endif 1382 1383 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1384 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1385 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1386 #else 1387 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1388 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1389 #endif 1390 1391 #if defined(CONFIG_DRM_AMD_DC) 1392 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1393 #else 1394 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1395 #endif 1396 1397 1398 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1399 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1400 1401 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1402 pci_channel_state_t state); 1403 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1404 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1405 void amdgpu_pci_resume(struct pci_dev *pdev); 1406 1407 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1408 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1409 1410 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1411 1412 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1413 enum amd_clockgating_state state); 1414 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1415 enum amd_powergating_state state); 1416 1417 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1418 { 1419 return amdgpu_gpu_recovery != 0 && 1420 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1421 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1422 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1423 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1424 } 1425 1426 #include "amdgpu_object.h" 1427 1428 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1429 { 1430 return adev->gmc.tmz_enabled; 1431 } 1432 1433 int amdgpu_in_reset(struct amdgpu_device *adev); 1434 1435 #endif 1436