1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/dma-fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_ttm.h" 55 #include "amdgpu_gds.h" 56 #include "amdgpu_sync.h" 57 #include "amdgpu_ring.h" 58 #include "amdgpu_vm.h" 59 #include "amd_powerplay.h" 60 #include "amdgpu_dpm.h" 61 #include "amdgpu_acp.h" 62 63 #include "gpu_scheduler.h" 64 #include "amdgpu_virt.h" 65 66 /* 67 * Modules parameters. 68 */ 69 extern int amdgpu_modeset; 70 extern int amdgpu_vram_limit; 71 extern int amdgpu_gart_size; 72 extern int amdgpu_moverate; 73 extern int amdgpu_benchmarking; 74 extern int amdgpu_testing; 75 extern int amdgpu_audio; 76 extern int amdgpu_disp_priority; 77 extern int amdgpu_hw_i2c; 78 extern int amdgpu_pcie_gen2; 79 extern int amdgpu_msi; 80 extern int amdgpu_lockup_timeout; 81 extern int amdgpu_dpm; 82 extern int amdgpu_smc_load_fw; 83 extern int amdgpu_aspm; 84 extern int amdgpu_runtime_pm; 85 extern unsigned amdgpu_ip_block_mask; 86 extern int amdgpu_bapm; 87 extern int amdgpu_deep_color; 88 extern int amdgpu_vm_size; 89 extern int amdgpu_vm_block_size; 90 extern int amdgpu_vm_fault_stop; 91 extern int amdgpu_vm_debug; 92 extern int amdgpu_sched_jobs; 93 extern int amdgpu_sched_hw_submission; 94 extern int amdgpu_no_evict; 95 extern int amdgpu_direct_gma_size; 96 extern unsigned amdgpu_pcie_gen_cap; 97 extern unsigned amdgpu_pcie_lane_cap; 98 extern unsigned amdgpu_cg_mask; 99 extern unsigned amdgpu_pg_mask; 100 extern char *amdgpu_disable_cu; 101 extern char *amdgpu_virtual_display; 102 extern unsigned amdgpu_pp_feature_mask; 103 extern int amdgpu_vram_page_split; 104 105 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 106 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 107 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 108 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 109 #define AMDGPU_IB_POOL_SIZE 16 110 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 111 #define AMDGPUFB_CONN_LIMIT 4 112 #define AMDGPU_BIOS_NUM_SCRATCH 8 113 114 /* max number of IP instances */ 115 #define AMDGPU_MAX_SDMA_INSTANCES 2 116 117 /* hardcode that limit for now */ 118 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 119 120 /* hard reset data */ 121 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 122 123 /* reset flags */ 124 #define AMDGPU_RESET_GFX (1 << 0) 125 #define AMDGPU_RESET_COMPUTE (1 << 1) 126 #define AMDGPU_RESET_DMA (1 << 2) 127 #define AMDGPU_RESET_CP (1 << 3) 128 #define AMDGPU_RESET_GRBM (1 << 4) 129 #define AMDGPU_RESET_DMA1 (1 << 5) 130 #define AMDGPU_RESET_RLC (1 << 6) 131 #define AMDGPU_RESET_SEM (1 << 7) 132 #define AMDGPU_RESET_IH (1 << 8) 133 #define AMDGPU_RESET_VMC (1 << 9) 134 #define AMDGPU_RESET_MC (1 << 10) 135 #define AMDGPU_RESET_DISPLAY (1 << 11) 136 #define AMDGPU_RESET_UVD (1 << 12) 137 #define AMDGPU_RESET_VCE (1 << 13) 138 #define AMDGPU_RESET_VCE1 (1 << 14) 139 140 /* GFX current status */ 141 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 142 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 143 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 144 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 145 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 146 147 /* max cursor sizes (in pixels) */ 148 #define CIK_CURSOR_WIDTH 128 149 #define CIK_CURSOR_HEIGHT 128 150 151 struct amdgpu_device; 152 struct amdgpu_ib; 153 struct amdgpu_cs_parser; 154 struct amdgpu_job; 155 struct amdgpu_irq_src; 156 struct amdgpu_fpriv; 157 158 enum amdgpu_cp_irq { 159 AMDGPU_CP_IRQ_GFX_EOP = 0, 160 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 161 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 162 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 163 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 164 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 165 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 166 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 167 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 168 169 AMDGPU_CP_IRQ_LAST 170 }; 171 172 enum amdgpu_sdma_irq { 173 AMDGPU_SDMA_IRQ_TRAP0 = 0, 174 AMDGPU_SDMA_IRQ_TRAP1, 175 176 AMDGPU_SDMA_IRQ_LAST 177 }; 178 179 enum amdgpu_thermal_irq { 180 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 181 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 182 183 AMDGPU_THERMAL_IRQ_LAST 184 }; 185 186 enum amdgpu_kiq_irq { 187 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 188 AMDGPU_CP_KIQ_IRQ_LAST 189 }; 190 191 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 192 enum amd_ip_block_type block_type, 193 enum amd_clockgating_state state); 194 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 195 enum amd_ip_block_type block_type, 196 enum amd_powergating_state state); 197 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); 198 int amdgpu_wait_for_idle(struct amdgpu_device *adev, 199 enum amd_ip_block_type block_type); 200 bool amdgpu_is_idle(struct amdgpu_device *adev, 201 enum amd_ip_block_type block_type); 202 203 #define AMDGPU_MAX_IP_NUM 16 204 205 struct amdgpu_ip_block_status { 206 bool valid; 207 bool sw; 208 bool hw; 209 bool late_initialized; 210 bool hang; 211 }; 212 213 struct amdgpu_ip_block_version { 214 const enum amd_ip_block_type type; 215 const u32 major; 216 const u32 minor; 217 const u32 rev; 218 const struct amd_ip_funcs *funcs; 219 }; 220 221 struct amdgpu_ip_block { 222 struct amdgpu_ip_block_status status; 223 const struct amdgpu_ip_block_version *version; 224 }; 225 226 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 227 enum amd_ip_block_type type, 228 u32 major, u32 minor); 229 230 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 231 enum amd_ip_block_type type); 232 233 int amdgpu_ip_block_add(struct amdgpu_device *adev, 234 const struct amdgpu_ip_block_version *ip_block_version); 235 236 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 237 struct amdgpu_buffer_funcs { 238 /* maximum bytes in a single operation */ 239 uint32_t copy_max_bytes; 240 241 /* number of dw to reserve per operation */ 242 unsigned copy_num_dw; 243 244 /* used for buffer migration */ 245 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 246 /* src addr in bytes */ 247 uint64_t src_offset, 248 /* dst addr in bytes */ 249 uint64_t dst_offset, 250 /* number of byte to transfer */ 251 uint32_t byte_count); 252 253 /* maximum bytes in a single operation */ 254 uint32_t fill_max_bytes; 255 256 /* number of dw to reserve per operation */ 257 unsigned fill_num_dw; 258 259 /* used for buffer clearing */ 260 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 261 /* value to write to memory */ 262 uint32_t src_data, 263 /* dst addr in bytes */ 264 uint64_t dst_offset, 265 /* number of byte to fill */ 266 uint32_t byte_count); 267 }; 268 269 /* provided by hw blocks that can write ptes, e.g., sdma */ 270 struct amdgpu_vm_pte_funcs { 271 /* copy pte entries from GART */ 272 void (*copy_pte)(struct amdgpu_ib *ib, 273 uint64_t pe, uint64_t src, 274 unsigned count); 275 /* write pte one entry at a time with addr mapping */ 276 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 277 uint64_t value, unsigned count, 278 uint32_t incr); 279 /* for linear pte/pde updates without addr mapping */ 280 void (*set_pte_pde)(struct amdgpu_ib *ib, 281 uint64_t pe, 282 uint64_t addr, unsigned count, 283 uint32_t incr, uint32_t flags); 284 }; 285 286 /* provided by the gmc block */ 287 struct amdgpu_gart_funcs { 288 /* flush the vm tlb via mmio */ 289 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 290 uint32_t vmid); 291 /* write pte/pde updates using the cpu */ 292 int (*set_pte_pde)(struct amdgpu_device *adev, 293 void *cpu_pt_addr, /* cpu addr of page table */ 294 uint32_t gpu_page_idx, /* pte/pde to update */ 295 uint64_t addr, /* addr to write into pte/pde */ 296 uint32_t flags); /* access flags */ 297 }; 298 299 /* provided by the ih block */ 300 struct amdgpu_ih_funcs { 301 /* ring read/write ptr handling, called from interrupt context */ 302 u32 (*get_wptr)(struct amdgpu_device *adev); 303 void (*decode_iv)(struct amdgpu_device *adev, 304 struct amdgpu_iv_entry *entry); 305 void (*set_rptr)(struct amdgpu_device *adev); 306 }; 307 308 /* 309 * BIOS. 310 */ 311 bool amdgpu_get_bios(struct amdgpu_device *adev); 312 bool amdgpu_read_bios(struct amdgpu_device *adev); 313 314 /* 315 * Dummy page 316 */ 317 struct amdgpu_dummy_page { 318 struct page *page; 319 dma_addr_t addr; 320 }; 321 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 322 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 323 324 325 /* 326 * Clocks 327 */ 328 329 #define AMDGPU_MAX_PPLL 3 330 331 struct amdgpu_clock { 332 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 333 struct amdgpu_pll spll; 334 struct amdgpu_pll mpll; 335 /* 10 Khz units */ 336 uint32_t default_mclk; 337 uint32_t default_sclk; 338 uint32_t default_dispclk; 339 uint32_t current_dispclk; 340 uint32_t dp_extclk; 341 uint32_t max_pixel_clock; 342 }; 343 344 /* 345 * BO. 346 */ 347 struct amdgpu_bo_list_entry { 348 struct amdgpu_bo *robj; 349 struct ttm_validate_buffer tv; 350 struct amdgpu_bo_va *bo_va; 351 uint32_t priority; 352 struct page **user_pages; 353 int user_invalidated; 354 }; 355 356 struct amdgpu_bo_va_mapping { 357 struct list_head list; 358 struct interval_tree_node it; 359 uint64_t offset; 360 uint64_t flags; 361 }; 362 363 /* bo virtual addresses in a specific vm */ 364 struct amdgpu_bo_va { 365 /* protected by bo being reserved */ 366 struct list_head bo_list; 367 struct dma_fence *last_pt_update; 368 unsigned ref_count; 369 370 /* protected by vm mutex and spinlock */ 371 struct list_head vm_status; 372 373 /* mappings for this bo_va */ 374 struct list_head invalids; 375 struct list_head valids; 376 377 /* constant after initialization */ 378 struct amdgpu_vm *vm; 379 struct amdgpu_bo *bo; 380 }; 381 382 #define AMDGPU_GEM_DOMAIN_MAX 0x3 383 384 struct amdgpu_bo { 385 /* Protected by tbo.reserved */ 386 u32 prefered_domains; 387 u32 allowed_domains; 388 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 389 struct ttm_placement placement; 390 struct ttm_buffer_object tbo; 391 struct ttm_bo_kmap_obj kmap; 392 u64 flags; 393 unsigned pin_count; 394 void *kptr; 395 u64 tiling_flags; 396 u64 metadata_flags; 397 void *metadata; 398 u32 metadata_size; 399 unsigned prime_shared_count; 400 /* list of all virtual address to which this bo 401 * is associated to 402 */ 403 struct list_head va; 404 /* Constant after initialization */ 405 struct drm_gem_object gem_base; 406 struct amdgpu_bo *parent; 407 struct amdgpu_bo *shadow; 408 409 struct ttm_bo_kmap_obj dma_buf_vmap; 410 struct amdgpu_mn *mn; 411 struct list_head mn_list; 412 struct list_head shadow_list; 413 }; 414 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 415 416 void amdgpu_gem_object_free(struct drm_gem_object *obj); 417 int amdgpu_gem_object_open(struct drm_gem_object *obj, 418 struct drm_file *file_priv); 419 void amdgpu_gem_object_close(struct drm_gem_object *obj, 420 struct drm_file *file_priv); 421 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 422 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 423 struct drm_gem_object * 424 amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 425 struct dma_buf_attachment *attach, 426 struct sg_table *sg); 427 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 428 struct drm_gem_object *gobj, 429 int flags); 430 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 431 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 432 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 433 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 434 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 435 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 436 437 /* sub-allocation manager, it has to be protected by another lock. 438 * By conception this is an helper for other part of the driver 439 * like the indirect buffer or semaphore, which both have their 440 * locking. 441 * 442 * Principe is simple, we keep a list of sub allocation in offset 443 * order (first entry has offset == 0, last entry has the highest 444 * offset). 445 * 446 * When allocating new object we first check if there is room at 447 * the end total_size - (last_object_offset + last_object_size) >= 448 * alloc_size. If so we allocate new object there. 449 * 450 * When there is not enough room at the end, we start waiting for 451 * each sub object until we reach object_offset+object_size >= 452 * alloc_size, this object then become the sub object we return. 453 * 454 * Alignment can't be bigger than page size. 455 * 456 * Hole are not considered for allocation to keep things simple. 457 * Assumption is that there won't be hole (all object on same 458 * alignment). 459 */ 460 461 #define AMDGPU_SA_NUM_FENCE_LISTS 32 462 463 struct amdgpu_sa_manager { 464 wait_queue_head_t wq; 465 struct amdgpu_bo *bo; 466 struct list_head *hole; 467 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 468 struct list_head olist; 469 unsigned size; 470 uint64_t gpu_addr; 471 void *cpu_ptr; 472 uint32_t domain; 473 uint32_t align; 474 }; 475 476 /* sub-allocation buffer */ 477 struct amdgpu_sa_bo { 478 struct list_head olist; 479 struct list_head flist; 480 struct amdgpu_sa_manager *manager; 481 unsigned soffset; 482 unsigned eoffset; 483 struct dma_fence *fence; 484 }; 485 486 /* 487 * GEM objects. 488 */ 489 void amdgpu_gem_force_release(struct amdgpu_device *adev); 490 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 491 int alignment, u32 initial_domain, 492 u64 flags, bool kernel, 493 struct drm_gem_object **obj); 494 495 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 496 struct drm_device *dev, 497 struct drm_mode_create_dumb *args); 498 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 499 struct drm_device *dev, 500 uint32_t handle, uint64_t *offset_p); 501 int amdgpu_fence_slab_init(void); 502 void amdgpu_fence_slab_fini(void); 503 504 /* 505 * GART structures, functions & helpers 506 */ 507 struct amdgpu_mc; 508 509 #define AMDGPU_GPU_PAGE_SIZE 4096 510 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 511 #define AMDGPU_GPU_PAGE_SHIFT 12 512 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 513 514 struct amdgpu_gart { 515 dma_addr_t table_addr; 516 struct amdgpu_bo *robj; 517 void *ptr; 518 unsigned num_gpu_pages; 519 unsigned num_cpu_pages; 520 unsigned table_size; 521 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 522 struct page **pages; 523 #endif 524 bool ready; 525 const struct amdgpu_gart_funcs *gart_funcs; 526 }; 527 528 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 529 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 530 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 531 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 532 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 533 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 534 int amdgpu_gart_init(struct amdgpu_device *adev); 535 void amdgpu_gart_fini(struct amdgpu_device *adev); 536 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 537 int pages); 538 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 539 int pages, struct page **pagelist, 540 dma_addr_t *dma_addr, uint32_t flags); 541 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev); 542 543 /* 544 * GPU MC structures, functions & helpers 545 */ 546 struct amdgpu_mc { 547 resource_size_t aper_size; 548 resource_size_t aper_base; 549 resource_size_t agp_base; 550 /* for some chips with <= 32MB we need to lie 551 * about vram size near mc fb location */ 552 u64 mc_vram_size; 553 u64 visible_vram_size; 554 u64 gtt_size; 555 u64 gtt_start; 556 u64 gtt_end; 557 u64 vram_start; 558 u64 vram_end; 559 unsigned vram_width; 560 u64 real_vram_size; 561 int vram_mtrr; 562 u64 gtt_base_align; 563 u64 mc_mask; 564 const struct firmware *fw; /* MC firmware */ 565 uint32_t fw_version; 566 struct amdgpu_irq_src vm_fault; 567 uint32_t vram_type; 568 uint32_t srbm_soft_reset; 569 struct amdgpu_mode_mc_save save; 570 }; 571 572 /* 573 * GPU doorbell structures, functions & helpers 574 */ 575 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 576 { 577 AMDGPU_DOORBELL_KIQ = 0x000, 578 AMDGPU_DOORBELL_HIQ = 0x001, 579 AMDGPU_DOORBELL_DIQ = 0x002, 580 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 581 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 582 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 583 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 584 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 585 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 586 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 587 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 588 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 589 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 590 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 591 AMDGPU_DOORBELL_IH = 0x1E8, 592 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 593 AMDGPU_DOORBELL_INVALID = 0xFFFF 594 } AMDGPU_DOORBELL_ASSIGNMENT; 595 596 struct amdgpu_doorbell { 597 /* doorbell mmio */ 598 resource_size_t base; 599 resource_size_t size; 600 u32 __iomem *ptr; 601 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 602 }; 603 604 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 605 phys_addr_t *aperture_base, 606 size_t *aperture_size, 607 size_t *start_offset); 608 609 /* 610 * IRQS. 611 */ 612 613 struct amdgpu_flip_work { 614 struct delayed_work flip_work; 615 struct work_struct unpin_work; 616 struct amdgpu_device *adev; 617 int crtc_id; 618 u32 target_vblank; 619 uint64_t base; 620 struct drm_pending_vblank_event *event; 621 struct amdgpu_bo *old_abo; 622 struct dma_fence *excl; 623 unsigned shared_count; 624 struct dma_fence **shared; 625 struct dma_fence_cb cb; 626 bool async; 627 }; 628 629 630 /* 631 * CP & rings. 632 */ 633 634 struct amdgpu_ib { 635 struct amdgpu_sa_bo *sa_bo; 636 uint32_t length_dw; 637 uint64_t gpu_addr; 638 uint32_t *ptr; 639 uint32_t flags; 640 }; 641 642 extern const struct amd_sched_backend_ops amdgpu_sched_ops; 643 644 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 645 struct amdgpu_job **job, struct amdgpu_vm *vm); 646 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 647 struct amdgpu_job **job); 648 649 void amdgpu_job_free_resources(struct amdgpu_job *job); 650 void amdgpu_job_free(struct amdgpu_job *job); 651 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 652 struct amd_sched_entity *entity, void *owner, 653 struct dma_fence **f); 654 655 /* 656 * context related structures 657 */ 658 659 struct amdgpu_ctx_ring { 660 uint64_t sequence; 661 struct dma_fence **fences; 662 struct amd_sched_entity entity; 663 }; 664 665 struct amdgpu_ctx { 666 struct kref refcount; 667 struct amdgpu_device *adev; 668 unsigned reset_counter; 669 spinlock_t ring_lock; 670 struct dma_fence **fences; 671 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 672 bool preamble_presented; 673 }; 674 675 struct amdgpu_ctx_mgr { 676 struct amdgpu_device *adev; 677 struct mutex lock; 678 /* protected by lock */ 679 struct idr ctx_handles; 680 }; 681 682 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 683 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 684 685 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 686 struct dma_fence *fence); 687 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 688 struct amdgpu_ring *ring, uint64_t seq); 689 690 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 691 struct drm_file *filp); 692 693 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 694 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 695 696 /* 697 * file private structure 698 */ 699 700 struct amdgpu_fpriv { 701 struct amdgpu_vm vm; 702 struct mutex bo_list_lock; 703 struct idr bo_list_handles; 704 struct amdgpu_ctx_mgr ctx_mgr; 705 }; 706 707 /* 708 * residency list 709 */ 710 711 struct amdgpu_bo_list { 712 struct mutex lock; 713 struct amdgpu_bo *gds_obj; 714 struct amdgpu_bo *gws_obj; 715 struct amdgpu_bo *oa_obj; 716 unsigned first_userptr; 717 unsigned num_entries; 718 struct amdgpu_bo_list_entry *array; 719 }; 720 721 struct amdgpu_bo_list * 722 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 723 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 724 struct list_head *validated); 725 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 726 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 727 728 /* 729 * GFX stuff 730 */ 731 #include "clearstate_defs.h" 732 733 struct amdgpu_rlc_funcs { 734 void (*enter_safe_mode)(struct amdgpu_device *adev); 735 void (*exit_safe_mode)(struct amdgpu_device *adev); 736 }; 737 738 struct amdgpu_rlc { 739 /* for power gating */ 740 struct amdgpu_bo *save_restore_obj; 741 uint64_t save_restore_gpu_addr; 742 volatile uint32_t *sr_ptr; 743 const u32 *reg_list; 744 u32 reg_list_size; 745 /* for clear state */ 746 struct amdgpu_bo *clear_state_obj; 747 uint64_t clear_state_gpu_addr; 748 volatile uint32_t *cs_ptr; 749 const struct cs_section_def *cs_data; 750 u32 clear_state_size; 751 /* for cp tables */ 752 struct amdgpu_bo *cp_table_obj; 753 uint64_t cp_table_gpu_addr; 754 volatile uint32_t *cp_table_ptr; 755 u32 cp_table_size; 756 757 /* safe mode for updating CG/PG state */ 758 bool in_safe_mode; 759 const struct amdgpu_rlc_funcs *funcs; 760 761 /* for firmware data */ 762 u32 save_and_restore_offset; 763 u32 clear_state_descriptor_offset; 764 u32 avail_scratch_ram_locations; 765 u32 reg_restore_list_size; 766 u32 reg_list_format_start; 767 u32 reg_list_format_separate_start; 768 u32 starting_offsets_start; 769 u32 reg_list_format_size_bytes; 770 u32 reg_list_size_bytes; 771 772 u32 *register_list_format; 773 u32 *register_restore; 774 }; 775 776 struct amdgpu_mec { 777 struct amdgpu_bo *hpd_eop_obj; 778 u64 hpd_eop_gpu_addr; 779 u32 num_pipe; 780 u32 num_mec; 781 u32 num_queue; 782 }; 783 784 struct amdgpu_kiq { 785 u64 eop_gpu_addr; 786 struct amdgpu_bo *eop_obj; 787 struct amdgpu_ring ring; 788 struct amdgpu_irq_src irq; 789 }; 790 791 /* 792 * GPU scratch registers structures, functions & helpers 793 */ 794 struct amdgpu_scratch { 795 unsigned num_reg; 796 uint32_t reg_base; 797 uint32_t free_mask; 798 }; 799 800 /* 801 * GFX configurations 802 */ 803 #define AMDGPU_GFX_MAX_SE 4 804 #define AMDGPU_GFX_MAX_SH_PER_SE 2 805 806 struct amdgpu_rb_config { 807 uint32_t rb_backend_disable; 808 uint32_t user_rb_backend_disable; 809 uint32_t raster_config; 810 uint32_t raster_config_1; 811 }; 812 813 struct amdgpu_gca_config { 814 unsigned max_shader_engines; 815 unsigned max_tile_pipes; 816 unsigned max_cu_per_sh; 817 unsigned max_sh_per_se; 818 unsigned max_backends_per_se; 819 unsigned max_texture_channel_caches; 820 unsigned max_gprs; 821 unsigned max_gs_threads; 822 unsigned max_hw_contexts; 823 unsigned sc_prim_fifo_size_frontend; 824 unsigned sc_prim_fifo_size_backend; 825 unsigned sc_hiz_tile_fifo_size; 826 unsigned sc_earlyz_tile_fifo_size; 827 828 unsigned num_tile_pipes; 829 unsigned backend_enable_mask; 830 unsigned mem_max_burst_length_bytes; 831 unsigned mem_row_size_in_kb; 832 unsigned shader_engine_tile_size; 833 unsigned num_gpus; 834 unsigned multi_gpu_tile_size; 835 unsigned mc_arb_ramcfg; 836 unsigned gb_addr_config; 837 unsigned num_rbs; 838 839 uint32_t tile_mode_array[32]; 840 uint32_t macrotile_mode_array[16]; 841 842 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 843 }; 844 845 struct amdgpu_cu_info { 846 uint32_t number; /* total active CU number */ 847 uint32_t ao_cu_mask; 848 uint32_t bitmap[4][4]; 849 }; 850 851 struct amdgpu_gfx_funcs { 852 /* get the gpu clock counter */ 853 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 854 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 855 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); 856 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); 857 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); 858 }; 859 860 struct amdgpu_gfx { 861 struct mutex gpu_clock_mutex; 862 struct amdgpu_gca_config config; 863 struct amdgpu_rlc rlc; 864 struct amdgpu_mec mec; 865 struct amdgpu_kiq kiq; 866 struct amdgpu_scratch scratch; 867 const struct firmware *me_fw; /* ME firmware */ 868 uint32_t me_fw_version; 869 const struct firmware *pfp_fw; /* PFP firmware */ 870 uint32_t pfp_fw_version; 871 const struct firmware *ce_fw; /* CE firmware */ 872 uint32_t ce_fw_version; 873 const struct firmware *rlc_fw; /* RLC firmware */ 874 uint32_t rlc_fw_version; 875 const struct firmware *mec_fw; /* MEC firmware */ 876 uint32_t mec_fw_version; 877 const struct firmware *mec2_fw; /* MEC2 firmware */ 878 uint32_t mec2_fw_version; 879 uint32_t me_feature_version; 880 uint32_t ce_feature_version; 881 uint32_t pfp_feature_version; 882 uint32_t rlc_feature_version; 883 uint32_t mec_feature_version; 884 uint32_t mec2_feature_version; 885 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 886 unsigned num_gfx_rings; 887 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 888 unsigned num_compute_rings; 889 struct amdgpu_irq_src eop_irq; 890 struct amdgpu_irq_src priv_reg_irq; 891 struct amdgpu_irq_src priv_inst_irq; 892 /* gfx status */ 893 uint32_t gfx_current_status; 894 /* ce ram size*/ 895 unsigned ce_ram_size; 896 struct amdgpu_cu_info cu_info; 897 const struct amdgpu_gfx_funcs *funcs; 898 899 /* reset mask */ 900 uint32_t grbm_soft_reset; 901 uint32_t srbm_soft_reset; 902 }; 903 904 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 905 unsigned size, struct amdgpu_ib *ib); 906 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 907 struct dma_fence *f); 908 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 909 struct amdgpu_ib *ibs, struct amdgpu_job *job, 910 struct dma_fence **f); 911 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 912 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 913 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 914 915 /* 916 * CS. 917 */ 918 struct amdgpu_cs_chunk { 919 uint32_t chunk_id; 920 uint32_t length_dw; 921 void *kdata; 922 }; 923 924 struct amdgpu_cs_parser { 925 struct amdgpu_device *adev; 926 struct drm_file *filp; 927 struct amdgpu_ctx *ctx; 928 929 /* chunks */ 930 unsigned nchunks; 931 struct amdgpu_cs_chunk *chunks; 932 933 /* scheduler job object */ 934 struct amdgpu_job *job; 935 936 /* buffer objects */ 937 struct ww_acquire_ctx ticket; 938 struct amdgpu_bo_list *bo_list; 939 struct amdgpu_bo_list_entry vm_pd; 940 struct list_head validated; 941 struct dma_fence *fence; 942 uint64_t bytes_moved_threshold; 943 uint64_t bytes_moved; 944 struct amdgpu_bo_list_entry *evictable; 945 946 /* user fence */ 947 struct amdgpu_bo_list_entry uf_entry; 948 }; 949 950 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ 951 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ 952 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ 953 #define AMDGPU_VM_DOMAIN (1 << 3) /* bit set means in virtual memory context */ 954 955 struct amdgpu_job { 956 struct amd_sched_job base; 957 struct amdgpu_device *adev; 958 struct amdgpu_vm *vm; 959 struct amdgpu_ring *ring; 960 struct amdgpu_sync sync; 961 struct amdgpu_ib *ibs; 962 struct dma_fence *fence; /* the hw fence */ 963 uint32_t preamble_status; 964 uint32_t num_ibs; 965 void *owner; 966 uint64_t fence_ctx; /* the fence_context this job uses */ 967 bool vm_needs_flush; 968 unsigned vm_id; 969 uint64_t vm_pd_addr; 970 uint32_t gds_base, gds_size; 971 uint32_t gws_base, gws_size; 972 uint32_t oa_base, oa_size; 973 974 /* user fence handling */ 975 uint64_t uf_addr; 976 uint64_t uf_sequence; 977 978 }; 979 #define to_amdgpu_job(sched_job) \ 980 container_of((sched_job), struct amdgpu_job, base) 981 982 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 983 uint32_t ib_idx, int idx) 984 { 985 return p->job->ibs[ib_idx].ptr[idx]; 986 } 987 988 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 989 uint32_t ib_idx, int idx, 990 uint32_t value) 991 { 992 p->job->ibs[ib_idx].ptr[idx] = value; 993 } 994 995 /* 996 * Writeback 997 */ 998 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 999 1000 struct amdgpu_wb { 1001 struct amdgpu_bo *wb_obj; 1002 volatile uint32_t *wb; 1003 uint64_t gpu_addr; 1004 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1005 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1006 }; 1007 1008 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1009 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1010 1011 void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1012 1013 /* 1014 * UVD 1015 */ 1016 #define AMDGPU_DEFAULT_UVD_HANDLES 10 1017 #define AMDGPU_MAX_UVD_HANDLES 40 1018 #define AMDGPU_UVD_STACK_SIZE (200*1024) 1019 #define AMDGPU_UVD_HEAP_SIZE (256*1024) 1020 #define AMDGPU_UVD_SESSION_SIZE (50*1024) 1021 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1022 1023 struct amdgpu_uvd { 1024 struct amdgpu_bo *vcpu_bo; 1025 void *cpu_addr; 1026 uint64_t gpu_addr; 1027 unsigned fw_version; 1028 void *saved_bo; 1029 unsigned max_handles; 1030 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1031 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1032 struct delayed_work idle_work; 1033 const struct firmware *fw; /* UVD firmware */ 1034 struct amdgpu_ring ring; 1035 struct amdgpu_irq_src irq; 1036 bool address_64_bit; 1037 bool use_ctx_buf; 1038 struct amd_sched_entity entity; 1039 uint32_t srbm_soft_reset; 1040 }; 1041 1042 /* 1043 * VCE 1044 */ 1045 #define AMDGPU_MAX_VCE_HANDLES 16 1046 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1047 1048 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1049 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1050 1051 struct amdgpu_vce { 1052 struct amdgpu_bo *vcpu_bo; 1053 uint64_t gpu_addr; 1054 unsigned fw_version; 1055 unsigned fb_version; 1056 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1057 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1058 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1059 struct delayed_work idle_work; 1060 struct mutex idle_mutex; 1061 const struct firmware *fw; /* VCE firmware */ 1062 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1063 struct amdgpu_irq_src irq; 1064 unsigned harvest_config; 1065 struct amd_sched_entity entity; 1066 uint32_t srbm_soft_reset; 1067 unsigned num_rings; 1068 }; 1069 1070 /* 1071 * SDMA 1072 */ 1073 struct amdgpu_sdma_instance { 1074 /* SDMA firmware */ 1075 const struct firmware *fw; 1076 uint32_t fw_version; 1077 uint32_t feature_version; 1078 1079 struct amdgpu_ring ring; 1080 bool burst_nop; 1081 }; 1082 1083 struct amdgpu_sdma { 1084 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1085 #ifdef CONFIG_DRM_AMDGPU_SI 1086 //SI DMA has a difference trap irq number for the second engine 1087 struct amdgpu_irq_src trap_irq_1; 1088 #endif 1089 struct amdgpu_irq_src trap_irq; 1090 struct amdgpu_irq_src illegal_inst_irq; 1091 int num_instances; 1092 uint32_t srbm_soft_reset; 1093 }; 1094 1095 /* 1096 * Firmware 1097 */ 1098 struct amdgpu_firmware { 1099 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1100 bool smu_load; 1101 struct amdgpu_bo *fw_buf; 1102 unsigned int fw_size; 1103 }; 1104 1105 /* 1106 * Benchmarking 1107 */ 1108 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1109 1110 1111 /* 1112 * Testing 1113 */ 1114 void amdgpu_test_moves(struct amdgpu_device *adev); 1115 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1116 struct amdgpu_ring *cpA, 1117 struct amdgpu_ring *cpB); 1118 void amdgpu_test_syncing(struct amdgpu_device *adev); 1119 1120 /* 1121 * MMU Notifier 1122 */ 1123 #if defined(CONFIG_MMU_NOTIFIER) 1124 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1125 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1126 #else 1127 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1128 { 1129 return -ENODEV; 1130 } 1131 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1132 #endif 1133 1134 /* 1135 * Debugfs 1136 */ 1137 struct amdgpu_debugfs { 1138 const struct drm_info_list *files; 1139 unsigned num_files; 1140 }; 1141 1142 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1143 const struct drm_info_list *files, 1144 unsigned nfiles); 1145 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1146 1147 #if defined(CONFIG_DEBUG_FS) 1148 int amdgpu_debugfs_init(struct drm_minor *minor); 1149 #endif 1150 1151 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); 1152 1153 /* 1154 * amdgpu smumgr functions 1155 */ 1156 struct amdgpu_smumgr_funcs { 1157 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1158 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1159 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1160 }; 1161 1162 /* 1163 * amdgpu smumgr 1164 */ 1165 struct amdgpu_smumgr { 1166 struct amdgpu_bo *toc_buf; 1167 struct amdgpu_bo *smu_buf; 1168 /* asic priv smu data */ 1169 void *priv; 1170 spinlock_t smu_lock; 1171 /* smumgr functions */ 1172 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1173 /* ucode loading complete flag */ 1174 uint32_t fw_flags; 1175 }; 1176 1177 /* 1178 * ASIC specific register table accessible by UMD 1179 */ 1180 struct amdgpu_allowed_register_entry { 1181 uint32_t reg_offset; 1182 bool untouched; 1183 bool grbm_indexed; 1184 }; 1185 1186 /* 1187 * ASIC specific functions. 1188 */ 1189 struct amdgpu_asic_funcs { 1190 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1191 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1192 u8 *bios, u32 length_bytes); 1193 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1194 u32 sh_num, u32 reg_offset, u32 *value); 1195 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1196 int (*reset)(struct amdgpu_device *adev); 1197 /* get the reference clock */ 1198 u32 (*get_xclk)(struct amdgpu_device *adev); 1199 /* MM block clocks */ 1200 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1201 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1202 /* static power management */ 1203 int (*get_pcie_lanes)(struct amdgpu_device *adev); 1204 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 1205 }; 1206 1207 /* 1208 * IOCTL. 1209 */ 1210 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1211 struct drm_file *filp); 1212 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1213 struct drm_file *filp); 1214 1215 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1216 struct drm_file *filp); 1217 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1218 struct drm_file *filp); 1219 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1220 struct drm_file *filp); 1221 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1222 struct drm_file *filp); 1223 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1224 struct drm_file *filp); 1225 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1226 struct drm_file *filp); 1227 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1228 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1229 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 1230 struct drm_file *filp); 1231 1232 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1233 struct drm_file *filp); 1234 1235 /* VRAM scratch page for HDP bug, default vram page */ 1236 struct amdgpu_vram_scratch { 1237 struct amdgpu_bo *robj; 1238 volatile uint32_t *ptr; 1239 u64 gpu_addr; 1240 }; 1241 1242 /* 1243 * ACPI 1244 */ 1245 struct amdgpu_atif_notification_cfg { 1246 bool enabled; 1247 int command_code; 1248 }; 1249 1250 struct amdgpu_atif_notifications { 1251 bool display_switch; 1252 bool expansion_mode_change; 1253 bool thermal_state; 1254 bool forced_power_state; 1255 bool system_power_state; 1256 bool display_conf_change; 1257 bool px_gfx_switch; 1258 bool brightness_change; 1259 bool dgpu_display_event; 1260 }; 1261 1262 struct amdgpu_atif_functions { 1263 bool system_params; 1264 bool sbios_requests; 1265 bool select_active_disp; 1266 bool lid_state; 1267 bool get_tv_standard; 1268 bool set_tv_standard; 1269 bool get_panel_expansion_mode; 1270 bool set_panel_expansion_mode; 1271 bool temperature_change; 1272 bool graphics_device_types; 1273 }; 1274 1275 struct amdgpu_atif { 1276 struct amdgpu_atif_notifications notifications; 1277 struct amdgpu_atif_functions functions; 1278 struct amdgpu_atif_notification_cfg notification_cfg; 1279 struct amdgpu_encoder *encoder_for_bl; 1280 }; 1281 1282 struct amdgpu_atcs_functions { 1283 bool get_ext_state; 1284 bool pcie_perf_req; 1285 bool pcie_dev_rdy; 1286 bool pcie_bus_width; 1287 }; 1288 1289 struct amdgpu_atcs { 1290 struct amdgpu_atcs_functions functions; 1291 }; 1292 1293 /* 1294 * CGS 1295 */ 1296 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1297 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1298 1299 /* 1300 * Core structure, functions and helpers. 1301 */ 1302 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1303 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1304 1305 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1306 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1307 1308 struct amdgpu_device { 1309 struct device *dev; 1310 struct drm_device *ddev; 1311 struct pci_dev *pdev; 1312 1313 #ifdef CONFIG_DRM_AMD_ACP 1314 struct amdgpu_acp acp; 1315 #endif 1316 1317 /* ASIC */ 1318 enum amd_asic_type asic_type; 1319 uint32_t family; 1320 uint32_t rev_id; 1321 uint32_t external_rev_id; 1322 unsigned long flags; 1323 int usec_timeout; 1324 const struct amdgpu_asic_funcs *asic_funcs; 1325 bool shutdown; 1326 bool need_dma32; 1327 bool accel_working; 1328 struct work_struct reset_work; 1329 struct notifier_block acpi_nb; 1330 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1331 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1332 unsigned debugfs_count; 1333 #if defined(CONFIG_DEBUG_FS) 1334 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1335 #endif 1336 struct amdgpu_atif atif; 1337 struct amdgpu_atcs atcs; 1338 struct mutex srbm_mutex; 1339 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1340 struct mutex grbm_idx_mutex; 1341 struct dev_pm_domain vga_pm_domain; 1342 bool have_disp_power_ref; 1343 1344 /* BIOS */ 1345 uint8_t *bios; 1346 uint32_t bios_size; 1347 struct amdgpu_bo *stollen_vga_memory; 1348 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1349 1350 /* Register/doorbell mmio */ 1351 resource_size_t rmmio_base; 1352 resource_size_t rmmio_size; 1353 void __iomem *rmmio; 1354 /* protects concurrent MM_INDEX/DATA based register access */ 1355 spinlock_t mmio_idx_lock; 1356 /* protects concurrent SMC based register access */ 1357 spinlock_t smc_idx_lock; 1358 amdgpu_rreg_t smc_rreg; 1359 amdgpu_wreg_t smc_wreg; 1360 /* protects concurrent PCIE register access */ 1361 spinlock_t pcie_idx_lock; 1362 amdgpu_rreg_t pcie_rreg; 1363 amdgpu_wreg_t pcie_wreg; 1364 amdgpu_rreg_t pciep_rreg; 1365 amdgpu_wreg_t pciep_wreg; 1366 /* protects concurrent UVD register access */ 1367 spinlock_t uvd_ctx_idx_lock; 1368 amdgpu_rreg_t uvd_ctx_rreg; 1369 amdgpu_wreg_t uvd_ctx_wreg; 1370 /* protects concurrent DIDT register access */ 1371 spinlock_t didt_idx_lock; 1372 amdgpu_rreg_t didt_rreg; 1373 amdgpu_wreg_t didt_wreg; 1374 /* protects concurrent gc_cac register access */ 1375 spinlock_t gc_cac_idx_lock; 1376 amdgpu_rreg_t gc_cac_rreg; 1377 amdgpu_wreg_t gc_cac_wreg; 1378 /* protects concurrent ENDPOINT (audio) register access */ 1379 spinlock_t audio_endpt_idx_lock; 1380 amdgpu_block_rreg_t audio_endpt_rreg; 1381 amdgpu_block_wreg_t audio_endpt_wreg; 1382 void __iomem *rio_mem; 1383 resource_size_t rio_mem_size; 1384 struct amdgpu_doorbell doorbell; 1385 1386 /* clock/pll info */ 1387 struct amdgpu_clock clock; 1388 1389 /* MC */ 1390 struct amdgpu_mc mc; 1391 struct amdgpu_gart gart; 1392 struct amdgpu_dummy_page dummy_page; 1393 struct amdgpu_vm_manager vm_manager; 1394 1395 /* memory management */ 1396 struct amdgpu_mman mman; 1397 struct amdgpu_vram_scratch vram_scratch; 1398 struct amdgpu_wb wb; 1399 atomic64_t vram_usage; 1400 atomic64_t vram_vis_usage; 1401 atomic64_t gtt_usage; 1402 atomic64_t num_bytes_moved; 1403 atomic64_t num_evictions; 1404 atomic_t gpu_reset_counter; 1405 1406 /* data for buffer migration throttling */ 1407 struct { 1408 spinlock_t lock; 1409 s64 last_update_us; 1410 s64 accum_us; /* accumulated microseconds */ 1411 u32 log2_max_MBps; 1412 } mm_stats; 1413 1414 /* display */ 1415 bool enable_virtual_display; 1416 struct amdgpu_mode_info mode_info; 1417 struct work_struct hotplug_work; 1418 struct amdgpu_irq_src crtc_irq; 1419 struct amdgpu_irq_src pageflip_irq; 1420 struct amdgpu_irq_src hpd_irq; 1421 1422 /* rings */ 1423 u64 fence_context; 1424 unsigned num_rings; 1425 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1426 bool ib_pool_ready; 1427 struct amdgpu_sa_manager ring_tmp_bo; 1428 1429 /* interrupts */ 1430 struct amdgpu_irq irq; 1431 1432 /* powerplay */ 1433 struct amd_powerplay powerplay; 1434 bool pp_enabled; 1435 bool pp_force_state_enabled; 1436 1437 /* dpm */ 1438 struct amdgpu_pm pm; 1439 u32 cg_flags; 1440 u32 pg_flags; 1441 1442 /* amdgpu smumgr */ 1443 struct amdgpu_smumgr smu; 1444 1445 /* gfx */ 1446 struct amdgpu_gfx gfx; 1447 1448 /* sdma */ 1449 struct amdgpu_sdma sdma; 1450 1451 /* uvd */ 1452 struct amdgpu_uvd uvd; 1453 1454 /* vce */ 1455 struct amdgpu_vce vce; 1456 1457 /* firmwares */ 1458 struct amdgpu_firmware firmware; 1459 1460 /* GDS */ 1461 struct amdgpu_gds gds; 1462 1463 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1464 int num_ip_blocks; 1465 struct mutex mn_lock; 1466 DECLARE_HASHTABLE(mn_hash, 7); 1467 1468 /* tracking pinned memory */ 1469 u64 vram_pin_size; 1470 u64 invisible_pin_size; 1471 u64 gart_pin_size; 1472 1473 /* amdkfd interface */ 1474 struct kfd_dev *kfd; 1475 1476 struct amdgpu_virt virt; 1477 1478 /* link all shadow bo */ 1479 struct list_head shadow_list; 1480 struct mutex shadow_list_lock; 1481 /* link all gtt */ 1482 spinlock_t gtt_list_lock; 1483 struct list_head gtt_list; 1484 1485 /* record hw reset is performed */ 1486 bool has_hw_reset; 1487 1488 }; 1489 1490 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1491 { 1492 return container_of(bdev, struct amdgpu_device, mman.bdev); 1493 } 1494 1495 bool amdgpu_device_is_px(struct drm_device *dev); 1496 int amdgpu_device_init(struct amdgpu_device *adev, 1497 struct drm_device *ddev, 1498 struct pci_dev *pdev, 1499 uint32_t flags); 1500 void amdgpu_device_fini(struct amdgpu_device *adev); 1501 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1502 1503 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1504 bool always_indirect); 1505 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1506 bool always_indirect); 1507 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1508 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1509 1510 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 1511 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1512 1513 /* 1514 * Registers read & write functions. 1515 */ 1516 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 1517 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 1518 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 1519 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 1520 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 1521 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1522 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1523 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1524 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1525 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1526 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1527 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1528 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1529 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1530 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1531 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1532 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1533 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1534 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1535 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1536 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1537 #define WREG32_P(reg, val, mask) \ 1538 do { \ 1539 uint32_t tmp_ = RREG32(reg); \ 1540 tmp_ &= (mask); \ 1541 tmp_ |= ((val) & ~(mask)); \ 1542 WREG32(reg, tmp_); \ 1543 } while (0) 1544 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1545 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1546 #define WREG32_PLL_P(reg, val, mask) \ 1547 do { \ 1548 uint32_t tmp_ = RREG32_PLL(reg); \ 1549 tmp_ &= (mask); \ 1550 tmp_ |= ((val) & ~(mask)); \ 1551 WREG32_PLL(reg, tmp_); \ 1552 } while (0) 1553 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1554 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1555 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1556 1557 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 1558 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1559 1560 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1561 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1562 1563 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1564 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1565 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1566 1567 #define REG_GET_FIELD(value, reg, field) \ 1568 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1569 1570 #define WREG32_FIELD(reg, field, val) \ 1571 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1572 1573 /* 1574 * BIOS helpers. 1575 */ 1576 #define RBIOS8(i) (adev->bios[i]) 1577 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1578 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1579 1580 /* 1581 * RING helpers. 1582 */ 1583 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 1584 { 1585 if (ring->count_dw <= 0) 1586 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 1587 ring->ring[ring->wptr++] = v; 1588 ring->wptr &= ring->ptr_mask; 1589 ring->count_dw--; 1590 } 1591 1592 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw) 1593 { 1594 unsigned occupied, chunk1, chunk2; 1595 void *dst; 1596 1597 if (ring->count_dw < count_dw) { 1598 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 1599 } else { 1600 occupied = ring->wptr & ring->ptr_mask; 1601 dst = (void *)&ring->ring[occupied]; 1602 chunk1 = ring->ptr_mask + 1 - occupied; 1603 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; 1604 chunk2 = count_dw - chunk1; 1605 chunk1 <<= 2; 1606 chunk2 <<= 2; 1607 1608 if (chunk1) 1609 memcpy(dst, src, chunk1); 1610 1611 if (chunk2) { 1612 src += chunk1; 1613 dst = (void *)ring->ring; 1614 memcpy(dst, src, chunk2); 1615 } 1616 1617 ring->wptr += count_dw; 1618 ring->wptr &= ring->ptr_mask; 1619 ring->count_dw -= count_dw; 1620 } 1621 } 1622 1623 static inline struct amdgpu_sdma_instance * 1624 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 1625 { 1626 struct amdgpu_device *adev = ring->adev; 1627 int i; 1628 1629 for (i = 0; i < adev->sdma.num_instances; i++) 1630 if (&adev->sdma.instance[i].ring == ring) 1631 break; 1632 1633 if (i < AMDGPU_MAX_SDMA_INSTANCES) 1634 return &adev->sdma.instance[i]; 1635 else 1636 return NULL; 1637 } 1638 1639 /* 1640 * ASICs macro. 1641 */ 1642 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1643 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1644 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1645 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1646 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1647 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1648 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1649 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1650 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1651 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1652 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1653 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 1654 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 1655 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 1656 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 1657 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 1658 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 1659 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 1660 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 1661 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 1662 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 1663 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 1664 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 1665 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 1666 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 1667 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 1668 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 1669 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 1670 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 1671 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 1672 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 1673 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) 1674 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 1675 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 1676 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 1677 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 1678 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 1679 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 1680 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 1681 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 1682 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 1683 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 1684 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 1685 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 1686 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 1687 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 1688 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 1689 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 1690 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 1691 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 1692 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 1693 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 1694 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 1695 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 1696 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 1697 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 1698 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 1699 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 1700 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 1701 1702 /* Common functions */ 1703 int amdgpu_gpu_reset(struct amdgpu_device *adev); 1704 bool amdgpu_need_backup(struct amdgpu_device *adev); 1705 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 1706 bool amdgpu_need_post(struct amdgpu_device *adev); 1707 void amdgpu_update_display_priority(struct amdgpu_device *adev); 1708 1709 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 1710 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 1711 u32 ip_instance, u32 ring, 1712 struct amdgpu_ring **out_ring); 1713 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes); 1714 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 1715 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 1716 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 1717 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 1718 uint32_t flags); 1719 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 1720 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 1721 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1722 unsigned long end); 1723 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 1724 int *last_invalidated); 1725 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 1726 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1727 struct ttm_mem_reg *mem); 1728 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 1729 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 1730 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 1731 int amdgpu_ttm_init(struct amdgpu_device *adev); 1732 void amdgpu_ttm_fini(struct amdgpu_device *adev); 1733 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 1734 const u32 *registers, 1735 const u32 array_size); 1736 1737 bool amdgpu_device_is_px(struct drm_device *dev); 1738 /* atpx handler */ 1739 #if defined(CONFIG_VGA_SWITCHEROO) 1740 void amdgpu_register_atpx_handler(void); 1741 void amdgpu_unregister_atpx_handler(void); 1742 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1743 bool amdgpu_is_atpx_hybrid(void); 1744 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1745 #else 1746 static inline void amdgpu_register_atpx_handler(void) {} 1747 static inline void amdgpu_unregister_atpx_handler(void) {} 1748 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1749 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1750 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1751 #endif 1752 1753 /* 1754 * KMS 1755 */ 1756 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1757 extern const int amdgpu_max_kms_ioctl; 1758 1759 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1760 void amdgpu_driver_unload_kms(struct drm_device *dev); 1761 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1762 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1763 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1764 struct drm_file *file_priv); 1765 void amdgpu_driver_preclose_kms(struct drm_device *dev, 1766 struct drm_file *file_priv); 1767 int amdgpu_suspend(struct amdgpu_device *adev); 1768 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1769 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1770 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1771 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1772 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1773 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 1774 int *max_error, 1775 struct timeval *vblank_time, 1776 unsigned flags); 1777 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1778 unsigned long arg); 1779 1780 /* 1781 * functions used by amdgpu_encoder.c 1782 */ 1783 struct amdgpu_afmt_acr { 1784 u32 clock; 1785 1786 int n_32khz; 1787 int cts_32khz; 1788 1789 int n_44_1khz; 1790 int cts_44_1khz; 1791 1792 int n_48khz; 1793 int cts_48khz; 1794 1795 }; 1796 1797 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1798 1799 /* amdgpu_acpi.c */ 1800 #if defined(CONFIG_ACPI) 1801 int amdgpu_acpi_init(struct amdgpu_device *adev); 1802 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1803 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1804 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1805 u8 perf_req, bool advertise); 1806 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1807 #else 1808 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1809 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1810 #endif 1811 1812 struct amdgpu_bo_va_mapping * 1813 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1814 uint64_t addr, struct amdgpu_bo **bo); 1815 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser); 1816 1817 #include "amdgpu_object.h" 1818 #endif 1819