1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include "amdgpu_ctx.h" 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/rbtree.h> 38 #include <linux/hashtable.h> 39 #include <linux/dma-fence.h> 40 41 #include <drm/ttm/ttm_bo_api.h> 42 #include <drm/ttm/ttm_bo_driver.h> 43 #include <drm/ttm/ttm_placement.h> 44 #include <drm/ttm/ttm_module.h> 45 #include <drm/ttm/ttm_execbuf_util.h> 46 47 #include <drm/amdgpu_drm.h> 48 #include <drm/drm_gem.h> 49 #include <drm/drm_ioctl.h> 50 #include <drm/gpu_scheduler.h> 51 52 #include <kgd_kfd_interface.h> 53 #include "dm_pp_interface.h" 54 #include "kgd_pp_interface.h" 55 56 #include "amd_shared.h" 57 #include "amdgpu_mode.h" 58 #include "amdgpu_ih.h" 59 #include "amdgpu_irq.h" 60 #include "amdgpu_ucode.h" 61 #include "amdgpu_ttm.h" 62 #include "amdgpu_psp.h" 63 #include "amdgpu_gds.h" 64 #include "amdgpu_sync.h" 65 #include "amdgpu_ring.h" 66 #include "amdgpu_vm.h" 67 #include "amdgpu_dpm.h" 68 #include "amdgpu_acp.h" 69 #include "amdgpu_uvd.h" 70 #include "amdgpu_vce.h" 71 #include "amdgpu_vcn.h" 72 #include "amdgpu_jpeg.h" 73 #include "amdgpu_mn.h" 74 #include "amdgpu_gmc.h" 75 #include "amdgpu_gfx.h" 76 #include "amdgpu_sdma.h" 77 #include "amdgpu_nbio.h" 78 #include "amdgpu_dm.h" 79 #include "amdgpu_virt.h" 80 #include "amdgpu_csa.h" 81 #include "amdgpu_gart.h" 82 #include "amdgpu_debugfs.h" 83 #include "amdgpu_job.h" 84 #include "amdgpu_bo_list.h" 85 #include "amdgpu_gem.h" 86 #include "amdgpu_doorbell.h" 87 #include "amdgpu_amdkfd.h" 88 #include "amdgpu_smu.h" 89 #include "amdgpu_discovery.h" 90 #include "amdgpu_mes.h" 91 #include "amdgpu_umc.h" 92 #include "amdgpu_mmhub.h" 93 #include "amdgpu_df.h" 94 95 #define MAX_GPU_INSTANCE 16 96 97 struct amdgpu_gpu_instance 98 { 99 struct amdgpu_device *adev; 100 int mgpu_fan_enabled; 101 }; 102 103 struct amdgpu_mgpu_info 104 { 105 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 106 struct mutex mutex; 107 uint32_t num_gpu; 108 uint32_t num_dgpu; 109 uint32_t num_apu; 110 }; 111 112 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 113 114 /* 115 * Modules parameters. 116 */ 117 extern int amdgpu_modeset; 118 extern int amdgpu_vram_limit; 119 extern int amdgpu_vis_vram_limit; 120 extern int amdgpu_gart_size; 121 extern int amdgpu_gtt_size; 122 extern int amdgpu_moverate; 123 extern int amdgpu_benchmarking; 124 extern int amdgpu_testing; 125 extern int amdgpu_audio; 126 extern int amdgpu_disp_priority; 127 extern int amdgpu_hw_i2c; 128 extern int amdgpu_pcie_gen2; 129 extern int amdgpu_msi; 130 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 131 extern int amdgpu_dpm; 132 extern int amdgpu_fw_load_type; 133 extern int amdgpu_aspm; 134 extern int amdgpu_runtime_pm; 135 extern uint amdgpu_ip_block_mask; 136 extern int amdgpu_bapm; 137 extern int amdgpu_deep_color; 138 extern int amdgpu_vm_size; 139 extern int amdgpu_vm_block_size; 140 extern int amdgpu_vm_fragment_size; 141 extern int amdgpu_vm_fault_stop; 142 extern int amdgpu_vm_debug; 143 extern int amdgpu_vm_update_mode; 144 extern int amdgpu_exp_hw_support; 145 extern int amdgpu_dc; 146 extern int amdgpu_sched_jobs; 147 extern int amdgpu_sched_hw_submission; 148 extern uint amdgpu_pcie_gen_cap; 149 extern uint amdgpu_pcie_lane_cap; 150 extern uint amdgpu_cg_mask; 151 extern uint amdgpu_pg_mask; 152 extern uint amdgpu_sdma_phase_quantum; 153 extern char *amdgpu_disable_cu; 154 extern char *amdgpu_virtual_display; 155 extern uint amdgpu_pp_feature_mask; 156 extern uint amdgpu_force_long_training; 157 extern int amdgpu_job_hang_limit; 158 extern int amdgpu_lbpw; 159 extern int amdgpu_compute_multipipe; 160 extern int amdgpu_gpu_recovery; 161 extern int amdgpu_emu_mode; 162 extern uint amdgpu_smu_memory_pool_size; 163 extern uint amdgpu_dc_feature_mask; 164 extern uint amdgpu_dm_abm_level; 165 extern struct amdgpu_mgpu_info mgpu_info; 166 extern int amdgpu_ras_enable; 167 extern uint amdgpu_ras_mask; 168 extern int amdgpu_async_gfx_ring; 169 extern int amdgpu_mcbp; 170 extern int amdgpu_discovery; 171 extern int amdgpu_mes; 172 extern int amdgpu_noretry; 173 extern int amdgpu_force_asic_type; 174 #ifdef CONFIG_HSA_AMD 175 extern int sched_policy; 176 #else 177 static const int sched_policy = KFD_SCHED_POLICY_HWS; 178 #endif 179 180 #ifdef CONFIG_DRM_AMDGPU_SI 181 extern int amdgpu_si_support; 182 #endif 183 #ifdef CONFIG_DRM_AMDGPU_CIK 184 extern int amdgpu_cik_support; 185 #endif 186 187 #define AMDGPU_VM_MAX_NUM_CTX 4096 188 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 189 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 190 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 191 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 192 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 193 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 194 #define AMDGPU_IB_POOL_SIZE 16 195 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 196 #define AMDGPUFB_CONN_LIMIT 4 197 #define AMDGPU_BIOS_NUM_SCRATCH 16 198 199 /* hard reset data */ 200 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 201 202 /* reset flags */ 203 #define AMDGPU_RESET_GFX (1 << 0) 204 #define AMDGPU_RESET_COMPUTE (1 << 1) 205 #define AMDGPU_RESET_DMA (1 << 2) 206 #define AMDGPU_RESET_CP (1 << 3) 207 #define AMDGPU_RESET_GRBM (1 << 4) 208 #define AMDGPU_RESET_DMA1 (1 << 5) 209 #define AMDGPU_RESET_RLC (1 << 6) 210 #define AMDGPU_RESET_SEM (1 << 7) 211 #define AMDGPU_RESET_IH (1 << 8) 212 #define AMDGPU_RESET_VMC (1 << 9) 213 #define AMDGPU_RESET_MC (1 << 10) 214 #define AMDGPU_RESET_DISPLAY (1 << 11) 215 #define AMDGPU_RESET_UVD (1 << 12) 216 #define AMDGPU_RESET_VCE (1 << 13) 217 #define AMDGPU_RESET_VCE1 (1 << 14) 218 219 /* max cursor sizes (in pixels) */ 220 #define CIK_CURSOR_WIDTH 128 221 #define CIK_CURSOR_HEIGHT 128 222 223 struct amdgpu_device; 224 struct amdgpu_ib; 225 struct amdgpu_cs_parser; 226 struct amdgpu_job; 227 struct amdgpu_irq_src; 228 struct amdgpu_fpriv; 229 struct amdgpu_bo_va_mapping; 230 struct amdgpu_atif; 231 struct kfd_vm_fault_info; 232 233 enum amdgpu_cp_irq { 234 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 235 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 236 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 237 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 238 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 239 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 240 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 241 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 242 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 243 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 244 245 AMDGPU_CP_IRQ_LAST 246 }; 247 248 enum amdgpu_thermal_irq { 249 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 250 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 251 252 AMDGPU_THERMAL_IRQ_LAST 253 }; 254 255 enum amdgpu_kiq_irq { 256 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 257 AMDGPU_CP_KIQ_IRQ_LAST 258 }; 259 260 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 261 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 262 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 263 264 int amdgpu_device_ip_set_clockgating_state(void *dev, 265 enum amd_ip_block_type block_type, 266 enum amd_clockgating_state state); 267 int amdgpu_device_ip_set_powergating_state(void *dev, 268 enum amd_ip_block_type block_type, 269 enum amd_powergating_state state); 270 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 271 u32 *flags); 272 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 273 enum amd_ip_block_type block_type); 274 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 275 enum amd_ip_block_type block_type); 276 277 #define AMDGPU_MAX_IP_NUM 16 278 279 struct amdgpu_ip_block_status { 280 bool valid; 281 bool sw; 282 bool hw; 283 bool late_initialized; 284 bool hang; 285 }; 286 287 struct amdgpu_ip_block_version { 288 const enum amd_ip_block_type type; 289 const u32 major; 290 const u32 minor; 291 const u32 rev; 292 const struct amd_ip_funcs *funcs; 293 }; 294 295 #define HW_REV(_Major, _Minor, _Rev) \ 296 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 297 298 struct amdgpu_ip_block { 299 struct amdgpu_ip_block_status status; 300 const struct amdgpu_ip_block_version *version; 301 }; 302 303 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 304 enum amd_ip_block_type type, 305 u32 major, u32 minor); 306 307 struct amdgpu_ip_block * 308 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 309 enum amd_ip_block_type type); 310 311 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 312 const struct amdgpu_ip_block_version *ip_block_version); 313 314 /* 315 * BIOS. 316 */ 317 bool amdgpu_get_bios(struct amdgpu_device *adev); 318 bool amdgpu_read_bios(struct amdgpu_device *adev); 319 320 /* 321 * Clocks 322 */ 323 324 #define AMDGPU_MAX_PPLL 3 325 326 struct amdgpu_clock { 327 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 328 struct amdgpu_pll spll; 329 struct amdgpu_pll mpll; 330 /* 10 Khz units */ 331 uint32_t default_mclk; 332 uint32_t default_sclk; 333 uint32_t default_dispclk; 334 uint32_t current_dispclk; 335 uint32_t dp_extclk; 336 uint32_t max_pixel_clock; 337 }; 338 339 /* sub-allocation manager, it has to be protected by another lock. 340 * By conception this is an helper for other part of the driver 341 * like the indirect buffer or semaphore, which both have their 342 * locking. 343 * 344 * Principe is simple, we keep a list of sub allocation in offset 345 * order (first entry has offset == 0, last entry has the highest 346 * offset). 347 * 348 * When allocating new object we first check if there is room at 349 * the end total_size - (last_object_offset + last_object_size) >= 350 * alloc_size. If so we allocate new object there. 351 * 352 * When there is not enough room at the end, we start waiting for 353 * each sub object until we reach object_offset+object_size >= 354 * alloc_size, this object then become the sub object we return. 355 * 356 * Alignment can't be bigger than page size. 357 * 358 * Hole are not considered for allocation to keep things simple. 359 * Assumption is that there won't be hole (all object on same 360 * alignment). 361 */ 362 363 #define AMDGPU_SA_NUM_FENCE_LISTS 32 364 365 struct amdgpu_sa_manager { 366 wait_queue_head_t wq; 367 struct amdgpu_bo *bo; 368 struct list_head *hole; 369 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 370 struct list_head olist; 371 unsigned size; 372 uint64_t gpu_addr; 373 void *cpu_ptr; 374 uint32_t domain; 375 uint32_t align; 376 }; 377 378 /* sub-allocation buffer */ 379 struct amdgpu_sa_bo { 380 struct list_head olist; 381 struct list_head flist; 382 struct amdgpu_sa_manager *manager; 383 unsigned soffset; 384 unsigned eoffset; 385 struct dma_fence *fence; 386 }; 387 388 int amdgpu_fence_slab_init(void); 389 void amdgpu_fence_slab_fini(void); 390 391 /* 392 * IRQS. 393 */ 394 395 struct amdgpu_flip_work { 396 struct delayed_work flip_work; 397 struct work_struct unpin_work; 398 struct amdgpu_device *adev; 399 int crtc_id; 400 u32 target_vblank; 401 uint64_t base; 402 struct drm_pending_vblank_event *event; 403 struct amdgpu_bo *old_abo; 404 struct dma_fence *excl; 405 unsigned shared_count; 406 struct dma_fence **shared; 407 struct dma_fence_cb cb; 408 bool async; 409 }; 410 411 412 /* 413 * CP & rings. 414 */ 415 416 struct amdgpu_ib { 417 struct amdgpu_sa_bo *sa_bo; 418 uint32_t length_dw; 419 uint64_t gpu_addr; 420 uint32_t *ptr; 421 uint32_t flags; 422 }; 423 424 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 425 426 /* 427 * file private structure 428 */ 429 430 struct amdgpu_fpriv { 431 struct amdgpu_vm vm; 432 struct amdgpu_bo_va *prt_va; 433 struct amdgpu_bo_va *csa_va; 434 struct mutex bo_list_lock; 435 struct idr bo_list_handles; 436 struct amdgpu_ctx_mgr ctx_mgr; 437 }; 438 439 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 440 441 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 442 unsigned size, struct amdgpu_ib *ib); 443 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 444 struct dma_fence *f); 445 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 446 struct amdgpu_ib *ibs, struct amdgpu_job *job, 447 struct dma_fence **f); 448 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 449 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 450 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 451 452 /* 453 * CS. 454 */ 455 struct amdgpu_cs_chunk { 456 uint32_t chunk_id; 457 uint32_t length_dw; 458 void *kdata; 459 }; 460 461 struct amdgpu_cs_post_dep { 462 struct drm_syncobj *syncobj; 463 struct dma_fence_chain *chain; 464 u64 point; 465 }; 466 467 struct amdgpu_cs_parser { 468 struct amdgpu_device *adev; 469 struct drm_file *filp; 470 struct amdgpu_ctx *ctx; 471 472 /* chunks */ 473 unsigned nchunks; 474 struct amdgpu_cs_chunk *chunks; 475 476 /* scheduler job object */ 477 struct amdgpu_job *job; 478 struct drm_sched_entity *entity; 479 480 /* buffer objects */ 481 struct ww_acquire_ctx ticket; 482 struct amdgpu_bo_list *bo_list; 483 struct amdgpu_mn *mn; 484 struct amdgpu_bo_list_entry vm_pd; 485 struct list_head validated; 486 struct dma_fence *fence; 487 uint64_t bytes_moved_threshold; 488 uint64_t bytes_moved_vis_threshold; 489 uint64_t bytes_moved; 490 uint64_t bytes_moved_vis; 491 492 /* user fence */ 493 struct amdgpu_bo_list_entry uf_entry; 494 495 unsigned num_post_deps; 496 struct amdgpu_cs_post_dep *post_deps; 497 }; 498 499 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 500 uint32_t ib_idx, int idx) 501 { 502 return p->job->ibs[ib_idx].ptr[idx]; 503 } 504 505 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 506 uint32_t ib_idx, int idx, 507 uint32_t value) 508 { 509 p->job->ibs[ib_idx].ptr[idx] = value; 510 } 511 512 /* 513 * Writeback 514 */ 515 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 516 517 struct amdgpu_wb { 518 struct amdgpu_bo *wb_obj; 519 volatile uint32_t *wb; 520 uint64_t gpu_addr; 521 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 522 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 523 }; 524 525 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 526 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 527 528 /* 529 * Benchmarking 530 */ 531 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 532 533 534 /* 535 * Testing 536 */ 537 void amdgpu_test_moves(struct amdgpu_device *adev); 538 539 /* 540 * ASIC specific register table accessible by UMD 541 */ 542 struct amdgpu_allowed_register_entry { 543 uint32_t reg_offset; 544 bool grbm_indexed; 545 }; 546 547 enum amd_reset_method { 548 AMD_RESET_METHOD_LEGACY = 0, 549 AMD_RESET_METHOD_MODE0, 550 AMD_RESET_METHOD_MODE1, 551 AMD_RESET_METHOD_MODE2, 552 AMD_RESET_METHOD_BACO 553 }; 554 555 /* 556 * ASIC specific functions. 557 */ 558 struct amdgpu_asic_funcs { 559 bool (*read_disabled_bios)(struct amdgpu_device *adev); 560 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 561 u8 *bios, u32 length_bytes); 562 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 563 u32 sh_num, u32 reg_offset, u32 *value); 564 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 565 int (*reset)(struct amdgpu_device *adev); 566 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 567 /* get the reference clock */ 568 u32 (*get_xclk)(struct amdgpu_device *adev); 569 /* MM block clocks */ 570 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 571 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 572 /* static power management */ 573 int (*get_pcie_lanes)(struct amdgpu_device *adev); 574 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 575 /* get config memsize register */ 576 u32 (*get_config_memsize)(struct amdgpu_device *adev); 577 /* flush hdp write queue */ 578 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 579 /* invalidate hdp read cache */ 580 void (*invalidate_hdp)(struct amdgpu_device *adev, 581 struct amdgpu_ring *ring); 582 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev); 583 /* check if the asic needs a full reset of if soft reset will work */ 584 bool (*need_full_reset)(struct amdgpu_device *adev); 585 /* initialize doorbell layout for specific asic*/ 586 void (*init_doorbell_index)(struct amdgpu_device *adev); 587 /* PCIe bandwidth usage */ 588 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 589 uint64_t *count1); 590 /* do we need to reset the asic at init time (e.g., kexec) */ 591 bool (*need_reset_on_init)(struct amdgpu_device *adev); 592 /* PCIe replay counter */ 593 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 594 /* device supports BACO */ 595 bool (*supports_baco)(struct amdgpu_device *adev); 596 }; 597 598 /* 599 * IOCTL. 600 */ 601 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 602 struct drm_file *filp); 603 604 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 605 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 606 struct drm_file *filp); 607 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 608 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 609 struct drm_file *filp); 610 611 /* VRAM scratch page for HDP bug, default vram page */ 612 struct amdgpu_vram_scratch { 613 struct amdgpu_bo *robj; 614 volatile uint32_t *ptr; 615 u64 gpu_addr; 616 }; 617 618 /* 619 * ACPI 620 */ 621 struct amdgpu_atcs_functions { 622 bool get_ext_state; 623 bool pcie_perf_req; 624 bool pcie_dev_rdy; 625 bool pcie_bus_width; 626 }; 627 628 struct amdgpu_atcs { 629 struct amdgpu_atcs_functions functions; 630 }; 631 632 /* 633 * Firmware VRAM reservation 634 */ 635 struct amdgpu_fw_vram_usage { 636 u64 start_offset; 637 u64 size; 638 struct amdgpu_bo *reserved_bo; 639 void *va; 640 641 /* GDDR6 training support flag. 642 */ 643 bool mem_train_support; 644 }; 645 646 /* 647 * CGS 648 */ 649 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 650 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 651 652 /* 653 * Core structure, functions and helpers. 654 */ 655 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 656 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 657 658 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 659 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 660 661 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 662 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 663 664 struct amdgpu_mmio_remap { 665 u32 reg_offset; 666 resource_size_t bus_addr; 667 }; 668 669 /* Define the HW IP blocks will be used in driver , add more if necessary */ 670 enum amd_hw_ip_block_type { 671 GC_HWIP = 1, 672 HDP_HWIP, 673 SDMA0_HWIP, 674 SDMA1_HWIP, 675 SDMA2_HWIP, 676 SDMA3_HWIP, 677 SDMA4_HWIP, 678 SDMA5_HWIP, 679 SDMA6_HWIP, 680 SDMA7_HWIP, 681 MMHUB_HWIP, 682 ATHUB_HWIP, 683 NBIO_HWIP, 684 MP0_HWIP, 685 MP1_HWIP, 686 UVD_HWIP, 687 VCN_HWIP = UVD_HWIP, 688 JPEG_HWIP = VCN_HWIP, 689 VCE_HWIP, 690 DF_HWIP, 691 DCE_HWIP, 692 OSSSYS_HWIP, 693 SMUIO_HWIP, 694 PWR_HWIP, 695 NBIF_HWIP, 696 THM_HWIP, 697 CLK_HWIP, 698 UMC_HWIP, 699 RSMU_HWIP, 700 MAX_HWIP 701 }; 702 703 #define HWIP_MAX_INSTANCE 8 704 705 struct amd_powerplay { 706 void *pp_handle; 707 const struct amd_pm_funcs *pp_funcs; 708 }; 709 710 #define AMDGPU_RESET_MAGIC_NUM 64 711 #define AMDGPU_MAX_DF_PERFMONS 4 712 struct amdgpu_device { 713 struct device *dev; 714 struct drm_device *ddev; 715 struct pci_dev *pdev; 716 717 #ifdef CONFIG_DRM_AMD_ACP 718 struct amdgpu_acp acp; 719 #endif 720 721 /* ASIC */ 722 enum amd_asic_type asic_type; 723 uint32_t family; 724 uint32_t rev_id; 725 uint32_t external_rev_id; 726 unsigned long flags; 727 int usec_timeout; 728 const struct amdgpu_asic_funcs *asic_funcs; 729 bool shutdown; 730 bool need_swiotlb; 731 bool accel_working; 732 struct notifier_block acpi_nb; 733 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 734 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 735 unsigned debugfs_count; 736 #if defined(CONFIG_DEBUG_FS) 737 struct dentry *debugfs_preempt; 738 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 739 #endif 740 struct amdgpu_atif *atif; 741 struct amdgpu_atcs atcs; 742 struct mutex srbm_mutex; 743 /* GRBM index mutex. Protects concurrent access to GRBM index */ 744 struct mutex grbm_idx_mutex; 745 struct dev_pm_domain vga_pm_domain; 746 bool have_disp_power_ref; 747 bool have_atomics_support; 748 749 /* BIOS */ 750 bool is_atom_fw; 751 uint8_t *bios; 752 uint32_t bios_size; 753 struct amdgpu_bo *stolen_vga_memory; 754 struct amdgpu_bo *discovery_memory; 755 uint32_t bios_scratch_reg_offset; 756 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 757 758 /* Register/doorbell mmio */ 759 resource_size_t rmmio_base; 760 resource_size_t rmmio_size; 761 void __iomem *rmmio; 762 /* protects concurrent MM_INDEX/DATA based register access */ 763 spinlock_t mmio_idx_lock; 764 struct amdgpu_mmio_remap rmmio_remap; 765 /* protects concurrent SMC based register access */ 766 spinlock_t smc_idx_lock; 767 amdgpu_rreg_t smc_rreg; 768 amdgpu_wreg_t smc_wreg; 769 /* protects concurrent PCIE register access */ 770 spinlock_t pcie_idx_lock; 771 amdgpu_rreg_t pcie_rreg; 772 amdgpu_wreg_t pcie_wreg; 773 amdgpu_rreg_t pciep_rreg; 774 amdgpu_wreg_t pciep_wreg; 775 amdgpu_rreg64_t pcie_rreg64; 776 amdgpu_wreg64_t pcie_wreg64; 777 /* protects concurrent UVD register access */ 778 spinlock_t uvd_ctx_idx_lock; 779 amdgpu_rreg_t uvd_ctx_rreg; 780 amdgpu_wreg_t uvd_ctx_wreg; 781 /* protects concurrent DIDT register access */ 782 spinlock_t didt_idx_lock; 783 amdgpu_rreg_t didt_rreg; 784 amdgpu_wreg_t didt_wreg; 785 /* protects concurrent gc_cac register access */ 786 spinlock_t gc_cac_idx_lock; 787 amdgpu_rreg_t gc_cac_rreg; 788 amdgpu_wreg_t gc_cac_wreg; 789 /* protects concurrent se_cac register access */ 790 spinlock_t se_cac_idx_lock; 791 amdgpu_rreg_t se_cac_rreg; 792 amdgpu_wreg_t se_cac_wreg; 793 /* protects concurrent ENDPOINT (audio) register access */ 794 spinlock_t audio_endpt_idx_lock; 795 amdgpu_block_rreg_t audio_endpt_rreg; 796 amdgpu_block_wreg_t audio_endpt_wreg; 797 void __iomem *rio_mem; 798 resource_size_t rio_mem_size; 799 struct amdgpu_doorbell doorbell; 800 801 /* clock/pll info */ 802 struct amdgpu_clock clock; 803 804 /* MC */ 805 struct amdgpu_gmc gmc; 806 struct amdgpu_gart gart; 807 dma_addr_t dummy_page_addr; 808 struct amdgpu_vm_manager vm_manager; 809 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 810 unsigned num_vmhubs; 811 812 /* memory management */ 813 struct amdgpu_mman mman; 814 struct amdgpu_vram_scratch vram_scratch; 815 struct amdgpu_wb wb; 816 atomic64_t num_bytes_moved; 817 atomic64_t num_evictions; 818 atomic64_t num_vram_cpu_page_faults; 819 atomic_t gpu_reset_counter; 820 atomic_t vram_lost_counter; 821 822 /* data for buffer migration throttling */ 823 struct { 824 spinlock_t lock; 825 s64 last_update_us; 826 s64 accum_us; /* accumulated microseconds */ 827 s64 accum_us_vis; /* for visible VRAM */ 828 u32 log2_max_MBps; 829 } mm_stats; 830 831 /* display */ 832 bool enable_virtual_display; 833 struct amdgpu_mode_info mode_info; 834 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 835 struct work_struct hotplug_work; 836 struct amdgpu_irq_src crtc_irq; 837 struct amdgpu_irq_src vupdate_irq; 838 struct amdgpu_irq_src pageflip_irq; 839 struct amdgpu_irq_src hpd_irq; 840 841 /* rings */ 842 u64 fence_context; 843 unsigned num_rings; 844 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 845 bool ib_pool_ready; 846 struct amdgpu_sa_manager ring_tmp_bo; 847 848 /* interrupts */ 849 struct amdgpu_irq irq; 850 851 /* powerplay */ 852 struct amd_powerplay powerplay; 853 bool pp_force_state_enabled; 854 855 /* smu */ 856 struct smu_context smu; 857 858 /* dpm */ 859 struct amdgpu_pm pm; 860 u32 cg_flags; 861 u32 pg_flags; 862 863 /* nbio */ 864 struct amdgpu_nbio nbio; 865 866 /* mmhub */ 867 struct amdgpu_mmhub mmhub; 868 869 /* gfx */ 870 struct amdgpu_gfx gfx; 871 872 /* sdma */ 873 struct amdgpu_sdma sdma; 874 875 /* uvd */ 876 struct amdgpu_uvd uvd; 877 878 /* vce */ 879 struct amdgpu_vce vce; 880 881 /* vcn */ 882 struct amdgpu_vcn vcn; 883 884 /* jpeg */ 885 struct amdgpu_jpeg jpeg; 886 887 /* firmwares */ 888 struct amdgpu_firmware firmware; 889 890 /* PSP */ 891 struct psp_context psp; 892 893 /* GDS */ 894 struct amdgpu_gds gds; 895 896 /* KFD */ 897 struct amdgpu_kfd_dev kfd; 898 899 /* UMC */ 900 struct amdgpu_umc umc; 901 902 /* display related functionality */ 903 struct amdgpu_display_manager dm; 904 905 /* discovery */ 906 uint8_t *discovery; 907 908 /* mes */ 909 bool enable_mes; 910 struct amdgpu_mes mes; 911 912 /* df */ 913 struct amdgpu_df df; 914 915 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 916 int num_ip_blocks; 917 struct mutex mn_lock; 918 DECLARE_HASHTABLE(mn_hash, 7); 919 920 /* tracking pinned memory */ 921 atomic64_t vram_pin_size; 922 atomic64_t visible_pin_size; 923 atomic64_t gart_pin_size; 924 925 /* soc15 register offset based on ip, instance and segment */ 926 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 927 928 /* delayed work_func for deferring clockgating during resume */ 929 struct delayed_work delayed_init_work; 930 931 struct amdgpu_virt virt; 932 /* firmware VRAM reservation */ 933 struct amdgpu_fw_vram_usage fw_vram_usage; 934 935 /* link all shadow bo */ 936 struct list_head shadow_list; 937 struct mutex shadow_list_lock; 938 /* keep an lru list of rings by HW IP */ 939 struct list_head ring_lru_list; 940 spinlock_t ring_lru_list_lock; 941 942 /* record hw reset is performed */ 943 bool has_hw_reset; 944 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 945 946 /* s3/s4 mask */ 947 bool in_suspend; 948 949 /* record last mm index being written through WREG32*/ 950 unsigned long last_mm_index; 951 bool in_gpu_reset; 952 enum pp_mp1_state mp1_state; 953 struct mutex lock_reset; 954 struct amdgpu_doorbell_index doorbell_index; 955 956 struct mutex notifier_lock; 957 958 int asic_reset_res; 959 struct work_struct xgmi_reset_work; 960 961 long gfx_timeout; 962 long sdma_timeout; 963 long video_timeout; 964 long compute_timeout; 965 966 uint64_t unique_id; 967 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 968 969 /* device pstate */ 970 int pstate; 971 /* enable runtime pm on the device */ 972 bool runpm; 973 bool in_runpm; 974 975 bool pm_sysfs_en; 976 bool ucode_sysfs_en; 977 }; 978 979 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 980 { 981 return container_of(bdev, struct amdgpu_device, mman.bdev); 982 } 983 984 int amdgpu_device_init(struct amdgpu_device *adev, 985 struct drm_device *ddev, 986 struct pci_dev *pdev, 987 uint32_t flags); 988 void amdgpu_device_fini(struct amdgpu_device *adev); 989 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 990 991 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 992 uint32_t *buf, size_t size, bool write); 993 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 994 uint32_t acc_flags); 995 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 996 uint32_t acc_flags); 997 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 998 uint32_t acc_flags); 999 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1000 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1001 1002 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1003 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1004 1005 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1006 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1007 1008 int emu_soc_asic_init(struct amdgpu_device *adev); 1009 1010 /* 1011 * Registers read & write functions. 1012 */ 1013 1014 #define AMDGPU_REGS_IDX (1<<0) 1015 #define AMDGPU_REGS_NO_KIQ (1<<1) 1016 #define AMDGPU_REGS_KIQ (1<<2) 1017 1018 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1019 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1020 1021 #define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ) 1022 #define WREG32_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_KIQ) 1023 1024 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1025 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1026 1027 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1028 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1029 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1030 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1031 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1032 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1033 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1034 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1035 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1036 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1037 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1038 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1039 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1040 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1041 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1042 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1043 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1044 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1045 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1046 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1047 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1048 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1049 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1050 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1051 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1052 #define WREG32_P(reg, val, mask) \ 1053 do { \ 1054 uint32_t tmp_ = RREG32(reg); \ 1055 tmp_ &= (mask); \ 1056 tmp_ |= ((val) & ~(mask)); \ 1057 WREG32(reg, tmp_); \ 1058 } while (0) 1059 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1060 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1061 #define WREG32_PLL_P(reg, val, mask) \ 1062 do { \ 1063 uint32_t tmp_ = RREG32_PLL(reg); \ 1064 tmp_ &= (mask); \ 1065 tmp_ |= ((val) & ~(mask)); \ 1066 WREG32_PLL(reg, tmp_); \ 1067 } while (0) 1068 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1069 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1070 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1071 1072 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1073 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1074 1075 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1076 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1077 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1078 1079 #define REG_GET_FIELD(value, reg, field) \ 1080 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1081 1082 #define WREG32_FIELD(reg, field, val) \ 1083 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1084 1085 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1086 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1087 1088 /* 1089 * BIOS helpers. 1090 */ 1091 #define RBIOS8(i) (adev->bios[i]) 1092 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1093 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1094 1095 /* 1096 * ASICs macro. 1097 */ 1098 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1099 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1100 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1101 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1102 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1103 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1104 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1105 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1106 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1107 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1108 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1109 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1110 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1111 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1112 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1113 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1114 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1115 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1116 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1117 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1118 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1119 1120 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1121 1122 /* Common functions */ 1123 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1124 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1125 struct amdgpu_job* job); 1126 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1127 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1128 1129 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1130 u64 num_vis_bytes); 1131 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1132 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1133 const u32 *registers, 1134 const u32 array_size); 1135 1136 bool amdgpu_device_supports_boco(struct drm_device *dev); 1137 bool amdgpu_device_supports_baco(struct drm_device *dev); 1138 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1139 struct amdgpu_device *peer_adev); 1140 int amdgpu_device_baco_enter(struct drm_device *dev); 1141 int amdgpu_device_baco_exit(struct drm_device *dev); 1142 1143 /* atpx handler */ 1144 #if defined(CONFIG_VGA_SWITCHEROO) 1145 void amdgpu_register_atpx_handler(void); 1146 void amdgpu_unregister_atpx_handler(void); 1147 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1148 bool amdgpu_is_atpx_hybrid(void); 1149 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1150 bool amdgpu_has_atpx(void); 1151 #else 1152 static inline void amdgpu_register_atpx_handler(void) {} 1153 static inline void amdgpu_unregister_atpx_handler(void) {} 1154 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1155 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1156 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1157 static inline bool amdgpu_has_atpx(void) { return false; } 1158 #endif 1159 1160 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1161 void *amdgpu_atpx_get_dhandle(void); 1162 #else 1163 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1164 #endif 1165 1166 /* 1167 * KMS 1168 */ 1169 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1170 extern const int amdgpu_max_kms_ioctl; 1171 1172 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1173 void amdgpu_driver_unload_kms(struct drm_device *dev); 1174 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1175 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1176 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1177 struct drm_file *file_priv); 1178 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1179 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1180 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1181 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1182 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1183 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1184 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1185 unsigned long arg); 1186 1187 /* 1188 * functions used by amdgpu_encoder.c 1189 */ 1190 struct amdgpu_afmt_acr { 1191 u32 clock; 1192 1193 int n_32khz; 1194 int cts_32khz; 1195 1196 int n_44_1khz; 1197 int cts_44_1khz; 1198 1199 int n_48khz; 1200 int cts_48khz; 1201 1202 }; 1203 1204 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1205 1206 /* amdgpu_acpi.c */ 1207 #if defined(CONFIG_ACPI) 1208 int amdgpu_acpi_init(struct amdgpu_device *adev); 1209 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1210 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1211 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1212 u8 perf_req, bool advertise); 1213 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1214 1215 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1216 struct amdgpu_dm_backlight_caps *caps); 1217 #else 1218 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1219 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1220 #endif 1221 1222 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1223 uint64_t addr, struct amdgpu_bo **bo, 1224 struct amdgpu_bo_va_mapping **mapping); 1225 1226 #if defined(CONFIG_DRM_AMD_DC) 1227 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1228 #else 1229 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1230 #endif 1231 1232 1233 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1234 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1235 1236 #include "amdgpu_object.h" 1237 1238 /* used by df_v3_6.c and amdgpu_pmu.c */ 1239 #define AMDGPU_PMU_ATTR(_name, _object) \ 1240 static ssize_t \ 1241 _name##_show(struct device *dev, \ 1242 struct device_attribute *attr, \ 1243 char *page) \ 1244 { \ 1245 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1246 return sprintf(page, _object "\n"); \ 1247 } \ 1248 \ 1249 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1250 1251 #endif 1252 1253