1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include "amdgpu_ctx.h" 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/rbtree.h> 38 #include <linux/hashtable.h> 39 #include <linux/dma-fence.h> 40 41 #include <drm/ttm/ttm_bo_api.h> 42 #include <drm/ttm/ttm_bo_driver.h> 43 #include <drm/ttm/ttm_placement.h> 44 #include <drm/ttm/ttm_module.h> 45 #include <drm/ttm/ttm_execbuf_util.h> 46 47 #include <drm/drmP.h> 48 #include <drm/drm_gem.h> 49 #include <drm/amdgpu_drm.h> 50 #include <drm/gpu_scheduler.h> 51 52 #include <kgd_kfd_interface.h> 53 #include "dm_pp_interface.h" 54 #include "kgd_pp_interface.h" 55 56 #include "amd_shared.h" 57 #include "amdgpu_mode.h" 58 #include "amdgpu_ih.h" 59 #include "amdgpu_irq.h" 60 #include "amdgpu_ucode.h" 61 #include "amdgpu_ttm.h" 62 #include "amdgpu_psp.h" 63 #include "amdgpu_gds.h" 64 #include "amdgpu_sync.h" 65 #include "amdgpu_ring.h" 66 #include "amdgpu_vm.h" 67 #include "amdgpu_dpm.h" 68 #include "amdgpu_acp.h" 69 #include "amdgpu_uvd.h" 70 #include "amdgpu_vce.h" 71 #include "amdgpu_vcn.h" 72 #include "amdgpu_mn.h" 73 #include "amdgpu_gmc.h" 74 #include "amdgpu_gfx.h" 75 #include "amdgpu_sdma.h" 76 #include "amdgpu_dm.h" 77 #include "amdgpu_virt.h" 78 #include "amdgpu_csa.h" 79 #include "amdgpu_gart.h" 80 #include "amdgpu_debugfs.h" 81 #include "amdgpu_job.h" 82 #include "amdgpu_bo_list.h" 83 #include "amdgpu_gem.h" 84 #include "amdgpu_doorbell.h" 85 #include "amdgpu_amdkfd.h" 86 87 #define MAX_GPU_INSTANCE 16 88 89 struct amdgpu_gpu_instance 90 { 91 struct amdgpu_device *adev; 92 int mgpu_fan_enabled; 93 }; 94 95 struct amdgpu_mgpu_info 96 { 97 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 98 struct mutex mutex; 99 uint32_t num_gpu; 100 uint32_t num_dgpu; 101 uint32_t num_apu; 102 }; 103 104 /* 105 * Modules parameters. 106 */ 107 extern int amdgpu_modeset; 108 extern int amdgpu_vram_limit; 109 extern int amdgpu_vis_vram_limit; 110 extern int amdgpu_gart_size; 111 extern int amdgpu_gtt_size; 112 extern int amdgpu_moverate; 113 extern int amdgpu_benchmarking; 114 extern int amdgpu_testing; 115 extern int amdgpu_audio; 116 extern int amdgpu_disp_priority; 117 extern int amdgpu_hw_i2c; 118 extern int amdgpu_pcie_gen2; 119 extern int amdgpu_msi; 120 extern int amdgpu_lockup_timeout; 121 extern int amdgpu_dpm; 122 extern int amdgpu_fw_load_type; 123 extern int amdgpu_aspm; 124 extern int amdgpu_runtime_pm; 125 extern uint amdgpu_ip_block_mask; 126 extern int amdgpu_bapm; 127 extern int amdgpu_deep_color; 128 extern int amdgpu_vm_size; 129 extern int amdgpu_vm_block_size; 130 extern int amdgpu_vm_fragment_size; 131 extern int amdgpu_vm_fault_stop; 132 extern int amdgpu_vm_debug; 133 extern int amdgpu_vm_update_mode; 134 extern int amdgpu_dc; 135 extern int amdgpu_sched_jobs; 136 extern int amdgpu_sched_hw_submission; 137 extern uint amdgpu_pcie_gen_cap; 138 extern uint amdgpu_pcie_lane_cap; 139 extern uint amdgpu_cg_mask; 140 extern uint amdgpu_pg_mask; 141 extern uint amdgpu_sdma_phase_quantum; 142 extern char *amdgpu_disable_cu; 143 extern char *amdgpu_virtual_display; 144 extern uint amdgpu_pp_feature_mask; 145 extern int amdgpu_vram_page_split; 146 extern int amdgpu_ngg; 147 extern int amdgpu_prim_buf_per_se; 148 extern int amdgpu_pos_buf_per_se; 149 extern int amdgpu_cntl_sb_buf_per_se; 150 extern int amdgpu_param_buf_per_se; 151 extern int amdgpu_job_hang_limit; 152 extern int amdgpu_lbpw; 153 extern int amdgpu_compute_multipipe; 154 extern int amdgpu_gpu_recovery; 155 extern int amdgpu_emu_mode; 156 extern uint amdgpu_smu_memory_pool_size; 157 extern uint amdgpu_dc_feature_mask; 158 extern struct amdgpu_mgpu_info mgpu_info; 159 160 #ifdef CONFIG_DRM_AMDGPU_SI 161 extern int amdgpu_si_support; 162 #endif 163 #ifdef CONFIG_DRM_AMDGPU_CIK 164 extern int amdgpu_cik_support; 165 #endif 166 167 #define AMDGPU_VM_MAX_NUM_CTX 4096 168 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 169 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 170 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 171 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 172 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 173 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 174 #define AMDGPU_IB_POOL_SIZE 16 175 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 176 #define AMDGPUFB_CONN_LIMIT 4 177 #define AMDGPU_BIOS_NUM_SCRATCH 16 178 179 /* hard reset data */ 180 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 181 182 /* reset flags */ 183 #define AMDGPU_RESET_GFX (1 << 0) 184 #define AMDGPU_RESET_COMPUTE (1 << 1) 185 #define AMDGPU_RESET_DMA (1 << 2) 186 #define AMDGPU_RESET_CP (1 << 3) 187 #define AMDGPU_RESET_GRBM (1 << 4) 188 #define AMDGPU_RESET_DMA1 (1 << 5) 189 #define AMDGPU_RESET_RLC (1 << 6) 190 #define AMDGPU_RESET_SEM (1 << 7) 191 #define AMDGPU_RESET_IH (1 << 8) 192 #define AMDGPU_RESET_VMC (1 << 9) 193 #define AMDGPU_RESET_MC (1 << 10) 194 #define AMDGPU_RESET_DISPLAY (1 << 11) 195 #define AMDGPU_RESET_UVD (1 << 12) 196 #define AMDGPU_RESET_VCE (1 << 13) 197 #define AMDGPU_RESET_VCE1 (1 << 14) 198 199 /* max cursor sizes (in pixels) */ 200 #define CIK_CURSOR_WIDTH 128 201 #define CIK_CURSOR_HEIGHT 128 202 203 struct amdgpu_device; 204 struct amdgpu_ib; 205 struct amdgpu_cs_parser; 206 struct amdgpu_job; 207 struct amdgpu_irq_src; 208 struct amdgpu_fpriv; 209 struct amdgpu_bo_va_mapping; 210 struct amdgpu_atif; 211 212 enum amdgpu_cp_irq { 213 AMDGPU_CP_IRQ_GFX_EOP = 0, 214 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 215 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 216 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 217 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 218 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 219 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 220 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 221 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 222 223 AMDGPU_CP_IRQ_LAST 224 }; 225 226 enum amdgpu_thermal_irq { 227 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 228 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 229 230 AMDGPU_THERMAL_IRQ_LAST 231 }; 232 233 enum amdgpu_kiq_irq { 234 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 235 AMDGPU_CP_KIQ_IRQ_LAST 236 }; 237 238 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 239 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 240 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 241 242 int amdgpu_device_ip_set_clockgating_state(void *dev, 243 enum amd_ip_block_type block_type, 244 enum amd_clockgating_state state); 245 int amdgpu_device_ip_set_powergating_state(void *dev, 246 enum amd_ip_block_type block_type, 247 enum amd_powergating_state state); 248 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 249 u32 *flags); 250 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 251 enum amd_ip_block_type block_type); 252 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 253 enum amd_ip_block_type block_type); 254 255 #define AMDGPU_MAX_IP_NUM 16 256 257 struct amdgpu_ip_block_status { 258 bool valid; 259 bool sw; 260 bool hw; 261 bool late_initialized; 262 bool hang; 263 }; 264 265 struct amdgpu_ip_block_version { 266 const enum amd_ip_block_type type; 267 const u32 major; 268 const u32 minor; 269 const u32 rev; 270 const struct amd_ip_funcs *funcs; 271 }; 272 273 struct amdgpu_ip_block { 274 struct amdgpu_ip_block_status status; 275 const struct amdgpu_ip_block_version *version; 276 }; 277 278 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 279 enum amd_ip_block_type type, 280 u32 major, u32 minor); 281 282 struct amdgpu_ip_block * 283 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 284 enum amd_ip_block_type type); 285 286 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 287 const struct amdgpu_ip_block_version *ip_block_version); 288 289 /* 290 * BIOS. 291 */ 292 bool amdgpu_get_bios(struct amdgpu_device *adev); 293 bool amdgpu_read_bios(struct amdgpu_device *adev); 294 295 /* 296 * Clocks 297 */ 298 299 #define AMDGPU_MAX_PPLL 3 300 301 struct amdgpu_clock { 302 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 303 struct amdgpu_pll spll; 304 struct amdgpu_pll mpll; 305 /* 10 Khz units */ 306 uint32_t default_mclk; 307 uint32_t default_sclk; 308 uint32_t default_dispclk; 309 uint32_t current_dispclk; 310 uint32_t dp_extclk; 311 uint32_t max_pixel_clock; 312 }; 313 314 /* sub-allocation manager, it has to be protected by another lock. 315 * By conception this is an helper for other part of the driver 316 * like the indirect buffer or semaphore, which both have their 317 * locking. 318 * 319 * Principe is simple, we keep a list of sub allocation in offset 320 * order (first entry has offset == 0, last entry has the highest 321 * offset). 322 * 323 * When allocating new object we first check if there is room at 324 * the end total_size - (last_object_offset + last_object_size) >= 325 * alloc_size. If so we allocate new object there. 326 * 327 * When there is not enough room at the end, we start waiting for 328 * each sub object until we reach object_offset+object_size >= 329 * alloc_size, this object then become the sub object we return. 330 * 331 * Alignment can't be bigger than page size. 332 * 333 * Hole are not considered for allocation to keep things simple. 334 * Assumption is that there won't be hole (all object on same 335 * alignment). 336 */ 337 338 #define AMDGPU_SA_NUM_FENCE_LISTS 32 339 340 struct amdgpu_sa_manager { 341 wait_queue_head_t wq; 342 struct amdgpu_bo *bo; 343 struct list_head *hole; 344 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 345 struct list_head olist; 346 unsigned size; 347 uint64_t gpu_addr; 348 void *cpu_ptr; 349 uint32_t domain; 350 uint32_t align; 351 }; 352 353 /* sub-allocation buffer */ 354 struct amdgpu_sa_bo { 355 struct list_head olist; 356 struct list_head flist; 357 struct amdgpu_sa_manager *manager; 358 unsigned soffset; 359 unsigned eoffset; 360 struct dma_fence *fence; 361 }; 362 363 int amdgpu_fence_slab_init(void); 364 void amdgpu_fence_slab_fini(void); 365 366 /* 367 * IRQS. 368 */ 369 370 struct amdgpu_flip_work { 371 struct delayed_work flip_work; 372 struct work_struct unpin_work; 373 struct amdgpu_device *adev; 374 int crtc_id; 375 u32 target_vblank; 376 uint64_t base; 377 struct drm_pending_vblank_event *event; 378 struct amdgpu_bo *old_abo; 379 struct dma_fence *excl; 380 unsigned shared_count; 381 struct dma_fence **shared; 382 struct dma_fence_cb cb; 383 bool async; 384 }; 385 386 387 /* 388 * CP & rings. 389 */ 390 391 struct amdgpu_ib { 392 struct amdgpu_sa_bo *sa_bo; 393 uint32_t length_dw; 394 uint64_t gpu_addr; 395 uint32_t *ptr; 396 uint32_t flags; 397 }; 398 399 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 400 401 /* 402 * file private structure 403 */ 404 405 struct amdgpu_fpriv { 406 struct amdgpu_vm vm; 407 struct amdgpu_bo_va *prt_va; 408 struct amdgpu_bo_va *csa_va; 409 struct mutex bo_list_lock; 410 struct idr bo_list_handles; 411 struct amdgpu_ctx_mgr ctx_mgr; 412 }; 413 414 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 415 unsigned size, struct amdgpu_ib *ib); 416 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 417 struct dma_fence *f); 418 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 419 struct amdgpu_ib *ibs, struct amdgpu_job *job, 420 struct dma_fence **f); 421 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 422 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 423 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 424 425 /* 426 * CS. 427 */ 428 struct amdgpu_cs_chunk { 429 uint32_t chunk_id; 430 uint32_t length_dw; 431 void *kdata; 432 }; 433 434 struct amdgpu_cs_parser { 435 struct amdgpu_device *adev; 436 struct drm_file *filp; 437 struct amdgpu_ctx *ctx; 438 439 /* chunks */ 440 unsigned nchunks; 441 struct amdgpu_cs_chunk *chunks; 442 443 /* scheduler job object */ 444 struct amdgpu_job *job; 445 struct drm_sched_entity *entity; 446 447 /* buffer objects */ 448 struct ww_acquire_ctx ticket; 449 struct amdgpu_bo_list *bo_list; 450 struct amdgpu_mn *mn; 451 struct amdgpu_bo_list_entry vm_pd; 452 struct list_head validated; 453 struct dma_fence *fence; 454 uint64_t bytes_moved_threshold; 455 uint64_t bytes_moved_vis_threshold; 456 uint64_t bytes_moved; 457 uint64_t bytes_moved_vis; 458 struct amdgpu_bo_list_entry *evictable; 459 460 /* user fence */ 461 struct amdgpu_bo_list_entry uf_entry; 462 463 unsigned num_post_dep_syncobjs; 464 struct drm_syncobj **post_dep_syncobjs; 465 }; 466 467 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 468 uint32_t ib_idx, int idx) 469 { 470 return p->job->ibs[ib_idx].ptr[idx]; 471 } 472 473 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 474 uint32_t ib_idx, int idx, 475 uint32_t value) 476 { 477 p->job->ibs[ib_idx].ptr[idx] = value; 478 } 479 480 /* 481 * Writeback 482 */ 483 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 484 485 struct amdgpu_wb { 486 struct amdgpu_bo *wb_obj; 487 volatile uint32_t *wb; 488 uint64_t gpu_addr; 489 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 490 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 491 }; 492 493 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 494 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 495 496 /* 497 * Benchmarking 498 */ 499 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 500 501 502 /* 503 * Testing 504 */ 505 void amdgpu_test_moves(struct amdgpu_device *adev); 506 507 /* 508 * ASIC specific register table accessible by UMD 509 */ 510 struct amdgpu_allowed_register_entry { 511 uint32_t reg_offset; 512 bool grbm_indexed; 513 }; 514 515 /* 516 * ASIC specific functions. 517 */ 518 struct amdgpu_asic_funcs { 519 bool (*read_disabled_bios)(struct amdgpu_device *adev); 520 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 521 u8 *bios, u32 length_bytes); 522 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 523 u32 sh_num, u32 reg_offset, u32 *value); 524 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 525 int (*reset)(struct amdgpu_device *adev); 526 /* get the reference clock */ 527 u32 (*get_xclk)(struct amdgpu_device *adev); 528 /* MM block clocks */ 529 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 530 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 531 /* static power management */ 532 int (*get_pcie_lanes)(struct amdgpu_device *adev); 533 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 534 /* get config memsize register */ 535 u32 (*get_config_memsize)(struct amdgpu_device *adev); 536 /* flush hdp write queue */ 537 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 538 /* invalidate hdp read cache */ 539 void (*invalidate_hdp)(struct amdgpu_device *adev, 540 struct amdgpu_ring *ring); 541 /* check if the asic needs a full reset of if soft reset will work */ 542 bool (*need_full_reset)(struct amdgpu_device *adev); 543 /* initialize doorbell layout for specific asic*/ 544 void (*init_doorbell_index)(struct amdgpu_device *adev); 545 }; 546 547 /* 548 * IOCTL. 549 */ 550 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 551 struct drm_file *filp); 552 553 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 554 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 555 struct drm_file *filp); 556 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 557 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 558 struct drm_file *filp); 559 560 /* VRAM scratch page for HDP bug, default vram page */ 561 struct amdgpu_vram_scratch { 562 struct amdgpu_bo *robj; 563 volatile uint32_t *ptr; 564 u64 gpu_addr; 565 }; 566 567 /* 568 * ACPI 569 */ 570 struct amdgpu_atcs_functions { 571 bool get_ext_state; 572 bool pcie_perf_req; 573 bool pcie_dev_rdy; 574 bool pcie_bus_width; 575 }; 576 577 struct amdgpu_atcs { 578 struct amdgpu_atcs_functions functions; 579 }; 580 581 /* 582 * Firmware VRAM reservation 583 */ 584 struct amdgpu_fw_vram_usage { 585 u64 start_offset; 586 u64 size; 587 struct amdgpu_bo *reserved_bo; 588 void *va; 589 }; 590 591 /* 592 * CGS 593 */ 594 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 595 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 596 597 /* 598 * Core structure, functions and helpers. 599 */ 600 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 601 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 602 603 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 604 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 605 606 607 /* 608 * amdgpu nbio functions 609 * 610 */ 611 struct nbio_hdp_flush_reg { 612 u32 ref_and_mask_cp0; 613 u32 ref_and_mask_cp1; 614 u32 ref_and_mask_cp2; 615 u32 ref_and_mask_cp3; 616 u32 ref_and_mask_cp4; 617 u32 ref_and_mask_cp5; 618 u32 ref_and_mask_cp6; 619 u32 ref_and_mask_cp7; 620 u32 ref_and_mask_cp8; 621 u32 ref_and_mask_cp9; 622 u32 ref_and_mask_sdma0; 623 u32 ref_and_mask_sdma1; 624 }; 625 626 struct amdgpu_nbio_funcs { 627 const struct nbio_hdp_flush_reg *hdp_flush_reg; 628 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 629 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 630 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 631 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 632 u32 (*get_rev_id)(struct amdgpu_device *adev); 633 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 634 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 635 u32 (*get_memsize)(struct amdgpu_device *adev); 636 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 637 bool use_doorbell, int doorbell_index); 638 void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 639 bool enable); 640 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 641 bool enable); 642 void (*ih_doorbell_range)(struct amdgpu_device *adev, 643 bool use_doorbell, int doorbell_index); 644 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 645 bool enable); 646 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 647 bool enable); 648 void (*get_clockgating_state)(struct amdgpu_device *adev, 649 u32 *flags); 650 void (*ih_control)(struct amdgpu_device *adev); 651 void (*init_registers)(struct amdgpu_device *adev); 652 void (*detect_hw_virt)(struct amdgpu_device *adev); 653 }; 654 655 struct amdgpu_df_funcs { 656 void (*init)(struct amdgpu_device *adev); 657 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 658 bool enable); 659 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 660 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 661 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 662 bool enable); 663 void (*get_clockgating_state)(struct amdgpu_device *adev, 664 u32 *flags); 665 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 666 bool enable); 667 }; 668 /* Define the HW IP blocks will be used in driver , add more if necessary */ 669 enum amd_hw_ip_block_type { 670 GC_HWIP = 1, 671 HDP_HWIP, 672 SDMA0_HWIP, 673 SDMA1_HWIP, 674 MMHUB_HWIP, 675 ATHUB_HWIP, 676 NBIO_HWIP, 677 MP0_HWIP, 678 MP1_HWIP, 679 UVD_HWIP, 680 VCN_HWIP = UVD_HWIP, 681 VCE_HWIP, 682 DF_HWIP, 683 DCE_HWIP, 684 OSSSYS_HWIP, 685 SMUIO_HWIP, 686 PWR_HWIP, 687 NBIF_HWIP, 688 THM_HWIP, 689 CLK_HWIP, 690 MAX_HWIP 691 }; 692 693 #define HWIP_MAX_INSTANCE 6 694 695 struct amd_powerplay { 696 void *pp_handle; 697 const struct amd_pm_funcs *pp_funcs; 698 uint32_t pp_feature; 699 }; 700 701 #define AMDGPU_RESET_MAGIC_NUM 64 702 struct amdgpu_device { 703 struct device *dev; 704 struct drm_device *ddev; 705 struct pci_dev *pdev; 706 707 #ifdef CONFIG_DRM_AMD_ACP 708 struct amdgpu_acp acp; 709 #endif 710 711 /* ASIC */ 712 enum amd_asic_type asic_type; 713 uint32_t family; 714 uint32_t rev_id; 715 uint32_t external_rev_id; 716 unsigned long flags; 717 int usec_timeout; 718 const struct amdgpu_asic_funcs *asic_funcs; 719 bool shutdown; 720 bool need_dma32; 721 bool need_swiotlb; 722 bool accel_working; 723 struct notifier_block acpi_nb; 724 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 725 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 726 unsigned debugfs_count; 727 #if defined(CONFIG_DEBUG_FS) 728 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 729 #endif 730 struct amdgpu_atif *atif; 731 struct amdgpu_atcs atcs; 732 struct mutex srbm_mutex; 733 /* GRBM index mutex. Protects concurrent access to GRBM index */ 734 struct mutex grbm_idx_mutex; 735 struct dev_pm_domain vga_pm_domain; 736 bool have_disp_power_ref; 737 738 /* BIOS */ 739 bool is_atom_fw; 740 uint8_t *bios; 741 uint32_t bios_size; 742 struct amdgpu_bo *stolen_vga_memory; 743 uint32_t bios_scratch_reg_offset; 744 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 745 746 /* Register/doorbell mmio */ 747 resource_size_t rmmio_base; 748 resource_size_t rmmio_size; 749 void __iomem *rmmio; 750 /* protects concurrent MM_INDEX/DATA based register access */ 751 spinlock_t mmio_idx_lock; 752 /* protects concurrent SMC based register access */ 753 spinlock_t smc_idx_lock; 754 amdgpu_rreg_t smc_rreg; 755 amdgpu_wreg_t smc_wreg; 756 /* protects concurrent PCIE register access */ 757 spinlock_t pcie_idx_lock; 758 amdgpu_rreg_t pcie_rreg; 759 amdgpu_wreg_t pcie_wreg; 760 amdgpu_rreg_t pciep_rreg; 761 amdgpu_wreg_t pciep_wreg; 762 /* protects concurrent UVD register access */ 763 spinlock_t uvd_ctx_idx_lock; 764 amdgpu_rreg_t uvd_ctx_rreg; 765 amdgpu_wreg_t uvd_ctx_wreg; 766 /* protects concurrent DIDT register access */ 767 spinlock_t didt_idx_lock; 768 amdgpu_rreg_t didt_rreg; 769 amdgpu_wreg_t didt_wreg; 770 /* protects concurrent gc_cac register access */ 771 spinlock_t gc_cac_idx_lock; 772 amdgpu_rreg_t gc_cac_rreg; 773 amdgpu_wreg_t gc_cac_wreg; 774 /* protects concurrent se_cac register access */ 775 spinlock_t se_cac_idx_lock; 776 amdgpu_rreg_t se_cac_rreg; 777 amdgpu_wreg_t se_cac_wreg; 778 /* protects concurrent ENDPOINT (audio) register access */ 779 spinlock_t audio_endpt_idx_lock; 780 amdgpu_block_rreg_t audio_endpt_rreg; 781 amdgpu_block_wreg_t audio_endpt_wreg; 782 void __iomem *rio_mem; 783 resource_size_t rio_mem_size; 784 struct amdgpu_doorbell doorbell; 785 786 /* clock/pll info */ 787 struct amdgpu_clock clock; 788 789 /* MC */ 790 struct amdgpu_gmc gmc; 791 struct amdgpu_gart gart; 792 dma_addr_t dummy_page_addr; 793 struct amdgpu_vm_manager vm_manager; 794 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 795 796 /* memory management */ 797 struct amdgpu_mman mman; 798 struct amdgpu_vram_scratch vram_scratch; 799 struct amdgpu_wb wb; 800 atomic64_t num_bytes_moved; 801 atomic64_t num_evictions; 802 atomic64_t num_vram_cpu_page_faults; 803 atomic_t gpu_reset_counter; 804 atomic_t vram_lost_counter; 805 806 /* data for buffer migration throttling */ 807 struct { 808 spinlock_t lock; 809 s64 last_update_us; 810 s64 accum_us; /* accumulated microseconds */ 811 s64 accum_us_vis; /* for visible VRAM */ 812 u32 log2_max_MBps; 813 } mm_stats; 814 815 /* display */ 816 bool enable_virtual_display; 817 struct amdgpu_mode_info mode_info; 818 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 819 struct work_struct hotplug_work; 820 struct amdgpu_irq_src crtc_irq; 821 struct amdgpu_irq_src pageflip_irq; 822 struct amdgpu_irq_src hpd_irq; 823 824 /* rings */ 825 u64 fence_context; 826 unsigned num_rings; 827 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 828 bool ib_pool_ready; 829 struct amdgpu_sa_manager ring_tmp_bo; 830 831 /* interrupts */ 832 struct amdgpu_irq irq; 833 834 /* powerplay */ 835 struct amd_powerplay powerplay; 836 bool pp_force_state_enabled; 837 838 /* dpm */ 839 struct amdgpu_pm pm; 840 u32 cg_flags; 841 u32 pg_flags; 842 843 /* gfx */ 844 struct amdgpu_gfx gfx; 845 846 /* sdma */ 847 struct amdgpu_sdma sdma; 848 849 /* uvd */ 850 struct amdgpu_uvd uvd; 851 852 /* vce */ 853 struct amdgpu_vce vce; 854 855 /* vcn */ 856 struct amdgpu_vcn vcn; 857 858 /* firmwares */ 859 struct amdgpu_firmware firmware; 860 861 /* PSP */ 862 struct psp_context psp; 863 864 /* GDS */ 865 struct amdgpu_gds gds; 866 867 /* KFD */ 868 struct amdgpu_kfd_dev kfd; 869 870 /* display related functionality */ 871 struct amdgpu_display_manager dm; 872 873 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 874 int num_ip_blocks; 875 struct mutex mn_lock; 876 DECLARE_HASHTABLE(mn_hash, 7); 877 878 /* tracking pinned memory */ 879 atomic64_t vram_pin_size; 880 atomic64_t visible_pin_size; 881 atomic64_t gart_pin_size; 882 883 /* soc15 register offset based on ip, instance and segment */ 884 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 885 886 const struct amdgpu_nbio_funcs *nbio_funcs; 887 const struct amdgpu_df_funcs *df_funcs; 888 889 /* delayed work_func for deferring clockgating during resume */ 890 struct delayed_work late_init_work; 891 892 struct amdgpu_virt virt; 893 /* firmware VRAM reservation */ 894 struct amdgpu_fw_vram_usage fw_vram_usage; 895 896 /* link all shadow bo */ 897 struct list_head shadow_list; 898 struct mutex shadow_list_lock; 899 /* keep an lru list of rings by HW IP */ 900 struct list_head ring_lru_list; 901 spinlock_t ring_lru_list_lock; 902 903 /* record hw reset is performed */ 904 bool has_hw_reset; 905 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 906 907 /* s3/s4 mask */ 908 bool in_suspend; 909 910 /* record last mm index being written through WREG32*/ 911 unsigned long last_mm_index; 912 bool in_gpu_reset; 913 struct mutex lock_reset; 914 struct amdgpu_doorbell_index doorbell_index; 915 916 int asic_reset_res; 917 struct work_struct xgmi_reset_work; 918 }; 919 920 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 921 { 922 return container_of(bdev, struct amdgpu_device, mman.bdev); 923 } 924 925 int amdgpu_device_init(struct amdgpu_device *adev, 926 struct drm_device *ddev, 927 struct pci_dev *pdev, 928 uint32_t flags); 929 void amdgpu_device_fini(struct amdgpu_device *adev); 930 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 931 932 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 933 uint32_t acc_flags); 934 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 935 uint32_t acc_flags); 936 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 937 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 938 939 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 940 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 941 942 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 943 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 944 945 int emu_soc_asic_init(struct amdgpu_device *adev); 946 947 /* 948 * Registers read & write functions. 949 */ 950 951 #define AMDGPU_REGS_IDX (1<<0) 952 #define AMDGPU_REGS_NO_KIQ (1<<1) 953 954 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 955 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 956 957 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 958 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 959 960 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 961 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 962 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 963 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 964 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 965 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 966 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 967 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 968 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 969 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 970 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 971 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 972 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 973 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 974 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 975 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 976 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 977 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 978 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 979 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 980 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 981 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 982 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 983 #define WREG32_P(reg, val, mask) \ 984 do { \ 985 uint32_t tmp_ = RREG32(reg); \ 986 tmp_ &= (mask); \ 987 tmp_ |= ((val) & ~(mask)); \ 988 WREG32(reg, tmp_); \ 989 } while (0) 990 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 991 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 992 #define WREG32_PLL_P(reg, val, mask) \ 993 do { \ 994 uint32_t tmp_ = RREG32_PLL(reg); \ 995 tmp_ &= (mask); \ 996 tmp_ |= ((val) & ~(mask)); \ 997 WREG32_PLL(reg, tmp_); \ 998 } while (0) 999 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1000 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1001 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1002 1003 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1004 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1005 1006 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1007 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1008 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1009 1010 #define REG_GET_FIELD(value, reg, field) \ 1011 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1012 1013 #define WREG32_FIELD(reg, field, val) \ 1014 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1015 1016 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1017 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1018 1019 /* 1020 * BIOS helpers. 1021 */ 1022 #define RBIOS8(i) (adev->bios[i]) 1023 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1024 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1025 1026 /* 1027 * ASICs macro. 1028 */ 1029 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1030 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1031 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1032 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1033 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1034 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1035 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1036 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1037 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1038 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1039 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1040 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1041 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1042 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1043 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1044 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1045 1046 /* Common functions */ 1047 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1048 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1049 struct amdgpu_job* job); 1050 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1051 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1052 1053 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1054 u64 num_vis_bytes); 1055 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1056 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1057 const u32 *registers, 1058 const u32 array_size); 1059 1060 bool amdgpu_device_is_px(struct drm_device *dev); 1061 /* atpx handler */ 1062 #if defined(CONFIG_VGA_SWITCHEROO) 1063 void amdgpu_register_atpx_handler(void); 1064 void amdgpu_unregister_atpx_handler(void); 1065 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1066 bool amdgpu_is_atpx_hybrid(void); 1067 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1068 bool amdgpu_has_atpx(void); 1069 #else 1070 static inline void amdgpu_register_atpx_handler(void) {} 1071 static inline void amdgpu_unregister_atpx_handler(void) {} 1072 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1073 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1074 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1075 static inline bool amdgpu_has_atpx(void) { return false; } 1076 #endif 1077 1078 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1079 void *amdgpu_atpx_get_dhandle(void); 1080 #else 1081 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1082 #endif 1083 1084 /* 1085 * KMS 1086 */ 1087 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1088 extern const int amdgpu_max_kms_ioctl; 1089 1090 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1091 void amdgpu_driver_unload_kms(struct drm_device *dev); 1092 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1093 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1094 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1095 struct drm_file *file_priv); 1096 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1097 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1098 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1099 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1100 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1101 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1102 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1103 unsigned long arg); 1104 1105 /* 1106 * functions used by amdgpu_encoder.c 1107 */ 1108 struct amdgpu_afmt_acr { 1109 u32 clock; 1110 1111 int n_32khz; 1112 int cts_32khz; 1113 1114 int n_44_1khz; 1115 int cts_44_1khz; 1116 1117 int n_48khz; 1118 int cts_48khz; 1119 1120 }; 1121 1122 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1123 1124 /* amdgpu_acpi.c */ 1125 #if defined(CONFIG_ACPI) 1126 int amdgpu_acpi_init(struct amdgpu_device *adev); 1127 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1128 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1129 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1130 u8 perf_req, bool advertise); 1131 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1132 1133 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1134 struct amdgpu_dm_backlight_caps *caps); 1135 #else 1136 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1137 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1138 #endif 1139 1140 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1141 uint64_t addr, struct amdgpu_bo **bo, 1142 struct amdgpu_bo_va_mapping **mapping); 1143 1144 #if defined(CONFIG_DRM_AMD_DC) 1145 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1146 #else 1147 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1148 #endif 1149 1150 #include "amdgpu_object.h" 1151 #endif 1152