xref: /openbmc/linux/drivers/gpu/drm/amd/amdgpu/amdgpu.h (revision 0f4b20ef)
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30 
31 #ifdef pr_fmt
32 #undef pr_fmt
33 #endif
34 
35 #define pr_fmt(fmt) "amdgpu: " fmt
36 
37 #ifdef dev_fmt
38 #undef dev_fmt
39 #endif
40 
41 #define dev_fmt(fmt) "amdgpu: " fmt
42 
43 #include "amdgpu_ctx.h"
44 
45 #include <linux/atomic.h>
46 #include <linux/wait.h>
47 #include <linux/list.h>
48 #include <linux/kref.h>
49 #include <linux/rbtree.h>
50 #include <linux/hashtable.h>
51 #include <linux/dma-fence.h>
52 #include <linux/pci.h>
53 #include <linux/aer.h>
54 
55 #include <drm/ttm/ttm_bo_api.h>
56 #include <drm/ttm/ttm_bo_driver.h>
57 #include <drm/ttm/ttm_placement.h>
58 #include <drm/ttm/ttm_execbuf_util.h>
59 
60 #include <drm/amdgpu_drm.h>
61 #include <drm/drm_gem.h>
62 #include <drm/drm_ioctl.h>
63 
64 #include <kgd_kfd_interface.h>
65 #include "dm_pp_interface.h"
66 #include "kgd_pp_interface.h"
67 
68 #include "amd_shared.h"
69 #include "amdgpu_mode.h"
70 #include "amdgpu_ih.h"
71 #include "amdgpu_irq.h"
72 #include "amdgpu_ucode.h"
73 #include "amdgpu_ttm.h"
74 #include "amdgpu_psp.h"
75 #include "amdgpu_gds.h"
76 #include "amdgpu_sync.h"
77 #include "amdgpu_ring.h"
78 #include "amdgpu_vm.h"
79 #include "amdgpu_dpm.h"
80 #include "amdgpu_acp.h"
81 #include "amdgpu_uvd.h"
82 #include "amdgpu_vce.h"
83 #include "amdgpu_vcn.h"
84 #include "amdgpu_jpeg.h"
85 #include "amdgpu_mn.h"
86 #include "amdgpu_gmc.h"
87 #include "amdgpu_gfx.h"
88 #include "amdgpu_sdma.h"
89 #include "amdgpu_nbio.h"
90 #include "amdgpu_hdp.h"
91 #include "amdgpu_dm.h"
92 #include "amdgpu_virt.h"
93 #include "amdgpu_csa.h"
94 #include "amdgpu_gart.h"
95 #include "amdgpu_debugfs.h"
96 #include "amdgpu_job.h"
97 #include "amdgpu_bo_list.h"
98 #include "amdgpu_gem.h"
99 #include "amdgpu_doorbell.h"
100 #include "amdgpu_amdkfd.h"
101 #include "amdgpu_discovery.h"
102 #include "amdgpu_mes.h"
103 #include "amdgpu_umc.h"
104 #include "amdgpu_mmhub.h"
105 #include "amdgpu_gfxhub.h"
106 #include "amdgpu_df.h"
107 #include "amdgpu_smuio.h"
108 #include "amdgpu_fdinfo.h"
109 #include "amdgpu_mca.h"
110 #include "amdgpu_ras.h"
111 
112 #define MAX_GPU_INSTANCE		16
113 
114 struct amdgpu_gpu_instance
115 {
116 	struct amdgpu_device		*adev;
117 	int				mgpu_fan_enabled;
118 };
119 
120 struct amdgpu_mgpu_info
121 {
122 	struct amdgpu_gpu_instance	gpu_ins[MAX_GPU_INSTANCE];
123 	struct mutex			mutex;
124 	uint32_t			num_gpu;
125 	uint32_t			num_dgpu;
126 	uint32_t			num_apu;
127 
128 	/* delayed reset_func for XGMI configuration if necessary */
129 	struct delayed_work		delayed_reset_work;
130 	bool				pending_reset;
131 };
132 
133 enum amdgpu_ss {
134 	AMDGPU_SS_DRV_LOAD,
135 	AMDGPU_SS_DEV_D0,
136 	AMDGPU_SS_DEV_D3,
137 	AMDGPU_SS_DRV_UNLOAD
138 };
139 
140 struct amdgpu_watchdog_timer
141 {
142 	bool timeout_fatal_disable;
143 	uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
144 };
145 
146 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH	256
147 
148 /*
149  * Modules parameters.
150  */
151 extern int amdgpu_modeset;
152 extern int amdgpu_vram_limit;
153 extern int amdgpu_vis_vram_limit;
154 extern int amdgpu_gart_size;
155 extern int amdgpu_gtt_size;
156 extern int amdgpu_moverate;
157 extern int amdgpu_audio;
158 extern int amdgpu_disp_priority;
159 extern int amdgpu_hw_i2c;
160 extern int amdgpu_pcie_gen2;
161 extern int amdgpu_msi;
162 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
163 extern int amdgpu_dpm;
164 extern int amdgpu_fw_load_type;
165 extern int amdgpu_aspm;
166 extern int amdgpu_runtime_pm;
167 extern uint amdgpu_ip_block_mask;
168 extern int amdgpu_bapm;
169 extern int amdgpu_deep_color;
170 extern int amdgpu_vm_size;
171 extern int amdgpu_vm_block_size;
172 extern int amdgpu_vm_fragment_size;
173 extern int amdgpu_vm_fault_stop;
174 extern int amdgpu_vm_debug;
175 extern int amdgpu_vm_update_mode;
176 extern int amdgpu_exp_hw_support;
177 extern int amdgpu_dc;
178 extern int amdgpu_sched_jobs;
179 extern int amdgpu_sched_hw_submission;
180 extern uint amdgpu_pcie_gen_cap;
181 extern uint amdgpu_pcie_lane_cap;
182 extern uint amdgpu_cg_mask;
183 extern uint amdgpu_pg_mask;
184 extern uint amdgpu_sdma_phase_quantum;
185 extern char *amdgpu_disable_cu;
186 extern char *amdgpu_virtual_display;
187 extern uint amdgpu_pp_feature_mask;
188 extern uint amdgpu_force_long_training;
189 extern int amdgpu_job_hang_limit;
190 extern int amdgpu_lbpw;
191 extern int amdgpu_compute_multipipe;
192 extern int amdgpu_gpu_recovery;
193 extern int amdgpu_emu_mode;
194 extern uint amdgpu_smu_memory_pool_size;
195 extern int amdgpu_smu_pptable_id;
196 extern uint amdgpu_dc_feature_mask;
197 extern uint amdgpu_dc_debug_mask;
198 extern uint amdgpu_dm_abm_level;
199 extern int amdgpu_backlight;
200 extern struct amdgpu_mgpu_info mgpu_info;
201 extern int amdgpu_ras_enable;
202 extern uint amdgpu_ras_mask;
203 extern int amdgpu_bad_page_threshold;
204 extern bool amdgpu_ignore_bad_page_threshold;
205 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
206 extern int amdgpu_async_gfx_ring;
207 extern int amdgpu_mcbp;
208 extern int amdgpu_discovery;
209 extern int amdgpu_mes;
210 extern int amdgpu_noretry;
211 extern int amdgpu_force_asic_type;
212 extern int amdgpu_smartshift_bias;
213 extern int amdgpu_use_xgmi_p2p;
214 #ifdef CONFIG_HSA_AMD
215 extern int sched_policy;
216 extern bool debug_evictions;
217 extern bool no_system_mem_limit;
218 #else
219 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
220 static const bool __maybe_unused debug_evictions; /* = false */
221 static const bool __maybe_unused no_system_mem_limit;
222 #endif
223 
224 extern int amdgpu_tmz;
225 extern int amdgpu_reset_method;
226 
227 #ifdef CONFIG_DRM_AMDGPU_SI
228 extern int amdgpu_si_support;
229 #endif
230 #ifdef CONFIG_DRM_AMDGPU_CIK
231 extern int amdgpu_cik_support;
232 #endif
233 extern int amdgpu_num_kcq;
234 
235 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
236 extern int amdgpu_vcnfw_log;
237 
238 #define AMDGPU_VM_MAX_NUM_CTX			4096
239 #define AMDGPU_SG_THRESHOLD			(256*1024*1024)
240 #define AMDGPU_DEFAULT_GTT_SIZE_MB		3072ULL /* 3GB by default */
241 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000
242 #define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */
243 #define AMDGPU_FENCE_JIFFIES_TIMEOUT		(HZ / 2)
244 #define AMDGPU_DEBUGFS_MAX_COMPONENTS		32
245 #define AMDGPUFB_CONN_LIMIT			4
246 #define AMDGPU_BIOS_NUM_SCRATCH			16
247 
248 #define AMDGPU_VBIOS_VGA_ALLOCATION		(9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
249 
250 /* hard reset data */
251 #define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b
252 
253 /* reset flags */
254 #define AMDGPU_RESET_GFX			(1 << 0)
255 #define AMDGPU_RESET_COMPUTE			(1 << 1)
256 #define AMDGPU_RESET_DMA			(1 << 2)
257 #define AMDGPU_RESET_CP				(1 << 3)
258 #define AMDGPU_RESET_GRBM			(1 << 4)
259 #define AMDGPU_RESET_DMA1			(1 << 5)
260 #define AMDGPU_RESET_RLC			(1 << 6)
261 #define AMDGPU_RESET_SEM			(1 << 7)
262 #define AMDGPU_RESET_IH				(1 << 8)
263 #define AMDGPU_RESET_VMC			(1 << 9)
264 #define AMDGPU_RESET_MC				(1 << 10)
265 #define AMDGPU_RESET_DISPLAY			(1 << 11)
266 #define AMDGPU_RESET_UVD			(1 << 12)
267 #define AMDGPU_RESET_VCE			(1 << 13)
268 #define AMDGPU_RESET_VCE1			(1 << 14)
269 
270 /* max cursor sizes (in pixels) */
271 #define CIK_CURSOR_WIDTH 128
272 #define CIK_CURSOR_HEIGHT 128
273 
274 /* smasrt shift bias level limits */
275 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
276 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
277 
278 struct amdgpu_device;
279 struct amdgpu_irq_src;
280 struct amdgpu_fpriv;
281 struct amdgpu_bo_va_mapping;
282 struct kfd_vm_fault_info;
283 struct amdgpu_hive_info;
284 struct amdgpu_reset_context;
285 struct amdgpu_reset_control;
286 
287 enum amdgpu_cp_irq {
288 	AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
289 	AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
290 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
291 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
292 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
293 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
294 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
295 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
296 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
297 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
298 
299 	AMDGPU_CP_IRQ_LAST
300 };
301 
302 enum amdgpu_thermal_irq {
303 	AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
304 	AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
305 
306 	AMDGPU_THERMAL_IRQ_LAST
307 };
308 
309 enum amdgpu_kiq_irq {
310 	AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
311 	AMDGPU_CP_KIQ_IRQ_LAST
312 };
313 
314 #define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */
315 #define MAX_KIQ_REG_BAILOUT_INTERVAL   5 /* in msecs, 5ms */
316 #define MAX_KIQ_REG_TRY 1000
317 
318 int amdgpu_device_ip_set_clockgating_state(void *dev,
319 					   enum amd_ip_block_type block_type,
320 					   enum amd_clockgating_state state);
321 int amdgpu_device_ip_set_powergating_state(void *dev,
322 					   enum amd_ip_block_type block_type,
323 					   enum amd_powergating_state state);
324 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
325 					    u32 *flags);
326 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
327 				   enum amd_ip_block_type block_type);
328 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
329 			      enum amd_ip_block_type block_type);
330 
331 #define AMDGPU_MAX_IP_NUM 16
332 
333 struct amdgpu_ip_block_status {
334 	bool valid;
335 	bool sw;
336 	bool hw;
337 	bool late_initialized;
338 	bool hang;
339 };
340 
341 struct amdgpu_ip_block_version {
342 	const enum amd_ip_block_type type;
343 	const u32 major;
344 	const u32 minor;
345 	const u32 rev;
346 	const struct amd_ip_funcs *funcs;
347 };
348 
349 #define HW_REV(_Major, _Minor, _Rev) \
350 	((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
351 
352 struct amdgpu_ip_block {
353 	struct amdgpu_ip_block_status status;
354 	const struct amdgpu_ip_block_version *version;
355 };
356 
357 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
358 				       enum amd_ip_block_type type,
359 				       u32 major, u32 minor);
360 
361 struct amdgpu_ip_block *
362 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
363 			      enum amd_ip_block_type type);
364 
365 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
366 			       const struct amdgpu_ip_block_version *ip_block_version);
367 
368 /*
369  * BIOS.
370  */
371 bool amdgpu_get_bios(struct amdgpu_device *adev);
372 bool amdgpu_read_bios(struct amdgpu_device *adev);
373 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
374 				     u8 *bios, u32 length_bytes);
375 /*
376  * Clocks
377  */
378 
379 #define AMDGPU_MAX_PPLL 3
380 
381 struct amdgpu_clock {
382 	struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
383 	struct amdgpu_pll spll;
384 	struct amdgpu_pll mpll;
385 	/* 10 Khz units */
386 	uint32_t default_mclk;
387 	uint32_t default_sclk;
388 	uint32_t default_dispclk;
389 	uint32_t current_dispclk;
390 	uint32_t dp_extclk;
391 	uint32_t max_pixel_clock;
392 };
393 
394 /* sub-allocation manager, it has to be protected by another lock.
395  * By conception this is an helper for other part of the driver
396  * like the indirect buffer or semaphore, which both have their
397  * locking.
398  *
399  * Principe is simple, we keep a list of sub allocation in offset
400  * order (first entry has offset == 0, last entry has the highest
401  * offset).
402  *
403  * When allocating new object we first check if there is room at
404  * the end total_size - (last_object_offset + last_object_size) >=
405  * alloc_size. If so we allocate new object there.
406  *
407  * When there is not enough room at the end, we start waiting for
408  * each sub object until we reach object_offset+object_size >=
409  * alloc_size, this object then become the sub object we return.
410  *
411  * Alignment can't be bigger than page size.
412  *
413  * Hole are not considered for allocation to keep things simple.
414  * Assumption is that there won't be hole (all object on same
415  * alignment).
416  */
417 
418 #define AMDGPU_SA_NUM_FENCE_LISTS	32
419 
420 struct amdgpu_sa_manager {
421 	wait_queue_head_t	wq;
422 	struct amdgpu_bo	*bo;
423 	struct list_head	*hole;
424 	struct list_head	flist[AMDGPU_SA_NUM_FENCE_LISTS];
425 	struct list_head	olist;
426 	unsigned		size;
427 	uint64_t		gpu_addr;
428 	void			*cpu_ptr;
429 	uint32_t		domain;
430 	uint32_t		align;
431 };
432 
433 /* sub-allocation buffer */
434 struct amdgpu_sa_bo {
435 	struct list_head		olist;
436 	struct list_head		flist;
437 	struct amdgpu_sa_manager	*manager;
438 	unsigned			soffset;
439 	unsigned			eoffset;
440 	struct dma_fence	        *fence;
441 };
442 
443 int amdgpu_fence_slab_init(void);
444 void amdgpu_fence_slab_fini(void);
445 
446 /*
447  * IRQS.
448  */
449 
450 struct amdgpu_flip_work {
451 	struct delayed_work		flip_work;
452 	struct work_struct		unpin_work;
453 	struct amdgpu_device		*adev;
454 	int				crtc_id;
455 	u32				target_vblank;
456 	uint64_t			base;
457 	struct drm_pending_vblank_event *event;
458 	struct amdgpu_bo		*old_abo;
459 	unsigned			shared_count;
460 	struct dma_fence		**shared;
461 	struct dma_fence_cb		cb;
462 	bool				async;
463 };
464 
465 
466 /*
467  * file private structure
468  */
469 
470 struct amdgpu_fpriv {
471 	struct amdgpu_vm	vm;
472 	struct amdgpu_bo_va	*prt_va;
473 	struct amdgpu_bo_va	*csa_va;
474 	struct mutex		bo_list_lock;
475 	struct idr		bo_list_handles;
476 	struct amdgpu_ctx_mgr	ctx_mgr;
477 };
478 
479 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
480 
481 /*
482  * Writeback
483  */
484 #define AMDGPU_MAX_WB 256	/* Reserve at most 256 WB slots for amdgpu-owned rings. */
485 
486 struct amdgpu_wb {
487 	struct amdgpu_bo	*wb_obj;
488 	volatile uint32_t	*wb;
489 	uint64_t		gpu_addr;
490 	u32			num_wb;	/* Number of wb slots actually reserved for amdgpu. */
491 	unsigned long		used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
492 };
493 
494 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
495 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
496 
497 /*
498  * Benchmarking
499  */
500 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
501 
502 /*
503  * ASIC specific register table accessible by UMD
504  */
505 struct amdgpu_allowed_register_entry {
506 	uint32_t reg_offset;
507 	bool grbm_indexed;
508 };
509 
510 enum amd_reset_method {
511 	AMD_RESET_METHOD_NONE = -1,
512 	AMD_RESET_METHOD_LEGACY = 0,
513 	AMD_RESET_METHOD_MODE0,
514 	AMD_RESET_METHOD_MODE1,
515 	AMD_RESET_METHOD_MODE2,
516 	AMD_RESET_METHOD_BACO,
517 	AMD_RESET_METHOD_PCI,
518 };
519 
520 struct amdgpu_video_codec_info {
521 	u32 codec_type;
522 	u32 max_width;
523 	u32 max_height;
524 	u32 max_pixels_per_frame;
525 	u32 max_level;
526 };
527 
528 #define codec_info_build(type, width, height, level) \
529 			 .codec_type = type,\
530 			 .max_width = width,\
531 			 .max_height = height,\
532 			 .max_pixels_per_frame = height * width,\
533 			 .max_level = level,
534 
535 struct amdgpu_video_codecs {
536 	const u32 codec_count;
537 	const struct amdgpu_video_codec_info *codec_array;
538 };
539 
540 /*
541  * ASIC specific functions.
542  */
543 struct amdgpu_asic_funcs {
544 	bool (*read_disabled_bios)(struct amdgpu_device *adev);
545 	bool (*read_bios_from_rom)(struct amdgpu_device *adev,
546 				   u8 *bios, u32 length_bytes);
547 	int (*read_register)(struct amdgpu_device *adev, u32 se_num,
548 			     u32 sh_num, u32 reg_offset, u32 *value);
549 	void (*set_vga_state)(struct amdgpu_device *adev, bool state);
550 	int (*reset)(struct amdgpu_device *adev);
551 	enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
552 	/* get the reference clock */
553 	u32 (*get_xclk)(struct amdgpu_device *adev);
554 	/* MM block clocks */
555 	int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
556 	int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
557 	/* static power management */
558 	int (*get_pcie_lanes)(struct amdgpu_device *adev);
559 	void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
560 	/* get config memsize register */
561 	u32 (*get_config_memsize)(struct amdgpu_device *adev);
562 	/* flush hdp write queue */
563 	void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
564 	/* invalidate hdp read cache */
565 	void (*invalidate_hdp)(struct amdgpu_device *adev,
566 			       struct amdgpu_ring *ring);
567 	/* check if the asic needs a full reset of if soft reset will work */
568 	bool (*need_full_reset)(struct amdgpu_device *adev);
569 	/* initialize doorbell layout for specific asic*/
570 	void (*init_doorbell_index)(struct amdgpu_device *adev);
571 	/* PCIe bandwidth usage */
572 	void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
573 			       uint64_t *count1);
574 	/* do we need to reset the asic at init time (e.g., kexec) */
575 	bool (*need_reset_on_init)(struct amdgpu_device *adev);
576 	/* PCIe replay counter */
577 	uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
578 	/* device supports BACO */
579 	bool (*supports_baco)(struct amdgpu_device *adev);
580 	/* pre asic_init quirks */
581 	void (*pre_asic_init)(struct amdgpu_device *adev);
582 	/* enter/exit umd stable pstate */
583 	int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
584 	/* query video codecs */
585 	int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
586 				  const struct amdgpu_video_codecs **codecs);
587 };
588 
589 /*
590  * IOCTL.
591  */
592 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
593 				struct drm_file *filp);
594 
595 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
596 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
597 				    struct drm_file *filp);
598 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
599 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
600 				struct drm_file *filp);
601 
602 /* VRAM scratch page for HDP bug, default vram page */
603 struct amdgpu_vram_scratch {
604 	struct amdgpu_bo		*robj;
605 	volatile uint32_t		*ptr;
606 	u64				gpu_addr;
607 };
608 
609 /*
610  * CGS
611  */
612 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
613 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
614 
615 /*
616  * Core structure, functions and helpers.
617  */
618 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
619 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
620 
621 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
622 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
623 
624 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
625 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
626 
627 struct amdgpu_mmio_remap {
628 	u32 reg_offset;
629 	resource_size_t bus_addr;
630 };
631 
632 /* Define the HW IP blocks will be used in driver , add more if necessary */
633 enum amd_hw_ip_block_type {
634 	GC_HWIP = 1,
635 	HDP_HWIP,
636 	SDMA0_HWIP,
637 	SDMA1_HWIP,
638 	SDMA2_HWIP,
639 	SDMA3_HWIP,
640 	SDMA4_HWIP,
641 	SDMA5_HWIP,
642 	SDMA6_HWIP,
643 	SDMA7_HWIP,
644 	MMHUB_HWIP,
645 	ATHUB_HWIP,
646 	NBIO_HWIP,
647 	MP0_HWIP,
648 	MP1_HWIP,
649 	UVD_HWIP,
650 	VCN_HWIP = UVD_HWIP,
651 	JPEG_HWIP = VCN_HWIP,
652 	VCN1_HWIP,
653 	VCE_HWIP,
654 	DF_HWIP,
655 	DCE_HWIP,
656 	OSSSYS_HWIP,
657 	SMUIO_HWIP,
658 	PWR_HWIP,
659 	NBIF_HWIP,
660 	THM_HWIP,
661 	CLK_HWIP,
662 	UMC_HWIP,
663 	RSMU_HWIP,
664 	XGMI_HWIP,
665 	DCI_HWIP,
666 	MAX_HWIP
667 };
668 
669 #define HWIP_MAX_INSTANCE	10
670 
671 #define HW_ID_MAX		300
672 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
673 
674 struct amd_powerplay {
675 	void *pp_handle;
676 	const struct amd_pm_funcs *pp_funcs;
677 };
678 
679 struct ip_discovery_top;
680 
681 /* polaris10 kickers */
682 #define ASICID_IS_P20(did, rid)		(((did == 0x67DF) && \
683 					 ((rid == 0xE3) || \
684 					  (rid == 0xE4) || \
685 					  (rid == 0xE5) || \
686 					  (rid == 0xE7) || \
687 					  (rid == 0xEF))) || \
688 					 ((did == 0x6FDF) && \
689 					 ((rid == 0xE7) || \
690 					  (rid == 0xEF) || \
691 					  (rid == 0xFF))))
692 
693 #define ASICID_IS_P30(did, rid)		((did == 0x67DF) && \
694 					((rid == 0xE1) || \
695 					 (rid == 0xF7)))
696 
697 /* polaris11 kickers */
698 #define ASICID_IS_P21(did, rid)		(((did == 0x67EF) && \
699 					 ((rid == 0xE0) || \
700 					  (rid == 0xE5))) || \
701 					 ((did == 0x67FF) && \
702 					 ((rid == 0xCF) || \
703 					  (rid == 0xEF) || \
704 					  (rid == 0xFF))))
705 
706 #define ASICID_IS_P31(did, rid)		((did == 0x67EF) && \
707 					((rid == 0xE2)))
708 
709 /* polaris12 kickers */
710 #define ASICID_IS_P23(did, rid)		(((did == 0x6987) && \
711 					 ((rid == 0xC0) || \
712 					  (rid == 0xC1) || \
713 					  (rid == 0xC3) || \
714 					  (rid == 0xC7))) || \
715 					 ((did == 0x6981) && \
716 					 ((rid == 0x00) || \
717 					  (rid == 0x01) || \
718 					  (rid == 0x10))))
719 
720 #define AMDGPU_RESET_MAGIC_NUM 64
721 #define AMDGPU_MAX_DF_PERFMONS 4
722 #define AMDGPU_PRODUCT_NAME_LEN 64
723 struct amdgpu_reset_domain;
724 
725 struct amdgpu_device {
726 	struct device			*dev;
727 	struct pci_dev			*pdev;
728 	struct drm_device		ddev;
729 
730 #ifdef CONFIG_DRM_AMD_ACP
731 	struct amdgpu_acp		acp;
732 #endif
733 	struct amdgpu_hive_info *hive;
734 	/* ASIC */
735 	enum amd_asic_type		asic_type;
736 	uint32_t			family;
737 	uint32_t			rev_id;
738 	uint32_t			external_rev_id;
739 	unsigned long			flags;
740 	unsigned long			apu_flags;
741 	int				usec_timeout;
742 	const struct amdgpu_asic_funcs	*asic_funcs;
743 	bool				shutdown;
744 	bool				need_swiotlb;
745 	bool				accel_working;
746 	struct notifier_block		acpi_nb;
747 	struct amdgpu_i2c_chan		*i2c_bus[AMDGPU_MAX_I2C_BUS];
748 	struct debugfs_blob_wrapper     debugfs_vbios_blob;
749 	struct debugfs_blob_wrapper     debugfs_discovery_blob;
750 	struct mutex			srbm_mutex;
751 	/* GRBM index mutex. Protects concurrent access to GRBM index */
752 	struct mutex                    grbm_idx_mutex;
753 	struct dev_pm_domain		vga_pm_domain;
754 	bool				have_disp_power_ref;
755 	bool                            have_atomics_support;
756 
757 	/* BIOS */
758 	bool				is_atom_fw;
759 	uint8_t				*bios;
760 	uint32_t			bios_size;
761 	uint32_t			bios_scratch_reg_offset;
762 	uint32_t			bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
763 
764 	/* Register/doorbell mmio */
765 	resource_size_t			rmmio_base;
766 	resource_size_t			rmmio_size;
767 	void __iomem			*rmmio;
768 	/* protects concurrent MM_INDEX/DATA based register access */
769 	spinlock_t mmio_idx_lock;
770 	struct amdgpu_mmio_remap        rmmio_remap;
771 	/* protects concurrent SMC based register access */
772 	spinlock_t smc_idx_lock;
773 	amdgpu_rreg_t			smc_rreg;
774 	amdgpu_wreg_t			smc_wreg;
775 	/* protects concurrent PCIE register access */
776 	spinlock_t pcie_idx_lock;
777 	amdgpu_rreg_t			pcie_rreg;
778 	amdgpu_wreg_t			pcie_wreg;
779 	amdgpu_rreg_t			pciep_rreg;
780 	amdgpu_wreg_t			pciep_wreg;
781 	amdgpu_rreg64_t			pcie_rreg64;
782 	amdgpu_wreg64_t			pcie_wreg64;
783 	/* protects concurrent UVD register access */
784 	spinlock_t uvd_ctx_idx_lock;
785 	amdgpu_rreg_t			uvd_ctx_rreg;
786 	amdgpu_wreg_t			uvd_ctx_wreg;
787 	/* protects concurrent DIDT register access */
788 	spinlock_t didt_idx_lock;
789 	amdgpu_rreg_t			didt_rreg;
790 	amdgpu_wreg_t			didt_wreg;
791 	/* protects concurrent gc_cac register access */
792 	spinlock_t gc_cac_idx_lock;
793 	amdgpu_rreg_t			gc_cac_rreg;
794 	amdgpu_wreg_t			gc_cac_wreg;
795 	/* protects concurrent se_cac register access */
796 	spinlock_t se_cac_idx_lock;
797 	amdgpu_rreg_t			se_cac_rreg;
798 	amdgpu_wreg_t			se_cac_wreg;
799 	/* protects concurrent ENDPOINT (audio) register access */
800 	spinlock_t audio_endpt_idx_lock;
801 	amdgpu_block_rreg_t		audio_endpt_rreg;
802 	amdgpu_block_wreg_t		audio_endpt_wreg;
803 	struct amdgpu_doorbell		doorbell;
804 
805 	/* clock/pll info */
806 	struct amdgpu_clock            clock;
807 
808 	/* MC */
809 	struct amdgpu_gmc		gmc;
810 	struct amdgpu_gart		gart;
811 	dma_addr_t			dummy_page_addr;
812 	struct amdgpu_vm_manager	vm_manager;
813 	struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];
814 	unsigned			num_vmhubs;
815 
816 	/* memory management */
817 	struct amdgpu_mman		mman;
818 	struct amdgpu_vram_scratch	vram_scratch;
819 	struct amdgpu_wb		wb;
820 	atomic64_t			num_bytes_moved;
821 	atomic64_t			num_evictions;
822 	atomic64_t			num_vram_cpu_page_faults;
823 	atomic_t			gpu_reset_counter;
824 	atomic_t			vram_lost_counter;
825 
826 	/* data for buffer migration throttling */
827 	struct {
828 		spinlock_t		lock;
829 		s64			last_update_us;
830 		s64			accum_us; /* accumulated microseconds */
831 		s64			accum_us_vis; /* for visible VRAM */
832 		u32			log2_max_MBps;
833 	} mm_stats;
834 
835 	/* display */
836 	bool				enable_virtual_display;
837 	struct amdgpu_vkms_output       *amdgpu_vkms_output;
838 	struct amdgpu_mode_info		mode_info;
839 	/* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
840 	struct work_struct		hotplug_work;
841 	struct amdgpu_irq_src		crtc_irq;
842 	struct amdgpu_irq_src		vline0_irq;
843 	struct amdgpu_irq_src		vupdate_irq;
844 	struct amdgpu_irq_src		pageflip_irq;
845 	struct amdgpu_irq_src		hpd_irq;
846 	struct amdgpu_irq_src		dmub_trace_irq;
847 	struct amdgpu_irq_src		dmub_outbox_irq;
848 
849 	/* rings */
850 	u64				fence_context;
851 	unsigned			num_rings;
852 	struct amdgpu_ring		*rings[AMDGPU_MAX_RINGS];
853 	bool				ib_pool_ready;
854 	struct amdgpu_sa_manager	ib_pools[AMDGPU_IB_POOL_MAX];
855 	struct amdgpu_sched		gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
856 
857 	/* interrupts */
858 	struct amdgpu_irq		irq;
859 
860 	/* powerplay */
861 	struct amd_powerplay		powerplay;
862 	struct amdgpu_pm		pm;
863 	u32				cg_flags;
864 	u32				pg_flags;
865 
866 	/* nbio */
867 	struct amdgpu_nbio		nbio;
868 
869 	/* hdp */
870 	struct amdgpu_hdp		hdp;
871 
872 	/* smuio */
873 	struct amdgpu_smuio		smuio;
874 
875 	/* mmhub */
876 	struct amdgpu_mmhub		mmhub;
877 
878 	/* gfxhub */
879 	struct amdgpu_gfxhub		gfxhub;
880 
881 	/* gfx */
882 	struct amdgpu_gfx		gfx;
883 
884 	/* sdma */
885 	struct amdgpu_sdma		sdma;
886 
887 	/* uvd */
888 	struct amdgpu_uvd		uvd;
889 
890 	/* vce */
891 	struct amdgpu_vce		vce;
892 
893 	/* vcn */
894 	struct amdgpu_vcn		vcn;
895 
896 	/* jpeg */
897 	struct amdgpu_jpeg		jpeg;
898 
899 	/* firmwares */
900 	struct amdgpu_firmware		firmware;
901 
902 	/* PSP */
903 	struct psp_context		psp;
904 
905 	/* GDS */
906 	struct amdgpu_gds		gds;
907 
908 	/* KFD */
909 	struct amdgpu_kfd_dev		kfd;
910 
911 	/* UMC */
912 	struct amdgpu_umc		umc;
913 
914 	/* display related functionality */
915 	struct amdgpu_display_manager dm;
916 
917 	/* mes */
918 	bool                            enable_mes;
919 	struct amdgpu_mes               mes;
920 
921 	/* df */
922 	struct amdgpu_df                df;
923 
924 	/* MCA */
925 	struct amdgpu_mca               mca;
926 
927 	struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];
928 	uint32_t		        harvest_ip_mask;
929 	int				num_ip_blocks;
930 	struct mutex	mn_lock;
931 	DECLARE_HASHTABLE(mn_hash, 7);
932 
933 	/* tracking pinned memory */
934 	atomic64_t vram_pin_size;
935 	atomic64_t visible_pin_size;
936 	atomic64_t gart_pin_size;
937 
938 	/* soc15 register offset based on ip, instance and  segment */
939 	uint32_t		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
940 
941 	/* delayed work_func for deferring clockgating during resume */
942 	struct delayed_work     delayed_init_work;
943 
944 	struct amdgpu_virt	virt;
945 
946 	/* link all shadow bo */
947 	struct list_head                shadow_list;
948 	struct mutex                    shadow_list_lock;
949 
950 	/* record hw reset is performed */
951 	bool has_hw_reset;
952 	u8				reset_magic[AMDGPU_RESET_MAGIC_NUM];
953 
954 	/* s3/s4 mask */
955 	bool                            in_suspend;
956 	bool				in_s3;
957 	bool				in_s4;
958 	bool				in_s0ix;
959 
960 	enum pp_mp1_state               mp1_state;
961 	struct amdgpu_doorbell_index doorbell_index;
962 
963 	struct mutex			notifier_lock;
964 
965 	int asic_reset_res;
966 	struct work_struct		xgmi_reset_work;
967 	struct list_head		reset_list;
968 
969 	long				gfx_timeout;
970 	long				sdma_timeout;
971 	long				video_timeout;
972 	long				compute_timeout;
973 
974 	uint64_t			unique_id;
975 	uint64_t	df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
976 
977 	/* enable runtime pm on the device */
978 	bool                            runpm;
979 	bool                            in_runpm;
980 	bool                            has_pr3;
981 	bool                            is_fw_fb;
982 
983 	bool                            pm_sysfs_en;
984 	bool                            ucode_sysfs_en;
985 
986 	/* Chip product information */
987 	char				product_number[16];
988 	char				product_name[AMDGPU_PRODUCT_NAME_LEN];
989 	char				serial[20];
990 
991 	atomic_t			throttling_logging_enabled;
992 	struct ratelimit_state		throttling_logging_rs;
993 	uint32_t                        ras_hw_enabled;
994 	uint32_t                        ras_enabled;
995 
996 	bool                            no_hw_access;
997 	struct pci_saved_state          *pci_state;
998 	pci_channel_state_t		pci_channel_state;
999 
1000 	struct amdgpu_reset_control     *reset_cntl;
1001 	uint32_t                        ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1002 
1003 	bool				ram_is_direct_mapped;
1004 
1005 	struct list_head                ras_list;
1006 
1007 	struct ip_discovery_top         *ip_top;
1008 
1009 	struct amdgpu_reset_domain	*reset_domain;
1010 
1011 	struct mutex			benchmark_mutex;
1012 
1013 	/* reset dump register */
1014 	uint32_t                        *reset_dump_reg_list;
1015 	int                             num_regs;
1016 };
1017 
1018 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1019 {
1020 	return container_of(ddev, struct amdgpu_device, ddev);
1021 }
1022 
1023 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1024 {
1025 	return &adev->ddev;
1026 }
1027 
1028 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1029 {
1030 	return container_of(bdev, struct amdgpu_device, mman.bdev);
1031 }
1032 
1033 int amdgpu_device_init(struct amdgpu_device *adev,
1034 		       uint32_t flags);
1035 void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1036 void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1037 
1038 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1039 
1040 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1041 			     void *buf, size_t size, bool write);
1042 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1043 				 void *buf, size_t size, bool write);
1044 
1045 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1046 			       void *buf, size_t size, bool write);
1047 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1048 			    uint32_t reg, uint32_t acc_flags);
1049 void amdgpu_device_wreg(struct amdgpu_device *adev,
1050 			uint32_t reg, uint32_t v,
1051 			uint32_t acc_flags);
1052 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1053 			     uint32_t reg, uint32_t v);
1054 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1055 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1056 
1057 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1058 				u32 pcie_index, u32 pcie_data,
1059 				u32 reg_addr);
1060 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1061 				  u32 pcie_index, u32 pcie_data,
1062 				  u32 reg_addr);
1063 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1064 				 u32 pcie_index, u32 pcie_data,
1065 				 u32 reg_addr, u32 reg_data);
1066 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1067 				   u32 pcie_index, u32 pcie_data,
1068 				   u32 reg_addr, u64 reg_data);
1069 
1070 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1071 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1072 
1073 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1074 				 struct amdgpu_reset_context *reset_context);
1075 
1076 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1077 			 struct amdgpu_reset_context *reset_context);
1078 
1079 int emu_soc_asic_init(struct amdgpu_device *adev);
1080 
1081 /*
1082  * Registers read & write functions.
1083  */
1084 #define AMDGPU_REGS_NO_KIQ    (1<<1)
1085 #define AMDGPU_REGS_RLC	(1<<2)
1086 
1087 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1088 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1089 
1090 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1091 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1092 
1093 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1094 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1095 
1096 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1097 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1098 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1099 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1100 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1101 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1102 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1103 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1104 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1105 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1106 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1107 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1108 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1109 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1110 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1111 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1112 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1113 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1114 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1115 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1116 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1117 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1118 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1119 #define WREG32_P(reg, val, mask)				\
1120 	do {							\
1121 		uint32_t tmp_ = RREG32(reg);			\
1122 		tmp_ &= (mask);					\
1123 		tmp_ |= ((val) & ~(mask));			\
1124 		WREG32(reg, tmp_);				\
1125 	} while (0)
1126 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1127 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1128 #define WREG32_PLL_P(reg, val, mask)				\
1129 	do {							\
1130 		uint32_t tmp_ = RREG32_PLL(reg);		\
1131 		tmp_ &= (mask);					\
1132 		tmp_ |= ((val) & ~(mask));			\
1133 		WREG32_PLL(reg, tmp_);				\
1134 	} while (0)
1135 
1136 #define WREG32_SMC_P(_Reg, _Val, _Mask)                         \
1137 	do {                                                    \
1138 		u32 tmp = RREG32_SMC(_Reg);                     \
1139 		tmp &= (_Mask);                                 \
1140 		tmp |= ((_Val) & ~(_Mask));                     \
1141 		WREG32_SMC(_Reg, tmp);                          \
1142 	} while (0)
1143 
1144 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1145 
1146 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1147 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1148 
1149 #define REG_SET_FIELD(orig_val, reg, field, field_val)			\
1150 	(((orig_val) & ~REG_FIELD_MASK(reg, field)) |			\
1151 	 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1152 
1153 #define REG_GET_FIELD(value, reg, field)				\
1154 	(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1155 
1156 #define WREG32_FIELD(reg, field, val)	\
1157 	WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1158 
1159 #define WREG32_FIELD_OFFSET(reg, offset, field, val)	\
1160 	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1161 
1162 /*
1163  * BIOS helpers.
1164  */
1165 #define RBIOS8(i) (adev->bios[i])
1166 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1167 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1168 
1169 /*
1170  * ASICs macro.
1171  */
1172 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1173 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1174 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1175 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1176 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1177 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1178 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1179 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1180 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1181 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1182 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1183 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1184 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1185 #define amdgpu_asic_flush_hdp(adev, r) \
1186 	((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1187 #define amdgpu_asic_invalidate_hdp(adev, r) \
1188 	((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r)))
1189 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1190 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1191 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1192 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1193 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1194 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1195 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1196 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1197 	((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1198 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1199 
1200 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1201 
1202 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
1203 
1204 /* Common functions */
1205 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1206 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1207 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1208 			      struct amdgpu_job* job);
1209 int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev,
1210 			      struct amdgpu_job *job);
1211 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1212 int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1213 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1214 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1215 
1216 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1217 				  u64 num_vis_bytes);
1218 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1219 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1220 					     const u32 *registers,
1221 					     const u32 array_size);
1222 
1223 int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1224 bool amdgpu_device_supports_atpx(struct drm_device *dev);
1225 bool amdgpu_device_supports_px(struct drm_device *dev);
1226 bool amdgpu_device_supports_boco(struct drm_device *dev);
1227 bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1228 bool amdgpu_device_supports_baco(struct drm_device *dev);
1229 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1230 				      struct amdgpu_device *peer_adev);
1231 int amdgpu_device_baco_enter(struct drm_device *dev);
1232 int amdgpu_device_baco_exit(struct drm_device *dev);
1233 
1234 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1235 		struct amdgpu_ring *ring);
1236 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1237 		struct amdgpu_ring *ring);
1238 
1239 void amdgpu_device_halt(struct amdgpu_device *adev);
1240 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1241 				u32 reg);
1242 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1243 				u32 reg, u32 v);
1244 
1245 /* atpx handler */
1246 #if defined(CONFIG_VGA_SWITCHEROO)
1247 void amdgpu_register_atpx_handler(void);
1248 void amdgpu_unregister_atpx_handler(void);
1249 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1250 bool amdgpu_is_atpx_hybrid(void);
1251 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1252 bool amdgpu_has_atpx(void);
1253 #else
1254 static inline void amdgpu_register_atpx_handler(void) {}
1255 static inline void amdgpu_unregister_atpx_handler(void) {}
1256 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1257 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1258 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1259 static inline bool amdgpu_has_atpx(void) { return false; }
1260 #endif
1261 
1262 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1263 void *amdgpu_atpx_get_dhandle(void);
1264 #else
1265 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1266 #endif
1267 
1268 /*
1269  * KMS
1270  */
1271 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1272 extern const int amdgpu_max_kms_ioctl;
1273 
1274 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1275 void amdgpu_driver_unload_kms(struct drm_device *dev);
1276 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1277 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1278 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1279 				 struct drm_file *file_priv);
1280 void amdgpu_driver_release_kms(struct drm_device *dev);
1281 
1282 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1283 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1284 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1285 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1286 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1287 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1288 int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1289 		      struct drm_file *filp);
1290 
1291 /*
1292  * functions used by amdgpu_encoder.c
1293  */
1294 struct amdgpu_afmt_acr {
1295 	u32 clock;
1296 
1297 	int n_32khz;
1298 	int cts_32khz;
1299 
1300 	int n_44_1khz;
1301 	int cts_44_1khz;
1302 
1303 	int n_48khz;
1304 	int cts_48khz;
1305 
1306 };
1307 
1308 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1309 
1310 /* amdgpu_acpi.c */
1311 
1312 /* ATCS Device/Driver State */
1313 #define AMDGPU_ATCS_PSC_DEV_STATE_D0		0
1314 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT	3
1315 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR		0
1316 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR	1
1317 
1318 #if defined(CONFIG_ACPI)
1319 int amdgpu_acpi_init(struct amdgpu_device *adev);
1320 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1321 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1322 bool amdgpu_acpi_is_power_shift_control_supported(void);
1323 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1324 						u8 perf_req, bool advertise);
1325 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1326 				    u8 dev_state, bool drv_state);
1327 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1328 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1329 
1330 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1331 void amdgpu_acpi_detect(void);
1332 #else
1333 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1334 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1335 static inline void amdgpu_acpi_detect(void) { }
1336 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1337 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1338 						  u8 dev_state, bool drv_state) { return 0; }
1339 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1340 						 enum amdgpu_ss ss_state) { return 0; }
1341 #endif
1342 
1343 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1344 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1345 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1346 #else
1347 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1348 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1349 #endif
1350 
1351 #if defined(CONFIG_DRM_AMD_DC)
1352 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1353 #else
1354 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1355 #endif
1356 
1357 
1358 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1359 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1360 
1361 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1362 					   pci_channel_state_t state);
1363 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1364 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1365 void amdgpu_pci_resume(struct pci_dev *pdev);
1366 
1367 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1368 bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1369 
1370 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1371 
1372 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1373 			       enum amd_clockgating_state state);
1374 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1375 			       enum amd_powergating_state state);
1376 
1377 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1378 {
1379 	return amdgpu_gpu_recovery != 0 &&
1380 		adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1381 		adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1382 		adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1383 		adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1384 }
1385 
1386 #include "amdgpu_object.h"
1387 
1388 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1389 {
1390        return adev->gmc.tmz_enabled;
1391 }
1392 
1393 int amdgpu_in_reset(struct amdgpu_device *adev);
1394 
1395 #endif
1396