1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_module.h> 59 #include <drm/ttm/ttm_execbuf_util.h> 60 61 #include <drm/amdgpu_drm.h> 62 #include <drm/drm_gem.h> 63 #include <drm/drm_ioctl.h> 64 #include <drm/gpu_scheduler.h> 65 66 #include <kgd_kfd_interface.h> 67 #include "dm_pp_interface.h" 68 #include "kgd_pp_interface.h" 69 70 #include "amd_shared.h" 71 #include "amdgpu_mode.h" 72 #include "amdgpu_ih.h" 73 #include "amdgpu_irq.h" 74 #include "amdgpu_ucode.h" 75 #include "amdgpu_ttm.h" 76 #include "amdgpu_psp.h" 77 #include "amdgpu_gds.h" 78 #include "amdgpu_sync.h" 79 #include "amdgpu_ring.h" 80 #include "amdgpu_vm.h" 81 #include "amdgpu_dpm.h" 82 #include "amdgpu_acp.h" 83 #include "amdgpu_uvd.h" 84 #include "amdgpu_vce.h" 85 #include "amdgpu_vcn.h" 86 #include "amdgpu_jpeg.h" 87 #include "amdgpu_mn.h" 88 #include "amdgpu_gmc.h" 89 #include "amdgpu_gfx.h" 90 #include "amdgpu_sdma.h" 91 #include "amdgpu_nbio.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_smu.h" 103 #include "amdgpu_discovery.h" 104 #include "amdgpu_mes.h" 105 #include "amdgpu_umc.h" 106 #include "amdgpu_mmhub.h" 107 #include "amdgpu_gfxhub.h" 108 #include "amdgpu_df.h" 109 #include "amdgpu_smuio.h" 110 111 #define MAX_GPU_INSTANCE 16 112 113 struct amdgpu_gpu_instance 114 { 115 struct amdgpu_device *adev; 116 int mgpu_fan_enabled; 117 }; 118 119 struct amdgpu_mgpu_info 120 { 121 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 122 struct mutex mutex; 123 uint32_t num_gpu; 124 uint32_t num_dgpu; 125 uint32_t num_apu; 126 }; 127 128 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 129 130 /* 131 * Modules parameters. 132 */ 133 extern int amdgpu_modeset; 134 extern int amdgpu_vram_limit; 135 extern int amdgpu_vis_vram_limit; 136 extern int amdgpu_gart_size; 137 extern int amdgpu_gtt_size; 138 extern int amdgpu_moverate; 139 extern int amdgpu_benchmarking; 140 extern int amdgpu_testing; 141 extern int amdgpu_audio; 142 extern int amdgpu_disp_priority; 143 extern int amdgpu_hw_i2c; 144 extern int amdgpu_pcie_gen2; 145 extern int amdgpu_msi; 146 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 147 extern int amdgpu_dpm; 148 extern int amdgpu_fw_load_type; 149 extern int amdgpu_aspm; 150 extern int amdgpu_runtime_pm; 151 extern uint amdgpu_ip_block_mask; 152 extern int amdgpu_bapm; 153 extern int amdgpu_deep_color; 154 extern int amdgpu_vm_size; 155 extern int amdgpu_vm_block_size; 156 extern int amdgpu_vm_fragment_size; 157 extern int amdgpu_vm_fault_stop; 158 extern int amdgpu_vm_debug; 159 extern int amdgpu_vm_update_mode; 160 extern int amdgpu_exp_hw_support; 161 extern int amdgpu_dc; 162 extern int amdgpu_sched_jobs; 163 extern int amdgpu_sched_hw_submission; 164 extern uint amdgpu_pcie_gen_cap; 165 extern uint amdgpu_pcie_lane_cap; 166 extern uint amdgpu_cg_mask; 167 extern uint amdgpu_pg_mask; 168 extern uint amdgpu_sdma_phase_quantum; 169 extern char *amdgpu_disable_cu; 170 extern char *amdgpu_virtual_display; 171 extern uint amdgpu_pp_feature_mask; 172 extern uint amdgpu_force_long_training; 173 extern int amdgpu_job_hang_limit; 174 extern int amdgpu_lbpw; 175 extern int amdgpu_compute_multipipe; 176 extern int amdgpu_gpu_recovery; 177 extern int amdgpu_emu_mode; 178 extern uint amdgpu_smu_memory_pool_size; 179 extern uint amdgpu_dc_feature_mask; 180 extern uint amdgpu_dc_debug_mask; 181 extern uint amdgpu_dm_abm_level; 182 extern struct amdgpu_mgpu_info mgpu_info; 183 extern int amdgpu_ras_enable; 184 extern uint amdgpu_ras_mask; 185 extern int amdgpu_bad_page_threshold; 186 extern int amdgpu_async_gfx_ring; 187 extern int amdgpu_mcbp; 188 extern int amdgpu_discovery; 189 extern int amdgpu_mes; 190 extern int amdgpu_noretry; 191 extern int amdgpu_force_asic_type; 192 #ifdef CONFIG_HSA_AMD 193 extern int sched_policy; 194 extern bool debug_evictions; 195 extern bool no_system_mem_limit; 196 #else 197 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 198 static const bool __maybe_unused debug_evictions; /* = false */ 199 static const bool __maybe_unused no_system_mem_limit; 200 #endif 201 202 extern int amdgpu_tmz; 203 extern int amdgpu_reset_method; 204 205 #ifdef CONFIG_DRM_AMDGPU_SI 206 extern int amdgpu_si_support; 207 #endif 208 #ifdef CONFIG_DRM_AMDGPU_CIK 209 extern int amdgpu_cik_support; 210 #endif 211 extern int amdgpu_num_kcq; 212 213 #define AMDGPU_VM_MAX_NUM_CTX 4096 214 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 215 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 216 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 217 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 218 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 219 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 220 #define AMDGPUFB_CONN_LIMIT 4 221 #define AMDGPU_BIOS_NUM_SCRATCH 16 222 223 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 224 225 /* hard reset data */ 226 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 227 228 /* reset flags */ 229 #define AMDGPU_RESET_GFX (1 << 0) 230 #define AMDGPU_RESET_COMPUTE (1 << 1) 231 #define AMDGPU_RESET_DMA (1 << 2) 232 #define AMDGPU_RESET_CP (1 << 3) 233 #define AMDGPU_RESET_GRBM (1 << 4) 234 #define AMDGPU_RESET_DMA1 (1 << 5) 235 #define AMDGPU_RESET_RLC (1 << 6) 236 #define AMDGPU_RESET_SEM (1 << 7) 237 #define AMDGPU_RESET_IH (1 << 8) 238 #define AMDGPU_RESET_VMC (1 << 9) 239 #define AMDGPU_RESET_MC (1 << 10) 240 #define AMDGPU_RESET_DISPLAY (1 << 11) 241 #define AMDGPU_RESET_UVD (1 << 12) 242 #define AMDGPU_RESET_VCE (1 << 13) 243 #define AMDGPU_RESET_VCE1 (1 << 14) 244 245 /* max cursor sizes (in pixels) */ 246 #define CIK_CURSOR_WIDTH 128 247 #define CIK_CURSOR_HEIGHT 128 248 249 struct amdgpu_device; 250 struct amdgpu_ib; 251 struct amdgpu_cs_parser; 252 struct amdgpu_job; 253 struct amdgpu_irq_src; 254 struct amdgpu_fpriv; 255 struct amdgpu_bo_va_mapping; 256 struct amdgpu_atif; 257 struct kfd_vm_fault_info; 258 struct amdgpu_hive_info; 259 260 enum amdgpu_cp_irq { 261 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 262 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 263 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 264 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 265 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 266 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 267 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 268 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 269 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 270 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 271 272 AMDGPU_CP_IRQ_LAST 273 }; 274 275 enum amdgpu_thermal_irq { 276 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 277 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 278 279 AMDGPU_THERMAL_IRQ_LAST 280 }; 281 282 enum amdgpu_kiq_irq { 283 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 284 AMDGPU_CP_KIQ_IRQ_LAST 285 }; 286 287 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 288 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 289 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 290 291 int amdgpu_device_ip_set_clockgating_state(void *dev, 292 enum amd_ip_block_type block_type, 293 enum amd_clockgating_state state); 294 int amdgpu_device_ip_set_powergating_state(void *dev, 295 enum amd_ip_block_type block_type, 296 enum amd_powergating_state state); 297 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 298 u32 *flags); 299 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 300 enum amd_ip_block_type block_type); 301 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 302 enum amd_ip_block_type block_type); 303 304 #define AMDGPU_MAX_IP_NUM 16 305 306 struct amdgpu_ip_block_status { 307 bool valid; 308 bool sw; 309 bool hw; 310 bool late_initialized; 311 bool hang; 312 }; 313 314 struct amdgpu_ip_block_version { 315 const enum amd_ip_block_type type; 316 const u32 major; 317 const u32 minor; 318 const u32 rev; 319 const struct amd_ip_funcs *funcs; 320 }; 321 322 #define HW_REV(_Major, _Minor, _Rev) \ 323 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 324 325 struct amdgpu_ip_block { 326 struct amdgpu_ip_block_status status; 327 const struct amdgpu_ip_block_version *version; 328 }; 329 330 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 331 enum amd_ip_block_type type, 332 u32 major, u32 minor); 333 334 struct amdgpu_ip_block * 335 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 336 enum amd_ip_block_type type); 337 338 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 339 const struct amdgpu_ip_block_version *ip_block_version); 340 341 /* 342 * BIOS. 343 */ 344 bool amdgpu_get_bios(struct amdgpu_device *adev); 345 bool amdgpu_read_bios(struct amdgpu_device *adev); 346 347 /* 348 * Clocks 349 */ 350 351 #define AMDGPU_MAX_PPLL 3 352 353 struct amdgpu_clock { 354 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 355 struct amdgpu_pll spll; 356 struct amdgpu_pll mpll; 357 /* 10 Khz units */ 358 uint32_t default_mclk; 359 uint32_t default_sclk; 360 uint32_t default_dispclk; 361 uint32_t current_dispclk; 362 uint32_t dp_extclk; 363 uint32_t max_pixel_clock; 364 }; 365 366 /* sub-allocation manager, it has to be protected by another lock. 367 * By conception this is an helper for other part of the driver 368 * like the indirect buffer or semaphore, which both have their 369 * locking. 370 * 371 * Principe is simple, we keep a list of sub allocation in offset 372 * order (first entry has offset == 0, last entry has the highest 373 * offset). 374 * 375 * When allocating new object we first check if there is room at 376 * the end total_size - (last_object_offset + last_object_size) >= 377 * alloc_size. If so we allocate new object there. 378 * 379 * When there is not enough room at the end, we start waiting for 380 * each sub object until we reach object_offset+object_size >= 381 * alloc_size, this object then become the sub object we return. 382 * 383 * Alignment can't be bigger than page size. 384 * 385 * Hole are not considered for allocation to keep things simple. 386 * Assumption is that there won't be hole (all object on same 387 * alignment). 388 */ 389 390 #define AMDGPU_SA_NUM_FENCE_LISTS 32 391 392 struct amdgpu_sa_manager { 393 wait_queue_head_t wq; 394 struct amdgpu_bo *bo; 395 struct list_head *hole; 396 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 397 struct list_head olist; 398 unsigned size; 399 uint64_t gpu_addr; 400 void *cpu_ptr; 401 uint32_t domain; 402 uint32_t align; 403 }; 404 405 /* sub-allocation buffer */ 406 struct amdgpu_sa_bo { 407 struct list_head olist; 408 struct list_head flist; 409 struct amdgpu_sa_manager *manager; 410 unsigned soffset; 411 unsigned eoffset; 412 struct dma_fence *fence; 413 }; 414 415 int amdgpu_fence_slab_init(void); 416 void amdgpu_fence_slab_fini(void); 417 418 /* 419 * IRQS. 420 */ 421 422 struct amdgpu_flip_work { 423 struct delayed_work flip_work; 424 struct work_struct unpin_work; 425 struct amdgpu_device *adev; 426 int crtc_id; 427 u32 target_vblank; 428 uint64_t base; 429 struct drm_pending_vblank_event *event; 430 struct amdgpu_bo *old_abo; 431 struct dma_fence *excl; 432 unsigned shared_count; 433 struct dma_fence **shared; 434 struct dma_fence_cb cb; 435 bool async; 436 }; 437 438 439 /* 440 * CP & rings. 441 */ 442 443 struct amdgpu_ib { 444 struct amdgpu_sa_bo *sa_bo; 445 uint32_t length_dw; 446 uint64_t gpu_addr; 447 uint32_t *ptr; 448 uint32_t flags; 449 }; 450 451 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 452 453 /* 454 * file private structure 455 */ 456 457 struct amdgpu_fpriv { 458 struct amdgpu_vm vm; 459 struct amdgpu_bo_va *prt_va; 460 struct amdgpu_bo_va *csa_va; 461 struct mutex bo_list_lock; 462 struct idr bo_list_handles; 463 struct amdgpu_ctx_mgr ctx_mgr; 464 }; 465 466 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 467 468 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 469 unsigned size, 470 enum amdgpu_ib_pool_type pool, 471 struct amdgpu_ib *ib); 472 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 473 struct dma_fence *f); 474 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 475 struct amdgpu_ib *ibs, struct amdgpu_job *job, 476 struct dma_fence **f); 477 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 478 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 479 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 480 481 /* 482 * CS. 483 */ 484 struct amdgpu_cs_chunk { 485 uint32_t chunk_id; 486 uint32_t length_dw; 487 void *kdata; 488 }; 489 490 struct amdgpu_cs_post_dep { 491 struct drm_syncobj *syncobj; 492 struct dma_fence_chain *chain; 493 u64 point; 494 }; 495 496 struct amdgpu_cs_parser { 497 struct amdgpu_device *adev; 498 struct drm_file *filp; 499 struct amdgpu_ctx *ctx; 500 501 /* chunks */ 502 unsigned nchunks; 503 struct amdgpu_cs_chunk *chunks; 504 505 /* scheduler job object */ 506 struct amdgpu_job *job; 507 struct drm_sched_entity *entity; 508 509 /* buffer objects */ 510 struct ww_acquire_ctx ticket; 511 struct amdgpu_bo_list *bo_list; 512 struct amdgpu_mn *mn; 513 struct amdgpu_bo_list_entry vm_pd; 514 struct list_head validated; 515 struct dma_fence *fence; 516 uint64_t bytes_moved_threshold; 517 uint64_t bytes_moved_vis_threshold; 518 uint64_t bytes_moved; 519 uint64_t bytes_moved_vis; 520 521 /* user fence */ 522 struct amdgpu_bo_list_entry uf_entry; 523 524 unsigned num_post_deps; 525 struct amdgpu_cs_post_dep *post_deps; 526 }; 527 528 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 529 uint32_t ib_idx, int idx) 530 { 531 return p->job->ibs[ib_idx].ptr[idx]; 532 } 533 534 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 535 uint32_t ib_idx, int idx, 536 uint32_t value) 537 { 538 p->job->ibs[ib_idx].ptr[idx] = value; 539 } 540 541 /* 542 * Writeback 543 */ 544 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 545 546 struct amdgpu_wb { 547 struct amdgpu_bo *wb_obj; 548 volatile uint32_t *wb; 549 uint64_t gpu_addr; 550 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 551 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 552 }; 553 554 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 555 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 556 557 /* 558 * Benchmarking 559 */ 560 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 561 562 563 /* 564 * Testing 565 */ 566 void amdgpu_test_moves(struct amdgpu_device *adev); 567 568 /* 569 * ASIC specific register table accessible by UMD 570 */ 571 struct amdgpu_allowed_register_entry { 572 uint32_t reg_offset; 573 bool grbm_indexed; 574 }; 575 576 enum amd_reset_method { 577 AMD_RESET_METHOD_LEGACY = 0, 578 AMD_RESET_METHOD_MODE0, 579 AMD_RESET_METHOD_MODE1, 580 AMD_RESET_METHOD_MODE2, 581 AMD_RESET_METHOD_BACO 582 }; 583 584 /* 585 * ASIC specific functions. 586 */ 587 struct amdgpu_asic_funcs { 588 bool (*read_disabled_bios)(struct amdgpu_device *adev); 589 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 590 u8 *bios, u32 length_bytes); 591 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 592 u32 sh_num, u32 reg_offset, u32 *value); 593 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 594 int (*reset)(struct amdgpu_device *adev); 595 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 596 /* get the reference clock */ 597 u32 (*get_xclk)(struct amdgpu_device *adev); 598 /* MM block clocks */ 599 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 600 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 601 /* static power management */ 602 int (*get_pcie_lanes)(struct amdgpu_device *adev); 603 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 604 /* get config memsize register */ 605 u32 (*get_config_memsize)(struct amdgpu_device *adev); 606 /* flush hdp write queue */ 607 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 608 /* invalidate hdp read cache */ 609 void (*invalidate_hdp)(struct amdgpu_device *adev, 610 struct amdgpu_ring *ring); 611 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev); 612 /* check if the asic needs a full reset of if soft reset will work */ 613 bool (*need_full_reset)(struct amdgpu_device *adev); 614 /* initialize doorbell layout for specific asic*/ 615 void (*init_doorbell_index)(struct amdgpu_device *adev); 616 /* PCIe bandwidth usage */ 617 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 618 uint64_t *count1); 619 /* do we need to reset the asic at init time (e.g., kexec) */ 620 bool (*need_reset_on_init)(struct amdgpu_device *adev); 621 /* PCIe replay counter */ 622 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 623 /* device supports BACO */ 624 bool (*supports_baco)(struct amdgpu_device *adev); 625 /* pre asic_init quirks */ 626 void (*pre_asic_init)(struct amdgpu_device *adev); 627 /* enter/exit umd stable pstate */ 628 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 629 }; 630 631 /* 632 * IOCTL. 633 */ 634 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 635 struct drm_file *filp); 636 637 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 638 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 639 struct drm_file *filp); 640 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 641 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 642 struct drm_file *filp); 643 644 /* VRAM scratch page for HDP bug, default vram page */ 645 struct amdgpu_vram_scratch { 646 struct amdgpu_bo *robj; 647 volatile uint32_t *ptr; 648 u64 gpu_addr; 649 }; 650 651 /* 652 * ACPI 653 */ 654 struct amdgpu_atcs_functions { 655 bool get_ext_state; 656 bool pcie_perf_req; 657 bool pcie_dev_rdy; 658 bool pcie_bus_width; 659 }; 660 661 struct amdgpu_atcs { 662 struct amdgpu_atcs_functions functions; 663 }; 664 665 /* 666 * CGS 667 */ 668 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 669 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 670 671 /* 672 * Core structure, functions and helpers. 673 */ 674 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 675 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 676 677 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 678 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 679 680 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 681 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 682 683 struct amdgpu_mmio_remap { 684 u32 reg_offset; 685 resource_size_t bus_addr; 686 }; 687 688 /* Define the HW IP blocks will be used in driver , add more if necessary */ 689 enum amd_hw_ip_block_type { 690 GC_HWIP = 1, 691 HDP_HWIP, 692 SDMA0_HWIP, 693 SDMA1_HWIP, 694 SDMA2_HWIP, 695 SDMA3_HWIP, 696 SDMA4_HWIP, 697 SDMA5_HWIP, 698 SDMA6_HWIP, 699 SDMA7_HWIP, 700 MMHUB_HWIP, 701 ATHUB_HWIP, 702 NBIO_HWIP, 703 MP0_HWIP, 704 MP1_HWIP, 705 UVD_HWIP, 706 VCN_HWIP = UVD_HWIP, 707 JPEG_HWIP = VCN_HWIP, 708 VCE_HWIP, 709 DF_HWIP, 710 DCE_HWIP, 711 OSSSYS_HWIP, 712 SMUIO_HWIP, 713 PWR_HWIP, 714 NBIF_HWIP, 715 THM_HWIP, 716 CLK_HWIP, 717 UMC_HWIP, 718 RSMU_HWIP, 719 MAX_HWIP 720 }; 721 722 #define HWIP_MAX_INSTANCE 8 723 724 struct amd_powerplay { 725 void *pp_handle; 726 const struct amd_pm_funcs *pp_funcs; 727 }; 728 729 /* polaris10 kickers */ 730 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 731 ((rid == 0xE3) || \ 732 (rid == 0xE4) || \ 733 (rid == 0xE5) || \ 734 (rid == 0xE7) || \ 735 (rid == 0xEF))) || \ 736 ((did == 0x6FDF) && \ 737 ((rid == 0xE7) || \ 738 (rid == 0xEF) || \ 739 (rid == 0xFF)))) 740 741 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 742 ((rid == 0xE1) || \ 743 (rid == 0xF7))) 744 745 /* polaris11 kickers */ 746 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 747 ((rid == 0xE0) || \ 748 (rid == 0xE5))) || \ 749 ((did == 0x67FF) && \ 750 ((rid == 0xCF) || \ 751 (rid == 0xEF) || \ 752 (rid == 0xFF)))) 753 754 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 755 ((rid == 0xE2))) 756 757 /* polaris12 kickers */ 758 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 759 ((rid == 0xC0) || \ 760 (rid == 0xC1) || \ 761 (rid == 0xC3) || \ 762 (rid == 0xC7))) || \ 763 ((did == 0x6981) && \ 764 ((rid == 0x00) || \ 765 (rid == 0x01) || \ 766 (rid == 0x10)))) 767 768 #define AMDGPU_RESET_MAGIC_NUM 64 769 #define AMDGPU_MAX_DF_PERFMONS 4 770 struct amdgpu_device { 771 struct device *dev; 772 struct pci_dev *pdev; 773 struct drm_device ddev; 774 775 #ifdef CONFIG_DRM_AMD_ACP 776 struct amdgpu_acp acp; 777 #endif 778 struct amdgpu_hive_info *hive; 779 /* ASIC */ 780 enum amd_asic_type asic_type; 781 uint32_t family; 782 uint32_t rev_id; 783 uint32_t external_rev_id; 784 unsigned long flags; 785 unsigned long apu_flags; 786 int usec_timeout; 787 const struct amdgpu_asic_funcs *asic_funcs; 788 bool shutdown; 789 bool need_swiotlb; 790 bool accel_working; 791 struct notifier_block acpi_nb; 792 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 793 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 794 unsigned debugfs_count; 795 #if defined(CONFIG_DEBUG_FS) 796 struct dentry *debugfs_preempt; 797 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 798 #endif 799 struct amdgpu_atif *atif; 800 struct amdgpu_atcs atcs; 801 struct mutex srbm_mutex; 802 /* GRBM index mutex. Protects concurrent access to GRBM index */ 803 struct mutex grbm_idx_mutex; 804 struct dev_pm_domain vga_pm_domain; 805 bool have_disp_power_ref; 806 bool have_atomics_support; 807 808 /* BIOS */ 809 bool is_atom_fw; 810 uint8_t *bios; 811 uint32_t bios_size; 812 uint32_t bios_scratch_reg_offset; 813 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 814 815 /* Register/doorbell mmio */ 816 resource_size_t rmmio_base; 817 resource_size_t rmmio_size; 818 void __iomem *rmmio; 819 /* protects concurrent MM_INDEX/DATA based register access */ 820 spinlock_t mmio_idx_lock; 821 struct amdgpu_mmio_remap rmmio_remap; 822 /* protects concurrent SMC based register access */ 823 spinlock_t smc_idx_lock; 824 amdgpu_rreg_t smc_rreg; 825 amdgpu_wreg_t smc_wreg; 826 /* protects concurrent PCIE register access */ 827 spinlock_t pcie_idx_lock; 828 amdgpu_rreg_t pcie_rreg; 829 amdgpu_wreg_t pcie_wreg; 830 amdgpu_rreg_t pciep_rreg; 831 amdgpu_wreg_t pciep_wreg; 832 amdgpu_rreg64_t pcie_rreg64; 833 amdgpu_wreg64_t pcie_wreg64; 834 /* protects concurrent UVD register access */ 835 spinlock_t uvd_ctx_idx_lock; 836 amdgpu_rreg_t uvd_ctx_rreg; 837 amdgpu_wreg_t uvd_ctx_wreg; 838 /* protects concurrent DIDT register access */ 839 spinlock_t didt_idx_lock; 840 amdgpu_rreg_t didt_rreg; 841 amdgpu_wreg_t didt_wreg; 842 /* protects concurrent gc_cac register access */ 843 spinlock_t gc_cac_idx_lock; 844 amdgpu_rreg_t gc_cac_rreg; 845 amdgpu_wreg_t gc_cac_wreg; 846 /* protects concurrent se_cac register access */ 847 spinlock_t se_cac_idx_lock; 848 amdgpu_rreg_t se_cac_rreg; 849 amdgpu_wreg_t se_cac_wreg; 850 /* protects concurrent ENDPOINT (audio) register access */ 851 spinlock_t audio_endpt_idx_lock; 852 amdgpu_block_rreg_t audio_endpt_rreg; 853 amdgpu_block_wreg_t audio_endpt_wreg; 854 void __iomem *rio_mem; 855 resource_size_t rio_mem_size; 856 struct amdgpu_doorbell doorbell; 857 858 /* clock/pll info */ 859 struct amdgpu_clock clock; 860 861 /* MC */ 862 struct amdgpu_gmc gmc; 863 struct amdgpu_gart gart; 864 dma_addr_t dummy_page_addr; 865 struct amdgpu_vm_manager vm_manager; 866 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 867 unsigned num_vmhubs; 868 869 /* memory management */ 870 struct amdgpu_mman mman; 871 struct amdgpu_vram_scratch vram_scratch; 872 struct amdgpu_wb wb; 873 atomic64_t num_bytes_moved; 874 atomic64_t num_evictions; 875 atomic64_t num_vram_cpu_page_faults; 876 atomic_t gpu_reset_counter; 877 atomic_t vram_lost_counter; 878 879 /* data for buffer migration throttling */ 880 struct { 881 spinlock_t lock; 882 s64 last_update_us; 883 s64 accum_us; /* accumulated microseconds */ 884 s64 accum_us_vis; /* for visible VRAM */ 885 u32 log2_max_MBps; 886 } mm_stats; 887 888 /* display */ 889 bool enable_virtual_display; 890 struct amdgpu_mode_info mode_info; 891 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 892 struct work_struct hotplug_work; 893 struct amdgpu_irq_src crtc_irq; 894 struct amdgpu_irq_src vupdate_irq; 895 struct amdgpu_irq_src pageflip_irq; 896 struct amdgpu_irq_src hpd_irq; 897 898 /* rings */ 899 u64 fence_context; 900 unsigned num_rings; 901 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 902 bool ib_pool_ready; 903 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 904 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 905 906 /* interrupts */ 907 struct amdgpu_irq irq; 908 909 /* powerplay */ 910 struct amd_powerplay powerplay; 911 bool pp_force_state_enabled; 912 913 /* smu */ 914 struct smu_context smu; 915 916 /* dpm */ 917 struct amdgpu_pm pm; 918 u32 cg_flags; 919 u32 pg_flags; 920 921 /* nbio */ 922 struct amdgpu_nbio nbio; 923 924 /* smuio */ 925 struct amdgpu_smuio smuio; 926 927 /* mmhub */ 928 struct amdgpu_mmhub mmhub; 929 930 /* gfxhub */ 931 struct amdgpu_gfxhub gfxhub; 932 933 /* gfx */ 934 struct amdgpu_gfx gfx; 935 936 /* sdma */ 937 struct amdgpu_sdma sdma; 938 939 /* uvd */ 940 struct amdgpu_uvd uvd; 941 942 /* vce */ 943 struct amdgpu_vce vce; 944 945 /* vcn */ 946 struct amdgpu_vcn vcn; 947 948 /* jpeg */ 949 struct amdgpu_jpeg jpeg; 950 951 /* firmwares */ 952 struct amdgpu_firmware firmware; 953 954 /* PSP */ 955 struct psp_context psp; 956 957 /* GDS */ 958 struct amdgpu_gds gds; 959 960 /* KFD */ 961 struct amdgpu_kfd_dev kfd; 962 963 /* UMC */ 964 struct amdgpu_umc umc; 965 966 /* display related functionality */ 967 struct amdgpu_display_manager dm; 968 969 /* mes */ 970 bool enable_mes; 971 struct amdgpu_mes mes; 972 973 /* df */ 974 struct amdgpu_df df; 975 976 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 977 int num_ip_blocks; 978 struct mutex mn_lock; 979 DECLARE_HASHTABLE(mn_hash, 7); 980 981 /* tracking pinned memory */ 982 atomic64_t vram_pin_size; 983 atomic64_t visible_pin_size; 984 atomic64_t gart_pin_size; 985 986 /* soc15 register offset based on ip, instance and segment */ 987 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 988 989 /* delayed work_func for deferring clockgating during resume */ 990 struct delayed_work delayed_init_work; 991 992 struct amdgpu_virt virt; 993 994 /* link all shadow bo */ 995 struct list_head shadow_list; 996 struct mutex shadow_list_lock; 997 998 /* record hw reset is performed */ 999 bool has_hw_reset; 1000 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1001 1002 /* s3/s4 mask */ 1003 bool in_suspend; 1004 bool in_hibernate; 1005 1006 atomic_t in_gpu_reset; 1007 enum pp_mp1_state mp1_state; 1008 struct rw_semaphore reset_sem; 1009 struct amdgpu_doorbell_index doorbell_index; 1010 1011 struct mutex notifier_lock; 1012 1013 int asic_reset_res; 1014 struct work_struct xgmi_reset_work; 1015 1016 long gfx_timeout; 1017 long sdma_timeout; 1018 long video_timeout; 1019 long compute_timeout; 1020 1021 uint64_t unique_id; 1022 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1023 1024 /* enable runtime pm on the device */ 1025 bool runpm; 1026 bool in_runpm; 1027 bool has_pr3; 1028 1029 bool pm_sysfs_en; 1030 bool ucode_sysfs_en; 1031 1032 /* Chip product information */ 1033 char product_number[16]; 1034 char product_name[32]; 1035 char serial[20]; 1036 1037 struct amdgpu_autodump autodump; 1038 1039 atomic_t throttling_logging_enabled; 1040 struct ratelimit_state throttling_logging_rs; 1041 uint32_t ras_features; 1042 1043 bool in_pci_err_recovery; 1044 struct pci_saved_state *pci_state; 1045 }; 1046 1047 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1048 { 1049 return container_of(ddev, struct amdgpu_device, ddev); 1050 } 1051 1052 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1053 { 1054 return &adev->ddev; 1055 } 1056 1057 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1058 { 1059 return container_of(bdev, struct amdgpu_device, mman.bdev); 1060 } 1061 1062 int amdgpu_device_init(struct amdgpu_device *adev, 1063 uint32_t flags); 1064 void amdgpu_device_fini(struct amdgpu_device *adev); 1065 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1066 1067 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1068 uint32_t *buf, size_t size, bool write); 1069 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1070 uint32_t reg, uint32_t acc_flags); 1071 void amdgpu_device_wreg(struct amdgpu_device *adev, 1072 uint32_t reg, uint32_t v, 1073 uint32_t acc_flags); 1074 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1075 uint32_t reg, uint32_t v); 1076 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1077 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1078 1079 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1080 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1081 1082 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1083 u32 pcie_index, u32 pcie_data, 1084 u32 reg_addr); 1085 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1086 u32 pcie_index, u32 pcie_data, 1087 u32 reg_addr); 1088 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1089 u32 pcie_index, u32 pcie_data, 1090 u32 reg_addr, u32 reg_data); 1091 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1092 u32 pcie_index, u32 pcie_data, 1093 u32 reg_addr, u64 reg_data); 1094 1095 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1096 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1097 1098 int emu_soc_asic_init(struct amdgpu_device *adev); 1099 1100 /* 1101 * Registers read & write functions. 1102 */ 1103 #define AMDGPU_REGS_NO_KIQ (1<<1) 1104 1105 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1106 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1107 1108 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1109 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1110 1111 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1112 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1113 1114 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1115 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1116 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1117 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1118 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1119 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1120 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1121 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1122 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1123 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1124 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1125 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1126 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1127 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1128 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1129 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1130 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1131 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1132 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1133 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1134 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1135 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1136 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1137 #define WREG32_P(reg, val, mask) \ 1138 do { \ 1139 uint32_t tmp_ = RREG32(reg); \ 1140 tmp_ &= (mask); \ 1141 tmp_ |= ((val) & ~(mask)); \ 1142 WREG32(reg, tmp_); \ 1143 } while (0) 1144 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1145 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1146 #define WREG32_PLL_P(reg, val, mask) \ 1147 do { \ 1148 uint32_t tmp_ = RREG32_PLL(reg); \ 1149 tmp_ &= (mask); \ 1150 tmp_ |= ((val) & ~(mask)); \ 1151 WREG32_PLL(reg, tmp_); \ 1152 } while (0) 1153 1154 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1155 do { \ 1156 u32 tmp = RREG32_SMC(_Reg); \ 1157 tmp &= (_Mask); \ 1158 tmp |= ((_Val) & ~(_Mask)); \ 1159 WREG32_SMC(_Reg, tmp); \ 1160 } while (0) 1161 1162 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1163 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1164 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1165 1166 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1167 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1168 1169 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1170 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1171 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1172 1173 #define REG_GET_FIELD(value, reg, field) \ 1174 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1175 1176 #define WREG32_FIELD(reg, field, val) \ 1177 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1178 1179 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1180 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1181 1182 /* 1183 * BIOS helpers. 1184 */ 1185 #define RBIOS8(i) (adev->bios[i]) 1186 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1187 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1188 1189 /* 1190 * ASICs macro. 1191 */ 1192 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1193 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1194 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1195 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1196 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1197 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1198 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1199 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1200 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1201 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1202 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1203 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1204 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1205 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1206 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1207 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1208 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1209 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1210 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1211 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1212 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1213 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1214 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1215 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1216 1217 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1218 1219 /* Common functions */ 1220 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1221 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1222 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1223 struct amdgpu_job* job); 1224 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1225 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1226 1227 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1228 u64 num_vis_bytes); 1229 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1230 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1231 const u32 *registers, 1232 const u32 array_size); 1233 1234 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1235 bool amdgpu_device_supports_boco(struct drm_device *dev); 1236 bool amdgpu_device_supports_baco(struct drm_device *dev); 1237 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1238 struct amdgpu_device *peer_adev); 1239 int amdgpu_device_baco_enter(struct drm_device *dev); 1240 int amdgpu_device_baco_exit(struct drm_device *dev); 1241 1242 /* atpx handler */ 1243 #if defined(CONFIG_VGA_SWITCHEROO) 1244 void amdgpu_register_atpx_handler(void); 1245 void amdgpu_unregister_atpx_handler(void); 1246 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1247 bool amdgpu_is_atpx_hybrid(void); 1248 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1249 bool amdgpu_has_atpx(void); 1250 #else 1251 static inline void amdgpu_register_atpx_handler(void) {} 1252 static inline void amdgpu_unregister_atpx_handler(void) {} 1253 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1254 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1255 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1256 static inline bool amdgpu_has_atpx(void) { return false; } 1257 #endif 1258 1259 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1260 void *amdgpu_atpx_get_dhandle(void); 1261 #else 1262 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1263 #endif 1264 1265 /* 1266 * KMS 1267 */ 1268 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1269 extern const int amdgpu_max_kms_ioctl; 1270 1271 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1272 void amdgpu_driver_unload_kms(struct drm_device *dev); 1273 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1274 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1275 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1276 struct drm_file *file_priv); 1277 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1278 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1279 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1280 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1281 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1282 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1283 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1284 unsigned long arg); 1285 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1286 struct drm_file *filp); 1287 1288 /* 1289 * functions used by amdgpu_encoder.c 1290 */ 1291 struct amdgpu_afmt_acr { 1292 u32 clock; 1293 1294 int n_32khz; 1295 int cts_32khz; 1296 1297 int n_44_1khz; 1298 int cts_44_1khz; 1299 1300 int n_48khz; 1301 int cts_48khz; 1302 1303 }; 1304 1305 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1306 1307 /* amdgpu_acpi.c */ 1308 #if defined(CONFIG_ACPI) 1309 int amdgpu_acpi_init(struct amdgpu_device *adev); 1310 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1311 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1312 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1313 u8 perf_req, bool advertise); 1314 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1315 1316 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1317 struct amdgpu_dm_backlight_caps *caps); 1318 bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev); 1319 #else 1320 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1321 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1322 static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; } 1323 #endif 1324 1325 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1326 uint64_t addr, struct amdgpu_bo **bo, 1327 struct amdgpu_bo_va_mapping **mapping); 1328 1329 #if defined(CONFIG_DRM_AMD_DC) 1330 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1331 #else 1332 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1333 #endif 1334 1335 1336 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1337 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1338 1339 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1340 pci_channel_state_t state); 1341 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1342 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1343 void amdgpu_pci_resume(struct pci_dev *pdev); 1344 1345 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1346 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1347 1348 #include "amdgpu_object.h" 1349 1350 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1351 { 1352 return adev->gmc.tmz_enabled; 1353 } 1354 1355 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1356 { 1357 return atomic_read(&adev->in_gpu_reset); 1358 } 1359 #endif 1360