1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_gmc.h" 83 #include "amdgpu_gfx.h" 84 #include "amdgpu_sdma.h" 85 #include "amdgpu_lsdma.h" 86 #include "amdgpu_nbio.h" 87 #include "amdgpu_hdp.h" 88 #include "amdgpu_dm.h" 89 #include "amdgpu_virt.h" 90 #include "amdgpu_csa.h" 91 #include "amdgpu_mes_ctx.h" 92 #include "amdgpu_gart.h" 93 #include "amdgpu_debugfs.h" 94 #include "amdgpu_job.h" 95 #include "amdgpu_bo_list.h" 96 #include "amdgpu_gem.h" 97 #include "amdgpu_doorbell.h" 98 #include "amdgpu_amdkfd.h" 99 #include "amdgpu_discovery.h" 100 #include "amdgpu_mes.h" 101 #include "amdgpu_umc.h" 102 #include "amdgpu_mmhub.h" 103 #include "amdgpu_gfxhub.h" 104 #include "amdgpu_df.h" 105 #include "amdgpu_smuio.h" 106 #include "amdgpu_fdinfo.h" 107 #include "amdgpu_mca.h" 108 #include "amdgpu_ras.h" 109 #include "amdgpu_xcp.h" 110 111 #define MAX_GPU_INSTANCE 64 112 113 struct amdgpu_gpu_instance 114 { 115 struct amdgpu_device *adev; 116 int mgpu_fan_enabled; 117 }; 118 119 struct amdgpu_mgpu_info 120 { 121 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 122 struct mutex mutex; 123 uint32_t num_gpu; 124 uint32_t num_dgpu; 125 uint32_t num_apu; 126 127 /* delayed reset_func for XGMI configuration if necessary */ 128 struct delayed_work delayed_reset_work; 129 bool pending_reset; 130 }; 131 132 enum amdgpu_ss { 133 AMDGPU_SS_DRV_LOAD, 134 AMDGPU_SS_DEV_D0, 135 AMDGPU_SS_DEV_D3, 136 AMDGPU_SS_DRV_UNLOAD 137 }; 138 139 struct amdgpu_watchdog_timer 140 { 141 bool timeout_fatal_disable; 142 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 143 }; 144 145 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 146 147 /* 148 * Modules parameters. 149 */ 150 extern int amdgpu_modeset; 151 extern unsigned int amdgpu_vram_limit; 152 extern int amdgpu_vis_vram_limit; 153 extern int amdgpu_gart_size; 154 extern int amdgpu_gtt_size; 155 extern int amdgpu_moverate; 156 extern int amdgpu_audio; 157 extern int amdgpu_disp_priority; 158 extern int amdgpu_hw_i2c; 159 extern int amdgpu_pcie_gen2; 160 extern int amdgpu_msi; 161 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 162 extern int amdgpu_dpm; 163 extern int amdgpu_fw_load_type; 164 extern int amdgpu_aspm; 165 extern int amdgpu_runtime_pm; 166 extern uint amdgpu_ip_block_mask; 167 extern int amdgpu_bapm; 168 extern int amdgpu_deep_color; 169 extern int amdgpu_vm_size; 170 extern int amdgpu_vm_block_size; 171 extern int amdgpu_vm_fragment_size; 172 extern int amdgpu_vm_fault_stop; 173 extern int amdgpu_vm_debug; 174 extern int amdgpu_vm_update_mode; 175 extern int amdgpu_exp_hw_support; 176 extern int amdgpu_dc; 177 extern int amdgpu_sched_jobs; 178 extern int amdgpu_sched_hw_submission; 179 extern uint amdgpu_pcie_gen_cap; 180 extern uint amdgpu_pcie_lane_cap; 181 extern u64 amdgpu_cg_mask; 182 extern uint amdgpu_pg_mask; 183 extern uint amdgpu_sdma_phase_quantum; 184 extern char *amdgpu_disable_cu; 185 extern char *amdgpu_virtual_display; 186 extern uint amdgpu_pp_feature_mask; 187 extern uint amdgpu_force_long_training; 188 extern int amdgpu_lbpw; 189 extern int amdgpu_compute_multipipe; 190 extern int amdgpu_gpu_recovery; 191 extern int amdgpu_emu_mode; 192 extern uint amdgpu_smu_memory_pool_size; 193 extern int amdgpu_smu_pptable_id; 194 extern uint amdgpu_dc_feature_mask; 195 extern uint amdgpu_freesync_vid_mode; 196 extern uint amdgpu_dc_debug_mask; 197 extern uint amdgpu_dc_visual_confirm; 198 extern uint amdgpu_dm_abm_level; 199 extern int amdgpu_backlight; 200 extern struct amdgpu_mgpu_info mgpu_info; 201 extern int amdgpu_ras_enable; 202 extern uint amdgpu_ras_mask; 203 extern int amdgpu_bad_page_threshold; 204 extern bool amdgpu_ignore_bad_page_threshold; 205 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 206 extern int amdgpu_async_gfx_ring; 207 extern int amdgpu_mcbp; 208 extern int amdgpu_discovery; 209 extern int amdgpu_mes; 210 extern int amdgpu_mes_kiq; 211 extern int amdgpu_noretry; 212 extern int amdgpu_force_asic_type; 213 extern int amdgpu_smartshift_bias; 214 extern int amdgpu_use_xgmi_p2p; 215 extern int amdgpu_mtype_local; 216 extern bool enforce_isolation; 217 #ifdef CONFIG_HSA_AMD 218 extern int sched_policy; 219 extern bool debug_evictions; 220 extern bool no_system_mem_limit; 221 extern int halt_if_hws_hang; 222 #else 223 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 224 static const bool __maybe_unused debug_evictions; /* = false */ 225 static const bool __maybe_unused no_system_mem_limit; 226 static const int __maybe_unused halt_if_hws_hang; 227 #endif 228 #ifdef CONFIG_HSA_AMD_P2P 229 extern bool pcie_p2p; 230 #endif 231 232 extern int amdgpu_tmz; 233 extern int amdgpu_reset_method; 234 235 #ifdef CONFIG_DRM_AMDGPU_SI 236 extern int amdgpu_si_support; 237 #endif 238 #ifdef CONFIG_DRM_AMDGPU_CIK 239 extern int amdgpu_cik_support; 240 #endif 241 extern int amdgpu_num_kcq; 242 243 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 244 extern int amdgpu_vcnfw_log; 245 extern int amdgpu_sg_display; 246 247 extern int amdgpu_user_partt_mode; 248 249 #define AMDGPU_VM_MAX_NUM_CTX 4096 250 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 251 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 252 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 253 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 254 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 255 #define AMDGPUFB_CONN_LIMIT 4 256 #define AMDGPU_BIOS_NUM_SCRATCH 16 257 258 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 259 260 /* hard reset data */ 261 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 262 263 /* reset flags */ 264 #define AMDGPU_RESET_GFX (1 << 0) 265 #define AMDGPU_RESET_COMPUTE (1 << 1) 266 #define AMDGPU_RESET_DMA (1 << 2) 267 #define AMDGPU_RESET_CP (1 << 3) 268 #define AMDGPU_RESET_GRBM (1 << 4) 269 #define AMDGPU_RESET_DMA1 (1 << 5) 270 #define AMDGPU_RESET_RLC (1 << 6) 271 #define AMDGPU_RESET_SEM (1 << 7) 272 #define AMDGPU_RESET_IH (1 << 8) 273 #define AMDGPU_RESET_VMC (1 << 9) 274 #define AMDGPU_RESET_MC (1 << 10) 275 #define AMDGPU_RESET_DISPLAY (1 << 11) 276 #define AMDGPU_RESET_UVD (1 << 12) 277 #define AMDGPU_RESET_VCE (1 << 13) 278 #define AMDGPU_RESET_VCE1 (1 << 14) 279 280 /* max cursor sizes (in pixels) */ 281 #define CIK_CURSOR_WIDTH 128 282 #define CIK_CURSOR_HEIGHT 128 283 284 /* smart shift bias level limits */ 285 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 286 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 287 288 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 289 #define AMDGPU_SWCTF_EXTRA_DELAY 50 290 291 struct amdgpu_xcp_mgr; 292 struct amdgpu_device; 293 struct amdgpu_irq_src; 294 struct amdgpu_fpriv; 295 struct amdgpu_bo_va_mapping; 296 struct kfd_vm_fault_info; 297 struct amdgpu_hive_info; 298 struct amdgpu_reset_context; 299 struct amdgpu_reset_control; 300 301 enum amdgpu_cp_irq { 302 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 303 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 304 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 305 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 306 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 307 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 308 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 309 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 310 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 311 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 312 313 AMDGPU_CP_IRQ_LAST 314 }; 315 316 enum amdgpu_thermal_irq { 317 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 318 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 319 320 AMDGPU_THERMAL_IRQ_LAST 321 }; 322 323 enum amdgpu_kiq_irq { 324 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 325 AMDGPU_CP_KIQ_IRQ_LAST 326 }; 327 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 328 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 329 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 330 #define MAX_KIQ_REG_TRY 1000 331 332 int amdgpu_device_ip_set_clockgating_state(void *dev, 333 enum amd_ip_block_type block_type, 334 enum amd_clockgating_state state); 335 int amdgpu_device_ip_set_powergating_state(void *dev, 336 enum amd_ip_block_type block_type, 337 enum amd_powergating_state state); 338 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 339 u64 *flags); 340 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 341 enum amd_ip_block_type block_type); 342 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 343 enum amd_ip_block_type block_type); 344 345 #define AMDGPU_MAX_IP_NUM 16 346 347 struct amdgpu_ip_block_status { 348 bool valid; 349 bool sw; 350 bool hw; 351 bool late_initialized; 352 bool hang; 353 }; 354 355 struct amdgpu_ip_block_version { 356 const enum amd_ip_block_type type; 357 const u32 major; 358 const u32 minor; 359 const u32 rev; 360 const struct amd_ip_funcs *funcs; 361 }; 362 363 #define HW_REV(_Major, _Minor, _Rev) \ 364 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 365 366 struct amdgpu_ip_block { 367 struct amdgpu_ip_block_status status; 368 const struct amdgpu_ip_block_version *version; 369 }; 370 371 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 372 enum amd_ip_block_type type, 373 u32 major, u32 minor); 374 375 struct amdgpu_ip_block * 376 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 377 enum amd_ip_block_type type); 378 379 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 380 const struct amdgpu_ip_block_version *ip_block_version); 381 382 /* 383 * BIOS. 384 */ 385 bool amdgpu_get_bios(struct amdgpu_device *adev); 386 bool amdgpu_read_bios(struct amdgpu_device *adev); 387 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 388 u8 *bios, u32 length_bytes); 389 /* 390 * Clocks 391 */ 392 393 #define AMDGPU_MAX_PPLL 3 394 395 struct amdgpu_clock { 396 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 397 struct amdgpu_pll spll; 398 struct amdgpu_pll mpll; 399 /* 10 Khz units */ 400 uint32_t default_mclk; 401 uint32_t default_sclk; 402 uint32_t default_dispclk; 403 uint32_t current_dispclk; 404 uint32_t dp_extclk; 405 uint32_t max_pixel_clock; 406 }; 407 408 /* sub-allocation manager, it has to be protected by another lock. 409 * By conception this is an helper for other part of the driver 410 * like the indirect buffer or semaphore, which both have their 411 * locking. 412 * 413 * Principe is simple, we keep a list of sub allocation in offset 414 * order (first entry has offset == 0, last entry has the highest 415 * offset). 416 * 417 * When allocating new object we first check if there is room at 418 * the end total_size - (last_object_offset + last_object_size) >= 419 * alloc_size. If so we allocate new object there. 420 * 421 * When there is not enough room at the end, we start waiting for 422 * each sub object until we reach object_offset+object_size >= 423 * alloc_size, this object then become the sub object we return. 424 * 425 * Alignment can't be bigger than page size. 426 * 427 * Hole are not considered for allocation to keep things simple. 428 * Assumption is that there won't be hole (all object on same 429 * alignment). 430 */ 431 432 struct amdgpu_sa_manager { 433 struct drm_suballoc_manager base; 434 struct amdgpu_bo *bo; 435 uint64_t gpu_addr; 436 void *cpu_ptr; 437 }; 438 439 int amdgpu_fence_slab_init(void); 440 void amdgpu_fence_slab_fini(void); 441 442 /* 443 * IRQS. 444 */ 445 446 struct amdgpu_flip_work { 447 struct delayed_work flip_work; 448 struct work_struct unpin_work; 449 struct amdgpu_device *adev; 450 int crtc_id; 451 u32 target_vblank; 452 uint64_t base; 453 struct drm_pending_vblank_event *event; 454 struct amdgpu_bo *old_abo; 455 unsigned shared_count; 456 struct dma_fence **shared; 457 struct dma_fence_cb cb; 458 bool async; 459 }; 460 461 462 /* 463 * file private structure 464 */ 465 466 struct amdgpu_fpriv { 467 struct amdgpu_vm vm; 468 struct amdgpu_bo_va *prt_va; 469 struct amdgpu_bo_va *csa_va; 470 struct mutex bo_list_lock; 471 struct idr bo_list_handles; 472 struct amdgpu_ctx_mgr ctx_mgr; 473 /** GPU partition selection */ 474 uint32_t xcp_id; 475 }; 476 477 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 478 479 /* 480 * Writeback 481 */ 482 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 483 484 struct amdgpu_wb { 485 struct amdgpu_bo *wb_obj; 486 volatile uint32_t *wb; 487 uint64_t gpu_addr; 488 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 489 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 490 }; 491 492 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 493 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 494 495 /* 496 * Benchmarking 497 */ 498 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 499 500 /* 501 * ASIC specific register table accessible by UMD 502 */ 503 struct amdgpu_allowed_register_entry { 504 uint32_t reg_offset; 505 bool grbm_indexed; 506 }; 507 508 enum amd_reset_method { 509 AMD_RESET_METHOD_NONE = -1, 510 AMD_RESET_METHOD_LEGACY = 0, 511 AMD_RESET_METHOD_MODE0, 512 AMD_RESET_METHOD_MODE1, 513 AMD_RESET_METHOD_MODE2, 514 AMD_RESET_METHOD_BACO, 515 AMD_RESET_METHOD_PCI, 516 }; 517 518 struct amdgpu_video_codec_info { 519 u32 codec_type; 520 u32 max_width; 521 u32 max_height; 522 u32 max_pixels_per_frame; 523 u32 max_level; 524 }; 525 526 #define codec_info_build(type, width, height, level) \ 527 .codec_type = type,\ 528 .max_width = width,\ 529 .max_height = height,\ 530 .max_pixels_per_frame = height * width,\ 531 .max_level = level, 532 533 struct amdgpu_video_codecs { 534 const u32 codec_count; 535 const struct amdgpu_video_codec_info *codec_array; 536 }; 537 538 /* 539 * ASIC specific functions. 540 */ 541 struct amdgpu_asic_funcs { 542 bool (*read_disabled_bios)(struct amdgpu_device *adev); 543 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 544 u8 *bios, u32 length_bytes); 545 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 546 u32 sh_num, u32 reg_offset, u32 *value); 547 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 548 int (*reset)(struct amdgpu_device *adev); 549 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 550 /* get the reference clock */ 551 u32 (*get_xclk)(struct amdgpu_device *adev); 552 /* MM block clocks */ 553 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 554 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 555 /* static power management */ 556 int (*get_pcie_lanes)(struct amdgpu_device *adev); 557 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 558 /* get config memsize register */ 559 u32 (*get_config_memsize)(struct amdgpu_device *adev); 560 /* flush hdp write queue */ 561 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 562 /* invalidate hdp read cache */ 563 void (*invalidate_hdp)(struct amdgpu_device *adev, 564 struct amdgpu_ring *ring); 565 /* check if the asic needs a full reset of if soft reset will work */ 566 bool (*need_full_reset)(struct amdgpu_device *adev); 567 /* initialize doorbell layout for specific asic*/ 568 void (*init_doorbell_index)(struct amdgpu_device *adev); 569 /* PCIe bandwidth usage */ 570 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 571 uint64_t *count1); 572 /* do we need to reset the asic at init time (e.g., kexec) */ 573 bool (*need_reset_on_init)(struct amdgpu_device *adev); 574 /* PCIe replay counter */ 575 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 576 /* device supports BACO */ 577 bool (*supports_baco)(struct amdgpu_device *adev); 578 /* pre asic_init quirks */ 579 void (*pre_asic_init)(struct amdgpu_device *adev); 580 /* enter/exit umd stable pstate */ 581 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 582 /* query video codecs */ 583 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 584 const struct amdgpu_video_codecs **codecs); 585 /* encode "> 32bits" smn addressing */ 586 u64 (*encode_ext_smn_addressing)(int ext_id); 587 }; 588 589 /* 590 * IOCTL. 591 */ 592 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 593 struct drm_file *filp); 594 595 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 596 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 597 struct drm_file *filp); 598 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 599 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 600 struct drm_file *filp); 601 602 /* VRAM scratch page for HDP bug, default vram page */ 603 struct amdgpu_mem_scratch { 604 struct amdgpu_bo *robj; 605 volatile uint32_t *ptr; 606 u64 gpu_addr; 607 }; 608 609 /* 610 * CGS 611 */ 612 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 613 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 614 615 /* 616 * Core structure, functions and helpers. 617 */ 618 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 619 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 620 621 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 622 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 623 624 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 625 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 626 627 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 628 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 629 630 struct amdgpu_mmio_remap { 631 u32 reg_offset; 632 resource_size_t bus_addr; 633 }; 634 635 /* Define the HW IP blocks will be used in driver , add more if necessary */ 636 enum amd_hw_ip_block_type { 637 GC_HWIP = 1, 638 HDP_HWIP, 639 SDMA0_HWIP, 640 SDMA1_HWIP, 641 SDMA2_HWIP, 642 SDMA3_HWIP, 643 SDMA4_HWIP, 644 SDMA5_HWIP, 645 SDMA6_HWIP, 646 SDMA7_HWIP, 647 LSDMA_HWIP, 648 MMHUB_HWIP, 649 ATHUB_HWIP, 650 NBIO_HWIP, 651 MP0_HWIP, 652 MP1_HWIP, 653 UVD_HWIP, 654 VCN_HWIP = UVD_HWIP, 655 JPEG_HWIP = VCN_HWIP, 656 VCN1_HWIP, 657 VCE_HWIP, 658 DF_HWIP, 659 DCE_HWIP, 660 OSSSYS_HWIP, 661 SMUIO_HWIP, 662 PWR_HWIP, 663 NBIF_HWIP, 664 THM_HWIP, 665 CLK_HWIP, 666 UMC_HWIP, 667 RSMU_HWIP, 668 XGMI_HWIP, 669 DCI_HWIP, 670 PCIE_HWIP, 671 MAX_HWIP 672 }; 673 674 #define HWIP_MAX_INSTANCE 44 675 676 #define HW_ID_MAX 300 677 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 678 #define IP_VERSION_MAJ(ver) ((ver) >> 16) 679 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF) 680 #define IP_VERSION_REV(ver) ((ver) & 0xFF) 681 682 struct amdgpu_ip_map_info { 683 /* Map of logical to actual dev instances/mask */ 684 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 685 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 686 enum amd_hw_ip_block_type block, 687 int8_t inst); 688 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 689 enum amd_hw_ip_block_type block, 690 uint32_t mask); 691 }; 692 693 struct amd_powerplay { 694 void *pp_handle; 695 const struct amd_pm_funcs *pp_funcs; 696 }; 697 698 struct ip_discovery_top; 699 700 /* polaris10 kickers */ 701 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 702 ((rid == 0xE3) || \ 703 (rid == 0xE4) || \ 704 (rid == 0xE5) || \ 705 (rid == 0xE7) || \ 706 (rid == 0xEF))) || \ 707 ((did == 0x6FDF) && \ 708 ((rid == 0xE7) || \ 709 (rid == 0xEF) || \ 710 (rid == 0xFF)))) 711 712 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 713 ((rid == 0xE1) || \ 714 (rid == 0xF7))) 715 716 /* polaris11 kickers */ 717 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 718 ((rid == 0xE0) || \ 719 (rid == 0xE5))) || \ 720 ((did == 0x67FF) && \ 721 ((rid == 0xCF) || \ 722 (rid == 0xEF) || \ 723 (rid == 0xFF)))) 724 725 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 726 ((rid == 0xE2))) 727 728 /* polaris12 kickers */ 729 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 730 ((rid == 0xC0) || \ 731 (rid == 0xC1) || \ 732 (rid == 0xC3) || \ 733 (rid == 0xC7))) || \ 734 ((did == 0x6981) && \ 735 ((rid == 0x00) || \ 736 (rid == 0x01) || \ 737 (rid == 0x10)))) 738 739 struct amdgpu_mqd_prop { 740 uint64_t mqd_gpu_addr; 741 uint64_t hqd_base_gpu_addr; 742 uint64_t rptr_gpu_addr; 743 uint64_t wptr_gpu_addr; 744 uint32_t queue_size; 745 bool use_doorbell; 746 uint32_t doorbell_index; 747 uint64_t eop_gpu_addr; 748 uint32_t hqd_pipe_priority; 749 uint32_t hqd_queue_priority; 750 bool hqd_active; 751 }; 752 753 struct amdgpu_mqd { 754 unsigned mqd_size; 755 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 756 struct amdgpu_mqd_prop *p); 757 }; 758 759 #define AMDGPU_RESET_MAGIC_NUM 64 760 #define AMDGPU_MAX_DF_PERFMONS 4 761 #define AMDGPU_PRODUCT_NAME_LEN 64 762 struct amdgpu_reset_domain; 763 764 /* 765 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 766 */ 767 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 768 769 struct amdgpu_device { 770 struct device *dev; 771 struct pci_dev *pdev; 772 struct drm_device ddev; 773 774 #ifdef CONFIG_DRM_AMD_ACP 775 struct amdgpu_acp acp; 776 #endif 777 struct amdgpu_hive_info *hive; 778 struct amdgpu_xcp_mgr *xcp_mgr; 779 /* ASIC */ 780 enum amd_asic_type asic_type; 781 uint32_t family; 782 uint32_t rev_id; 783 uint32_t external_rev_id; 784 unsigned long flags; 785 unsigned long apu_flags; 786 int usec_timeout; 787 const struct amdgpu_asic_funcs *asic_funcs; 788 bool shutdown; 789 bool need_swiotlb; 790 bool accel_working; 791 struct notifier_block acpi_nb; 792 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 793 struct debugfs_blob_wrapper debugfs_vbios_blob; 794 struct debugfs_blob_wrapper debugfs_discovery_blob; 795 struct mutex srbm_mutex; 796 /* GRBM index mutex. Protects concurrent access to GRBM index */ 797 struct mutex grbm_idx_mutex; 798 struct dev_pm_domain vga_pm_domain; 799 bool have_disp_power_ref; 800 bool have_atomics_support; 801 802 /* BIOS */ 803 bool is_atom_fw; 804 uint8_t *bios; 805 uint32_t bios_size; 806 uint32_t bios_scratch_reg_offset; 807 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 808 809 /* Register/doorbell mmio */ 810 resource_size_t rmmio_base; 811 resource_size_t rmmio_size; 812 void __iomem *rmmio; 813 /* protects concurrent MM_INDEX/DATA based register access */ 814 spinlock_t mmio_idx_lock; 815 struct amdgpu_mmio_remap rmmio_remap; 816 /* protects concurrent SMC based register access */ 817 spinlock_t smc_idx_lock; 818 amdgpu_rreg_t smc_rreg; 819 amdgpu_wreg_t smc_wreg; 820 /* protects concurrent PCIE register access */ 821 spinlock_t pcie_idx_lock; 822 amdgpu_rreg_t pcie_rreg; 823 amdgpu_wreg_t pcie_wreg; 824 amdgpu_rreg_t pciep_rreg; 825 amdgpu_wreg_t pciep_wreg; 826 amdgpu_rreg_ext_t pcie_rreg_ext; 827 amdgpu_wreg_ext_t pcie_wreg_ext; 828 amdgpu_rreg64_t pcie_rreg64; 829 amdgpu_wreg64_t pcie_wreg64; 830 /* protects concurrent UVD register access */ 831 spinlock_t uvd_ctx_idx_lock; 832 amdgpu_rreg_t uvd_ctx_rreg; 833 amdgpu_wreg_t uvd_ctx_wreg; 834 /* protects concurrent DIDT register access */ 835 spinlock_t didt_idx_lock; 836 amdgpu_rreg_t didt_rreg; 837 amdgpu_wreg_t didt_wreg; 838 /* protects concurrent gc_cac register access */ 839 spinlock_t gc_cac_idx_lock; 840 amdgpu_rreg_t gc_cac_rreg; 841 amdgpu_wreg_t gc_cac_wreg; 842 /* protects concurrent se_cac register access */ 843 spinlock_t se_cac_idx_lock; 844 amdgpu_rreg_t se_cac_rreg; 845 amdgpu_wreg_t se_cac_wreg; 846 /* protects concurrent ENDPOINT (audio) register access */ 847 spinlock_t audio_endpt_idx_lock; 848 amdgpu_block_rreg_t audio_endpt_rreg; 849 amdgpu_block_wreg_t audio_endpt_wreg; 850 struct amdgpu_doorbell doorbell; 851 852 /* clock/pll info */ 853 struct amdgpu_clock clock; 854 855 /* MC */ 856 struct amdgpu_gmc gmc; 857 struct amdgpu_gart gart; 858 dma_addr_t dummy_page_addr; 859 struct amdgpu_vm_manager vm_manager; 860 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 861 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 862 863 /* memory management */ 864 struct amdgpu_mman mman; 865 struct amdgpu_mem_scratch mem_scratch; 866 struct amdgpu_wb wb; 867 atomic64_t num_bytes_moved; 868 atomic64_t num_evictions; 869 atomic64_t num_vram_cpu_page_faults; 870 atomic_t gpu_reset_counter; 871 atomic_t vram_lost_counter; 872 873 /* data for buffer migration throttling */ 874 struct { 875 spinlock_t lock; 876 s64 last_update_us; 877 s64 accum_us; /* accumulated microseconds */ 878 s64 accum_us_vis; /* for visible VRAM */ 879 u32 log2_max_MBps; 880 } mm_stats; 881 882 /* display */ 883 bool enable_virtual_display; 884 struct amdgpu_vkms_output *amdgpu_vkms_output; 885 struct amdgpu_mode_info mode_info; 886 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 887 struct delayed_work hotplug_work; 888 struct amdgpu_irq_src crtc_irq; 889 struct amdgpu_irq_src vline0_irq; 890 struct amdgpu_irq_src vupdate_irq; 891 struct amdgpu_irq_src pageflip_irq; 892 struct amdgpu_irq_src hpd_irq; 893 struct amdgpu_irq_src dmub_trace_irq; 894 struct amdgpu_irq_src dmub_outbox_irq; 895 896 /* rings */ 897 u64 fence_context; 898 unsigned num_rings; 899 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 900 struct dma_fence __rcu *gang_submit; 901 bool ib_pool_ready; 902 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 903 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 904 905 /* interrupts */ 906 struct amdgpu_irq irq; 907 908 /* powerplay */ 909 struct amd_powerplay powerplay; 910 struct amdgpu_pm pm; 911 u64 cg_flags; 912 u32 pg_flags; 913 914 /* nbio */ 915 struct amdgpu_nbio nbio; 916 917 /* hdp */ 918 struct amdgpu_hdp hdp; 919 920 /* smuio */ 921 struct amdgpu_smuio smuio; 922 923 /* mmhub */ 924 struct amdgpu_mmhub mmhub; 925 926 /* gfxhub */ 927 struct amdgpu_gfxhub gfxhub; 928 929 /* gfx */ 930 struct amdgpu_gfx gfx; 931 932 /* sdma */ 933 struct amdgpu_sdma sdma; 934 935 /* lsdma */ 936 struct amdgpu_lsdma lsdma; 937 938 /* uvd */ 939 struct amdgpu_uvd uvd; 940 941 /* vce */ 942 struct amdgpu_vce vce; 943 944 /* vcn */ 945 struct amdgpu_vcn vcn; 946 947 /* jpeg */ 948 struct amdgpu_jpeg jpeg; 949 950 /* firmwares */ 951 struct amdgpu_firmware firmware; 952 953 /* PSP */ 954 struct psp_context psp; 955 956 /* GDS */ 957 struct amdgpu_gds gds; 958 959 /* KFD */ 960 struct amdgpu_kfd_dev kfd; 961 962 /* UMC */ 963 struct amdgpu_umc umc; 964 965 /* display related functionality */ 966 struct amdgpu_display_manager dm; 967 968 /* mes */ 969 bool enable_mes; 970 bool enable_mes_kiq; 971 struct amdgpu_mes mes; 972 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 973 974 /* df */ 975 struct amdgpu_df df; 976 977 /* MCA */ 978 struct amdgpu_mca mca; 979 980 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 981 uint32_t harvest_ip_mask; 982 int num_ip_blocks; 983 struct mutex mn_lock; 984 DECLARE_HASHTABLE(mn_hash, 7); 985 986 /* tracking pinned memory */ 987 atomic64_t vram_pin_size; 988 atomic64_t visible_pin_size; 989 atomic64_t gart_pin_size; 990 991 /* soc15 register offset based on ip, instance and segment */ 992 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 993 struct amdgpu_ip_map_info ip_map; 994 995 /* delayed work_func for deferring clockgating during resume */ 996 struct delayed_work delayed_init_work; 997 998 struct amdgpu_virt virt; 999 1000 /* link all shadow bo */ 1001 struct list_head shadow_list; 1002 struct mutex shadow_list_lock; 1003 1004 /* record hw reset is performed */ 1005 bool has_hw_reset; 1006 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1007 1008 /* s3/s4 mask */ 1009 bool in_suspend; 1010 bool in_s3; 1011 bool in_s4; 1012 bool in_s0ix; 1013 1014 enum pp_mp1_state mp1_state; 1015 struct amdgpu_doorbell_index doorbell_index; 1016 1017 struct mutex notifier_lock; 1018 1019 int asic_reset_res; 1020 struct work_struct xgmi_reset_work; 1021 struct list_head reset_list; 1022 1023 long gfx_timeout; 1024 long sdma_timeout; 1025 long video_timeout; 1026 long compute_timeout; 1027 1028 uint64_t unique_id; 1029 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1030 1031 /* enable runtime pm on the device */ 1032 bool in_runpm; 1033 bool has_pr3; 1034 1035 bool ucode_sysfs_en; 1036 bool psp_sysfs_en; 1037 1038 /* Chip product information */ 1039 char product_number[20]; 1040 char product_name[AMDGPU_PRODUCT_NAME_LEN]; 1041 char serial[20]; 1042 1043 atomic_t throttling_logging_enabled; 1044 struct ratelimit_state throttling_logging_rs; 1045 uint32_t ras_hw_enabled; 1046 uint32_t ras_enabled; 1047 1048 bool no_hw_access; 1049 struct pci_saved_state *pci_state; 1050 pci_channel_state_t pci_channel_state; 1051 1052 /* Track auto wait count on s_barrier settings */ 1053 bool barrier_has_auto_waitcnt; 1054 1055 struct amdgpu_reset_control *reset_cntl; 1056 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1057 1058 bool ram_is_direct_mapped; 1059 1060 struct list_head ras_list; 1061 1062 struct ip_discovery_top *ip_top; 1063 1064 struct amdgpu_reset_domain *reset_domain; 1065 1066 struct mutex benchmark_mutex; 1067 1068 /* reset dump register */ 1069 uint32_t *reset_dump_reg_list; 1070 uint32_t *reset_dump_reg_value; 1071 int num_regs; 1072 #ifdef CONFIG_DEV_COREDUMP 1073 struct amdgpu_task_info reset_task_info; 1074 bool reset_vram_lost; 1075 struct timespec64 reset_time; 1076 #endif 1077 1078 bool scpm_enabled; 1079 uint32_t scpm_status; 1080 1081 struct work_struct reset_work; 1082 1083 bool job_hang; 1084 bool dc_enabled; 1085 /* Mask of active clusters */ 1086 uint32_t aid_mask; 1087 }; 1088 1089 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1090 { 1091 return container_of(ddev, struct amdgpu_device, ddev); 1092 } 1093 1094 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1095 { 1096 return &adev->ddev; 1097 } 1098 1099 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1100 { 1101 return container_of(bdev, struct amdgpu_device, mman.bdev); 1102 } 1103 1104 int amdgpu_device_init(struct amdgpu_device *adev, 1105 uint32_t flags); 1106 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1107 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1108 1109 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1110 1111 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1112 void *buf, size_t size, bool write); 1113 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1114 void *buf, size_t size, bool write); 1115 1116 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1117 void *buf, size_t size, bool write); 1118 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1119 uint32_t inst, uint32_t reg_addr, char reg_name[], 1120 uint32_t expected_value, uint32_t mask); 1121 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1122 uint32_t reg, uint32_t acc_flags); 1123 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1124 u64 reg_addr); 1125 void amdgpu_device_wreg(struct amdgpu_device *adev, 1126 uint32_t reg, uint32_t v, 1127 uint32_t acc_flags); 1128 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1129 u64 reg_addr, u32 reg_data); 1130 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1131 uint32_t reg, uint32_t v); 1132 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1133 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1134 1135 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1136 u32 reg_addr); 1137 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1138 u32 reg_addr); 1139 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1140 u32 reg_addr, u32 reg_data); 1141 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1142 u32 reg_addr, u64 reg_data); 1143 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1144 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1145 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1146 1147 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1148 1149 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1150 struct amdgpu_reset_context *reset_context); 1151 1152 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1153 struct amdgpu_reset_context *reset_context); 1154 1155 int emu_soc_asic_init(struct amdgpu_device *adev); 1156 1157 /* 1158 * Registers read & write functions. 1159 */ 1160 #define AMDGPU_REGS_NO_KIQ (1<<1) 1161 #define AMDGPU_REGS_RLC (1<<2) 1162 1163 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1164 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1165 1166 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1167 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1168 1169 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1170 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1171 1172 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1173 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1174 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1175 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1176 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1177 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1178 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1179 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1180 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1181 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1182 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1183 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1184 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1185 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1186 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1187 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1188 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1189 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1190 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1191 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1192 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1193 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1194 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1195 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1196 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1197 #define WREG32_P(reg, val, mask) \ 1198 do { \ 1199 uint32_t tmp_ = RREG32(reg); \ 1200 tmp_ &= (mask); \ 1201 tmp_ |= ((val) & ~(mask)); \ 1202 WREG32(reg, tmp_); \ 1203 } while (0) 1204 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1205 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1206 #define WREG32_PLL_P(reg, val, mask) \ 1207 do { \ 1208 uint32_t tmp_ = RREG32_PLL(reg); \ 1209 tmp_ &= (mask); \ 1210 tmp_ |= ((val) & ~(mask)); \ 1211 WREG32_PLL(reg, tmp_); \ 1212 } while (0) 1213 1214 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1215 do { \ 1216 u32 tmp = RREG32_SMC(_Reg); \ 1217 tmp &= (_Mask); \ 1218 tmp |= ((_Val) & ~(_Mask)); \ 1219 WREG32_SMC(_Reg, tmp); \ 1220 } while (0) 1221 1222 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1223 1224 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1225 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1226 1227 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1228 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1229 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1230 1231 #define REG_GET_FIELD(value, reg, field) \ 1232 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1233 1234 #define WREG32_FIELD(reg, field, val) \ 1235 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1236 1237 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1238 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1239 1240 /* 1241 * BIOS helpers. 1242 */ 1243 #define RBIOS8(i) (adev->bios[i]) 1244 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1245 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1246 1247 /* 1248 * ASICs macro. 1249 */ 1250 #define amdgpu_asic_set_vga_state(adev, state) \ 1251 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1252 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1253 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1254 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1255 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1256 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1257 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1258 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1259 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1260 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1261 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1262 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1263 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1264 #define amdgpu_asic_flush_hdp(adev, r) \ 1265 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1266 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1267 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1268 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1269 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1270 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1271 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1272 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1273 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1274 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1275 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1276 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1277 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1278 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1279 1280 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1281 1282 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1283 #define for_each_inst(i, inst_mask) \ 1284 for (i = ffs(inst_mask); i-- != 0; \ 1285 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1286 1287 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 1288 1289 /* Common functions */ 1290 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1291 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1292 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1293 struct amdgpu_job *job, 1294 struct amdgpu_reset_context *reset_context); 1295 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1296 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1297 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1298 bool amdgpu_device_pcie_dynamic_switching_supported(void); 1299 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1300 bool amdgpu_device_aspm_support_quirk(void); 1301 1302 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1303 u64 num_vis_bytes); 1304 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1305 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1306 const u32 *registers, 1307 const u32 array_size); 1308 1309 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1310 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1311 bool amdgpu_device_supports_px(struct drm_device *dev); 1312 bool amdgpu_device_supports_boco(struct drm_device *dev); 1313 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1314 bool amdgpu_device_supports_baco(struct drm_device *dev); 1315 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1316 struct amdgpu_device *peer_adev); 1317 int amdgpu_device_baco_enter(struct drm_device *dev); 1318 int amdgpu_device_baco_exit(struct drm_device *dev); 1319 1320 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1321 struct amdgpu_ring *ring); 1322 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1323 struct amdgpu_ring *ring); 1324 1325 void amdgpu_device_halt(struct amdgpu_device *adev); 1326 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1327 u32 reg); 1328 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1329 u32 reg, u32 v); 1330 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1331 struct dma_fence *gang); 1332 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1333 1334 /* atpx handler */ 1335 #if defined(CONFIG_VGA_SWITCHEROO) 1336 void amdgpu_register_atpx_handler(void); 1337 void amdgpu_unregister_atpx_handler(void); 1338 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1339 bool amdgpu_is_atpx_hybrid(void); 1340 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1341 bool amdgpu_has_atpx(void); 1342 #else 1343 static inline void amdgpu_register_atpx_handler(void) {} 1344 static inline void amdgpu_unregister_atpx_handler(void) {} 1345 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1346 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1347 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1348 static inline bool amdgpu_has_atpx(void) { return false; } 1349 #endif 1350 1351 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1352 void *amdgpu_atpx_get_dhandle(void); 1353 #else 1354 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1355 #endif 1356 1357 /* 1358 * KMS 1359 */ 1360 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1361 extern const int amdgpu_max_kms_ioctl; 1362 1363 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1364 void amdgpu_driver_unload_kms(struct drm_device *dev); 1365 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1366 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1367 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1368 struct drm_file *file_priv); 1369 void amdgpu_driver_release_kms(struct drm_device *dev); 1370 1371 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1372 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1373 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1374 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1375 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1376 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1377 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1378 struct drm_file *filp); 1379 1380 /* 1381 * functions used by amdgpu_encoder.c 1382 */ 1383 struct amdgpu_afmt_acr { 1384 u32 clock; 1385 1386 int n_32khz; 1387 int cts_32khz; 1388 1389 int n_44_1khz; 1390 int cts_44_1khz; 1391 1392 int n_48khz; 1393 int cts_48khz; 1394 1395 }; 1396 1397 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1398 1399 /* amdgpu_acpi.c */ 1400 1401 struct amdgpu_numa_info { 1402 uint64_t size; 1403 int pxm; 1404 int nid; 1405 }; 1406 1407 /* ATCS Device/Driver State */ 1408 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1409 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1410 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1411 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1412 1413 #if defined(CONFIG_ACPI) 1414 int amdgpu_acpi_init(struct amdgpu_device *adev); 1415 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1416 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1417 bool amdgpu_acpi_is_power_shift_control_supported(void); 1418 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1419 u8 perf_req, bool advertise); 1420 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1421 u8 dev_state, bool drv_state); 1422 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1423 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1424 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1425 u64 *tmr_size); 1426 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1427 struct amdgpu_numa_info *numa_info); 1428 1429 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1430 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1431 void amdgpu_acpi_detect(void); 1432 void amdgpu_acpi_release(void); 1433 #else 1434 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1435 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1436 u64 *tmr_offset, u64 *tmr_size) 1437 { 1438 return -EINVAL; 1439 } 1440 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1441 int xcc_id, 1442 struct amdgpu_numa_info *numa_info) 1443 { 1444 return -EINVAL; 1445 } 1446 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1447 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1448 static inline void amdgpu_acpi_detect(void) { } 1449 static inline void amdgpu_acpi_release(void) { } 1450 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1451 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1452 u8 dev_state, bool drv_state) { return 0; } 1453 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1454 enum amdgpu_ss ss_state) { return 0; } 1455 #endif 1456 1457 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1458 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1459 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1460 #else 1461 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1462 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1463 #endif 1464 1465 #if defined(CONFIG_DRM_AMD_DC) 1466 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1467 #else 1468 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1469 #endif 1470 1471 1472 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1473 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1474 1475 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1476 pci_channel_state_t state); 1477 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1478 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1479 void amdgpu_pci_resume(struct pci_dev *pdev); 1480 1481 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1482 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1483 1484 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1485 1486 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1487 enum amd_clockgating_state state); 1488 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1489 enum amd_powergating_state state); 1490 1491 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1492 { 1493 return amdgpu_gpu_recovery != 0 && 1494 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1495 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1496 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1497 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1498 } 1499 1500 #include "amdgpu_object.h" 1501 1502 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1503 { 1504 return adev->gmc.tmz_enabled; 1505 } 1506 1507 int amdgpu_in_reset(struct amdgpu_device *adev); 1508 1509 #endif 1510