1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 53 #include <drm/ttm/ttm_bo_api.h> 54 #include <drm/ttm/ttm_bo_driver.h> 55 #include <drm/ttm/ttm_placement.h> 56 #include <drm/ttm/ttm_module.h> 57 #include <drm/ttm/ttm_execbuf_util.h> 58 59 #include <drm/amdgpu_drm.h> 60 #include <drm/drm_gem.h> 61 #include <drm/drm_ioctl.h> 62 #include <drm/gpu_scheduler.h> 63 64 #include <kgd_kfd_interface.h> 65 #include "dm_pp_interface.h" 66 #include "kgd_pp_interface.h" 67 68 #include "amd_shared.h" 69 #include "amdgpu_mode.h" 70 #include "amdgpu_ih.h" 71 #include "amdgpu_irq.h" 72 #include "amdgpu_ucode.h" 73 #include "amdgpu_ttm.h" 74 #include "amdgpu_psp.h" 75 #include "amdgpu_gds.h" 76 #include "amdgpu_sync.h" 77 #include "amdgpu_ring.h" 78 #include "amdgpu_vm.h" 79 #include "amdgpu_dpm.h" 80 #include "amdgpu_acp.h" 81 #include "amdgpu_uvd.h" 82 #include "amdgpu_vce.h" 83 #include "amdgpu_vcn.h" 84 #include "amdgpu_jpeg.h" 85 #include "amdgpu_mn.h" 86 #include "amdgpu_gmc.h" 87 #include "amdgpu_gfx.h" 88 #include "amdgpu_sdma.h" 89 #include "amdgpu_nbio.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_gart.h" 94 #include "amdgpu_debugfs.h" 95 #include "amdgpu_job.h" 96 #include "amdgpu_bo_list.h" 97 #include "amdgpu_gem.h" 98 #include "amdgpu_doorbell.h" 99 #include "amdgpu_amdkfd.h" 100 #include "amdgpu_smu.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_df.h" 106 107 #define MAX_GPU_INSTANCE 16 108 109 struct amdgpu_gpu_instance 110 { 111 struct amdgpu_device *adev; 112 int mgpu_fan_enabled; 113 }; 114 115 struct amdgpu_mgpu_info 116 { 117 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 118 struct mutex mutex; 119 uint32_t num_gpu; 120 uint32_t num_dgpu; 121 uint32_t num_apu; 122 }; 123 124 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 125 126 /* 127 * Modules parameters. 128 */ 129 extern int amdgpu_modeset; 130 extern int amdgpu_vram_limit; 131 extern int amdgpu_vis_vram_limit; 132 extern int amdgpu_gart_size; 133 extern int amdgpu_gtt_size; 134 extern int amdgpu_moverate; 135 extern int amdgpu_benchmarking; 136 extern int amdgpu_testing; 137 extern int amdgpu_audio; 138 extern int amdgpu_disp_priority; 139 extern int amdgpu_hw_i2c; 140 extern int amdgpu_pcie_gen2; 141 extern int amdgpu_msi; 142 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 143 extern int amdgpu_dpm; 144 extern int amdgpu_fw_load_type; 145 extern int amdgpu_aspm; 146 extern int amdgpu_runtime_pm; 147 extern uint amdgpu_ip_block_mask; 148 extern int amdgpu_bapm; 149 extern int amdgpu_deep_color; 150 extern int amdgpu_vm_size; 151 extern int amdgpu_vm_block_size; 152 extern int amdgpu_vm_fragment_size; 153 extern int amdgpu_vm_fault_stop; 154 extern int amdgpu_vm_debug; 155 extern int amdgpu_vm_update_mode; 156 extern int amdgpu_exp_hw_support; 157 extern int amdgpu_dc; 158 extern int amdgpu_sched_jobs; 159 extern int amdgpu_sched_hw_submission; 160 extern uint amdgpu_pcie_gen_cap; 161 extern uint amdgpu_pcie_lane_cap; 162 extern uint amdgpu_cg_mask; 163 extern uint amdgpu_pg_mask; 164 extern uint amdgpu_sdma_phase_quantum; 165 extern char *amdgpu_disable_cu; 166 extern char *amdgpu_virtual_display; 167 extern uint amdgpu_pp_feature_mask; 168 extern uint amdgpu_force_long_training; 169 extern int amdgpu_job_hang_limit; 170 extern int amdgpu_lbpw; 171 extern int amdgpu_compute_multipipe; 172 extern int amdgpu_gpu_recovery; 173 extern int amdgpu_emu_mode; 174 extern uint amdgpu_smu_memory_pool_size; 175 extern uint amdgpu_dc_feature_mask; 176 extern uint amdgpu_dc_debug_mask; 177 extern uint amdgpu_dm_abm_level; 178 extern struct amdgpu_mgpu_info mgpu_info; 179 extern int amdgpu_ras_enable; 180 extern uint amdgpu_ras_mask; 181 extern int amdgpu_async_gfx_ring; 182 extern int amdgpu_mcbp; 183 extern int amdgpu_discovery; 184 extern int amdgpu_mes; 185 extern int amdgpu_noretry; 186 extern int amdgpu_force_asic_type; 187 #ifdef CONFIG_HSA_AMD 188 extern int sched_policy; 189 #else 190 static const int sched_policy = KFD_SCHED_POLICY_HWS; 191 #endif 192 193 extern int amdgpu_tmz; 194 195 #ifdef CONFIG_DRM_AMDGPU_SI 196 extern int amdgpu_si_support; 197 #endif 198 #ifdef CONFIG_DRM_AMDGPU_CIK 199 extern int amdgpu_cik_support; 200 #endif 201 202 #define AMDGPU_VM_MAX_NUM_CTX 4096 203 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 204 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 205 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 206 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 207 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 208 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 209 #define AMDGPUFB_CONN_LIMIT 4 210 #define AMDGPU_BIOS_NUM_SCRATCH 16 211 212 /* hard reset data */ 213 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 214 215 /* reset flags */ 216 #define AMDGPU_RESET_GFX (1 << 0) 217 #define AMDGPU_RESET_COMPUTE (1 << 1) 218 #define AMDGPU_RESET_DMA (1 << 2) 219 #define AMDGPU_RESET_CP (1 << 3) 220 #define AMDGPU_RESET_GRBM (1 << 4) 221 #define AMDGPU_RESET_DMA1 (1 << 5) 222 #define AMDGPU_RESET_RLC (1 << 6) 223 #define AMDGPU_RESET_SEM (1 << 7) 224 #define AMDGPU_RESET_IH (1 << 8) 225 #define AMDGPU_RESET_VMC (1 << 9) 226 #define AMDGPU_RESET_MC (1 << 10) 227 #define AMDGPU_RESET_DISPLAY (1 << 11) 228 #define AMDGPU_RESET_UVD (1 << 12) 229 #define AMDGPU_RESET_VCE (1 << 13) 230 #define AMDGPU_RESET_VCE1 (1 << 14) 231 232 /* max cursor sizes (in pixels) */ 233 #define CIK_CURSOR_WIDTH 128 234 #define CIK_CURSOR_HEIGHT 128 235 236 struct amdgpu_device; 237 struct amdgpu_ib; 238 struct amdgpu_cs_parser; 239 struct amdgpu_job; 240 struct amdgpu_irq_src; 241 struct amdgpu_fpriv; 242 struct amdgpu_bo_va_mapping; 243 struct amdgpu_atif; 244 struct kfd_vm_fault_info; 245 246 enum amdgpu_cp_irq { 247 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 248 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 249 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 250 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 251 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 252 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 253 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 254 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 255 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 256 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 257 258 AMDGPU_CP_IRQ_LAST 259 }; 260 261 enum amdgpu_thermal_irq { 262 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 263 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 264 265 AMDGPU_THERMAL_IRQ_LAST 266 }; 267 268 enum amdgpu_kiq_irq { 269 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 270 AMDGPU_CP_KIQ_IRQ_LAST 271 }; 272 273 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 274 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 275 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 276 277 int amdgpu_device_ip_set_clockgating_state(void *dev, 278 enum amd_ip_block_type block_type, 279 enum amd_clockgating_state state); 280 int amdgpu_device_ip_set_powergating_state(void *dev, 281 enum amd_ip_block_type block_type, 282 enum amd_powergating_state state); 283 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 284 u32 *flags); 285 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 286 enum amd_ip_block_type block_type); 287 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 288 enum amd_ip_block_type block_type); 289 290 #define AMDGPU_MAX_IP_NUM 16 291 292 struct amdgpu_ip_block_status { 293 bool valid; 294 bool sw; 295 bool hw; 296 bool late_initialized; 297 bool hang; 298 }; 299 300 struct amdgpu_ip_block_version { 301 const enum amd_ip_block_type type; 302 const u32 major; 303 const u32 minor; 304 const u32 rev; 305 const struct amd_ip_funcs *funcs; 306 }; 307 308 #define HW_REV(_Major, _Minor, _Rev) \ 309 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 310 311 struct amdgpu_ip_block { 312 struct amdgpu_ip_block_status status; 313 const struct amdgpu_ip_block_version *version; 314 }; 315 316 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 317 enum amd_ip_block_type type, 318 u32 major, u32 minor); 319 320 struct amdgpu_ip_block * 321 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 322 enum amd_ip_block_type type); 323 324 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 325 const struct amdgpu_ip_block_version *ip_block_version); 326 327 /* 328 * BIOS. 329 */ 330 bool amdgpu_get_bios(struct amdgpu_device *adev); 331 bool amdgpu_read_bios(struct amdgpu_device *adev); 332 333 /* 334 * Clocks 335 */ 336 337 #define AMDGPU_MAX_PPLL 3 338 339 struct amdgpu_clock { 340 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 341 struct amdgpu_pll spll; 342 struct amdgpu_pll mpll; 343 /* 10 Khz units */ 344 uint32_t default_mclk; 345 uint32_t default_sclk; 346 uint32_t default_dispclk; 347 uint32_t current_dispclk; 348 uint32_t dp_extclk; 349 uint32_t max_pixel_clock; 350 }; 351 352 /* sub-allocation manager, it has to be protected by another lock. 353 * By conception this is an helper for other part of the driver 354 * like the indirect buffer or semaphore, which both have their 355 * locking. 356 * 357 * Principe is simple, we keep a list of sub allocation in offset 358 * order (first entry has offset == 0, last entry has the highest 359 * offset). 360 * 361 * When allocating new object we first check if there is room at 362 * the end total_size - (last_object_offset + last_object_size) >= 363 * alloc_size. If so we allocate new object there. 364 * 365 * When there is not enough room at the end, we start waiting for 366 * each sub object until we reach object_offset+object_size >= 367 * alloc_size, this object then become the sub object we return. 368 * 369 * Alignment can't be bigger than page size. 370 * 371 * Hole are not considered for allocation to keep things simple. 372 * Assumption is that there won't be hole (all object on same 373 * alignment). 374 */ 375 376 #define AMDGPU_SA_NUM_FENCE_LISTS 32 377 378 struct amdgpu_sa_manager { 379 wait_queue_head_t wq; 380 struct amdgpu_bo *bo; 381 struct list_head *hole; 382 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 383 struct list_head olist; 384 unsigned size; 385 uint64_t gpu_addr; 386 void *cpu_ptr; 387 uint32_t domain; 388 uint32_t align; 389 }; 390 391 /* sub-allocation buffer */ 392 struct amdgpu_sa_bo { 393 struct list_head olist; 394 struct list_head flist; 395 struct amdgpu_sa_manager *manager; 396 unsigned soffset; 397 unsigned eoffset; 398 struct dma_fence *fence; 399 }; 400 401 int amdgpu_fence_slab_init(void); 402 void amdgpu_fence_slab_fini(void); 403 404 /* 405 * IRQS. 406 */ 407 408 struct amdgpu_flip_work { 409 struct delayed_work flip_work; 410 struct work_struct unpin_work; 411 struct amdgpu_device *adev; 412 int crtc_id; 413 u32 target_vblank; 414 uint64_t base; 415 struct drm_pending_vblank_event *event; 416 struct amdgpu_bo *old_abo; 417 struct dma_fence *excl; 418 unsigned shared_count; 419 struct dma_fence **shared; 420 struct dma_fence_cb cb; 421 bool async; 422 }; 423 424 425 /* 426 * CP & rings. 427 */ 428 429 struct amdgpu_ib { 430 struct amdgpu_sa_bo *sa_bo; 431 uint32_t length_dw; 432 uint64_t gpu_addr; 433 uint32_t *ptr; 434 uint32_t flags; 435 }; 436 437 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 438 439 /* 440 * file private structure 441 */ 442 443 struct amdgpu_fpriv { 444 struct amdgpu_vm vm; 445 struct amdgpu_bo_va *prt_va; 446 struct amdgpu_bo_va *csa_va; 447 struct mutex bo_list_lock; 448 struct idr bo_list_handles; 449 struct amdgpu_ctx_mgr ctx_mgr; 450 }; 451 452 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 453 454 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 455 unsigned size, 456 enum amdgpu_ib_pool_type pool, 457 struct amdgpu_ib *ib); 458 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 459 struct dma_fence *f); 460 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 461 struct amdgpu_ib *ibs, struct amdgpu_job *job, 462 struct dma_fence **f); 463 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 464 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 465 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 466 467 /* 468 * CS. 469 */ 470 struct amdgpu_cs_chunk { 471 uint32_t chunk_id; 472 uint32_t length_dw; 473 void *kdata; 474 }; 475 476 struct amdgpu_cs_post_dep { 477 struct drm_syncobj *syncobj; 478 struct dma_fence_chain *chain; 479 u64 point; 480 }; 481 482 struct amdgpu_cs_parser { 483 struct amdgpu_device *adev; 484 struct drm_file *filp; 485 struct amdgpu_ctx *ctx; 486 487 /* chunks */ 488 unsigned nchunks; 489 struct amdgpu_cs_chunk *chunks; 490 491 /* scheduler job object */ 492 struct amdgpu_job *job; 493 struct drm_sched_entity *entity; 494 495 /* buffer objects */ 496 struct ww_acquire_ctx ticket; 497 struct amdgpu_bo_list *bo_list; 498 struct amdgpu_mn *mn; 499 struct amdgpu_bo_list_entry vm_pd; 500 struct list_head validated; 501 struct dma_fence *fence; 502 uint64_t bytes_moved_threshold; 503 uint64_t bytes_moved_vis_threshold; 504 uint64_t bytes_moved; 505 uint64_t bytes_moved_vis; 506 507 /* user fence */ 508 struct amdgpu_bo_list_entry uf_entry; 509 510 unsigned num_post_deps; 511 struct amdgpu_cs_post_dep *post_deps; 512 }; 513 514 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 515 uint32_t ib_idx, int idx) 516 { 517 return p->job->ibs[ib_idx].ptr[idx]; 518 } 519 520 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 521 uint32_t ib_idx, int idx, 522 uint32_t value) 523 { 524 p->job->ibs[ib_idx].ptr[idx] = value; 525 } 526 527 /* 528 * Writeback 529 */ 530 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 531 532 struct amdgpu_wb { 533 struct amdgpu_bo *wb_obj; 534 volatile uint32_t *wb; 535 uint64_t gpu_addr; 536 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 537 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 538 }; 539 540 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 541 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 542 543 /* 544 * Benchmarking 545 */ 546 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 547 548 549 /* 550 * Testing 551 */ 552 void amdgpu_test_moves(struct amdgpu_device *adev); 553 554 /* 555 * ASIC specific register table accessible by UMD 556 */ 557 struct amdgpu_allowed_register_entry { 558 uint32_t reg_offset; 559 bool grbm_indexed; 560 }; 561 562 enum amd_reset_method { 563 AMD_RESET_METHOD_LEGACY = 0, 564 AMD_RESET_METHOD_MODE0, 565 AMD_RESET_METHOD_MODE1, 566 AMD_RESET_METHOD_MODE2, 567 AMD_RESET_METHOD_BACO 568 }; 569 570 /* 571 * ASIC specific functions. 572 */ 573 struct amdgpu_asic_funcs { 574 bool (*read_disabled_bios)(struct amdgpu_device *adev); 575 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 576 u8 *bios, u32 length_bytes); 577 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 578 u32 sh_num, u32 reg_offset, u32 *value); 579 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 580 int (*reset)(struct amdgpu_device *adev); 581 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 582 /* get the reference clock */ 583 u32 (*get_xclk)(struct amdgpu_device *adev); 584 /* MM block clocks */ 585 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 586 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 587 /* static power management */ 588 int (*get_pcie_lanes)(struct amdgpu_device *adev); 589 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 590 /* get config memsize register */ 591 u32 (*get_config_memsize)(struct amdgpu_device *adev); 592 /* flush hdp write queue */ 593 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 594 /* invalidate hdp read cache */ 595 void (*invalidate_hdp)(struct amdgpu_device *adev, 596 struct amdgpu_ring *ring); 597 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev); 598 /* check if the asic needs a full reset of if soft reset will work */ 599 bool (*need_full_reset)(struct amdgpu_device *adev); 600 /* initialize doorbell layout for specific asic*/ 601 void (*init_doorbell_index)(struct amdgpu_device *adev); 602 /* PCIe bandwidth usage */ 603 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 604 uint64_t *count1); 605 /* do we need to reset the asic at init time (e.g., kexec) */ 606 bool (*need_reset_on_init)(struct amdgpu_device *adev); 607 /* PCIe replay counter */ 608 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 609 /* device supports BACO */ 610 bool (*supports_baco)(struct amdgpu_device *adev); 611 }; 612 613 /* 614 * IOCTL. 615 */ 616 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 617 struct drm_file *filp); 618 619 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 620 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 621 struct drm_file *filp); 622 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 623 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 624 struct drm_file *filp); 625 626 /* VRAM scratch page for HDP bug, default vram page */ 627 struct amdgpu_vram_scratch { 628 struct amdgpu_bo *robj; 629 volatile uint32_t *ptr; 630 u64 gpu_addr; 631 }; 632 633 /* 634 * ACPI 635 */ 636 struct amdgpu_atcs_functions { 637 bool get_ext_state; 638 bool pcie_perf_req; 639 bool pcie_dev_rdy; 640 bool pcie_bus_width; 641 }; 642 643 struct amdgpu_atcs { 644 struct amdgpu_atcs_functions functions; 645 }; 646 647 /* 648 * Firmware VRAM reservation 649 */ 650 struct amdgpu_fw_vram_usage { 651 u64 start_offset; 652 u64 size; 653 struct amdgpu_bo *reserved_bo; 654 void *va; 655 }; 656 657 /* 658 * CGS 659 */ 660 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 661 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 662 663 /* 664 * Core structure, functions and helpers. 665 */ 666 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 667 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 668 669 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 670 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 671 672 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 673 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 674 675 struct amdgpu_mmio_remap { 676 u32 reg_offset; 677 resource_size_t bus_addr; 678 }; 679 680 /* Define the HW IP blocks will be used in driver , add more if necessary */ 681 enum amd_hw_ip_block_type { 682 GC_HWIP = 1, 683 HDP_HWIP, 684 SDMA0_HWIP, 685 SDMA1_HWIP, 686 SDMA2_HWIP, 687 SDMA3_HWIP, 688 SDMA4_HWIP, 689 SDMA5_HWIP, 690 SDMA6_HWIP, 691 SDMA7_HWIP, 692 MMHUB_HWIP, 693 ATHUB_HWIP, 694 NBIO_HWIP, 695 MP0_HWIP, 696 MP1_HWIP, 697 UVD_HWIP, 698 VCN_HWIP = UVD_HWIP, 699 JPEG_HWIP = VCN_HWIP, 700 VCE_HWIP, 701 DF_HWIP, 702 DCE_HWIP, 703 OSSSYS_HWIP, 704 SMUIO_HWIP, 705 PWR_HWIP, 706 NBIF_HWIP, 707 THM_HWIP, 708 CLK_HWIP, 709 UMC_HWIP, 710 RSMU_HWIP, 711 MAX_HWIP 712 }; 713 714 #define HWIP_MAX_INSTANCE 8 715 716 struct amd_powerplay { 717 void *pp_handle; 718 const struct amd_pm_funcs *pp_funcs; 719 }; 720 721 #define AMDGPU_RESET_MAGIC_NUM 64 722 #define AMDGPU_MAX_DF_PERFMONS 4 723 struct amdgpu_device { 724 struct device *dev; 725 struct drm_device *ddev; 726 struct pci_dev *pdev; 727 728 #ifdef CONFIG_DRM_AMD_ACP 729 struct amdgpu_acp acp; 730 #endif 731 732 /* ASIC */ 733 enum amd_asic_type asic_type; 734 uint32_t family; 735 uint32_t rev_id; 736 uint32_t external_rev_id; 737 unsigned long flags; 738 unsigned long apu_flags; 739 int usec_timeout; 740 const struct amdgpu_asic_funcs *asic_funcs; 741 bool shutdown; 742 bool need_swiotlb; 743 bool accel_working; 744 struct notifier_block acpi_nb; 745 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 746 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 747 unsigned debugfs_count; 748 #if defined(CONFIG_DEBUG_FS) 749 struct dentry *debugfs_preempt; 750 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 751 #endif 752 struct amdgpu_atif *atif; 753 struct amdgpu_atcs atcs; 754 struct mutex srbm_mutex; 755 /* GRBM index mutex. Protects concurrent access to GRBM index */ 756 struct mutex grbm_idx_mutex; 757 struct dev_pm_domain vga_pm_domain; 758 bool have_disp_power_ref; 759 bool have_atomics_support; 760 761 /* BIOS */ 762 bool is_atom_fw; 763 uint8_t *bios; 764 uint32_t bios_size; 765 struct amdgpu_bo *stolen_vga_memory; 766 uint32_t bios_scratch_reg_offset; 767 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 768 769 /* Register/doorbell mmio */ 770 resource_size_t rmmio_base; 771 resource_size_t rmmio_size; 772 void __iomem *rmmio; 773 /* protects concurrent MM_INDEX/DATA based register access */ 774 spinlock_t mmio_idx_lock; 775 struct amdgpu_mmio_remap rmmio_remap; 776 /* protects concurrent SMC based register access */ 777 spinlock_t smc_idx_lock; 778 amdgpu_rreg_t smc_rreg; 779 amdgpu_wreg_t smc_wreg; 780 /* protects concurrent PCIE register access */ 781 spinlock_t pcie_idx_lock; 782 amdgpu_rreg_t pcie_rreg; 783 amdgpu_wreg_t pcie_wreg; 784 amdgpu_rreg_t pciep_rreg; 785 amdgpu_wreg_t pciep_wreg; 786 amdgpu_rreg64_t pcie_rreg64; 787 amdgpu_wreg64_t pcie_wreg64; 788 /* protects concurrent UVD register access */ 789 spinlock_t uvd_ctx_idx_lock; 790 amdgpu_rreg_t uvd_ctx_rreg; 791 amdgpu_wreg_t uvd_ctx_wreg; 792 /* protects concurrent DIDT register access */ 793 spinlock_t didt_idx_lock; 794 amdgpu_rreg_t didt_rreg; 795 amdgpu_wreg_t didt_wreg; 796 /* protects concurrent gc_cac register access */ 797 spinlock_t gc_cac_idx_lock; 798 amdgpu_rreg_t gc_cac_rreg; 799 amdgpu_wreg_t gc_cac_wreg; 800 /* protects concurrent se_cac register access */ 801 spinlock_t se_cac_idx_lock; 802 amdgpu_rreg_t se_cac_rreg; 803 amdgpu_wreg_t se_cac_wreg; 804 /* protects concurrent ENDPOINT (audio) register access */ 805 spinlock_t audio_endpt_idx_lock; 806 amdgpu_block_rreg_t audio_endpt_rreg; 807 amdgpu_block_wreg_t audio_endpt_wreg; 808 void __iomem *rio_mem; 809 resource_size_t rio_mem_size; 810 struct amdgpu_doorbell doorbell; 811 812 /* clock/pll info */ 813 struct amdgpu_clock clock; 814 815 /* MC */ 816 struct amdgpu_gmc gmc; 817 struct amdgpu_gart gart; 818 dma_addr_t dummy_page_addr; 819 struct amdgpu_vm_manager vm_manager; 820 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 821 unsigned num_vmhubs; 822 823 /* memory management */ 824 struct amdgpu_mman mman; 825 struct amdgpu_vram_scratch vram_scratch; 826 struct amdgpu_wb wb; 827 atomic64_t num_bytes_moved; 828 atomic64_t num_evictions; 829 atomic64_t num_vram_cpu_page_faults; 830 atomic_t gpu_reset_counter; 831 atomic_t vram_lost_counter; 832 833 /* data for buffer migration throttling */ 834 struct { 835 spinlock_t lock; 836 s64 last_update_us; 837 s64 accum_us; /* accumulated microseconds */ 838 s64 accum_us_vis; /* for visible VRAM */ 839 u32 log2_max_MBps; 840 } mm_stats; 841 842 /* display */ 843 bool enable_virtual_display; 844 struct amdgpu_mode_info mode_info; 845 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 846 struct work_struct hotplug_work; 847 struct amdgpu_irq_src crtc_irq; 848 struct amdgpu_irq_src vupdate_irq; 849 struct amdgpu_irq_src pageflip_irq; 850 struct amdgpu_irq_src hpd_irq; 851 852 /* rings */ 853 u64 fence_context; 854 unsigned num_rings; 855 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 856 bool ib_pool_ready; 857 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 858 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 859 860 /* interrupts */ 861 struct amdgpu_irq irq; 862 863 /* powerplay */ 864 struct amd_powerplay powerplay; 865 bool pp_force_state_enabled; 866 867 /* smu */ 868 struct smu_context smu; 869 870 /* dpm */ 871 struct amdgpu_pm pm; 872 u32 cg_flags; 873 u32 pg_flags; 874 875 /* nbio */ 876 struct amdgpu_nbio nbio; 877 878 /* mmhub */ 879 struct amdgpu_mmhub mmhub; 880 881 /* gfx */ 882 struct amdgpu_gfx gfx; 883 884 /* sdma */ 885 struct amdgpu_sdma sdma; 886 887 /* uvd */ 888 struct amdgpu_uvd uvd; 889 890 /* vce */ 891 struct amdgpu_vce vce; 892 893 /* vcn */ 894 struct amdgpu_vcn vcn; 895 896 /* jpeg */ 897 struct amdgpu_jpeg jpeg; 898 899 /* firmwares */ 900 struct amdgpu_firmware firmware; 901 902 /* PSP */ 903 struct psp_context psp; 904 905 /* GDS */ 906 struct amdgpu_gds gds; 907 908 /* KFD */ 909 struct amdgpu_kfd_dev kfd; 910 911 /* UMC */ 912 struct amdgpu_umc umc; 913 914 /* display related functionality */ 915 struct amdgpu_display_manager dm; 916 917 /* discovery */ 918 uint8_t *discovery_bin; 919 uint32_t discovery_tmr_size; 920 struct amdgpu_bo *discovery_memory; 921 922 /* mes */ 923 bool enable_mes; 924 struct amdgpu_mes mes; 925 926 /* df */ 927 struct amdgpu_df df; 928 929 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 930 int num_ip_blocks; 931 struct mutex mn_lock; 932 DECLARE_HASHTABLE(mn_hash, 7); 933 934 /* tracking pinned memory */ 935 atomic64_t vram_pin_size; 936 atomic64_t visible_pin_size; 937 atomic64_t gart_pin_size; 938 939 /* soc15 register offset based on ip, instance and segment */ 940 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 941 942 /* delayed work_func for deferring clockgating during resume */ 943 struct delayed_work delayed_init_work; 944 945 struct amdgpu_virt virt; 946 /* firmware VRAM reservation */ 947 struct amdgpu_fw_vram_usage fw_vram_usage; 948 949 /* link all shadow bo */ 950 struct list_head shadow_list; 951 struct mutex shadow_list_lock; 952 953 /* record hw reset is performed */ 954 bool has_hw_reset; 955 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 956 957 /* s3/s4 mask */ 958 bool in_suspend; 959 bool in_hibernate; 960 961 bool in_gpu_reset; 962 enum pp_mp1_state mp1_state; 963 struct mutex lock_reset; 964 struct amdgpu_doorbell_index doorbell_index; 965 966 struct mutex notifier_lock; 967 968 int asic_reset_res; 969 struct work_struct xgmi_reset_work; 970 971 long gfx_timeout; 972 long sdma_timeout; 973 long video_timeout; 974 long compute_timeout; 975 976 uint64_t unique_id; 977 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 978 979 /* enable runtime pm on the device */ 980 bool runpm; 981 bool in_runpm; 982 983 bool pm_sysfs_en; 984 bool ucode_sysfs_en; 985 986 /* Chip product information */ 987 char product_number[16]; 988 char product_name[32]; 989 char serial[16]; 990 991 struct amdgpu_autodump autodump; 992 993 atomic_t throttling_logging_enabled; 994 struct ratelimit_state throttling_logging_rs; 995 }; 996 997 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 998 { 999 return container_of(bdev, struct amdgpu_device, mman.bdev); 1000 } 1001 1002 int amdgpu_device_init(struct amdgpu_device *adev, 1003 struct drm_device *ddev, 1004 struct pci_dev *pdev, 1005 uint32_t flags); 1006 void amdgpu_device_fini(struct amdgpu_device *adev); 1007 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1008 1009 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1010 uint32_t *buf, size_t size, bool write); 1011 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, 1012 uint32_t acc_flags); 1013 void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1014 uint32_t acc_flags); 1015 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1016 uint32_t acc_flags); 1017 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1018 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1019 1020 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1021 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1022 1023 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1024 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1025 1026 int emu_soc_asic_init(struct amdgpu_device *adev); 1027 1028 /* 1029 * Registers read & write functions. 1030 */ 1031 #define AMDGPU_REGS_NO_KIQ (1<<1) 1032 1033 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1034 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1035 1036 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1037 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1038 1039 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1040 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1041 1042 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1043 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1044 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1045 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1046 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1047 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1048 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1049 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1050 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1051 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1052 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1053 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1054 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1055 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1056 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1057 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1058 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1059 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1060 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1061 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1062 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1063 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1064 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1065 #define WREG32_P(reg, val, mask) \ 1066 do { \ 1067 uint32_t tmp_ = RREG32(reg); \ 1068 tmp_ &= (mask); \ 1069 tmp_ |= ((val) & ~(mask)); \ 1070 WREG32(reg, tmp_); \ 1071 } while (0) 1072 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1073 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1074 #define WREG32_PLL_P(reg, val, mask) \ 1075 do { \ 1076 uint32_t tmp_ = RREG32_PLL(reg); \ 1077 tmp_ &= (mask); \ 1078 tmp_ |= ((val) & ~(mask)); \ 1079 WREG32_PLL(reg, tmp_); \ 1080 } while (0) 1081 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1082 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1083 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1084 1085 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1086 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1087 1088 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1089 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1090 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1091 1092 #define REG_GET_FIELD(value, reg, field) \ 1093 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1094 1095 #define WREG32_FIELD(reg, field, val) \ 1096 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1097 1098 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1099 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1100 1101 /* 1102 * BIOS helpers. 1103 */ 1104 #define RBIOS8(i) (adev->bios[i]) 1105 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1106 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1107 1108 /* 1109 * ASICs macro. 1110 */ 1111 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1112 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1113 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1114 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1115 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1116 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1117 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1118 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1119 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1120 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1121 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1122 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1123 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1124 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1125 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1126 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1127 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1128 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1129 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1130 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1131 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1132 1133 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1134 1135 /* Common functions */ 1136 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1137 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1138 struct amdgpu_job* job); 1139 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1140 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1141 1142 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1143 u64 num_vis_bytes); 1144 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1145 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1146 const u32 *registers, 1147 const u32 array_size); 1148 1149 bool amdgpu_device_supports_boco(struct drm_device *dev); 1150 bool amdgpu_device_supports_baco(struct drm_device *dev); 1151 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1152 struct amdgpu_device *peer_adev); 1153 int amdgpu_device_baco_enter(struct drm_device *dev); 1154 int amdgpu_device_baco_exit(struct drm_device *dev); 1155 1156 /* atpx handler */ 1157 #if defined(CONFIG_VGA_SWITCHEROO) 1158 void amdgpu_register_atpx_handler(void); 1159 void amdgpu_unregister_atpx_handler(void); 1160 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1161 bool amdgpu_is_atpx_hybrid(void); 1162 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1163 bool amdgpu_has_atpx(void); 1164 #else 1165 static inline void amdgpu_register_atpx_handler(void) {} 1166 static inline void amdgpu_unregister_atpx_handler(void) {} 1167 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1168 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1169 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1170 static inline bool amdgpu_has_atpx(void) { return false; } 1171 #endif 1172 1173 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1174 void *amdgpu_atpx_get_dhandle(void); 1175 #else 1176 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1177 #endif 1178 1179 /* 1180 * KMS 1181 */ 1182 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1183 extern const int amdgpu_max_kms_ioctl; 1184 1185 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1186 void amdgpu_driver_unload_kms(struct drm_device *dev); 1187 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1188 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1189 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1190 struct drm_file *file_priv); 1191 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1192 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1193 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1194 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1195 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1196 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1197 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1198 unsigned long arg); 1199 1200 /* 1201 * functions used by amdgpu_encoder.c 1202 */ 1203 struct amdgpu_afmt_acr { 1204 u32 clock; 1205 1206 int n_32khz; 1207 int cts_32khz; 1208 1209 int n_44_1khz; 1210 int cts_44_1khz; 1211 1212 int n_48khz; 1213 int cts_48khz; 1214 1215 }; 1216 1217 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1218 1219 /* amdgpu_acpi.c */ 1220 #if defined(CONFIG_ACPI) 1221 int amdgpu_acpi_init(struct amdgpu_device *adev); 1222 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1223 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1224 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1225 u8 perf_req, bool advertise); 1226 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1227 1228 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1229 struct amdgpu_dm_backlight_caps *caps); 1230 #else 1231 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1232 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1233 #endif 1234 1235 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1236 uint64_t addr, struct amdgpu_bo **bo, 1237 struct amdgpu_bo_va_mapping **mapping); 1238 1239 #if defined(CONFIG_DRM_AMD_DC) 1240 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1241 #else 1242 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1243 #endif 1244 1245 1246 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1247 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1248 1249 #include "amdgpu_object.h" 1250 1251 /* used by df_v3_6.c and amdgpu_pmu.c */ 1252 #define AMDGPU_PMU_ATTR(_name, _object) \ 1253 static ssize_t \ 1254 _name##_show(struct device *dev, \ 1255 struct device_attribute *attr, \ 1256 char *page) \ 1257 { \ 1258 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1259 return sprintf(page, _object "\n"); \ 1260 } \ 1261 \ 1262 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1263 1264 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1265 { 1266 return adev->gmc.tmz_enabled; 1267 } 1268 1269 #endif 1270