1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_gds.h" 55 56 #include "gpu_scheduler.h" 57 58 /* 59 * Modules parameters. 60 */ 61 extern int amdgpu_modeset; 62 extern int amdgpu_vram_limit; 63 extern int amdgpu_gart_size; 64 extern int amdgpu_benchmarking; 65 extern int amdgpu_testing; 66 extern int amdgpu_audio; 67 extern int amdgpu_disp_priority; 68 extern int amdgpu_hw_i2c; 69 extern int amdgpu_pcie_gen2; 70 extern int amdgpu_msi; 71 extern int amdgpu_lockup_timeout; 72 extern int amdgpu_dpm; 73 extern int amdgpu_smc_load_fw; 74 extern int amdgpu_aspm; 75 extern int amdgpu_runtime_pm; 76 extern int amdgpu_hard_reset; 77 extern unsigned amdgpu_ip_block_mask; 78 extern int amdgpu_bapm; 79 extern int amdgpu_deep_color; 80 extern int amdgpu_vm_size; 81 extern int amdgpu_vm_block_size; 82 extern int amdgpu_enable_scheduler; 83 extern int amdgpu_sched_jobs; 84 extern int amdgpu_sched_hw_submission; 85 86 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 87 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 88 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 89 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 90 #define AMDGPU_IB_POOL_SIZE 16 91 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 92 #define AMDGPUFB_CONN_LIMIT 4 93 #define AMDGPU_BIOS_NUM_SCRATCH 8 94 95 /* max number of rings */ 96 #define AMDGPU_MAX_RINGS 16 97 #define AMDGPU_MAX_GFX_RINGS 1 98 #define AMDGPU_MAX_COMPUTE_RINGS 8 99 #define AMDGPU_MAX_VCE_RINGS 2 100 101 /* max number of IP instances */ 102 #define AMDGPU_MAX_SDMA_INSTANCES 2 103 104 /* number of hw syncs before falling back on blocking */ 105 #define AMDGPU_NUM_SYNCS 4 106 107 /* hardcode that limit for now */ 108 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 109 110 /* hard reset data */ 111 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 112 113 /* reset flags */ 114 #define AMDGPU_RESET_GFX (1 << 0) 115 #define AMDGPU_RESET_COMPUTE (1 << 1) 116 #define AMDGPU_RESET_DMA (1 << 2) 117 #define AMDGPU_RESET_CP (1 << 3) 118 #define AMDGPU_RESET_GRBM (1 << 4) 119 #define AMDGPU_RESET_DMA1 (1 << 5) 120 #define AMDGPU_RESET_RLC (1 << 6) 121 #define AMDGPU_RESET_SEM (1 << 7) 122 #define AMDGPU_RESET_IH (1 << 8) 123 #define AMDGPU_RESET_VMC (1 << 9) 124 #define AMDGPU_RESET_MC (1 << 10) 125 #define AMDGPU_RESET_DISPLAY (1 << 11) 126 #define AMDGPU_RESET_UVD (1 << 12) 127 #define AMDGPU_RESET_VCE (1 << 13) 128 #define AMDGPU_RESET_VCE1 (1 << 14) 129 130 /* CG block flags */ 131 #define AMDGPU_CG_BLOCK_GFX (1 << 0) 132 #define AMDGPU_CG_BLOCK_MC (1 << 1) 133 #define AMDGPU_CG_BLOCK_SDMA (1 << 2) 134 #define AMDGPU_CG_BLOCK_UVD (1 << 3) 135 #define AMDGPU_CG_BLOCK_VCE (1 << 4) 136 #define AMDGPU_CG_BLOCK_HDP (1 << 5) 137 #define AMDGPU_CG_BLOCK_BIF (1 << 6) 138 139 /* CG flags */ 140 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0) 141 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1) 142 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2) 143 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3) 144 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4) 145 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 146 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6) 147 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7) 148 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8) 149 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9) 150 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10) 151 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11) 152 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12) 153 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13) 154 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14) 155 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15) 156 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16) 157 158 /* PG flags */ 159 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) 160 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) 161 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) 162 #define AMDGPU_PG_SUPPORT_UVD (1 << 3) 163 #define AMDGPU_PG_SUPPORT_VCE (1 << 4) 164 #define AMDGPU_PG_SUPPORT_CP (1 << 5) 165 #define AMDGPU_PG_SUPPORT_GDS (1 << 6) 166 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7) 167 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8) 168 #define AMDGPU_PG_SUPPORT_ACP (1 << 9) 169 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10) 170 171 /* GFX current status */ 172 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 173 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 174 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 175 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 176 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 177 178 /* max cursor sizes (in pixels) */ 179 #define CIK_CURSOR_WIDTH 128 180 #define CIK_CURSOR_HEIGHT 128 181 182 struct amdgpu_device; 183 struct amdgpu_fence; 184 struct amdgpu_ib; 185 struct amdgpu_vm; 186 struct amdgpu_ring; 187 struct amdgpu_semaphore; 188 struct amdgpu_cs_parser; 189 struct amdgpu_job; 190 struct amdgpu_irq_src; 191 struct amdgpu_fpriv; 192 193 enum amdgpu_cp_irq { 194 AMDGPU_CP_IRQ_GFX_EOP = 0, 195 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 199 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 203 204 AMDGPU_CP_IRQ_LAST 205 }; 206 207 enum amdgpu_sdma_irq { 208 AMDGPU_SDMA_IRQ_TRAP0 = 0, 209 AMDGPU_SDMA_IRQ_TRAP1, 210 211 AMDGPU_SDMA_IRQ_LAST 212 }; 213 214 enum amdgpu_thermal_irq { 215 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 216 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 217 218 AMDGPU_THERMAL_IRQ_LAST 219 }; 220 221 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 222 enum amd_ip_block_type block_type, 223 enum amd_clockgating_state state); 224 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 225 enum amd_ip_block_type block_type, 226 enum amd_powergating_state state); 227 228 struct amdgpu_ip_block_version { 229 enum amd_ip_block_type type; 230 u32 major; 231 u32 minor; 232 u32 rev; 233 const struct amd_ip_funcs *funcs; 234 }; 235 236 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 237 enum amd_ip_block_type type, 238 u32 major, u32 minor); 239 240 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 241 struct amdgpu_device *adev, 242 enum amd_ip_block_type type); 243 244 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 245 struct amdgpu_buffer_funcs { 246 /* maximum bytes in a single operation */ 247 uint32_t copy_max_bytes; 248 249 /* number of dw to reserve per operation */ 250 unsigned copy_num_dw; 251 252 /* used for buffer migration */ 253 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 254 /* src addr in bytes */ 255 uint64_t src_offset, 256 /* dst addr in bytes */ 257 uint64_t dst_offset, 258 /* number of byte to transfer */ 259 uint32_t byte_count); 260 261 /* maximum bytes in a single operation */ 262 uint32_t fill_max_bytes; 263 264 /* number of dw to reserve per operation */ 265 unsigned fill_num_dw; 266 267 /* used for buffer clearing */ 268 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 269 /* value to write to memory */ 270 uint32_t src_data, 271 /* dst addr in bytes */ 272 uint64_t dst_offset, 273 /* number of byte to fill */ 274 uint32_t byte_count); 275 }; 276 277 /* provided by hw blocks that can write ptes, e.g., sdma */ 278 struct amdgpu_vm_pte_funcs { 279 /* copy pte entries from GART */ 280 void (*copy_pte)(struct amdgpu_ib *ib, 281 uint64_t pe, uint64_t src, 282 unsigned count); 283 /* write pte one entry at a time with addr mapping */ 284 void (*write_pte)(struct amdgpu_ib *ib, 285 uint64_t pe, 286 uint64_t addr, unsigned count, 287 uint32_t incr, uint32_t flags); 288 /* for linear pte/pde updates without addr mapping */ 289 void (*set_pte_pde)(struct amdgpu_ib *ib, 290 uint64_t pe, 291 uint64_t addr, unsigned count, 292 uint32_t incr, uint32_t flags); 293 /* pad the indirect buffer to the necessary number of dw */ 294 void (*pad_ib)(struct amdgpu_ib *ib); 295 }; 296 297 /* provided by the gmc block */ 298 struct amdgpu_gart_funcs { 299 /* flush the vm tlb via mmio */ 300 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 301 uint32_t vmid); 302 /* write pte/pde updates using the cpu */ 303 int (*set_pte_pde)(struct amdgpu_device *adev, 304 void *cpu_pt_addr, /* cpu addr of page table */ 305 uint32_t gpu_page_idx, /* pte/pde to update */ 306 uint64_t addr, /* addr to write into pte/pde */ 307 uint32_t flags); /* access flags */ 308 }; 309 310 /* provided by the ih block */ 311 struct amdgpu_ih_funcs { 312 /* ring read/write ptr handling, called from interrupt context */ 313 u32 (*get_wptr)(struct amdgpu_device *adev); 314 void (*decode_iv)(struct amdgpu_device *adev, 315 struct amdgpu_iv_entry *entry); 316 void (*set_rptr)(struct amdgpu_device *adev); 317 }; 318 319 /* provided by hw blocks that expose a ring buffer for commands */ 320 struct amdgpu_ring_funcs { 321 /* ring read/write ptr handling */ 322 u32 (*get_rptr)(struct amdgpu_ring *ring); 323 u32 (*get_wptr)(struct amdgpu_ring *ring); 324 void (*set_wptr)(struct amdgpu_ring *ring); 325 /* validating and patching of IBs */ 326 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 327 /* command emit functions */ 328 void (*emit_ib)(struct amdgpu_ring *ring, 329 struct amdgpu_ib *ib); 330 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 331 uint64_t seq, unsigned flags); 332 bool (*emit_semaphore)(struct amdgpu_ring *ring, 333 struct amdgpu_semaphore *semaphore, 334 bool emit_wait); 335 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 336 uint64_t pd_addr); 337 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 338 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 339 uint32_t gds_base, uint32_t gds_size, 340 uint32_t gws_base, uint32_t gws_size, 341 uint32_t oa_base, uint32_t oa_size); 342 /* testing functions */ 343 int (*test_ring)(struct amdgpu_ring *ring); 344 int (*test_ib)(struct amdgpu_ring *ring); 345 bool (*is_lockup)(struct amdgpu_ring *ring); 346 /* insert NOP packets */ 347 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 348 }; 349 350 /* 351 * BIOS. 352 */ 353 bool amdgpu_get_bios(struct amdgpu_device *adev); 354 bool amdgpu_read_bios(struct amdgpu_device *adev); 355 356 /* 357 * Dummy page 358 */ 359 struct amdgpu_dummy_page { 360 struct page *page; 361 dma_addr_t addr; 362 }; 363 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 364 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 365 366 367 /* 368 * Clocks 369 */ 370 371 #define AMDGPU_MAX_PPLL 3 372 373 struct amdgpu_clock { 374 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 375 struct amdgpu_pll spll; 376 struct amdgpu_pll mpll; 377 /* 10 Khz units */ 378 uint32_t default_mclk; 379 uint32_t default_sclk; 380 uint32_t default_dispclk; 381 uint32_t current_dispclk; 382 uint32_t dp_extclk; 383 uint32_t max_pixel_clock; 384 }; 385 386 /* 387 * Fences. 388 */ 389 struct amdgpu_fence_driver { 390 struct amdgpu_ring *ring; 391 uint64_t gpu_addr; 392 volatile uint32_t *cpu_addr; 393 /* sync_seq is protected by ring emission lock */ 394 uint64_t sync_seq[AMDGPU_MAX_RINGS]; 395 atomic64_t last_seq; 396 bool initialized; 397 struct amdgpu_irq_src *irq_src; 398 unsigned irq_type; 399 struct delayed_work lockup_work; 400 wait_queue_head_t fence_queue; 401 }; 402 403 /* some special values for the owner field */ 404 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 405 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 406 #define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul) 407 408 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 409 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 410 411 struct amdgpu_fence { 412 struct fence base; 413 414 /* RB, DMA, etc. */ 415 struct amdgpu_ring *ring; 416 uint64_t seq; 417 418 /* filp or special value for fence creator */ 419 void *owner; 420 421 wait_queue_t fence_wake; 422 }; 423 424 struct amdgpu_user_fence { 425 /* write-back bo */ 426 struct amdgpu_bo *bo; 427 /* write-back address offset to bo start */ 428 uint32_t offset; 429 }; 430 431 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 432 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 433 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 434 435 void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 436 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 437 struct amdgpu_irq_src *irq_src, 438 unsigned irq_type); 439 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 440 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 441 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, 442 struct amdgpu_fence **fence); 443 void amdgpu_fence_process(struct amdgpu_ring *ring); 444 int amdgpu_fence_wait_next(struct amdgpu_ring *ring); 445 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 446 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 447 448 signed long amdgpu_fence_wait_any(struct amdgpu_device *adev, 449 struct fence **array, 450 uint32_t count, 451 bool intr, 452 signed long t); 453 struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence); 454 void amdgpu_fence_unref(struct amdgpu_fence **fence); 455 456 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, 457 struct amdgpu_ring *ring); 458 void amdgpu_fence_note_sync(struct amdgpu_fence *fence, 459 struct amdgpu_ring *ring); 460 461 static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a, 462 struct amdgpu_fence *b) 463 { 464 if (!a) { 465 return b; 466 } 467 468 if (!b) { 469 return a; 470 } 471 472 BUG_ON(a->ring != b->ring); 473 474 if (a->seq > b->seq) { 475 return a; 476 } else { 477 return b; 478 } 479 } 480 481 static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a, 482 struct amdgpu_fence *b) 483 { 484 if (!a) { 485 return false; 486 } 487 488 if (!b) { 489 return true; 490 } 491 492 BUG_ON(a->ring != b->ring); 493 494 return a->seq < b->seq; 495 } 496 497 int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user, 498 void *owner, struct amdgpu_fence **fence); 499 500 /* 501 * TTM. 502 */ 503 struct amdgpu_mman { 504 struct ttm_bo_global_ref bo_global_ref; 505 struct drm_global_reference mem_global_ref; 506 struct ttm_bo_device bdev; 507 bool mem_global_referenced; 508 bool initialized; 509 510 #if defined(CONFIG_DEBUG_FS) 511 struct dentry *vram; 512 struct dentry *gtt; 513 #endif 514 515 /* buffer handling */ 516 const struct amdgpu_buffer_funcs *buffer_funcs; 517 struct amdgpu_ring *buffer_funcs_ring; 518 }; 519 520 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 521 uint64_t src_offset, 522 uint64_t dst_offset, 523 uint32_t byte_count, 524 struct reservation_object *resv, 525 struct fence **fence); 526 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 527 528 struct amdgpu_bo_list_entry { 529 struct amdgpu_bo *robj; 530 struct ttm_validate_buffer tv; 531 struct amdgpu_bo_va *bo_va; 532 unsigned prefered_domains; 533 unsigned allowed_domains; 534 uint32_t priority; 535 }; 536 537 struct amdgpu_bo_va_mapping { 538 struct list_head list; 539 struct interval_tree_node it; 540 uint64_t offset; 541 uint32_t flags; 542 }; 543 544 /* bo virtual addresses in a specific vm */ 545 struct amdgpu_bo_va { 546 /* protected by bo being reserved */ 547 struct list_head bo_list; 548 struct fence *last_pt_update; 549 unsigned ref_count; 550 551 /* protected by vm mutex and spinlock */ 552 struct list_head vm_status; 553 554 /* mappings for this bo_va */ 555 struct list_head invalids; 556 struct list_head valids; 557 558 /* constant after initialization */ 559 struct amdgpu_vm *vm; 560 struct amdgpu_bo *bo; 561 }; 562 563 #define AMDGPU_GEM_DOMAIN_MAX 0x3 564 565 struct amdgpu_bo { 566 /* Protected by gem.mutex */ 567 struct list_head list; 568 /* Protected by tbo.reserved */ 569 u32 initial_domain; 570 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 571 struct ttm_placement placement; 572 struct ttm_buffer_object tbo; 573 struct ttm_bo_kmap_obj kmap; 574 u64 flags; 575 unsigned pin_count; 576 void *kptr; 577 u64 tiling_flags; 578 u64 metadata_flags; 579 void *metadata; 580 u32 metadata_size; 581 /* list of all virtual address to which this bo 582 * is associated to 583 */ 584 struct list_head va; 585 /* Constant after initialization */ 586 struct amdgpu_device *adev; 587 struct drm_gem_object gem_base; 588 589 struct ttm_bo_kmap_obj dma_buf_vmap; 590 pid_t pid; 591 struct amdgpu_mn *mn; 592 struct list_head mn_list; 593 }; 594 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 595 596 void amdgpu_gem_object_free(struct drm_gem_object *obj); 597 int amdgpu_gem_object_open(struct drm_gem_object *obj, 598 struct drm_file *file_priv); 599 void amdgpu_gem_object_close(struct drm_gem_object *obj, 600 struct drm_file *file_priv); 601 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 602 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 603 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 604 struct dma_buf_attachment *attach, 605 struct sg_table *sg); 606 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 607 struct drm_gem_object *gobj, 608 int flags); 609 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 610 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 611 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 612 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 613 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 614 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 615 616 /* sub-allocation manager, it has to be protected by another lock. 617 * By conception this is an helper for other part of the driver 618 * like the indirect buffer or semaphore, which both have their 619 * locking. 620 * 621 * Principe is simple, we keep a list of sub allocation in offset 622 * order (first entry has offset == 0, last entry has the highest 623 * offset). 624 * 625 * When allocating new object we first check if there is room at 626 * the end total_size - (last_object_offset + last_object_size) >= 627 * alloc_size. If so we allocate new object there. 628 * 629 * When there is not enough room at the end, we start waiting for 630 * each sub object until we reach object_offset+object_size >= 631 * alloc_size, this object then become the sub object we return. 632 * 633 * Alignment can't be bigger than page size. 634 * 635 * Hole are not considered for allocation to keep things simple. 636 * Assumption is that there won't be hole (all object on same 637 * alignment). 638 */ 639 struct amdgpu_sa_manager { 640 wait_queue_head_t wq; 641 struct amdgpu_bo *bo; 642 struct list_head *hole; 643 struct list_head flist[AMDGPU_MAX_RINGS]; 644 struct list_head olist; 645 unsigned size; 646 uint64_t gpu_addr; 647 void *cpu_ptr; 648 uint32_t domain; 649 uint32_t align; 650 }; 651 652 struct amdgpu_sa_bo; 653 654 /* sub-allocation buffer */ 655 struct amdgpu_sa_bo { 656 struct list_head olist; 657 struct list_head flist; 658 struct amdgpu_sa_manager *manager; 659 unsigned soffset; 660 unsigned eoffset; 661 struct fence *fence; 662 }; 663 664 /* 665 * GEM objects. 666 */ 667 struct amdgpu_gem { 668 struct mutex mutex; 669 struct list_head objects; 670 }; 671 672 int amdgpu_gem_init(struct amdgpu_device *adev); 673 void amdgpu_gem_fini(struct amdgpu_device *adev); 674 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 675 int alignment, u32 initial_domain, 676 u64 flags, bool kernel, 677 struct drm_gem_object **obj); 678 679 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 680 struct drm_device *dev, 681 struct drm_mode_create_dumb *args); 682 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 683 struct drm_device *dev, 684 uint32_t handle, uint64_t *offset_p); 685 686 /* 687 * Semaphores. 688 */ 689 struct amdgpu_semaphore { 690 struct amdgpu_sa_bo *sa_bo; 691 signed waiters; 692 uint64_t gpu_addr; 693 }; 694 695 int amdgpu_semaphore_create(struct amdgpu_device *adev, 696 struct amdgpu_semaphore **semaphore); 697 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, 698 struct amdgpu_semaphore *semaphore); 699 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, 700 struct amdgpu_semaphore *semaphore); 701 void amdgpu_semaphore_free(struct amdgpu_device *adev, 702 struct amdgpu_semaphore **semaphore, 703 struct fence *fence); 704 705 /* 706 * Synchronization 707 */ 708 struct amdgpu_sync { 709 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS]; 710 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS]; 711 DECLARE_HASHTABLE(fences, 4); 712 struct fence *last_vm_update; 713 }; 714 715 void amdgpu_sync_create(struct amdgpu_sync *sync); 716 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 717 struct fence *f); 718 int amdgpu_sync_resv(struct amdgpu_device *adev, 719 struct amdgpu_sync *sync, 720 struct reservation_object *resv, 721 void *owner); 722 int amdgpu_sync_rings(struct amdgpu_sync *sync, 723 struct amdgpu_ring *ring); 724 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 725 int amdgpu_sync_wait(struct amdgpu_sync *sync); 726 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, 727 struct fence *fence); 728 729 /* 730 * GART structures, functions & helpers 731 */ 732 struct amdgpu_mc; 733 734 #define AMDGPU_GPU_PAGE_SIZE 4096 735 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 736 #define AMDGPU_GPU_PAGE_SHIFT 12 737 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 738 739 struct amdgpu_gart { 740 dma_addr_t table_addr; 741 struct amdgpu_bo *robj; 742 void *ptr; 743 unsigned num_gpu_pages; 744 unsigned num_cpu_pages; 745 unsigned table_size; 746 struct page **pages; 747 dma_addr_t *pages_addr; 748 bool ready; 749 const struct amdgpu_gart_funcs *gart_funcs; 750 }; 751 752 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 753 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 754 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 755 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 756 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 757 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 758 int amdgpu_gart_init(struct amdgpu_device *adev); 759 void amdgpu_gart_fini(struct amdgpu_device *adev); 760 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 761 int pages); 762 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 763 int pages, struct page **pagelist, 764 dma_addr_t *dma_addr, uint32_t flags); 765 766 /* 767 * GPU MC structures, functions & helpers 768 */ 769 struct amdgpu_mc { 770 resource_size_t aper_size; 771 resource_size_t aper_base; 772 resource_size_t agp_base; 773 /* for some chips with <= 32MB we need to lie 774 * about vram size near mc fb location */ 775 u64 mc_vram_size; 776 u64 visible_vram_size; 777 u64 gtt_size; 778 u64 gtt_start; 779 u64 gtt_end; 780 u64 vram_start; 781 u64 vram_end; 782 unsigned vram_width; 783 u64 real_vram_size; 784 int vram_mtrr; 785 u64 gtt_base_align; 786 u64 mc_mask; 787 const struct firmware *fw; /* MC firmware */ 788 uint32_t fw_version; 789 struct amdgpu_irq_src vm_fault; 790 uint32_t vram_type; 791 }; 792 793 /* 794 * GPU doorbell structures, functions & helpers 795 */ 796 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 797 { 798 AMDGPU_DOORBELL_KIQ = 0x000, 799 AMDGPU_DOORBELL_HIQ = 0x001, 800 AMDGPU_DOORBELL_DIQ = 0x002, 801 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 802 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 803 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 804 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 805 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 806 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 807 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 808 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 809 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 810 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 811 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 812 AMDGPU_DOORBELL_IH = 0x1E8, 813 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 814 AMDGPU_DOORBELL_INVALID = 0xFFFF 815 } AMDGPU_DOORBELL_ASSIGNMENT; 816 817 struct amdgpu_doorbell { 818 /* doorbell mmio */ 819 resource_size_t base; 820 resource_size_t size; 821 u32 __iomem *ptr; 822 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 823 }; 824 825 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 826 phys_addr_t *aperture_base, 827 size_t *aperture_size, 828 size_t *start_offset); 829 830 /* 831 * IRQS. 832 */ 833 834 struct amdgpu_flip_work { 835 struct work_struct flip_work; 836 struct work_struct unpin_work; 837 struct amdgpu_device *adev; 838 int crtc_id; 839 uint64_t base; 840 struct drm_pending_vblank_event *event; 841 struct amdgpu_bo *old_rbo; 842 struct fence *excl; 843 unsigned shared_count; 844 struct fence **shared; 845 }; 846 847 848 /* 849 * CP & rings. 850 */ 851 852 struct amdgpu_ib { 853 struct amdgpu_sa_bo *sa_bo; 854 uint32_t length_dw; 855 uint64_t gpu_addr; 856 uint32_t *ptr; 857 struct amdgpu_ring *ring; 858 struct amdgpu_fence *fence; 859 struct amdgpu_user_fence *user; 860 struct amdgpu_vm *vm; 861 struct amdgpu_ctx *ctx; 862 struct amdgpu_sync sync; 863 uint32_t gds_base, gds_size; 864 uint32_t gws_base, gws_size; 865 uint32_t oa_base, oa_size; 866 uint32_t flags; 867 /* resulting sequence number */ 868 uint64_t sequence; 869 }; 870 871 enum amdgpu_ring_type { 872 AMDGPU_RING_TYPE_GFX, 873 AMDGPU_RING_TYPE_COMPUTE, 874 AMDGPU_RING_TYPE_SDMA, 875 AMDGPU_RING_TYPE_UVD, 876 AMDGPU_RING_TYPE_VCE 877 }; 878 879 extern struct amd_sched_backend_ops amdgpu_sched_ops; 880 881 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev, 882 struct amdgpu_ring *ring, 883 struct amdgpu_ib *ibs, 884 unsigned num_ibs, 885 int (*free_job)(struct amdgpu_job *), 886 void *owner, 887 struct fence **fence); 888 889 struct amdgpu_ring { 890 struct amdgpu_device *adev; 891 const struct amdgpu_ring_funcs *funcs; 892 struct amdgpu_fence_driver fence_drv; 893 struct amd_gpu_scheduler *scheduler; 894 895 spinlock_t fence_lock; 896 struct mutex *ring_lock; 897 struct amdgpu_bo *ring_obj; 898 volatile uint32_t *ring; 899 unsigned rptr_offs; 900 u64 next_rptr_gpu_addr; 901 volatile u32 *next_rptr_cpu_addr; 902 unsigned wptr; 903 unsigned wptr_old; 904 unsigned ring_size; 905 unsigned ring_free_dw; 906 int count_dw; 907 atomic_t last_rptr; 908 atomic64_t last_activity; 909 uint64_t gpu_addr; 910 uint32_t align_mask; 911 uint32_t ptr_mask; 912 bool ready; 913 u32 nop; 914 u32 idx; 915 u64 last_semaphore_signal_addr; 916 u64 last_semaphore_wait_addr; 917 u32 me; 918 u32 pipe; 919 u32 queue; 920 struct amdgpu_bo *mqd_obj; 921 u32 doorbell_index; 922 bool use_doorbell; 923 unsigned wptr_offs; 924 unsigned next_rptr_offs; 925 unsigned fence_offs; 926 struct amdgpu_ctx *current_ctx; 927 enum amdgpu_ring_type type; 928 char name[16]; 929 bool is_pte_ring; 930 }; 931 932 /* 933 * VM 934 */ 935 936 /* maximum number of VMIDs */ 937 #define AMDGPU_NUM_VM 16 938 939 /* number of entries in page table */ 940 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 941 942 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 943 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 944 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 945 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 946 947 #define AMDGPU_PTE_VALID (1 << 0) 948 #define AMDGPU_PTE_SYSTEM (1 << 1) 949 #define AMDGPU_PTE_SNOOPED (1 << 2) 950 951 /* VI only */ 952 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 953 954 #define AMDGPU_PTE_READABLE (1 << 5) 955 #define AMDGPU_PTE_WRITEABLE (1 << 6) 956 957 /* PTE (Page Table Entry) fragment field for different page sizes */ 958 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 959 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 960 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 961 962 struct amdgpu_vm_pt { 963 struct amdgpu_bo *bo; 964 uint64_t addr; 965 }; 966 967 struct amdgpu_vm_id { 968 unsigned id; 969 uint64_t pd_gpu_addr; 970 /* last flushed PD/PT update */ 971 struct fence *flushed_updates; 972 /* last use of vmid */ 973 struct amdgpu_fence *last_id_use; 974 }; 975 976 struct amdgpu_vm { 977 struct mutex mutex; 978 979 struct rb_root va; 980 981 /* protecting invalidated */ 982 spinlock_t status_lock; 983 984 /* BOs moved, but not yet updated in the PT */ 985 struct list_head invalidated; 986 987 /* BOs cleared in the PT because of a move */ 988 struct list_head cleared; 989 990 /* BO mappings freed, but not yet updated in the PT */ 991 struct list_head freed; 992 993 /* contains the page directory */ 994 struct amdgpu_bo *page_directory; 995 unsigned max_pde_used; 996 struct fence *page_directory_fence; 997 998 /* array of page tables, one for each page directory entry */ 999 struct amdgpu_vm_pt *page_tables; 1000 1001 /* for id and flush management per ring */ 1002 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; 1003 }; 1004 1005 struct amdgpu_vm_manager { 1006 struct amdgpu_fence *active[AMDGPU_NUM_VM]; 1007 uint32_t max_pfn; 1008 /* number of VMIDs */ 1009 unsigned nvm; 1010 /* vram base address for page table entry */ 1011 u64 vram_base_offset; 1012 /* is vm enabled? */ 1013 bool enabled; 1014 /* for hw to save the PD addr on suspend/resume */ 1015 uint32_t saved_table_addr[AMDGPU_NUM_VM]; 1016 /* vm pte handling */ 1017 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 1018 struct amdgpu_ring *vm_pte_funcs_ring; 1019 }; 1020 1021 /* 1022 * context related structures 1023 */ 1024 1025 #define AMDGPU_CTX_MAX_CS_PENDING 16 1026 1027 struct amdgpu_ctx_ring { 1028 uint64_t sequence; 1029 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING]; 1030 struct amd_sched_entity entity; 1031 }; 1032 1033 struct amdgpu_ctx { 1034 struct kref refcount; 1035 struct amdgpu_device *adev; 1036 unsigned reset_counter; 1037 spinlock_t ring_lock; 1038 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 1039 }; 1040 1041 struct amdgpu_ctx_mgr { 1042 struct amdgpu_device *adev; 1043 struct mutex lock; 1044 /* protected by lock */ 1045 struct idr ctx_handles; 1046 }; 1047 1048 int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel, 1049 struct amdgpu_ctx *ctx); 1050 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx); 1051 1052 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 1053 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 1054 1055 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 1056 struct fence *fence); 1057 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 1058 struct amdgpu_ring *ring, uint64_t seq); 1059 1060 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 1061 struct drm_file *filp); 1062 1063 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1064 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 1065 1066 /* 1067 * file private structure 1068 */ 1069 1070 struct amdgpu_fpriv { 1071 struct amdgpu_vm vm; 1072 struct mutex bo_list_lock; 1073 struct idr bo_list_handles; 1074 struct amdgpu_ctx_mgr ctx_mgr; 1075 }; 1076 1077 /* 1078 * residency list 1079 */ 1080 1081 struct amdgpu_bo_list { 1082 struct mutex lock; 1083 struct amdgpu_bo *gds_obj; 1084 struct amdgpu_bo *gws_obj; 1085 struct amdgpu_bo *oa_obj; 1086 bool has_userptr; 1087 unsigned num_entries; 1088 struct amdgpu_bo_list_entry *array; 1089 }; 1090 1091 struct amdgpu_bo_list * 1092 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1093 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1094 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1095 1096 /* 1097 * GFX stuff 1098 */ 1099 #include "clearstate_defs.h" 1100 1101 struct amdgpu_rlc { 1102 /* for power gating */ 1103 struct amdgpu_bo *save_restore_obj; 1104 uint64_t save_restore_gpu_addr; 1105 volatile uint32_t *sr_ptr; 1106 const u32 *reg_list; 1107 u32 reg_list_size; 1108 /* for clear state */ 1109 struct amdgpu_bo *clear_state_obj; 1110 uint64_t clear_state_gpu_addr; 1111 volatile uint32_t *cs_ptr; 1112 const struct cs_section_def *cs_data; 1113 u32 clear_state_size; 1114 /* for cp tables */ 1115 struct amdgpu_bo *cp_table_obj; 1116 uint64_t cp_table_gpu_addr; 1117 volatile uint32_t *cp_table_ptr; 1118 u32 cp_table_size; 1119 }; 1120 1121 struct amdgpu_mec { 1122 struct amdgpu_bo *hpd_eop_obj; 1123 u64 hpd_eop_gpu_addr; 1124 u32 num_pipe; 1125 u32 num_mec; 1126 u32 num_queue; 1127 }; 1128 1129 /* 1130 * GPU scratch registers structures, functions & helpers 1131 */ 1132 struct amdgpu_scratch { 1133 unsigned num_reg; 1134 uint32_t reg_base; 1135 bool free[32]; 1136 uint32_t reg[32]; 1137 }; 1138 1139 /* 1140 * GFX configurations 1141 */ 1142 struct amdgpu_gca_config { 1143 unsigned max_shader_engines; 1144 unsigned max_tile_pipes; 1145 unsigned max_cu_per_sh; 1146 unsigned max_sh_per_se; 1147 unsigned max_backends_per_se; 1148 unsigned max_texture_channel_caches; 1149 unsigned max_gprs; 1150 unsigned max_gs_threads; 1151 unsigned max_hw_contexts; 1152 unsigned sc_prim_fifo_size_frontend; 1153 unsigned sc_prim_fifo_size_backend; 1154 unsigned sc_hiz_tile_fifo_size; 1155 unsigned sc_earlyz_tile_fifo_size; 1156 1157 unsigned num_tile_pipes; 1158 unsigned backend_enable_mask; 1159 unsigned mem_max_burst_length_bytes; 1160 unsigned mem_row_size_in_kb; 1161 unsigned shader_engine_tile_size; 1162 unsigned num_gpus; 1163 unsigned multi_gpu_tile_size; 1164 unsigned mc_arb_ramcfg; 1165 unsigned gb_addr_config; 1166 1167 uint32_t tile_mode_array[32]; 1168 uint32_t macrotile_mode_array[16]; 1169 }; 1170 1171 struct amdgpu_gfx { 1172 struct mutex gpu_clock_mutex; 1173 struct amdgpu_gca_config config; 1174 struct amdgpu_rlc rlc; 1175 struct amdgpu_mec mec; 1176 struct amdgpu_scratch scratch; 1177 const struct firmware *me_fw; /* ME firmware */ 1178 uint32_t me_fw_version; 1179 const struct firmware *pfp_fw; /* PFP firmware */ 1180 uint32_t pfp_fw_version; 1181 const struct firmware *ce_fw; /* CE firmware */ 1182 uint32_t ce_fw_version; 1183 const struct firmware *rlc_fw; /* RLC firmware */ 1184 uint32_t rlc_fw_version; 1185 const struct firmware *mec_fw; /* MEC firmware */ 1186 uint32_t mec_fw_version; 1187 const struct firmware *mec2_fw; /* MEC2 firmware */ 1188 uint32_t mec2_fw_version; 1189 uint32_t me_feature_version; 1190 uint32_t ce_feature_version; 1191 uint32_t pfp_feature_version; 1192 uint32_t rlc_feature_version; 1193 uint32_t mec_feature_version; 1194 uint32_t mec2_feature_version; 1195 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1196 unsigned num_gfx_rings; 1197 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1198 unsigned num_compute_rings; 1199 struct amdgpu_irq_src eop_irq; 1200 struct amdgpu_irq_src priv_reg_irq; 1201 struct amdgpu_irq_src priv_inst_irq; 1202 /* gfx status */ 1203 uint32_t gfx_current_status; 1204 /* sync signal for const engine */ 1205 unsigned ce_sync_offs; 1206 /* ce ram size*/ 1207 unsigned ce_ram_size; 1208 }; 1209 1210 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, 1211 unsigned size, struct amdgpu_ib *ib); 1212 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib); 1213 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, 1214 struct amdgpu_ib *ib, void *owner); 1215 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1216 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1217 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1218 /* Ring access between begin & end cannot sleep */ 1219 void amdgpu_ring_free_size(struct amdgpu_ring *ring); 1220 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1221 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw); 1222 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 1223 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1224 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); 1225 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1226 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); 1227 void amdgpu_ring_lockup_update(struct amdgpu_ring *ring); 1228 bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring); 1229 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1230 uint32_t **data); 1231 int amdgpu_ring_restore(struct amdgpu_ring *ring, 1232 unsigned size, uint32_t *data); 1233 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1234 unsigned ring_size, u32 nop, u32 align_mask, 1235 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1236 enum amdgpu_ring_type ring_type); 1237 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1238 1239 /* 1240 * CS. 1241 */ 1242 struct amdgpu_cs_chunk { 1243 uint32_t chunk_id; 1244 uint32_t length_dw; 1245 uint32_t *kdata; 1246 void __user *user_ptr; 1247 }; 1248 1249 struct amdgpu_cs_parser { 1250 struct amdgpu_device *adev; 1251 struct drm_file *filp; 1252 struct amdgpu_ctx *ctx; 1253 struct amdgpu_bo_list *bo_list; 1254 /* chunks */ 1255 unsigned nchunks; 1256 struct amdgpu_cs_chunk *chunks; 1257 /* relocations */ 1258 struct amdgpu_bo_list_entry *vm_bos; 1259 struct list_head validated; 1260 1261 struct amdgpu_ib *ibs; 1262 uint32_t num_ibs; 1263 1264 struct ww_acquire_ctx ticket; 1265 1266 /* user fence */ 1267 struct amdgpu_user_fence uf; 1268 }; 1269 1270 struct amdgpu_job { 1271 struct amd_sched_job base; 1272 struct amdgpu_device *adev; 1273 struct amdgpu_ib *ibs; 1274 uint32_t num_ibs; 1275 struct mutex job_lock; 1276 struct amdgpu_user_fence uf; 1277 int (*free_job)(struct amdgpu_job *sched_job); 1278 }; 1279 1280 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx) 1281 { 1282 return p->ibs[ib_idx].ptr[idx]; 1283 } 1284 1285 /* 1286 * Writeback 1287 */ 1288 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1289 1290 struct amdgpu_wb { 1291 struct amdgpu_bo *wb_obj; 1292 volatile uint32_t *wb; 1293 uint64_t gpu_addr; 1294 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1295 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1296 }; 1297 1298 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1299 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1300 1301 /** 1302 * struct amdgpu_pm - power management datas 1303 * It keeps track of various data needed to take powermanagement decision. 1304 */ 1305 1306 enum amdgpu_pm_state_type { 1307 /* not used for dpm */ 1308 POWER_STATE_TYPE_DEFAULT, 1309 POWER_STATE_TYPE_POWERSAVE, 1310 /* user selectable states */ 1311 POWER_STATE_TYPE_BATTERY, 1312 POWER_STATE_TYPE_BALANCED, 1313 POWER_STATE_TYPE_PERFORMANCE, 1314 /* internal states */ 1315 POWER_STATE_TYPE_INTERNAL_UVD, 1316 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1317 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1318 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1319 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1320 POWER_STATE_TYPE_INTERNAL_BOOT, 1321 POWER_STATE_TYPE_INTERNAL_THERMAL, 1322 POWER_STATE_TYPE_INTERNAL_ACPI, 1323 POWER_STATE_TYPE_INTERNAL_ULV, 1324 POWER_STATE_TYPE_INTERNAL_3DPERF, 1325 }; 1326 1327 enum amdgpu_int_thermal_type { 1328 THERMAL_TYPE_NONE, 1329 THERMAL_TYPE_EXTERNAL, 1330 THERMAL_TYPE_EXTERNAL_GPIO, 1331 THERMAL_TYPE_RV6XX, 1332 THERMAL_TYPE_RV770, 1333 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1334 THERMAL_TYPE_EVERGREEN, 1335 THERMAL_TYPE_SUMO, 1336 THERMAL_TYPE_NI, 1337 THERMAL_TYPE_SI, 1338 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1339 THERMAL_TYPE_CI, 1340 THERMAL_TYPE_KV, 1341 }; 1342 1343 enum amdgpu_dpm_auto_throttle_src { 1344 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1345 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1346 }; 1347 1348 enum amdgpu_dpm_event_src { 1349 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1350 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1351 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1352 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1353 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1354 }; 1355 1356 #define AMDGPU_MAX_VCE_LEVELS 6 1357 1358 enum amdgpu_vce_level { 1359 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1360 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1361 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1362 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1363 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1364 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1365 }; 1366 1367 struct amdgpu_ps { 1368 u32 caps; /* vbios flags */ 1369 u32 class; /* vbios flags */ 1370 u32 class2; /* vbios flags */ 1371 /* UVD clocks */ 1372 u32 vclk; 1373 u32 dclk; 1374 /* VCE clocks */ 1375 u32 evclk; 1376 u32 ecclk; 1377 bool vce_active; 1378 enum amdgpu_vce_level vce_level; 1379 /* asic priv */ 1380 void *ps_priv; 1381 }; 1382 1383 struct amdgpu_dpm_thermal { 1384 /* thermal interrupt work */ 1385 struct work_struct work; 1386 /* low temperature threshold */ 1387 int min_temp; 1388 /* high temperature threshold */ 1389 int max_temp; 1390 /* was last interrupt low to high or high to low */ 1391 bool high_to_low; 1392 /* interrupt source */ 1393 struct amdgpu_irq_src irq; 1394 }; 1395 1396 enum amdgpu_clk_action 1397 { 1398 AMDGPU_SCLK_UP = 1, 1399 AMDGPU_SCLK_DOWN 1400 }; 1401 1402 struct amdgpu_blacklist_clocks 1403 { 1404 u32 sclk; 1405 u32 mclk; 1406 enum amdgpu_clk_action action; 1407 }; 1408 1409 struct amdgpu_clock_and_voltage_limits { 1410 u32 sclk; 1411 u32 mclk; 1412 u16 vddc; 1413 u16 vddci; 1414 }; 1415 1416 struct amdgpu_clock_array { 1417 u32 count; 1418 u32 *values; 1419 }; 1420 1421 struct amdgpu_clock_voltage_dependency_entry { 1422 u32 clk; 1423 u16 v; 1424 }; 1425 1426 struct amdgpu_clock_voltage_dependency_table { 1427 u32 count; 1428 struct amdgpu_clock_voltage_dependency_entry *entries; 1429 }; 1430 1431 union amdgpu_cac_leakage_entry { 1432 struct { 1433 u16 vddc; 1434 u32 leakage; 1435 }; 1436 struct { 1437 u16 vddc1; 1438 u16 vddc2; 1439 u16 vddc3; 1440 }; 1441 }; 1442 1443 struct amdgpu_cac_leakage_table { 1444 u32 count; 1445 union amdgpu_cac_leakage_entry *entries; 1446 }; 1447 1448 struct amdgpu_phase_shedding_limits_entry { 1449 u16 voltage; 1450 u32 sclk; 1451 u32 mclk; 1452 }; 1453 1454 struct amdgpu_phase_shedding_limits_table { 1455 u32 count; 1456 struct amdgpu_phase_shedding_limits_entry *entries; 1457 }; 1458 1459 struct amdgpu_uvd_clock_voltage_dependency_entry { 1460 u32 vclk; 1461 u32 dclk; 1462 u16 v; 1463 }; 1464 1465 struct amdgpu_uvd_clock_voltage_dependency_table { 1466 u8 count; 1467 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1468 }; 1469 1470 struct amdgpu_vce_clock_voltage_dependency_entry { 1471 u32 ecclk; 1472 u32 evclk; 1473 u16 v; 1474 }; 1475 1476 struct amdgpu_vce_clock_voltage_dependency_table { 1477 u8 count; 1478 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1479 }; 1480 1481 struct amdgpu_ppm_table { 1482 u8 ppm_design; 1483 u16 cpu_core_number; 1484 u32 platform_tdp; 1485 u32 small_ac_platform_tdp; 1486 u32 platform_tdc; 1487 u32 small_ac_platform_tdc; 1488 u32 apu_tdp; 1489 u32 dgpu_tdp; 1490 u32 dgpu_ulv_power; 1491 u32 tj_max; 1492 }; 1493 1494 struct amdgpu_cac_tdp_table { 1495 u16 tdp; 1496 u16 configurable_tdp; 1497 u16 tdc; 1498 u16 battery_power_limit; 1499 u16 small_power_limit; 1500 u16 low_cac_leakage; 1501 u16 high_cac_leakage; 1502 u16 maximum_power_delivery_limit; 1503 }; 1504 1505 struct amdgpu_dpm_dynamic_state { 1506 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1507 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1508 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1509 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1510 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1511 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1512 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1513 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1514 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1515 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1516 struct amdgpu_clock_array valid_sclk_values; 1517 struct amdgpu_clock_array valid_mclk_values; 1518 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1519 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1520 u32 mclk_sclk_ratio; 1521 u32 sclk_mclk_delta; 1522 u16 vddc_vddci_delta; 1523 u16 min_vddc_for_pcie_gen2; 1524 struct amdgpu_cac_leakage_table cac_leakage_table; 1525 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1526 struct amdgpu_ppm_table *ppm_table; 1527 struct amdgpu_cac_tdp_table *cac_tdp_table; 1528 }; 1529 1530 struct amdgpu_dpm_fan { 1531 u16 t_min; 1532 u16 t_med; 1533 u16 t_high; 1534 u16 pwm_min; 1535 u16 pwm_med; 1536 u16 pwm_high; 1537 u8 t_hyst; 1538 u32 cycle_delay; 1539 u16 t_max; 1540 u8 control_mode; 1541 u16 default_max_fan_pwm; 1542 u16 default_fan_output_sensitivity; 1543 u16 fan_output_sensitivity; 1544 bool ucode_fan_control; 1545 }; 1546 1547 enum amdgpu_pcie_gen { 1548 AMDGPU_PCIE_GEN1 = 0, 1549 AMDGPU_PCIE_GEN2 = 1, 1550 AMDGPU_PCIE_GEN3 = 2, 1551 AMDGPU_PCIE_GEN_INVALID = 0xffff 1552 }; 1553 1554 enum amdgpu_dpm_forced_level { 1555 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1556 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1557 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1558 }; 1559 1560 struct amdgpu_vce_state { 1561 /* vce clocks */ 1562 u32 evclk; 1563 u32 ecclk; 1564 /* gpu clocks */ 1565 u32 sclk; 1566 u32 mclk; 1567 u8 clk_idx; 1568 u8 pstate; 1569 }; 1570 1571 struct amdgpu_dpm_funcs { 1572 int (*get_temperature)(struct amdgpu_device *adev); 1573 int (*pre_set_power_state)(struct amdgpu_device *adev); 1574 int (*set_power_state)(struct amdgpu_device *adev); 1575 void (*post_set_power_state)(struct amdgpu_device *adev); 1576 void (*display_configuration_changed)(struct amdgpu_device *adev); 1577 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1578 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1579 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1580 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1581 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1582 bool (*vblank_too_short)(struct amdgpu_device *adev); 1583 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1584 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1585 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1586 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1587 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1588 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1589 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1590 }; 1591 1592 struct amdgpu_dpm { 1593 struct amdgpu_ps *ps; 1594 /* number of valid power states */ 1595 int num_ps; 1596 /* current power state that is active */ 1597 struct amdgpu_ps *current_ps; 1598 /* requested power state */ 1599 struct amdgpu_ps *requested_ps; 1600 /* boot up power state */ 1601 struct amdgpu_ps *boot_ps; 1602 /* default uvd power state */ 1603 struct amdgpu_ps *uvd_ps; 1604 /* vce requirements */ 1605 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1606 enum amdgpu_vce_level vce_level; 1607 enum amdgpu_pm_state_type state; 1608 enum amdgpu_pm_state_type user_state; 1609 u32 platform_caps; 1610 u32 voltage_response_time; 1611 u32 backbias_response_time; 1612 void *priv; 1613 u32 new_active_crtcs; 1614 int new_active_crtc_count; 1615 u32 current_active_crtcs; 1616 int current_active_crtc_count; 1617 struct amdgpu_dpm_dynamic_state dyn_state; 1618 struct amdgpu_dpm_fan fan; 1619 u32 tdp_limit; 1620 u32 near_tdp_limit; 1621 u32 near_tdp_limit_adjusted; 1622 u32 sq_ramping_threshold; 1623 u32 cac_leakage; 1624 u16 tdp_od_limit; 1625 u32 tdp_adjustment; 1626 u16 load_line_slope; 1627 bool power_control; 1628 bool ac_power; 1629 /* special states active */ 1630 bool thermal_active; 1631 bool uvd_active; 1632 bool vce_active; 1633 /* thermal handling */ 1634 struct amdgpu_dpm_thermal thermal; 1635 /* forced levels */ 1636 enum amdgpu_dpm_forced_level forced_level; 1637 }; 1638 1639 struct amdgpu_pm { 1640 struct mutex mutex; 1641 u32 current_sclk; 1642 u32 current_mclk; 1643 u32 default_sclk; 1644 u32 default_mclk; 1645 struct amdgpu_i2c_chan *i2c_bus; 1646 /* internal thermal controller on rv6xx+ */ 1647 enum amdgpu_int_thermal_type int_thermal_type; 1648 struct device *int_hwmon_dev; 1649 /* fan control parameters */ 1650 bool no_fan; 1651 u8 fan_pulses_per_revolution; 1652 u8 fan_min_rpm; 1653 u8 fan_max_rpm; 1654 /* dpm */ 1655 bool dpm_enabled; 1656 struct amdgpu_dpm dpm; 1657 const struct firmware *fw; /* SMC firmware */ 1658 uint32_t fw_version; 1659 const struct amdgpu_dpm_funcs *funcs; 1660 }; 1661 1662 /* 1663 * UVD 1664 */ 1665 #define AMDGPU_MAX_UVD_HANDLES 10 1666 #define AMDGPU_UVD_STACK_SIZE (1024*1024) 1667 #define AMDGPU_UVD_HEAP_SIZE (1024*1024) 1668 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1669 1670 struct amdgpu_uvd { 1671 struct amdgpu_bo *vcpu_bo; 1672 void *cpu_addr; 1673 uint64_t gpu_addr; 1674 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1675 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1676 struct delayed_work idle_work; 1677 const struct firmware *fw; /* UVD firmware */ 1678 struct amdgpu_ring ring; 1679 struct amdgpu_irq_src irq; 1680 bool address_64_bit; 1681 }; 1682 1683 /* 1684 * VCE 1685 */ 1686 #define AMDGPU_MAX_VCE_HANDLES 16 1687 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1688 1689 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1690 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1691 1692 struct amdgpu_vce { 1693 struct amdgpu_bo *vcpu_bo; 1694 uint64_t gpu_addr; 1695 unsigned fw_version; 1696 unsigned fb_version; 1697 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1698 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1699 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1700 struct delayed_work idle_work; 1701 const struct firmware *fw; /* VCE firmware */ 1702 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1703 struct amdgpu_irq_src irq; 1704 unsigned harvest_config; 1705 }; 1706 1707 /* 1708 * SDMA 1709 */ 1710 struct amdgpu_sdma { 1711 /* SDMA firmware */ 1712 const struct firmware *fw; 1713 uint32_t fw_version; 1714 uint32_t feature_version; 1715 1716 struct amdgpu_ring ring; 1717 bool burst_nop; 1718 }; 1719 1720 /* 1721 * Firmware 1722 */ 1723 struct amdgpu_firmware { 1724 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1725 bool smu_load; 1726 struct amdgpu_bo *fw_buf; 1727 unsigned int fw_size; 1728 }; 1729 1730 /* 1731 * Benchmarking 1732 */ 1733 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1734 1735 1736 /* 1737 * Testing 1738 */ 1739 void amdgpu_test_moves(struct amdgpu_device *adev); 1740 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1741 struct amdgpu_ring *cpA, 1742 struct amdgpu_ring *cpB); 1743 void amdgpu_test_syncing(struct amdgpu_device *adev); 1744 1745 /* 1746 * MMU Notifier 1747 */ 1748 #if defined(CONFIG_MMU_NOTIFIER) 1749 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1750 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1751 #else 1752 static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1753 { 1754 return -ENODEV; 1755 } 1756 static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1757 #endif 1758 1759 /* 1760 * Debugfs 1761 */ 1762 struct amdgpu_debugfs { 1763 struct drm_info_list *files; 1764 unsigned num_files; 1765 }; 1766 1767 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1768 struct drm_info_list *files, 1769 unsigned nfiles); 1770 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1771 1772 #if defined(CONFIG_DEBUG_FS) 1773 int amdgpu_debugfs_init(struct drm_minor *minor); 1774 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1775 #endif 1776 1777 /* 1778 * amdgpu smumgr functions 1779 */ 1780 struct amdgpu_smumgr_funcs { 1781 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1782 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1783 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1784 }; 1785 1786 /* 1787 * amdgpu smumgr 1788 */ 1789 struct amdgpu_smumgr { 1790 struct amdgpu_bo *toc_buf; 1791 struct amdgpu_bo *smu_buf; 1792 /* asic priv smu data */ 1793 void *priv; 1794 spinlock_t smu_lock; 1795 /* smumgr functions */ 1796 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1797 /* ucode loading complete flag */ 1798 uint32_t fw_flags; 1799 }; 1800 1801 /* 1802 * ASIC specific register table accessible by UMD 1803 */ 1804 struct amdgpu_allowed_register_entry { 1805 uint32_t reg_offset; 1806 bool untouched; 1807 bool grbm_indexed; 1808 }; 1809 1810 struct amdgpu_cu_info { 1811 uint32_t number; /* total active CU number */ 1812 uint32_t ao_cu_mask; 1813 uint32_t bitmap[4][4]; 1814 }; 1815 1816 1817 /* 1818 * ASIC specific functions. 1819 */ 1820 struct amdgpu_asic_funcs { 1821 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1822 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1823 u32 sh_num, u32 reg_offset, u32 *value); 1824 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1825 int (*reset)(struct amdgpu_device *adev); 1826 /* wait for mc_idle */ 1827 int (*wait_for_mc_idle)(struct amdgpu_device *adev); 1828 /* get the reference clock */ 1829 u32 (*get_xclk)(struct amdgpu_device *adev); 1830 /* get the gpu clock counter */ 1831 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1832 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); 1833 /* MM block clocks */ 1834 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1835 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1836 }; 1837 1838 /* 1839 * IOCTL. 1840 */ 1841 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1842 struct drm_file *filp); 1843 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1844 struct drm_file *filp); 1845 1846 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1847 struct drm_file *filp); 1848 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1849 struct drm_file *filp); 1850 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1851 struct drm_file *filp); 1852 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1853 struct drm_file *filp); 1854 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1855 struct drm_file *filp); 1856 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1857 struct drm_file *filp); 1858 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1859 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1860 1861 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1862 struct drm_file *filp); 1863 1864 /* VRAM scratch page for HDP bug, default vram page */ 1865 struct amdgpu_vram_scratch { 1866 struct amdgpu_bo *robj; 1867 volatile uint32_t *ptr; 1868 u64 gpu_addr; 1869 }; 1870 1871 /* 1872 * ACPI 1873 */ 1874 struct amdgpu_atif_notification_cfg { 1875 bool enabled; 1876 int command_code; 1877 }; 1878 1879 struct amdgpu_atif_notifications { 1880 bool display_switch; 1881 bool expansion_mode_change; 1882 bool thermal_state; 1883 bool forced_power_state; 1884 bool system_power_state; 1885 bool display_conf_change; 1886 bool px_gfx_switch; 1887 bool brightness_change; 1888 bool dgpu_display_event; 1889 }; 1890 1891 struct amdgpu_atif_functions { 1892 bool system_params; 1893 bool sbios_requests; 1894 bool select_active_disp; 1895 bool lid_state; 1896 bool get_tv_standard; 1897 bool set_tv_standard; 1898 bool get_panel_expansion_mode; 1899 bool set_panel_expansion_mode; 1900 bool temperature_change; 1901 bool graphics_device_types; 1902 }; 1903 1904 struct amdgpu_atif { 1905 struct amdgpu_atif_notifications notifications; 1906 struct amdgpu_atif_functions functions; 1907 struct amdgpu_atif_notification_cfg notification_cfg; 1908 struct amdgpu_encoder *encoder_for_bl; 1909 }; 1910 1911 struct amdgpu_atcs_functions { 1912 bool get_ext_state; 1913 bool pcie_perf_req; 1914 bool pcie_dev_rdy; 1915 bool pcie_bus_width; 1916 }; 1917 1918 struct amdgpu_atcs { 1919 struct amdgpu_atcs_functions functions; 1920 }; 1921 1922 /* 1923 * CGS 1924 */ 1925 void *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1926 void amdgpu_cgs_destroy_device(void *cgs_device); 1927 1928 1929 /* 1930 * Core structure, functions and helpers. 1931 */ 1932 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1933 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1934 1935 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1936 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1937 1938 struct amdgpu_ip_block_status { 1939 bool valid; 1940 bool sw; 1941 bool hw; 1942 }; 1943 1944 struct amdgpu_device { 1945 struct device *dev; 1946 struct drm_device *ddev; 1947 struct pci_dev *pdev; 1948 struct rw_semaphore exclusive_lock; 1949 1950 /* ASIC */ 1951 enum amd_asic_type asic_type; 1952 uint32_t family; 1953 uint32_t rev_id; 1954 uint32_t external_rev_id; 1955 unsigned long flags; 1956 int usec_timeout; 1957 const struct amdgpu_asic_funcs *asic_funcs; 1958 bool shutdown; 1959 bool suspend; 1960 bool need_dma32; 1961 bool accel_working; 1962 bool needs_reset; 1963 struct work_struct reset_work; 1964 struct notifier_block acpi_nb; 1965 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1966 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1967 unsigned debugfs_count; 1968 #if defined(CONFIG_DEBUG_FS) 1969 struct dentry *debugfs_regs; 1970 #endif 1971 struct amdgpu_atif atif; 1972 struct amdgpu_atcs atcs; 1973 struct mutex srbm_mutex; 1974 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1975 struct mutex grbm_idx_mutex; 1976 struct dev_pm_domain vga_pm_domain; 1977 bool have_disp_power_ref; 1978 1979 /* BIOS */ 1980 uint8_t *bios; 1981 bool is_atom_bios; 1982 uint16_t bios_header_start; 1983 struct amdgpu_bo *stollen_vga_memory; 1984 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1985 1986 /* Register/doorbell mmio */ 1987 resource_size_t rmmio_base; 1988 resource_size_t rmmio_size; 1989 void __iomem *rmmio; 1990 /* protects concurrent MM_INDEX/DATA based register access */ 1991 spinlock_t mmio_idx_lock; 1992 /* protects concurrent SMC based register access */ 1993 spinlock_t smc_idx_lock; 1994 amdgpu_rreg_t smc_rreg; 1995 amdgpu_wreg_t smc_wreg; 1996 /* protects concurrent PCIE register access */ 1997 spinlock_t pcie_idx_lock; 1998 amdgpu_rreg_t pcie_rreg; 1999 amdgpu_wreg_t pcie_wreg; 2000 /* protects concurrent UVD register access */ 2001 spinlock_t uvd_ctx_idx_lock; 2002 amdgpu_rreg_t uvd_ctx_rreg; 2003 amdgpu_wreg_t uvd_ctx_wreg; 2004 /* protects concurrent DIDT register access */ 2005 spinlock_t didt_idx_lock; 2006 amdgpu_rreg_t didt_rreg; 2007 amdgpu_wreg_t didt_wreg; 2008 /* protects concurrent ENDPOINT (audio) register access */ 2009 spinlock_t audio_endpt_idx_lock; 2010 amdgpu_block_rreg_t audio_endpt_rreg; 2011 amdgpu_block_wreg_t audio_endpt_wreg; 2012 void __iomem *rio_mem; 2013 resource_size_t rio_mem_size; 2014 struct amdgpu_doorbell doorbell; 2015 2016 /* clock/pll info */ 2017 struct amdgpu_clock clock; 2018 2019 /* MC */ 2020 struct amdgpu_mc mc; 2021 struct amdgpu_gart gart; 2022 struct amdgpu_dummy_page dummy_page; 2023 struct amdgpu_vm_manager vm_manager; 2024 2025 /* memory management */ 2026 struct amdgpu_mman mman; 2027 struct amdgpu_gem gem; 2028 struct amdgpu_vram_scratch vram_scratch; 2029 struct amdgpu_wb wb; 2030 atomic64_t vram_usage; 2031 atomic64_t vram_vis_usage; 2032 atomic64_t gtt_usage; 2033 atomic64_t num_bytes_moved; 2034 atomic_t gpu_reset_counter; 2035 2036 /* display */ 2037 struct amdgpu_mode_info mode_info; 2038 struct work_struct hotplug_work; 2039 struct amdgpu_irq_src crtc_irq; 2040 struct amdgpu_irq_src pageflip_irq; 2041 struct amdgpu_irq_src hpd_irq; 2042 2043 /* rings */ 2044 unsigned fence_context; 2045 struct mutex ring_lock; 2046 unsigned num_rings; 2047 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 2048 bool ib_pool_ready; 2049 struct amdgpu_sa_manager ring_tmp_bo; 2050 2051 /* interrupts */ 2052 struct amdgpu_irq irq; 2053 2054 /* dpm */ 2055 struct amdgpu_pm pm; 2056 u32 cg_flags; 2057 u32 pg_flags; 2058 2059 /* amdgpu smumgr */ 2060 struct amdgpu_smumgr smu; 2061 2062 /* gfx */ 2063 struct amdgpu_gfx gfx; 2064 2065 /* sdma */ 2066 struct amdgpu_sdma sdma[AMDGPU_MAX_SDMA_INSTANCES]; 2067 struct amdgpu_irq_src sdma_trap_irq; 2068 struct amdgpu_irq_src sdma_illegal_inst_irq; 2069 2070 /* uvd */ 2071 bool has_uvd; 2072 struct amdgpu_uvd uvd; 2073 2074 /* vce */ 2075 struct amdgpu_vce vce; 2076 2077 /* firmwares */ 2078 struct amdgpu_firmware firmware; 2079 2080 /* GDS */ 2081 struct amdgpu_gds gds; 2082 2083 const struct amdgpu_ip_block_version *ip_blocks; 2084 int num_ip_blocks; 2085 struct amdgpu_ip_block_status *ip_block_status; 2086 struct mutex mn_lock; 2087 DECLARE_HASHTABLE(mn_hash, 7); 2088 2089 /* tracking pinned memory */ 2090 u64 vram_pin_size; 2091 u64 gart_pin_size; 2092 2093 /* amdkfd interface */ 2094 struct kfd_dev *kfd; 2095 2096 /* kernel conext for IB submission */ 2097 struct amdgpu_ctx kernel_ctx; 2098 }; 2099 2100 bool amdgpu_device_is_px(struct drm_device *dev); 2101 int amdgpu_device_init(struct amdgpu_device *adev, 2102 struct drm_device *ddev, 2103 struct pci_dev *pdev, 2104 uint32_t flags); 2105 void amdgpu_device_fini(struct amdgpu_device *adev); 2106 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2107 2108 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2109 bool always_indirect); 2110 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2111 bool always_indirect); 2112 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2113 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2114 2115 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2116 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2117 2118 /* 2119 * Cast helper 2120 */ 2121 extern const struct fence_ops amdgpu_fence_ops; 2122 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) 2123 { 2124 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 2125 2126 if (__f->base.ops == &amdgpu_fence_ops) 2127 return __f; 2128 2129 return NULL; 2130 } 2131 2132 /* 2133 * Registers read & write functions. 2134 */ 2135 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2136 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2137 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2138 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2139 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2140 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2141 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2142 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2143 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2144 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2145 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2146 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2147 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2148 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2149 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2150 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2151 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2152 #define WREG32_P(reg, val, mask) \ 2153 do { \ 2154 uint32_t tmp_ = RREG32(reg); \ 2155 tmp_ &= (mask); \ 2156 tmp_ |= ((val) & ~(mask)); \ 2157 WREG32(reg, tmp_); \ 2158 } while (0) 2159 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2160 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2161 #define WREG32_PLL_P(reg, val, mask) \ 2162 do { \ 2163 uint32_t tmp_ = RREG32_PLL(reg); \ 2164 tmp_ &= (mask); \ 2165 tmp_ |= ((val) & ~(mask)); \ 2166 WREG32_PLL(reg, tmp_); \ 2167 } while (0) 2168 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2169 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2170 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2171 2172 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2173 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2174 2175 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2176 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2177 2178 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2179 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2180 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2181 2182 #define REG_GET_FIELD(value, reg, field) \ 2183 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2184 2185 /* 2186 * BIOS helpers. 2187 */ 2188 #define RBIOS8(i) (adev->bios[i]) 2189 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2190 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2191 2192 /* 2193 * RING helpers. 2194 */ 2195 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2196 { 2197 if (ring->count_dw <= 0) 2198 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2199 ring->ring[ring->wptr++] = v; 2200 ring->wptr &= ring->ptr_mask; 2201 ring->count_dw--; 2202 ring->ring_free_dw--; 2203 } 2204 2205 static inline struct amdgpu_sdma * amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 2206 { 2207 struct amdgpu_device *adev = ring->adev; 2208 int i; 2209 2210 for (i = 0; i < AMDGPU_MAX_SDMA_INSTANCES; i++) 2211 if (&adev->sdma[i].ring == ring) 2212 break; 2213 2214 if (i < AMDGPU_MAX_SDMA_INSTANCES) 2215 return &adev->sdma[i]; 2216 else 2217 return NULL; 2218 } 2219 2220 /* 2221 * ASICs macro. 2222 */ 2223 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2224 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2225 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) 2226 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2227 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2228 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2229 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2230 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2231 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2232 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) 2233 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2234 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2235 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2236 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags))) 2237 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2238 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib))) 2239 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2240 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2241 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2242 #define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r)) 2243 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2244 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2245 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2246 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) 2247 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2248 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2249 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) 2250 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2251 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2252 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2253 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2254 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2255 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2256 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2257 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2258 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2259 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2260 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2261 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2262 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2263 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2264 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2265 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) 2266 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2267 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2268 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2269 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2270 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2271 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 2272 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 2273 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev)) 2274 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2275 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2276 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2277 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2278 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l)) 2279 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l)) 2280 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2281 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)) 2282 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l)) 2283 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2284 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g)) 2285 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g)) 2286 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2287 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m)) 2288 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev)) 2289 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s)) 2290 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s)) 2291 2292 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2293 2294 /* Common functions */ 2295 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2296 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2297 bool amdgpu_card_posted(struct amdgpu_device *adev); 2298 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2299 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev); 2300 struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev, 2301 struct drm_file *filp, 2302 struct amdgpu_ctx *ctx, 2303 struct amdgpu_ib *ibs, 2304 uint32_t num_ibs); 2305 2306 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2307 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2308 u32 ip_instance, u32 ring, 2309 struct amdgpu_ring **out_ring); 2310 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2311 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2312 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2313 uint32_t flags); 2314 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2315 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2316 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2317 struct ttm_mem_reg *mem); 2318 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2319 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2320 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2321 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2322 const u32 *registers, 2323 const u32 array_size); 2324 2325 bool amdgpu_device_is_px(struct drm_device *dev); 2326 /* atpx handler */ 2327 #if defined(CONFIG_VGA_SWITCHEROO) 2328 void amdgpu_register_atpx_handler(void); 2329 void amdgpu_unregister_atpx_handler(void); 2330 #else 2331 static inline void amdgpu_register_atpx_handler(void) {} 2332 static inline void amdgpu_unregister_atpx_handler(void) {} 2333 #endif 2334 2335 /* 2336 * KMS 2337 */ 2338 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2339 extern int amdgpu_max_kms_ioctl; 2340 2341 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2342 int amdgpu_driver_unload_kms(struct drm_device *dev); 2343 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2344 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2345 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2346 struct drm_file *file_priv); 2347 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2348 struct drm_file *file_priv); 2349 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2350 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2351 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc); 2352 int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc); 2353 void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc); 2354 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 2355 int *max_error, 2356 struct timeval *vblank_time, 2357 unsigned flags); 2358 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2359 unsigned long arg); 2360 2361 /* 2362 * vm 2363 */ 2364 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 2365 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 2366 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, 2367 struct amdgpu_vm *vm, 2368 struct list_head *head); 2369 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 2370 struct amdgpu_sync *sync); 2371 void amdgpu_vm_flush(struct amdgpu_ring *ring, 2372 struct amdgpu_vm *vm, 2373 struct fence *updates); 2374 void amdgpu_vm_fence(struct amdgpu_device *adev, 2375 struct amdgpu_vm *vm, 2376 struct amdgpu_fence *fence); 2377 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); 2378 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 2379 struct amdgpu_vm *vm); 2380 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 2381 struct amdgpu_vm *vm); 2382 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, 2383 struct amdgpu_vm *vm, struct amdgpu_sync *sync); 2384 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 2385 struct amdgpu_bo_va *bo_va, 2386 struct ttm_mem_reg *mem); 2387 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 2388 struct amdgpu_bo *bo); 2389 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 2390 struct amdgpu_bo *bo); 2391 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 2392 struct amdgpu_vm *vm, 2393 struct amdgpu_bo *bo); 2394 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 2395 struct amdgpu_bo_va *bo_va, 2396 uint64_t addr, uint64_t offset, 2397 uint64_t size, uint32_t flags); 2398 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 2399 struct amdgpu_bo_va *bo_va, 2400 uint64_t addr); 2401 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 2402 struct amdgpu_bo_va *bo_va); 2403 int amdgpu_vm_free_job(struct amdgpu_job *job); 2404 /* 2405 * functions used by amdgpu_encoder.c 2406 */ 2407 struct amdgpu_afmt_acr { 2408 u32 clock; 2409 2410 int n_32khz; 2411 int cts_32khz; 2412 2413 int n_44_1khz; 2414 int cts_44_1khz; 2415 2416 int n_48khz; 2417 int cts_48khz; 2418 2419 }; 2420 2421 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2422 2423 /* amdgpu_acpi.c */ 2424 #if defined(CONFIG_ACPI) 2425 int amdgpu_acpi_init(struct amdgpu_device *adev); 2426 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2427 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2428 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2429 u8 perf_req, bool advertise); 2430 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2431 #else 2432 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2433 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2434 #endif 2435 2436 struct amdgpu_bo_va_mapping * 2437 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2438 uint64_t addr, struct amdgpu_bo **bo); 2439 2440 #include "amdgpu_object.h" 2441 2442 #endif 2443