197b2e202SAlex Deucher /* 297b2e202SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 397b2e202SAlex Deucher * Copyright 2008 Red Hat Inc. 497b2e202SAlex Deucher * Copyright 2009 Jerome Glisse. 597b2e202SAlex Deucher * 697b2e202SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 797b2e202SAlex Deucher * copy of this software and associated documentation files (the "Software"), 897b2e202SAlex Deucher * to deal in the Software without restriction, including without limitation 997b2e202SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1097b2e202SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1197b2e202SAlex Deucher * Software is furnished to do so, subject to the following conditions: 1297b2e202SAlex Deucher * 1397b2e202SAlex Deucher * The above copyright notice and this permission notice shall be included in 1497b2e202SAlex Deucher * all copies or substantial portions of the Software. 1597b2e202SAlex Deucher * 1697b2e202SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1797b2e202SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1897b2e202SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1997b2e202SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2097b2e202SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2197b2e202SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2297b2e202SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2397b2e202SAlex Deucher * 2497b2e202SAlex Deucher * Authors: Dave Airlie 2597b2e202SAlex Deucher * Alex Deucher 2697b2e202SAlex Deucher * Jerome Glisse 2797b2e202SAlex Deucher */ 2897b2e202SAlex Deucher #ifndef __AMDGPU_H__ 2997b2e202SAlex Deucher #define __AMDGPU_H__ 3097b2e202SAlex Deucher 3197b2e202SAlex Deucher #include <linux/atomic.h> 3297b2e202SAlex Deucher #include <linux/wait.h> 3397b2e202SAlex Deucher #include <linux/list.h> 3497b2e202SAlex Deucher #include <linux/kref.h> 35a9f87f64SChristian König #include <linux/rbtree.h> 3697b2e202SAlex Deucher #include <linux/hashtable.h> 37f54d1867SChris Wilson #include <linux/dma-fence.h> 3897b2e202SAlex Deucher 39248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_bo_api.h> 40248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_bo_driver.h> 41248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_placement.h> 42248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_module.h> 43248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_execbuf_util.h> 4497b2e202SAlex Deucher 45d03846afSChunming Zhou #include <drm/drmP.h> 4697b2e202SAlex Deucher #include <drm/drm_gem.h> 477e5a547fSChunming Zhou #include <drm/amdgpu_drm.h> 4897b2e202SAlex Deucher 4978c16834SAndres Rodriguez #include <kgd_kfd_interface.h> 5078c16834SAndres Rodriguez 515fc3aeebSyanyang1 #include "amd_shared.h" 5297b2e202SAlex Deucher #include "amdgpu_mode.h" 5397b2e202SAlex Deucher #include "amdgpu_ih.h" 5497b2e202SAlex Deucher #include "amdgpu_irq.h" 5597b2e202SAlex Deucher #include "amdgpu_ucode.h" 56c632d799SFlora Cui #include "amdgpu_ttm.h" 570e5ca0d1SHuang Rui #include "amdgpu_psp.h" 5897b2e202SAlex Deucher #include "amdgpu_gds.h" 5956113504SChristian König #include "amdgpu_sync.h" 6078023016SChristian König #include "amdgpu_ring.h" 61073440d2SChristian König #include "amdgpu_vm.h" 621f7371b2SAlex Deucher #include "amd_powerplay.h" 63cf097881SAlex Deucher #include "amdgpu_dpm.h" 64a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h" 654df654d2SLeo Liu #include "amdgpu_uvd.h" 665e568178SLeo Liu #include "amdgpu_vce.h" 6795aa13f6SLeo Liu #include "amdgpu_vcn.h" 689a189996SChristian König #include "amdgpu_mn.h" 6997b2e202SAlex Deucher 70b80d8475SAlex Deucher #include "gpu_scheduler.h" 71ceeb50edSMonk Liu #include "amdgpu_virt.h" 723490bdb5SChristian König #include "amdgpu_gart.h" 73b80d8475SAlex Deucher 7497b2e202SAlex Deucher /* 7597b2e202SAlex Deucher * Modules parameters. 7697b2e202SAlex Deucher */ 7797b2e202SAlex Deucher extern int amdgpu_modeset; 7897b2e202SAlex Deucher extern int amdgpu_vram_limit; 79218b5dcdSJohn Brooks extern int amdgpu_vis_vram_limit; 8083e74db6SAlex Deucher extern int amdgpu_gart_size; 8136d38372SChristian König extern int amdgpu_gtt_size; 8295844d20SMarek Olšák extern int amdgpu_moverate; 8397b2e202SAlex Deucher extern int amdgpu_benchmarking; 8497b2e202SAlex Deucher extern int amdgpu_testing; 8597b2e202SAlex Deucher extern int amdgpu_audio; 8697b2e202SAlex Deucher extern int amdgpu_disp_priority; 8797b2e202SAlex Deucher extern int amdgpu_hw_i2c; 8897b2e202SAlex Deucher extern int amdgpu_pcie_gen2; 8997b2e202SAlex Deucher extern int amdgpu_msi; 9097b2e202SAlex Deucher extern int amdgpu_lockup_timeout; 9197b2e202SAlex Deucher extern int amdgpu_dpm; 92e635ee07SHuang Rui extern int amdgpu_fw_load_type; 9397b2e202SAlex Deucher extern int amdgpu_aspm; 9497b2e202SAlex Deucher extern int amdgpu_runtime_pm; 950b693f0bSRex Zhu extern uint amdgpu_ip_block_mask; 9697b2e202SAlex Deucher extern int amdgpu_bapm; 9797b2e202SAlex Deucher extern int amdgpu_deep_color; 9897b2e202SAlex Deucher extern int amdgpu_vm_size; 9997b2e202SAlex Deucher extern int amdgpu_vm_block_size; 100d07f14beSRoger He extern int amdgpu_vm_fragment_size; 101d9c13156SChristian König extern int amdgpu_vm_fault_stop; 102b495bd3aSChristian König extern int amdgpu_vm_debug; 1039a4b7d4cSHarish Kasiviswanathan extern int amdgpu_vm_update_mode; 1041333f723SJammy Zhou extern int amdgpu_sched_jobs; 1054afcb303SJammy Zhou extern int amdgpu_sched_hw_submission; 1063ca67300SRex Zhu extern int amdgpu_no_evict; 1073ca67300SRex Zhu extern int amdgpu_direct_gma_size; 1080b693f0bSRex Zhu extern uint amdgpu_pcie_gen_cap; 1090b693f0bSRex Zhu extern uint amdgpu_pcie_lane_cap; 1100b693f0bSRex Zhu extern uint amdgpu_cg_mask; 1110b693f0bSRex Zhu extern uint amdgpu_pg_mask; 1120b693f0bSRex Zhu extern uint amdgpu_sdma_phase_quantum; 1136f8941a2SNicolai Hähnle extern char *amdgpu_disable_cu; 1149accf2fdSEmily Deng extern char *amdgpu_virtual_display; 1150b693f0bSRex Zhu extern uint amdgpu_pp_feature_mask; 1166a7f76e7SChristian König extern int amdgpu_vram_page_split; 117bce23e00SAlex Deucher extern int amdgpu_ngg; 118bce23e00SAlex Deucher extern int amdgpu_prim_buf_per_se; 119bce23e00SAlex Deucher extern int amdgpu_pos_buf_per_se; 120bce23e00SAlex Deucher extern int amdgpu_cntl_sb_buf_per_se; 121bce23e00SAlex Deucher extern int amdgpu_param_buf_per_se; 12265781c78SMonk Liu extern int amdgpu_job_hang_limit; 123e8835e0eSHawking Zhang extern int amdgpu_lbpw; 12497b2e202SAlex Deucher 1256dd13096SFelix Kuehling #ifdef CONFIG_DRM_AMDGPU_SI 1266dd13096SFelix Kuehling extern int amdgpu_si_support; 1276dd13096SFelix Kuehling #endif 1287df28986SFelix Kuehling #ifdef CONFIG_DRM_AMDGPU_CIK 1297df28986SFelix Kuehling extern int amdgpu_cik_support; 1307df28986SFelix Kuehling #endif 13197b2e202SAlex Deucher 13255ed8cafSChunming Zhou #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 1334b559c90SChunming Zhou #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 13497b2e202SAlex Deucher #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 13597b2e202SAlex Deucher #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 13697b2e202SAlex Deucher /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 13797b2e202SAlex Deucher #define AMDGPU_IB_POOL_SIZE 16 13897b2e202SAlex Deucher #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 13997b2e202SAlex Deucher #define AMDGPUFB_CONN_LIMIT 4 140a5bde2f9SAlex Deucher #define AMDGPU_BIOS_NUM_SCRATCH 16 14197b2e202SAlex Deucher 14236f523a7SJammy Zhou /* max number of IP instances */ 14336f523a7SJammy Zhou #define AMDGPU_MAX_SDMA_INSTANCES 2 14436f523a7SJammy Zhou 14597b2e202SAlex Deucher /* hard reset data */ 14697b2e202SAlex Deucher #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 14797b2e202SAlex Deucher 14897b2e202SAlex Deucher /* reset flags */ 14997b2e202SAlex Deucher #define AMDGPU_RESET_GFX (1 << 0) 15097b2e202SAlex Deucher #define AMDGPU_RESET_COMPUTE (1 << 1) 15197b2e202SAlex Deucher #define AMDGPU_RESET_DMA (1 << 2) 15297b2e202SAlex Deucher #define AMDGPU_RESET_CP (1 << 3) 15397b2e202SAlex Deucher #define AMDGPU_RESET_GRBM (1 << 4) 15497b2e202SAlex Deucher #define AMDGPU_RESET_DMA1 (1 << 5) 15597b2e202SAlex Deucher #define AMDGPU_RESET_RLC (1 << 6) 15697b2e202SAlex Deucher #define AMDGPU_RESET_SEM (1 << 7) 15797b2e202SAlex Deucher #define AMDGPU_RESET_IH (1 << 8) 15897b2e202SAlex Deucher #define AMDGPU_RESET_VMC (1 << 9) 15997b2e202SAlex Deucher #define AMDGPU_RESET_MC (1 << 10) 16097b2e202SAlex Deucher #define AMDGPU_RESET_DISPLAY (1 << 11) 16197b2e202SAlex Deucher #define AMDGPU_RESET_UVD (1 << 12) 16297b2e202SAlex Deucher #define AMDGPU_RESET_VCE (1 << 13) 16397b2e202SAlex Deucher #define AMDGPU_RESET_VCE1 (1 << 14) 16497b2e202SAlex Deucher 16597b2e202SAlex Deucher /* GFX current status */ 16697b2e202SAlex Deucher #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 16797b2e202SAlex Deucher #define AMDGPU_GFX_SAFE_MODE 0x00000001L 16897b2e202SAlex Deucher #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 16997b2e202SAlex Deucher #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 17097b2e202SAlex Deucher #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 17197b2e202SAlex Deucher 17297b2e202SAlex Deucher /* max cursor sizes (in pixels) */ 17397b2e202SAlex Deucher #define CIK_CURSOR_WIDTH 128 17497b2e202SAlex Deucher #define CIK_CURSOR_HEIGHT 128 17597b2e202SAlex Deucher 17697b2e202SAlex Deucher struct amdgpu_device; 17797b2e202SAlex Deucher struct amdgpu_ib; 17897b2e202SAlex Deucher struct amdgpu_cs_parser; 179bb977d37SChunming Zhou struct amdgpu_job; 18097b2e202SAlex Deucher struct amdgpu_irq_src; 1810b492a4cSAlex Deucher struct amdgpu_fpriv; 1829cca0b8eSChristian König struct amdgpu_bo_va_mapping; 18397b2e202SAlex Deucher 18497b2e202SAlex Deucher enum amdgpu_cp_irq { 18597b2e202SAlex Deucher AMDGPU_CP_IRQ_GFX_EOP = 0, 18697b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 18797b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 18897b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 18997b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 19097b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 19197b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 19297b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 19397b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 19497b2e202SAlex Deucher 19597b2e202SAlex Deucher AMDGPU_CP_IRQ_LAST 19697b2e202SAlex Deucher }; 19797b2e202SAlex Deucher 19897b2e202SAlex Deucher enum amdgpu_sdma_irq { 19997b2e202SAlex Deucher AMDGPU_SDMA_IRQ_TRAP0 = 0, 20097b2e202SAlex Deucher AMDGPU_SDMA_IRQ_TRAP1, 20197b2e202SAlex Deucher 20297b2e202SAlex Deucher AMDGPU_SDMA_IRQ_LAST 20397b2e202SAlex Deucher }; 20497b2e202SAlex Deucher 20597b2e202SAlex Deucher enum amdgpu_thermal_irq { 20697b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 20797b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 20897b2e202SAlex Deucher 20997b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LAST 21097b2e202SAlex Deucher }; 21197b2e202SAlex Deucher 2124e638ae9SXiangliang Yu enum amdgpu_kiq_irq { 2134e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 2144e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_LAST 2154e638ae9SXiangliang Yu }; 2164e638ae9SXiangliang Yu 21797b2e202SAlex Deucher int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 2185fc3aeebSyanyang1 enum amd_ip_block_type block_type, 2195fc3aeebSyanyang1 enum amd_clockgating_state state); 22097b2e202SAlex Deucher int amdgpu_set_powergating_state(struct amdgpu_device *adev, 2215fc3aeebSyanyang1 enum amd_ip_block_type block_type, 2225fc3aeebSyanyang1 enum amd_powergating_state state); 2236cb2d4e4SHuang Rui void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); 2245dbbb60bSAlex Deucher int amdgpu_wait_for_idle(struct amdgpu_device *adev, 2255dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 2265dbbb60bSAlex Deucher bool amdgpu_is_idle(struct amdgpu_device *adev, 2275dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 22897b2e202SAlex Deucher 229a1255107SAlex Deucher #define AMDGPU_MAX_IP_NUM 16 230a1255107SAlex Deucher 231a1255107SAlex Deucher struct amdgpu_ip_block_status { 232a1255107SAlex Deucher bool valid; 233a1255107SAlex Deucher bool sw; 234a1255107SAlex Deucher bool hw; 235a1255107SAlex Deucher bool late_initialized; 236a1255107SAlex Deucher bool hang; 237a1255107SAlex Deucher }; 238a1255107SAlex Deucher 23997b2e202SAlex Deucher struct amdgpu_ip_block_version { 240a1255107SAlex Deucher const enum amd_ip_block_type type; 241a1255107SAlex Deucher const u32 major; 242a1255107SAlex Deucher const u32 minor; 243a1255107SAlex Deucher const u32 rev; 2445fc3aeebSyanyang1 const struct amd_ip_funcs *funcs; 24597b2e202SAlex Deucher }; 24697b2e202SAlex Deucher 247a1255107SAlex Deucher struct amdgpu_ip_block { 248a1255107SAlex Deucher struct amdgpu_ip_block_status status; 249a1255107SAlex Deucher const struct amdgpu_ip_block_version *version; 250a1255107SAlex Deucher }; 251a1255107SAlex Deucher 25297b2e202SAlex Deucher int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 2535fc3aeebSyanyang1 enum amd_ip_block_type type, 25497b2e202SAlex Deucher u32 major, u32 minor); 25597b2e202SAlex Deucher 256a1255107SAlex Deucher struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 2575fc3aeebSyanyang1 enum amd_ip_block_type type); 25897b2e202SAlex Deucher 259a1255107SAlex Deucher int amdgpu_ip_block_add(struct amdgpu_device *adev, 260a1255107SAlex Deucher const struct amdgpu_ip_block_version *ip_block_version); 261a1255107SAlex Deucher 26297b2e202SAlex Deucher /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 26397b2e202SAlex Deucher struct amdgpu_buffer_funcs { 26497b2e202SAlex Deucher /* maximum bytes in a single operation */ 26597b2e202SAlex Deucher uint32_t copy_max_bytes; 26697b2e202SAlex Deucher 26797b2e202SAlex Deucher /* number of dw to reserve per operation */ 26897b2e202SAlex Deucher unsigned copy_num_dw; 26997b2e202SAlex Deucher 27097b2e202SAlex Deucher /* used for buffer migration */ 271c7ae72c0SChunming Zhou void (*emit_copy_buffer)(struct amdgpu_ib *ib, 27297b2e202SAlex Deucher /* src addr in bytes */ 27397b2e202SAlex Deucher uint64_t src_offset, 27497b2e202SAlex Deucher /* dst addr in bytes */ 27597b2e202SAlex Deucher uint64_t dst_offset, 27697b2e202SAlex Deucher /* number of byte to transfer */ 27797b2e202SAlex Deucher uint32_t byte_count); 27897b2e202SAlex Deucher 27997b2e202SAlex Deucher /* maximum bytes in a single operation */ 28097b2e202SAlex Deucher uint32_t fill_max_bytes; 28197b2e202SAlex Deucher 28297b2e202SAlex Deucher /* number of dw to reserve per operation */ 28397b2e202SAlex Deucher unsigned fill_num_dw; 28497b2e202SAlex Deucher 28597b2e202SAlex Deucher /* used for buffer clearing */ 2866e7a3840SChunming Zhou void (*emit_fill_buffer)(struct amdgpu_ib *ib, 28797b2e202SAlex Deucher /* value to write to memory */ 28897b2e202SAlex Deucher uint32_t src_data, 28997b2e202SAlex Deucher /* dst addr in bytes */ 29097b2e202SAlex Deucher uint64_t dst_offset, 29197b2e202SAlex Deucher /* number of byte to fill */ 29297b2e202SAlex Deucher uint32_t byte_count); 29397b2e202SAlex Deucher }; 29497b2e202SAlex Deucher 29597b2e202SAlex Deucher /* provided by hw blocks that can write ptes, e.g., sdma */ 29697b2e202SAlex Deucher struct amdgpu_vm_pte_funcs { 297e6d92197SYong Zhao /* number of dw to reserve per operation */ 298e6d92197SYong Zhao unsigned copy_pte_num_dw; 299e6d92197SYong Zhao 30097b2e202SAlex Deucher /* copy pte entries from GART */ 30197b2e202SAlex Deucher void (*copy_pte)(struct amdgpu_ib *ib, 30297b2e202SAlex Deucher uint64_t pe, uint64_t src, 30397b2e202SAlex Deucher unsigned count); 304e6d92197SYong Zhao 30597b2e202SAlex Deucher /* write pte one entry at a time with addr mapping */ 306de9ea7bdSChristian König void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 307de9ea7bdSChristian König uint64_t value, unsigned count, 308de9ea7bdSChristian König uint32_t incr); 3097bdc53f9SYong Zhao 3107bdc53f9SYong Zhao /* maximum nums of PTEs/PDEs in a single operation */ 3117bdc53f9SYong Zhao uint32_t set_max_nums_pte_pde; 3127bdc53f9SYong Zhao 3137bdc53f9SYong Zhao /* number of dw to reserve per operation */ 3147bdc53f9SYong Zhao unsigned set_pte_pde_num_dw; 3157bdc53f9SYong Zhao 31697b2e202SAlex Deucher /* for linear pte/pde updates without addr mapping */ 31797b2e202SAlex Deucher void (*set_pte_pde)(struct amdgpu_ib *ib, 31897b2e202SAlex Deucher uint64_t pe, 31997b2e202SAlex Deucher uint64_t addr, unsigned count, 3206b777607SChunming Zhou uint32_t incr, uint64_t flags); 32197b2e202SAlex Deucher }; 32297b2e202SAlex Deucher 32397b2e202SAlex Deucher /* provided by the gmc block */ 32497b2e202SAlex Deucher struct amdgpu_gart_funcs { 32597b2e202SAlex Deucher /* flush the vm tlb via mmio */ 32697b2e202SAlex Deucher void (*flush_gpu_tlb)(struct amdgpu_device *adev, 32797b2e202SAlex Deucher uint32_t vmid); 32897b2e202SAlex Deucher /* write pte/pde updates using the cpu */ 32997b2e202SAlex Deucher int (*set_pte_pde)(struct amdgpu_device *adev, 33097b2e202SAlex Deucher void *cpu_pt_addr, /* cpu addr of page table */ 33197b2e202SAlex Deucher uint32_t gpu_page_idx, /* pte/pde to update */ 33297b2e202SAlex Deucher uint64_t addr, /* addr to write into pte/pde */ 3336b777607SChunming Zhou uint64_t flags); /* access flags */ 334284710faSChristian König /* enable/disable PRT support */ 335284710faSChristian König void (*set_prt)(struct amdgpu_device *adev, bool enable); 3365463545bSAlex Xie /* set pte flags based per asic */ 3375463545bSAlex Xie uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, 3385463545bSAlex Xie uint32_t flags); 339b1166325SChristian König /* get the pde for a given mc addr */ 340b1166325SChristian König u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr); 34103f89febSChristian König uint32_t (*get_invalidate_req)(unsigned int vm_id); 342e60f8db5SAlex Xie }; 343e60f8db5SAlex Xie 34497b2e202SAlex Deucher /* provided by the ih block */ 34597b2e202SAlex Deucher struct amdgpu_ih_funcs { 34697b2e202SAlex Deucher /* ring read/write ptr handling, called from interrupt context */ 34797b2e202SAlex Deucher u32 (*get_wptr)(struct amdgpu_device *adev); 34800ecd8a2SFelix Kuehling bool (*prescreen_iv)(struct amdgpu_device *adev); 34997b2e202SAlex Deucher void (*decode_iv)(struct amdgpu_device *adev, 35097b2e202SAlex Deucher struct amdgpu_iv_entry *entry); 35197b2e202SAlex Deucher void (*set_rptr)(struct amdgpu_device *adev); 35297b2e202SAlex Deucher }; 35397b2e202SAlex Deucher 35497b2e202SAlex Deucher /* 35597b2e202SAlex Deucher * BIOS. 35697b2e202SAlex Deucher */ 35797b2e202SAlex Deucher bool amdgpu_get_bios(struct amdgpu_device *adev); 35897b2e202SAlex Deucher bool amdgpu_read_bios(struct amdgpu_device *adev); 35997b2e202SAlex Deucher 36097b2e202SAlex Deucher /* 36197b2e202SAlex Deucher * Dummy page 36297b2e202SAlex Deucher */ 36397b2e202SAlex Deucher struct amdgpu_dummy_page { 36497b2e202SAlex Deucher struct page *page; 36597b2e202SAlex Deucher dma_addr_t addr; 36697b2e202SAlex Deucher }; 36797b2e202SAlex Deucher int amdgpu_dummy_page_init(struct amdgpu_device *adev); 36897b2e202SAlex Deucher void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 36997b2e202SAlex Deucher 37097b2e202SAlex Deucher 37197b2e202SAlex Deucher /* 37297b2e202SAlex Deucher * Clocks 37397b2e202SAlex Deucher */ 37497b2e202SAlex Deucher 37597b2e202SAlex Deucher #define AMDGPU_MAX_PPLL 3 37697b2e202SAlex Deucher 37797b2e202SAlex Deucher struct amdgpu_clock { 37897b2e202SAlex Deucher struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 37997b2e202SAlex Deucher struct amdgpu_pll spll; 38097b2e202SAlex Deucher struct amdgpu_pll mpll; 38197b2e202SAlex Deucher /* 10 Khz units */ 38297b2e202SAlex Deucher uint32_t default_mclk; 38397b2e202SAlex Deucher uint32_t default_sclk; 38497b2e202SAlex Deucher uint32_t default_dispclk; 38597b2e202SAlex Deucher uint32_t current_dispclk; 38697b2e202SAlex Deucher uint32_t dp_extclk; 38797b2e202SAlex Deucher uint32_t max_pixel_clock; 38897b2e202SAlex Deucher }; 38997b2e202SAlex Deucher 39097b2e202SAlex Deucher /* 3919124a398SChristian König * GEM. 39297b2e202SAlex Deucher */ 39397b2e202SAlex Deucher 3947e5a547fSChunming Zhou #define AMDGPU_GEM_DOMAIN_MAX 0x3 39597b2e202SAlex Deucher #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 39697b2e202SAlex Deucher 39797b2e202SAlex Deucher void amdgpu_gem_object_free(struct drm_gem_object *obj); 39897b2e202SAlex Deucher int amdgpu_gem_object_open(struct drm_gem_object *obj, 39997b2e202SAlex Deucher struct drm_file *file_priv); 40097b2e202SAlex Deucher void amdgpu_gem_object_close(struct drm_gem_object *obj, 40197b2e202SAlex Deucher struct drm_file *file_priv); 40297b2e202SAlex Deucher unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 40397b2e202SAlex Deucher struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 4044d9c514dSChristian König struct drm_gem_object * 4054d9c514dSChristian König amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 40697b2e202SAlex Deucher struct dma_buf_attachment *attach, 40797b2e202SAlex Deucher struct sg_table *sg); 40897b2e202SAlex Deucher struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 40997b2e202SAlex Deucher struct drm_gem_object *gobj, 41097b2e202SAlex Deucher int flags); 41197b2e202SAlex Deucher int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 41297b2e202SAlex Deucher void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 41397b2e202SAlex Deucher struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 41497b2e202SAlex Deucher void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 41597b2e202SAlex Deucher void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 41697b2e202SAlex Deucher int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 41797b2e202SAlex Deucher 41897b2e202SAlex Deucher /* sub-allocation manager, it has to be protected by another lock. 41997b2e202SAlex Deucher * By conception this is an helper for other part of the driver 42097b2e202SAlex Deucher * like the indirect buffer or semaphore, which both have their 42197b2e202SAlex Deucher * locking. 42297b2e202SAlex Deucher * 42397b2e202SAlex Deucher * Principe is simple, we keep a list of sub allocation in offset 42497b2e202SAlex Deucher * order (first entry has offset == 0, last entry has the highest 42597b2e202SAlex Deucher * offset). 42697b2e202SAlex Deucher * 42797b2e202SAlex Deucher * When allocating new object we first check if there is room at 42897b2e202SAlex Deucher * the end total_size - (last_object_offset + last_object_size) >= 42997b2e202SAlex Deucher * alloc_size. If so we allocate new object there. 43097b2e202SAlex Deucher * 43197b2e202SAlex Deucher * When there is not enough room at the end, we start waiting for 43297b2e202SAlex Deucher * each sub object until we reach object_offset+object_size >= 43397b2e202SAlex Deucher * alloc_size, this object then become the sub object we return. 43497b2e202SAlex Deucher * 43597b2e202SAlex Deucher * Alignment can't be bigger than page size. 43697b2e202SAlex Deucher * 43797b2e202SAlex Deucher * Hole are not considered for allocation to keep things simple. 43897b2e202SAlex Deucher * Assumption is that there won't be hole (all object on same 43997b2e202SAlex Deucher * alignment). 44097b2e202SAlex Deucher */ 4416ba60b89SChristian König 4426ba60b89SChristian König #define AMDGPU_SA_NUM_FENCE_LISTS 32 4436ba60b89SChristian König 44497b2e202SAlex Deucher struct amdgpu_sa_manager { 44597b2e202SAlex Deucher wait_queue_head_t wq; 44697b2e202SAlex Deucher struct amdgpu_bo *bo; 44797b2e202SAlex Deucher struct list_head *hole; 4486ba60b89SChristian König struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 44997b2e202SAlex Deucher struct list_head olist; 45097b2e202SAlex Deucher unsigned size; 45197b2e202SAlex Deucher uint64_t gpu_addr; 45297b2e202SAlex Deucher void *cpu_ptr; 45397b2e202SAlex Deucher uint32_t domain; 45497b2e202SAlex Deucher uint32_t align; 45597b2e202SAlex Deucher }; 45697b2e202SAlex Deucher 45797b2e202SAlex Deucher /* sub-allocation buffer */ 45897b2e202SAlex Deucher struct amdgpu_sa_bo { 45997b2e202SAlex Deucher struct list_head olist; 46097b2e202SAlex Deucher struct list_head flist; 46197b2e202SAlex Deucher struct amdgpu_sa_manager *manager; 46297b2e202SAlex Deucher unsigned soffset; 46397b2e202SAlex Deucher unsigned eoffset; 464f54d1867SChris Wilson struct dma_fence *fence; 46597b2e202SAlex Deucher }; 46697b2e202SAlex Deucher 46797b2e202SAlex Deucher /* 46897b2e202SAlex Deucher * GEM objects. 46997b2e202SAlex Deucher */ 470418aa0c2SChristian König void amdgpu_gem_force_release(struct amdgpu_device *adev); 47197b2e202SAlex Deucher int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 47297b2e202SAlex Deucher int alignment, u32 initial_domain, 47397b2e202SAlex Deucher u64 flags, bool kernel, 474e1eb899bSChristian König struct reservation_object *resv, 47597b2e202SAlex Deucher struct drm_gem_object **obj); 47697b2e202SAlex Deucher 47797b2e202SAlex Deucher int amdgpu_mode_dumb_create(struct drm_file *file_priv, 47897b2e202SAlex Deucher struct drm_device *dev, 47997b2e202SAlex Deucher struct drm_mode_create_dumb *args); 48097b2e202SAlex Deucher int amdgpu_mode_dumb_mmap(struct drm_file *filp, 48197b2e202SAlex Deucher struct drm_device *dev, 48297b2e202SAlex Deucher uint32_t handle, uint64_t *offset_p); 483d573de2dSRex Zhu int amdgpu_fence_slab_init(void); 484d573de2dSRex Zhu void amdgpu_fence_slab_fini(void); 48597b2e202SAlex Deucher 48697b2e202SAlex Deucher /* 487e60f8db5SAlex Xie * VMHUB structures, functions & helpers 488e60f8db5SAlex Xie */ 489e60f8db5SAlex Xie struct amdgpu_vmhub { 490e60f8db5SAlex Xie uint32_t ctx0_ptb_addr_lo32; 491e60f8db5SAlex Xie uint32_t ctx0_ptb_addr_hi32; 492e60f8db5SAlex Xie uint32_t vm_inv_eng0_req; 493e60f8db5SAlex Xie uint32_t vm_inv_eng0_ack; 494e60f8db5SAlex Xie uint32_t vm_context0_cntl; 495e60f8db5SAlex Xie uint32_t vm_l2_pro_fault_status; 496e60f8db5SAlex Xie uint32_t vm_l2_pro_fault_cntl; 497e60f8db5SAlex Xie }; 498e60f8db5SAlex Xie 499e60f8db5SAlex Xie /* 50097b2e202SAlex Deucher * GPU MC structures, functions & helpers 50197b2e202SAlex Deucher */ 50297b2e202SAlex Deucher struct amdgpu_mc { 50397b2e202SAlex Deucher resource_size_t aper_size; 50497b2e202SAlex Deucher resource_size_t aper_base; 50597b2e202SAlex Deucher resource_size_t agp_base; 50697b2e202SAlex Deucher /* for some chips with <= 32MB we need to lie 50797b2e202SAlex Deucher * about vram size near mc fb location */ 50897b2e202SAlex Deucher u64 mc_vram_size; 50997b2e202SAlex Deucher u64 visible_vram_size; 5106f02a696SChristian König u64 gart_size; 5116f02a696SChristian König u64 gart_start; 5126f02a696SChristian König u64 gart_end; 51397b2e202SAlex Deucher u64 vram_start; 51497b2e202SAlex Deucher u64 vram_end; 51597b2e202SAlex Deucher unsigned vram_width; 51697b2e202SAlex Deucher u64 real_vram_size; 51797b2e202SAlex Deucher int vram_mtrr; 51897b2e202SAlex Deucher u64 mc_mask; 51997b2e202SAlex Deucher const struct firmware *fw; /* MC firmware */ 52097b2e202SAlex Deucher uint32_t fw_version; 52197b2e202SAlex Deucher struct amdgpu_irq_src vm_fault; 52281c59f54SKen Wang uint32_t vram_type; 52350b0197aSChunming Zhou uint32_t srbm_soft_reset; 524f7c35abeSChristian König bool prt_warning; 525916910adSHuang Rui uint64_t stolen_size; 5268fe73328SJunwei Zhang /* apertures */ 5278fe73328SJunwei Zhang u64 shared_aperture_start; 5288fe73328SJunwei Zhang u64 shared_aperture_end; 5298fe73328SJunwei Zhang u64 private_aperture_start; 5308fe73328SJunwei Zhang u64 private_aperture_end; 531e60f8db5SAlex Xie /* protects concurrent invalidation */ 532e60f8db5SAlex Xie spinlock_t invalidate_lock; 53397b2e202SAlex Deucher }; 53497b2e202SAlex Deucher 53597b2e202SAlex Deucher /* 53697b2e202SAlex Deucher * GPU doorbell structures, functions & helpers 53797b2e202SAlex Deucher */ 53897b2e202SAlex Deucher typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 53997b2e202SAlex Deucher { 54097b2e202SAlex Deucher AMDGPU_DOORBELL_KIQ = 0x000, 54197b2e202SAlex Deucher AMDGPU_DOORBELL_HIQ = 0x001, 54297b2e202SAlex Deucher AMDGPU_DOORBELL_DIQ = 0x002, 54397b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING0 = 0x010, 54497b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING1 = 0x011, 54597b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING2 = 0x012, 54697b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING3 = 0x013, 54797b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING4 = 0x014, 54897b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING5 = 0x015, 54997b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING6 = 0x016, 55097b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING7 = 0x017, 55197b2e202SAlex Deucher AMDGPU_DOORBELL_GFX_RING0 = 0x020, 55297b2e202SAlex Deucher AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 55397b2e202SAlex Deucher AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 55497b2e202SAlex Deucher AMDGPU_DOORBELL_IH = 0x1E8, 55597b2e202SAlex Deucher AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 55697b2e202SAlex Deucher AMDGPU_DOORBELL_INVALID = 0xFFFF 55797b2e202SAlex Deucher } AMDGPU_DOORBELL_ASSIGNMENT; 55897b2e202SAlex Deucher 55997b2e202SAlex Deucher struct amdgpu_doorbell { 56097b2e202SAlex Deucher /* doorbell mmio */ 56197b2e202SAlex Deucher resource_size_t base; 56297b2e202SAlex Deucher resource_size_t size; 56397b2e202SAlex Deucher u32 __iomem *ptr; 56497b2e202SAlex Deucher u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 56597b2e202SAlex Deucher }; 56697b2e202SAlex Deucher 56739807b93SKen Wang /* 56839807b93SKen Wang * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 56939807b93SKen Wang */ 57039807b93SKen Wang typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 57139807b93SKen Wang { 57239807b93SKen Wang /* 57339807b93SKen Wang * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 57439807b93SKen Wang * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 57539807b93SKen Wang * Compute related doorbells are allocated from 0x00 to 0x8a 57639807b93SKen Wang */ 57739807b93SKen Wang 57839807b93SKen Wang 57939807b93SKen Wang /* kernel scheduling */ 58039807b93SKen Wang AMDGPU_DOORBELL64_KIQ = 0x00, 58139807b93SKen Wang 58239807b93SKen Wang /* HSA interface queue and debug queue */ 58339807b93SKen Wang AMDGPU_DOORBELL64_HIQ = 0x01, 58439807b93SKen Wang AMDGPU_DOORBELL64_DIQ = 0x02, 58539807b93SKen Wang 58639807b93SKen Wang /* Compute engines */ 58739807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 58839807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 58939807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 59039807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 59139807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 59239807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 59339807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 59439807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 59539807b93SKen Wang 59639807b93SKen Wang /* User queue doorbell range (128 doorbells) */ 59739807b93SKen Wang AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 59839807b93SKen Wang AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 59939807b93SKen Wang 60039807b93SKen Wang /* Graphics engine */ 60139807b93SKen Wang AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 60239807b93SKen Wang 60339807b93SKen Wang /* 60439807b93SKen Wang * Other graphics doorbells can be allocated here: from 0x8c to 0xef 60539807b93SKen Wang * Graphics voltage island aperture 1 60639807b93SKen Wang * default non-graphics QWORD index is 0xF0 - 0xFF inclusive 60739807b93SKen Wang */ 60839807b93SKen Wang 60939807b93SKen Wang /* sDMA engines */ 61039807b93SKen Wang AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 61139807b93SKen Wang AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 61239807b93SKen Wang AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 61339807b93SKen Wang AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 61439807b93SKen Wang 61539807b93SKen Wang /* Interrupt handler */ 61639807b93SKen Wang AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 61739807b93SKen Wang AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 61839807b93SKen Wang AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 61939807b93SKen Wang 620e6b3ecb4SMonk Liu /* VCN engine use 32 bits doorbell */ 621e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 622e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 623e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 624e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 625e6b3ecb4SMonk Liu 626e6b3ecb4SMonk Liu /* overlap the doorbell assignment with VCN as they are mutually exclusive 627e6b3ecb4SMonk Liu * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 628e6b3ecb4SMonk Liu */ 6294ed11d79SFrank Min AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 6304ed11d79SFrank Min AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 6314ed11d79SFrank Min AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 6324ed11d79SFrank Min AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 633e6b3ecb4SMonk Liu 6344ed11d79SFrank Min AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 6354ed11d79SFrank Min AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 6364ed11d79SFrank Min AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 6374ed11d79SFrank Min AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 63839807b93SKen Wang 63939807b93SKen Wang AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 64039807b93SKen Wang AMDGPU_DOORBELL64_INVALID = 0xFFFF 64139807b93SKen Wang } AMDGPU_DOORBELL64_ASSIGNMENT; 64239807b93SKen Wang 64339807b93SKen Wang 64497b2e202SAlex Deucher void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 64597b2e202SAlex Deucher phys_addr_t *aperture_base, 64697b2e202SAlex Deucher size_t *aperture_size, 64797b2e202SAlex Deucher size_t *start_offset); 64897b2e202SAlex Deucher 64997b2e202SAlex Deucher /* 65097b2e202SAlex Deucher * IRQS. 65197b2e202SAlex Deucher */ 65297b2e202SAlex Deucher 65397b2e202SAlex Deucher struct amdgpu_flip_work { 654325cbba1SMichel Dänzer struct delayed_work flip_work; 65597b2e202SAlex Deucher struct work_struct unpin_work; 65697b2e202SAlex Deucher struct amdgpu_device *adev; 65797b2e202SAlex Deucher int crtc_id; 658325cbba1SMichel Dänzer u32 target_vblank; 65997b2e202SAlex Deucher uint64_t base; 66097b2e202SAlex Deucher struct drm_pending_vblank_event *event; 661765e7fbfSChristian König struct amdgpu_bo *old_abo; 662f54d1867SChris Wilson struct dma_fence *excl; 6631ffd2652SChristian König unsigned shared_count; 664f54d1867SChris Wilson struct dma_fence **shared; 665f54d1867SChris Wilson struct dma_fence_cb cb; 666cb9e59d7SAlex Deucher bool async; 66797b2e202SAlex Deucher }; 66897b2e202SAlex Deucher 66997b2e202SAlex Deucher 67097b2e202SAlex Deucher /* 67197b2e202SAlex Deucher * CP & rings. 67297b2e202SAlex Deucher */ 67397b2e202SAlex Deucher 67497b2e202SAlex Deucher struct amdgpu_ib { 67597b2e202SAlex Deucher struct amdgpu_sa_bo *sa_bo; 67697b2e202SAlex Deucher uint32_t length_dw; 67797b2e202SAlex Deucher uint64_t gpu_addr; 67897b2e202SAlex Deucher uint32_t *ptr; 679de807f81SJammy Zhou uint32_t flags; 68097b2e202SAlex Deucher }; 68197b2e202SAlex Deucher 68262250a91SNils Wallménius extern const struct amd_sched_backend_ops amdgpu_sched_ops; 683c1b69ed0SChunming Zhou 68450838c8cSChristian König int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 685c5637837SMonk Liu struct amdgpu_job **job, struct amdgpu_vm *vm); 686d71518b5SChristian König int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 687d71518b5SChristian König struct amdgpu_job **job); 688b6723c8dSMonk Liu 689a5fb4ec2SChristian König void amdgpu_job_free_resources(struct amdgpu_job *job); 69050838c8cSChristian König void amdgpu_job_free(struct amdgpu_job *job); 691d71518b5SChristian König int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 6922bd9ccfaSChristian König struct amd_sched_entity *entity, void *owner, 693f54d1867SChris Wilson struct dma_fence **f); 6948b4fb00bSChristian König 69597b2e202SAlex Deucher /* 696effd924dSAndres Rodriguez * Queue manager 697effd924dSAndres Rodriguez */ 698effd924dSAndres Rodriguez struct amdgpu_queue_mapper { 699effd924dSAndres Rodriguez int hw_ip; 700effd924dSAndres Rodriguez struct mutex lock; 701effd924dSAndres Rodriguez /* protected by lock */ 702effd924dSAndres Rodriguez struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS]; 703effd924dSAndres Rodriguez }; 704effd924dSAndres Rodriguez 705effd924dSAndres Rodriguez struct amdgpu_queue_mgr { 706effd924dSAndres Rodriguez struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM]; 707effd924dSAndres Rodriguez }; 708effd924dSAndres Rodriguez 709effd924dSAndres Rodriguez int amdgpu_queue_mgr_init(struct amdgpu_device *adev, 710effd924dSAndres Rodriguez struct amdgpu_queue_mgr *mgr); 711effd924dSAndres Rodriguez int amdgpu_queue_mgr_fini(struct amdgpu_device *adev, 712effd924dSAndres Rodriguez struct amdgpu_queue_mgr *mgr); 713effd924dSAndres Rodriguez int amdgpu_queue_mgr_map(struct amdgpu_device *adev, 714effd924dSAndres Rodriguez struct amdgpu_queue_mgr *mgr, 715effd924dSAndres Rodriguez int hw_ip, int instance, int ring, 716effd924dSAndres Rodriguez struct amdgpu_ring **out_ring); 717effd924dSAndres Rodriguez 718effd924dSAndres Rodriguez /* 71997b2e202SAlex Deucher * context related structures 72097b2e202SAlex Deucher */ 72197b2e202SAlex Deucher 72221c16bf6SChristian König struct amdgpu_ctx_ring { 72321c16bf6SChristian König uint64_t sequence; 724f54d1867SChris Wilson struct dma_fence **fences; 72591404fb2SChristian König struct amd_sched_entity entity; 72621c16bf6SChristian König }; 72721c16bf6SChristian König 72897b2e202SAlex Deucher struct amdgpu_ctx { 72997b2e202SAlex Deucher struct kref refcount; 7309cb7e5a9SChunming Zhou struct amdgpu_device *adev; 731effd924dSAndres Rodriguez struct amdgpu_queue_mgr queue_mgr; 732d94aed5aSMarek Olšák unsigned reset_counter; 73321c16bf6SChristian König spinlock_t ring_lock; 734f54d1867SChris Wilson struct dma_fence **fences; 73521c16bf6SChristian König struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 736753ad49cSMonk Liu bool preamble_presented; 73797b2e202SAlex Deucher }; 73897b2e202SAlex Deucher 73997b2e202SAlex Deucher struct amdgpu_ctx_mgr { 74097b2e202SAlex Deucher struct amdgpu_device *adev; 7410147ee0fSMarek Olšák struct mutex lock; 7420b492a4cSAlex Deucher /* protected by lock */ 7430b492a4cSAlex Deucher struct idr ctx_handles; 74497b2e202SAlex Deucher }; 74597b2e202SAlex Deucher 7460b492a4cSAlex Deucher struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 7470b492a4cSAlex Deucher int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 7480b492a4cSAlex Deucher 749eb01abc7SMonk Liu int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 750eb01abc7SMonk Liu struct dma_fence *fence, uint64_t *seq); 751f54d1867SChris Wilson struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 75221c16bf6SChristian König struct amdgpu_ring *ring, uint64_t seq); 75321c16bf6SChristian König 7540b492a4cSAlex Deucher int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 7550b492a4cSAlex Deucher struct drm_file *filp); 7560b492a4cSAlex Deucher 757efd4ccb5SChristian König void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 758efd4ccb5SChristian König void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 7590b492a4cSAlex Deucher 76097b2e202SAlex Deucher /* 76197b2e202SAlex Deucher * file private structure 76297b2e202SAlex Deucher */ 76397b2e202SAlex Deucher 76497b2e202SAlex Deucher struct amdgpu_fpriv { 76597b2e202SAlex Deucher struct amdgpu_vm vm; 766b85891bdSJunwei Zhang struct amdgpu_bo_va *prt_va; 7670f4b3c68SChristian König struct amdgpu_bo_va *csa_va; 76897b2e202SAlex Deucher struct mutex bo_list_lock; 76997b2e202SAlex Deucher struct idr bo_list_handles; 77097b2e202SAlex Deucher struct amdgpu_ctx_mgr ctx_mgr; 771f1892138SChunming Zhou u32 vram_lost_counter; 77297b2e202SAlex Deucher }; 77397b2e202SAlex Deucher 77497b2e202SAlex Deucher /* 77597b2e202SAlex Deucher * residency list 77697b2e202SAlex Deucher */ 7779124a398SChristian König struct amdgpu_bo_list_entry { 7789124a398SChristian König struct amdgpu_bo *robj; 7799124a398SChristian König struct ttm_validate_buffer tv; 7809124a398SChristian König struct amdgpu_bo_va *bo_va; 7819124a398SChristian König uint32_t priority; 7829124a398SChristian König struct page **user_pages; 7839124a398SChristian König int user_invalidated; 7849124a398SChristian König }; 78597b2e202SAlex Deucher 78697b2e202SAlex Deucher struct amdgpu_bo_list { 78797b2e202SAlex Deucher struct mutex lock; 7885ac55629SAlex Xie struct rcu_head rhead; 7895ac55629SAlex Xie struct kref refcount; 79097b2e202SAlex Deucher struct amdgpu_bo *gds_obj; 79197b2e202SAlex Deucher struct amdgpu_bo *gws_obj; 79297b2e202SAlex Deucher struct amdgpu_bo *oa_obj; 793211dff55SChristian König unsigned first_userptr; 79497b2e202SAlex Deucher unsigned num_entries; 79597b2e202SAlex Deucher struct amdgpu_bo_list_entry *array; 79697b2e202SAlex Deucher }; 79797b2e202SAlex Deucher 79897b2e202SAlex Deucher struct amdgpu_bo_list * 79997b2e202SAlex Deucher amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 800636ce25cSChristian König void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 801636ce25cSChristian König struct list_head *validated); 80297b2e202SAlex Deucher void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 80397b2e202SAlex Deucher void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 80497b2e202SAlex Deucher 80597b2e202SAlex Deucher /* 80697b2e202SAlex Deucher * GFX stuff 80797b2e202SAlex Deucher */ 80897b2e202SAlex Deucher #include "clearstate_defs.h" 80997b2e202SAlex Deucher 81079e5412cSAlex Deucher struct amdgpu_rlc_funcs { 81179e5412cSAlex Deucher void (*enter_safe_mode)(struct amdgpu_device *adev); 81279e5412cSAlex Deucher void (*exit_safe_mode)(struct amdgpu_device *adev); 81379e5412cSAlex Deucher }; 81479e5412cSAlex Deucher 81597b2e202SAlex Deucher struct amdgpu_rlc { 81697b2e202SAlex Deucher /* for power gating */ 81797b2e202SAlex Deucher struct amdgpu_bo *save_restore_obj; 81897b2e202SAlex Deucher uint64_t save_restore_gpu_addr; 81997b2e202SAlex Deucher volatile uint32_t *sr_ptr; 82097b2e202SAlex Deucher const u32 *reg_list; 82197b2e202SAlex Deucher u32 reg_list_size; 82297b2e202SAlex Deucher /* for clear state */ 82397b2e202SAlex Deucher struct amdgpu_bo *clear_state_obj; 82497b2e202SAlex Deucher uint64_t clear_state_gpu_addr; 82597b2e202SAlex Deucher volatile uint32_t *cs_ptr; 82697b2e202SAlex Deucher const struct cs_section_def *cs_data; 82797b2e202SAlex Deucher u32 clear_state_size; 82897b2e202SAlex Deucher /* for cp tables */ 82997b2e202SAlex Deucher struct amdgpu_bo *cp_table_obj; 83097b2e202SAlex Deucher uint64_t cp_table_gpu_addr; 83197b2e202SAlex Deucher volatile uint32_t *cp_table_ptr; 83297b2e202SAlex Deucher u32 cp_table_size; 83379e5412cSAlex Deucher 83479e5412cSAlex Deucher /* safe mode for updating CG/PG state */ 83579e5412cSAlex Deucher bool in_safe_mode; 83679e5412cSAlex Deucher const struct amdgpu_rlc_funcs *funcs; 8372b6cd977SEric Huang 8382b6cd977SEric Huang /* for firmware data */ 8392b6cd977SEric Huang u32 save_and_restore_offset; 8402b6cd977SEric Huang u32 clear_state_descriptor_offset; 8412b6cd977SEric Huang u32 avail_scratch_ram_locations; 8422b6cd977SEric Huang u32 reg_restore_list_size; 8432b6cd977SEric Huang u32 reg_list_format_start; 8442b6cd977SEric Huang u32 reg_list_format_separate_start; 8452b6cd977SEric Huang u32 starting_offsets_start; 8462b6cd977SEric Huang u32 reg_list_format_size_bytes; 8472b6cd977SEric Huang u32 reg_list_size_bytes; 8482b6cd977SEric Huang 8492b6cd977SEric Huang u32 *register_list_format; 8502b6cd977SEric Huang u32 *register_restore; 85197b2e202SAlex Deucher }; 85297b2e202SAlex Deucher 85378c16834SAndres Rodriguez #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 85478c16834SAndres Rodriguez 85597b2e202SAlex Deucher struct amdgpu_mec { 85697b2e202SAlex Deucher struct amdgpu_bo *hpd_eop_obj; 85797b2e202SAlex Deucher u64 hpd_eop_gpu_addr; 858b1023571SKen Wang struct amdgpu_bo *mec_fw_obj; 859b1023571SKen Wang u64 mec_fw_gpu_addr; 86097b2e202SAlex Deucher u32 num_mec; 86142794b27SAndres Rodriguez u32 num_pipe_per_mec; 86242794b27SAndres Rodriguez u32 num_queue_per_pipe; 86359a82d7dSXiangliang Yu void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 86478c16834SAndres Rodriguez 86578c16834SAndres Rodriguez /* These are the resources for which amdgpu takes ownership */ 86678c16834SAndres Rodriguez DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 86797b2e202SAlex Deucher }; 86897b2e202SAlex Deucher 8694e638ae9SXiangliang Yu struct amdgpu_kiq { 8704e638ae9SXiangliang Yu u64 eop_gpu_addr; 8714e638ae9SXiangliang Yu struct amdgpu_bo *eop_obj; 872cdf6adb2SShaoyun Liu struct mutex ring_mutex; 8734e638ae9SXiangliang Yu struct amdgpu_ring ring; 8744e638ae9SXiangliang Yu struct amdgpu_irq_src irq; 8754e638ae9SXiangliang Yu }; 8764e638ae9SXiangliang Yu 87797b2e202SAlex Deucher /* 87897b2e202SAlex Deucher * GPU scratch registers structures, functions & helpers 87997b2e202SAlex Deucher */ 88097b2e202SAlex Deucher struct amdgpu_scratch { 88197b2e202SAlex Deucher unsigned num_reg; 88297b2e202SAlex Deucher uint32_t reg_base; 88350261151SNils Wallménius uint32_t free_mask; 88497b2e202SAlex Deucher }; 88597b2e202SAlex Deucher 88697b2e202SAlex Deucher /* 88797b2e202SAlex Deucher * GFX configurations 88897b2e202SAlex Deucher */ 889e3fa7630SAlex Deucher #define AMDGPU_GFX_MAX_SE 4 890e3fa7630SAlex Deucher #define AMDGPU_GFX_MAX_SH_PER_SE 2 891e3fa7630SAlex Deucher 892e3fa7630SAlex Deucher struct amdgpu_rb_config { 893e3fa7630SAlex Deucher uint32_t rb_backend_disable; 894e3fa7630SAlex Deucher uint32_t user_rb_backend_disable; 895e3fa7630SAlex Deucher uint32_t raster_config; 896e3fa7630SAlex Deucher uint32_t raster_config_1; 897e3fa7630SAlex Deucher }; 898e3fa7630SAlex Deucher 899d0e95758SAndrey Grodzovsky struct gb_addr_config { 900d0e95758SAndrey Grodzovsky uint16_t pipe_interleave_size; 901d0e95758SAndrey Grodzovsky uint8_t num_pipes; 902d0e95758SAndrey Grodzovsky uint8_t max_compress_frags; 903d0e95758SAndrey Grodzovsky uint8_t num_banks; 904d0e95758SAndrey Grodzovsky uint8_t num_se; 905d0e95758SAndrey Grodzovsky uint8_t num_rb_per_se; 906d0e95758SAndrey Grodzovsky }; 907d0e95758SAndrey Grodzovsky 908ea323f88SJunwei Zhang struct amdgpu_gfx_config { 90997b2e202SAlex Deucher unsigned max_shader_engines; 91097b2e202SAlex Deucher unsigned max_tile_pipes; 91197b2e202SAlex Deucher unsigned max_cu_per_sh; 91297b2e202SAlex Deucher unsigned max_sh_per_se; 91397b2e202SAlex Deucher unsigned max_backends_per_se; 91497b2e202SAlex Deucher unsigned max_texture_channel_caches; 91597b2e202SAlex Deucher unsigned max_gprs; 91697b2e202SAlex Deucher unsigned max_gs_threads; 91797b2e202SAlex Deucher unsigned max_hw_contexts; 91897b2e202SAlex Deucher unsigned sc_prim_fifo_size_frontend; 91997b2e202SAlex Deucher unsigned sc_prim_fifo_size_backend; 92097b2e202SAlex Deucher unsigned sc_hiz_tile_fifo_size; 92197b2e202SAlex Deucher unsigned sc_earlyz_tile_fifo_size; 92297b2e202SAlex Deucher 92397b2e202SAlex Deucher unsigned num_tile_pipes; 92497b2e202SAlex Deucher unsigned backend_enable_mask; 92597b2e202SAlex Deucher unsigned mem_max_burst_length_bytes; 92697b2e202SAlex Deucher unsigned mem_row_size_in_kb; 92797b2e202SAlex Deucher unsigned shader_engine_tile_size; 92897b2e202SAlex Deucher unsigned num_gpus; 92997b2e202SAlex Deucher unsigned multi_gpu_tile_size; 93097b2e202SAlex Deucher unsigned mc_arb_ramcfg; 93197b2e202SAlex Deucher unsigned gb_addr_config; 9328f8e00c1SAlex Deucher unsigned num_rbs; 933408bfe7cSJunwei Zhang unsigned gs_vgt_table_depth; 934408bfe7cSJunwei Zhang unsigned gs_prim_buffer_depth; 93597b2e202SAlex Deucher 93697b2e202SAlex Deucher uint32_t tile_mode_array[32]; 93797b2e202SAlex Deucher uint32_t macrotile_mode_array[16]; 938e3fa7630SAlex Deucher 939d0e95758SAndrey Grodzovsky struct gb_addr_config gb_addr_config_fields; 940e3fa7630SAlex Deucher struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 941df6e2c4aSJunwei Zhang 942df6e2c4aSJunwei Zhang /* gfx configure feature */ 943df6e2c4aSJunwei Zhang uint32_t double_offchip_lds_buf; 94497b2e202SAlex Deucher }; 94597b2e202SAlex Deucher 9467dae69a2SAlex Deucher struct amdgpu_cu_info { 94751fd0370SHawking Zhang uint32_t max_waves_per_simd; 948408bfe7cSJunwei Zhang uint32_t wave_front_size; 94951fd0370SHawking Zhang uint32_t max_scratch_slots_per_cu; 95051fd0370SHawking Zhang uint32_t lds_size; 951dbfe85eaSFlora Cui 952dbfe85eaSFlora Cui /* total active CU number */ 953dbfe85eaSFlora Cui uint32_t number; 954dbfe85eaSFlora Cui uint32_t ao_cu_mask; 955dbfe85eaSFlora Cui uint32_t ao_cu_bitmap[4][4]; 9567dae69a2SAlex Deucher uint32_t bitmap[4][4]; 9577dae69a2SAlex Deucher }; 9587dae69a2SAlex Deucher 959b95e31fdSAlex Deucher struct amdgpu_gfx_funcs { 960b95e31fdSAlex Deucher /* get the gpu clock counter */ 961b95e31fdSAlex Deucher uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 9629559ef5bSTom St Denis void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 963472259f0STom St Denis void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); 964c5a60ce8STom St Denis void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); 965c5a60ce8STom St Denis void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); 966b95e31fdSAlex Deucher }; 967b95e31fdSAlex Deucher 968bce23e00SAlex Deucher struct amdgpu_ngg_buf { 969bce23e00SAlex Deucher struct amdgpu_bo *bo; 970bce23e00SAlex Deucher uint64_t gpu_addr; 971bce23e00SAlex Deucher uint32_t size; 972bce23e00SAlex Deucher uint32_t bo_size; 973bce23e00SAlex Deucher }; 974bce23e00SAlex Deucher 975bce23e00SAlex Deucher enum { 976af8baf15SGuenter Roeck NGG_PRIM = 0, 977af8baf15SGuenter Roeck NGG_POS, 978af8baf15SGuenter Roeck NGG_CNTL, 979af8baf15SGuenter Roeck NGG_PARAM, 980bce23e00SAlex Deucher NGG_BUF_MAX 981bce23e00SAlex Deucher }; 982bce23e00SAlex Deucher 983bce23e00SAlex Deucher struct amdgpu_ngg { 984bce23e00SAlex Deucher struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; 985bce23e00SAlex Deucher uint32_t gds_reserve_addr; 986bce23e00SAlex Deucher uint32_t gds_reserve_size; 987bce23e00SAlex Deucher bool init; 988bce23e00SAlex Deucher }; 989bce23e00SAlex Deucher 99097b2e202SAlex Deucher struct amdgpu_gfx { 99197b2e202SAlex Deucher struct mutex gpu_clock_mutex; 992ea323f88SJunwei Zhang struct amdgpu_gfx_config config; 99397b2e202SAlex Deucher struct amdgpu_rlc rlc; 99497b2e202SAlex Deucher struct amdgpu_mec mec; 9954e638ae9SXiangliang Yu struct amdgpu_kiq kiq; 99697b2e202SAlex Deucher struct amdgpu_scratch scratch; 99797b2e202SAlex Deucher const struct firmware *me_fw; /* ME firmware */ 99897b2e202SAlex Deucher uint32_t me_fw_version; 99997b2e202SAlex Deucher const struct firmware *pfp_fw; /* PFP firmware */ 100097b2e202SAlex Deucher uint32_t pfp_fw_version; 100197b2e202SAlex Deucher const struct firmware *ce_fw; /* CE firmware */ 100297b2e202SAlex Deucher uint32_t ce_fw_version; 100397b2e202SAlex Deucher const struct firmware *rlc_fw; /* RLC firmware */ 100497b2e202SAlex Deucher uint32_t rlc_fw_version; 100597b2e202SAlex Deucher const struct firmware *mec_fw; /* MEC firmware */ 100697b2e202SAlex Deucher uint32_t mec_fw_version; 100797b2e202SAlex Deucher const struct firmware *mec2_fw; /* MEC2 firmware */ 100897b2e202SAlex Deucher uint32_t mec2_fw_version; 100902558a00SKen Wang uint32_t me_feature_version; 101002558a00SKen Wang uint32_t ce_feature_version; 101102558a00SKen Wang uint32_t pfp_feature_version; 1012351643d7SJammy Zhou uint32_t rlc_feature_version; 1013351643d7SJammy Zhou uint32_t mec_feature_version; 1014351643d7SJammy Zhou uint32_t mec2_feature_version; 101597b2e202SAlex Deucher struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 101697b2e202SAlex Deucher unsigned num_gfx_rings; 101797b2e202SAlex Deucher struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 101897b2e202SAlex Deucher unsigned num_compute_rings; 101997b2e202SAlex Deucher struct amdgpu_irq_src eop_irq; 102097b2e202SAlex Deucher struct amdgpu_irq_src priv_reg_irq; 102197b2e202SAlex Deucher struct amdgpu_irq_src priv_inst_irq; 102297b2e202SAlex Deucher /* gfx status */ 102397b2e202SAlex Deucher uint32_t gfx_current_status; 1024a101a899SKen Wang /* ce ram size*/ 1025a101a899SKen Wang unsigned ce_ram_size; 10267dae69a2SAlex Deucher struct amdgpu_cu_info cu_info; 1027b95e31fdSAlex Deucher const struct amdgpu_gfx_funcs *funcs; 10283d7c6384SChunming Zhou 10293d7c6384SChunming Zhou /* reset mask */ 10303d7c6384SChunming Zhou uint32_t grbm_soft_reset; 10313d7c6384SChunming Zhou uint32_t srbm_soft_reset; 1032b4e40676SDavid Panariti /* s3/s4 mask */ 1033b4e40676SDavid Panariti bool in_suspend; 1034bce23e00SAlex Deucher /* NGG */ 1035bce23e00SAlex Deucher struct amdgpu_ngg ngg; 103697b2e202SAlex Deucher }; 103797b2e202SAlex Deucher 1038b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 103997b2e202SAlex Deucher unsigned size, struct amdgpu_ib *ib); 10404d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 1041f54d1867SChris Wilson struct dma_fence *f); 1042b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 104350ddc75eSJunwei Zhang struct amdgpu_ib *ibs, struct amdgpu_job *job, 104450ddc75eSJunwei Zhang struct dma_fence **f); 104597b2e202SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev); 104697b2e202SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 104797b2e202SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 104897b2e202SAlex Deucher 104997b2e202SAlex Deucher /* 105097b2e202SAlex Deucher * CS. 105197b2e202SAlex Deucher */ 105297b2e202SAlex Deucher struct amdgpu_cs_chunk { 105397b2e202SAlex Deucher uint32_t chunk_id; 105497b2e202SAlex Deucher uint32_t length_dw; 1055758ac17fSChristian König void *kdata; 105697b2e202SAlex Deucher }; 105797b2e202SAlex Deucher 105897b2e202SAlex Deucher struct amdgpu_cs_parser { 105997b2e202SAlex Deucher struct amdgpu_device *adev; 106097b2e202SAlex Deucher struct drm_file *filp; 10613cb485f3SChristian König struct amdgpu_ctx *ctx; 1062c3cca41eSChristian König 106397b2e202SAlex Deucher /* chunks */ 106497b2e202SAlex Deucher unsigned nchunks; 106597b2e202SAlex Deucher struct amdgpu_cs_chunk *chunks; 1066c3cca41eSChristian König 106750838c8cSChristian König /* scheduler job object */ 106850838c8cSChristian König struct amdgpu_job *job; 1069c3cca41eSChristian König 1070c3cca41eSChristian König /* buffer objects */ 1071c3cca41eSChristian König struct ww_acquire_ctx ticket; 1072c3cca41eSChristian König struct amdgpu_bo_list *bo_list; 10733fe89771SChristian König struct amdgpu_mn *mn; 107456467ebfSChristian König struct amdgpu_bo_list_entry vm_pd; 107597b2e202SAlex Deucher struct list_head validated; 1076f54d1867SChris Wilson struct dma_fence *fence; 1077f69f90a1SChristian König uint64_t bytes_moved_threshold; 107800f06b24SJohn Brooks uint64_t bytes_moved_vis_threshold; 1079f69f90a1SChristian König uint64_t bytes_moved; 108000f06b24SJohn Brooks uint64_t bytes_moved_vis; 1081662bfa61SChristian König struct amdgpu_bo_list_entry *evictable; 108297b2e202SAlex Deucher 108397b2e202SAlex Deucher /* user fence */ 108491acbeb6SChristian König struct amdgpu_bo_list_entry uf_entry; 1085660e8558SDave Airlie 1086660e8558SDave Airlie unsigned num_post_dep_syncobjs; 1087660e8558SDave Airlie struct drm_syncobj **post_dep_syncobjs; 108897b2e202SAlex Deucher }; 108997b2e202SAlex Deucher 1090753ad49cSMonk Liu #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ 1091753ad49cSMonk Liu #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ 1092753ad49cSMonk Liu #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ 1093753ad49cSMonk Liu 1094bb977d37SChunming Zhou struct amdgpu_job { 1095bb977d37SChunming Zhou struct amd_sched_job base; 1096bb977d37SChunming Zhou struct amdgpu_device *adev; 1097c5637837SMonk Liu struct amdgpu_vm *vm; 1098b07c60c0SChristian König struct amdgpu_ring *ring; 1099e86f9ceeSChristian König struct amdgpu_sync sync; 1100a340c7bcSChunming Zhou struct amdgpu_sync dep_sync; 1101df83d1ebSChunming Zhou struct amdgpu_sync sched_sync; 1102bb977d37SChunming Zhou struct amdgpu_ib *ibs; 1103f54d1867SChris Wilson struct dma_fence *fence; /* the hw fence */ 1104753ad49cSMonk Liu uint32_t preamble_status; 1105bb977d37SChunming Zhou uint32_t num_ibs; 1106e2840221SChristian König void *owner; 11073aecd24cSMonk Liu uint64_t fence_ctx; /* the fence_context this job uses */ 1108fd53be30SChunming Zhou bool vm_needs_flush; 1109d88bf583SChristian König unsigned vm_id; 1110d88bf583SChristian König uint64_t vm_pd_addr; 1111d88bf583SChristian König uint32_t gds_base, gds_size; 1112d88bf583SChristian König uint32_t gws_base, gws_size; 1113d88bf583SChristian König uint32_t oa_base, oa_size; 1114758ac17fSChristian König 1115758ac17fSChristian König /* user fence handling */ 1116b5f5acbcSChristian König uint64_t uf_addr; 1117758ac17fSChristian König uint64_t uf_sequence; 1118758ac17fSChristian König 1119bb977d37SChunming Zhou }; 1120a6db8a33SJunwei Zhang #define to_amdgpu_job(sched_job) \ 1121a6db8a33SJunwei Zhang container_of((sched_job), struct amdgpu_job, base) 1122bb977d37SChunming Zhou 11237270f839SChristian König static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 11247270f839SChristian König uint32_t ib_idx, int idx) 112597b2e202SAlex Deucher { 112650838c8cSChristian König return p->job->ibs[ib_idx].ptr[idx]; 112797b2e202SAlex Deucher } 112897b2e202SAlex Deucher 11297270f839SChristian König static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 11307270f839SChristian König uint32_t ib_idx, int idx, 11317270f839SChristian König uint32_t value) 11327270f839SChristian König { 113350838c8cSChristian König p->job->ibs[ib_idx].ptr[idx] = value; 11347270f839SChristian König } 11357270f839SChristian König 113697b2e202SAlex Deucher /* 113797b2e202SAlex Deucher * Writeback 113897b2e202SAlex Deucher */ 113997b2e202SAlex Deucher #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 114097b2e202SAlex Deucher 114197b2e202SAlex Deucher struct amdgpu_wb { 114297b2e202SAlex Deucher struct amdgpu_bo *wb_obj; 114397b2e202SAlex Deucher volatile uint32_t *wb; 114497b2e202SAlex Deucher uint64_t gpu_addr; 114597b2e202SAlex Deucher u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 114697b2e202SAlex Deucher unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 114797b2e202SAlex Deucher }; 114897b2e202SAlex Deucher 114997b2e202SAlex Deucher int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 115097b2e202SAlex Deucher void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 115197b2e202SAlex Deucher 1152d0dd7f0cSAlex Deucher void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1153d0dd7f0cSAlex Deucher 115497b2e202SAlex Deucher /* 115597b2e202SAlex Deucher * SDMA 115697b2e202SAlex Deucher */ 1157c113ea1cSAlex Deucher struct amdgpu_sdma_instance { 115897b2e202SAlex Deucher /* SDMA firmware */ 115997b2e202SAlex Deucher const struct firmware *fw; 116097b2e202SAlex Deucher uint32_t fw_version; 1161cfa2104fSJammy Zhou uint32_t feature_version; 116297b2e202SAlex Deucher 116397b2e202SAlex Deucher struct amdgpu_ring ring; 116418111de0SJammy Zhou bool burst_nop; 116597b2e202SAlex Deucher }; 116697b2e202SAlex Deucher 1167c113ea1cSAlex Deucher struct amdgpu_sdma { 1168c113ea1cSAlex Deucher struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 116930d1574fSKen Wang #ifdef CONFIG_DRM_AMDGPU_SI 117030d1574fSKen Wang //SI DMA has a difference trap irq number for the second engine 117130d1574fSKen Wang struct amdgpu_irq_src trap_irq_1; 117230d1574fSKen Wang #endif 1173c113ea1cSAlex Deucher struct amdgpu_irq_src trap_irq; 1174c113ea1cSAlex Deucher struct amdgpu_irq_src illegal_inst_irq; 1175c113ea1cSAlex Deucher int num_instances; 1176e702a680SChunming Zhou uint32_t srbm_soft_reset; 1177c113ea1cSAlex Deucher }; 1178c113ea1cSAlex Deucher 117997b2e202SAlex Deucher /* 118097b2e202SAlex Deucher * Firmware 118197b2e202SAlex Deucher */ 1182e635ee07SHuang Rui enum amdgpu_firmware_load_type { 1183e635ee07SHuang Rui AMDGPU_FW_LOAD_DIRECT = 0, 1184e635ee07SHuang Rui AMDGPU_FW_LOAD_SMU, 1185e635ee07SHuang Rui AMDGPU_FW_LOAD_PSP, 1186e635ee07SHuang Rui }; 1187e635ee07SHuang Rui 118897b2e202SAlex Deucher struct amdgpu_firmware { 118997b2e202SAlex Deucher struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1190e635ee07SHuang Rui enum amdgpu_firmware_load_type load_type; 119197b2e202SAlex Deucher struct amdgpu_bo *fw_buf; 119297b2e202SAlex Deucher unsigned int fw_size; 11932445b227SHuang Rui unsigned int max_ucodes; 11940e5ca0d1SHuang Rui /* firmwares are loaded by psp instead of smu from vega10 */ 11950e5ca0d1SHuang Rui const struct amdgpu_psp_funcs *funcs; 11960e5ca0d1SHuang Rui struct amdgpu_bo *rbuf; 11970e5ca0d1SHuang Rui struct mutex mutex; 1198ab4fe3e1SHuang Rui 1199ab4fe3e1SHuang Rui /* gpu info firmware data pointer */ 1200ab4fe3e1SHuang Rui const struct firmware *gpu_info_fw; 1201d59c026bSMonk Liu 1202d59c026bSMonk Liu void *fw_buf_ptr; 1203d59c026bSMonk Liu uint64_t fw_buf_mc; 120497b2e202SAlex Deucher }; 120597b2e202SAlex Deucher 120697b2e202SAlex Deucher /* 120797b2e202SAlex Deucher * Benchmarking 120897b2e202SAlex Deucher */ 120997b2e202SAlex Deucher void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 121097b2e202SAlex Deucher 121197b2e202SAlex Deucher 121297b2e202SAlex Deucher /* 121397b2e202SAlex Deucher * Testing 121497b2e202SAlex Deucher */ 121597b2e202SAlex Deucher void amdgpu_test_moves(struct amdgpu_device *adev); 121697b2e202SAlex Deucher 121797b2e202SAlex Deucher /* 121897b2e202SAlex Deucher * Debugfs 121997b2e202SAlex Deucher */ 122097b2e202SAlex Deucher struct amdgpu_debugfs { 122106ab6832SNils Wallménius const struct drm_info_list *files; 122297b2e202SAlex Deucher unsigned num_files; 122397b2e202SAlex Deucher }; 122497b2e202SAlex Deucher 122597b2e202SAlex Deucher int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 122606ab6832SNils Wallménius const struct drm_info_list *files, 122797b2e202SAlex Deucher unsigned nfiles); 122897b2e202SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 122997b2e202SAlex Deucher 123097b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS) 123197b2e202SAlex Deucher int amdgpu_debugfs_init(struct drm_minor *minor); 123297b2e202SAlex Deucher #endif 123397b2e202SAlex Deucher 123450ab2533SHuang Rui int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); 123550ab2533SHuang Rui 123697b2e202SAlex Deucher /* 123797b2e202SAlex Deucher * amdgpu smumgr functions 123897b2e202SAlex Deucher */ 123997b2e202SAlex Deucher struct amdgpu_smumgr_funcs { 124097b2e202SAlex Deucher int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 124197b2e202SAlex Deucher int (*request_smu_load_fw)(struct amdgpu_device *adev); 124297b2e202SAlex Deucher int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 124397b2e202SAlex Deucher }; 124497b2e202SAlex Deucher 124597b2e202SAlex Deucher /* 124697b2e202SAlex Deucher * amdgpu smumgr 124797b2e202SAlex Deucher */ 124897b2e202SAlex Deucher struct amdgpu_smumgr { 124997b2e202SAlex Deucher struct amdgpu_bo *toc_buf; 125097b2e202SAlex Deucher struct amdgpu_bo *smu_buf; 125197b2e202SAlex Deucher /* asic priv smu data */ 125297b2e202SAlex Deucher void *priv; 125397b2e202SAlex Deucher spinlock_t smu_lock; 125497b2e202SAlex Deucher /* smumgr functions */ 125597b2e202SAlex Deucher const struct amdgpu_smumgr_funcs *smumgr_funcs; 125697b2e202SAlex Deucher /* ucode loading complete flag */ 125797b2e202SAlex Deucher uint32_t fw_flags; 125897b2e202SAlex Deucher }; 125997b2e202SAlex Deucher 126097b2e202SAlex Deucher /* 126197b2e202SAlex Deucher * ASIC specific register table accessible by UMD 126297b2e202SAlex Deucher */ 126397b2e202SAlex Deucher struct amdgpu_allowed_register_entry { 126497b2e202SAlex Deucher uint32_t reg_offset; 126597b2e202SAlex Deucher bool grbm_indexed; 126697b2e202SAlex Deucher }; 126797b2e202SAlex Deucher 126897b2e202SAlex Deucher /* 126997b2e202SAlex Deucher * ASIC specific functions. 127097b2e202SAlex Deucher */ 127197b2e202SAlex Deucher struct amdgpu_asic_funcs { 127297b2e202SAlex Deucher bool (*read_disabled_bios)(struct amdgpu_device *adev); 12737946b878SAlex Deucher bool (*read_bios_from_rom)(struct amdgpu_device *adev, 12747946b878SAlex Deucher u8 *bios, u32 length_bytes); 127597b2e202SAlex Deucher int (*read_register)(struct amdgpu_device *adev, u32 se_num, 127697b2e202SAlex Deucher u32 sh_num, u32 reg_offset, u32 *value); 127797b2e202SAlex Deucher void (*set_vga_state)(struct amdgpu_device *adev, bool state); 127897b2e202SAlex Deucher int (*reset)(struct amdgpu_device *adev); 127997b2e202SAlex Deucher /* get the reference clock */ 128097b2e202SAlex Deucher u32 (*get_xclk)(struct amdgpu_device *adev); 128197b2e202SAlex Deucher /* MM block clocks */ 128297b2e202SAlex Deucher int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 128397b2e202SAlex Deucher int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1284841686dfSMaruthi Bayyavarapu /* static power management */ 1285841686dfSMaruthi Bayyavarapu int (*get_pcie_lanes)(struct amdgpu_device *adev); 1286841686dfSMaruthi Bayyavarapu void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 1287bbf282d8SAlex Deucher /* get config memsize register */ 1288bbf282d8SAlex Deucher u32 (*get_config_memsize)(struct amdgpu_device *adev); 128997b2e202SAlex Deucher }; 129097b2e202SAlex Deucher 129197b2e202SAlex Deucher /* 129297b2e202SAlex Deucher * IOCTL. 129397b2e202SAlex Deucher */ 129497b2e202SAlex Deucher int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 129597b2e202SAlex Deucher struct drm_file *filp); 129697b2e202SAlex Deucher int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 129797b2e202SAlex Deucher struct drm_file *filp); 129897b2e202SAlex Deucher 129997b2e202SAlex Deucher int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 130097b2e202SAlex Deucher struct drm_file *filp); 130197b2e202SAlex Deucher int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 130297b2e202SAlex Deucher struct drm_file *filp); 130397b2e202SAlex Deucher int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 130497b2e202SAlex Deucher struct drm_file *filp); 130597b2e202SAlex Deucher int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 130697b2e202SAlex Deucher struct drm_file *filp); 130797b2e202SAlex Deucher int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 130897b2e202SAlex Deucher struct drm_file *filp); 130997b2e202SAlex Deucher int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 131097b2e202SAlex Deucher struct drm_file *filp); 131197b2e202SAlex Deucher int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 131297b2e202SAlex Deucher int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1313eef18a82SJunwei Zhang int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 1314eef18a82SJunwei Zhang struct drm_file *filp); 131597b2e202SAlex Deucher 131697b2e202SAlex Deucher int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 131797b2e202SAlex Deucher struct drm_file *filp); 131897b2e202SAlex Deucher 131997b2e202SAlex Deucher /* VRAM scratch page for HDP bug, default vram page */ 132097b2e202SAlex Deucher struct amdgpu_vram_scratch { 132197b2e202SAlex Deucher struct amdgpu_bo *robj; 132297b2e202SAlex Deucher volatile uint32_t *ptr; 132397b2e202SAlex Deucher u64 gpu_addr; 132497b2e202SAlex Deucher }; 132597b2e202SAlex Deucher 132697b2e202SAlex Deucher /* 132797b2e202SAlex Deucher * ACPI 132897b2e202SAlex Deucher */ 132997b2e202SAlex Deucher struct amdgpu_atif_notification_cfg { 133097b2e202SAlex Deucher bool enabled; 133197b2e202SAlex Deucher int command_code; 133297b2e202SAlex Deucher }; 133397b2e202SAlex Deucher 133497b2e202SAlex Deucher struct amdgpu_atif_notifications { 133597b2e202SAlex Deucher bool display_switch; 133697b2e202SAlex Deucher bool expansion_mode_change; 133797b2e202SAlex Deucher bool thermal_state; 133897b2e202SAlex Deucher bool forced_power_state; 133997b2e202SAlex Deucher bool system_power_state; 134097b2e202SAlex Deucher bool display_conf_change; 134197b2e202SAlex Deucher bool px_gfx_switch; 134297b2e202SAlex Deucher bool brightness_change; 134397b2e202SAlex Deucher bool dgpu_display_event; 134497b2e202SAlex Deucher }; 134597b2e202SAlex Deucher 134697b2e202SAlex Deucher struct amdgpu_atif_functions { 134797b2e202SAlex Deucher bool system_params; 134897b2e202SAlex Deucher bool sbios_requests; 134997b2e202SAlex Deucher bool select_active_disp; 135097b2e202SAlex Deucher bool lid_state; 135197b2e202SAlex Deucher bool get_tv_standard; 135297b2e202SAlex Deucher bool set_tv_standard; 135397b2e202SAlex Deucher bool get_panel_expansion_mode; 135497b2e202SAlex Deucher bool set_panel_expansion_mode; 135597b2e202SAlex Deucher bool temperature_change; 135697b2e202SAlex Deucher bool graphics_device_types; 135797b2e202SAlex Deucher }; 135897b2e202SAlex Deucher 135997b2e202SAlex Deucher struct amdgpu_atif { 136097b2e202SAlex Deucher struct amdgpu_atif_notifications notifications; 136197b2e202SAlex Deucher struct amdgpu_atif_functions functions; 136297b2e202SAlex Deucher struct amdgpu_atif_notification_cfg notification_cfg; 136397b2e202SAlex Deucher struct amdgpu_encoder *encoder_for_bl; 136497b2e202SAlex Deucher }; 136597b2e202SAlex Deucher 136697b2e202SAlex Deucher struct amdgpu_atcs_functions { 136797b2e202SAlex Deucher bool get_ext_state; 136897b2e202SAlex Deucher bool pcie_perf_req; 136997b2e202SAlex Deucher bool pcie_dev_rdy; 137097b2e202SAlex Deucher bool pcie_bus_width; 137197b2e202SAlex Deucher }; 137297b2e202SAlex Deucher 137397b2e202SAlex Deucher struct amdgpu_atcs { 137497b2e202SAlex Deucher struct amdgpu_atcs_functions functions; 137597b2e202SAlex Deucher }; 137697b2e202SAlex Deucher 137797b2e202SAlex Deucher /* 1378d03846afSChunming Zhou * CGS 1379d03846afSChunming Zhou */ 1380110e6f26SDave Airlie struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1381110e6f26SDave Airlie void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1382a8fe58ceSMaruthi Bayyavarapu 1383a8fe58ceSMaruthi Bayyavarapu /* 138497b2e202SAlex Deucher * Core structure, functions and helpers. 138597b2e202SAlex Deucher */ 138697b2e202SAlex Deucher typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 138797b2e202SAlex Deucher typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 138897b2e202SAlex Deucher 138997b2e202SAlex Deucher typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 139097b2e202SAlex Deucher typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 139197b2e202SAlex Deucher 13920c49e0b8SChunming Zhou #define AMDGPU_RESET_MAGIC_NUM 64 139397b2e202SAlex Deucher struct amdgpu_device { 139497b2e202SAlex Deucher struct device *dev; 139597b2e202SAlex Deucher struct drm_device *ddev; 139697b2e202SAlex Deucher struct pci_dev *pdev; 139797b2e202SAlex Deucher 1398a8fe58ceSMaruthi Bayyavarapu #ifdef CONFIG_DRM_AMD_ACP 1399a8fe58ceSMaruthi Bayyavarapu struct amdgpu_acp acp; 1400a8fe58ceSMaruthi Bayyavarapu #endif 1401a8fe58ceSMaruthi Bayyavarapu 140297b2e202SAlex Deucher /* ASIC */ 14032f7d10b3SJammy Zhou enum amd_asic_type asic_type; 140497b2e202SAlex Deucher uint32_t family; 140597b2e202SAlex Deucher uint32_t rev_id; 140697b2e202SAlex Deucher uint32_t external_rev_id; 140797b2e202SAlex Deucher unsigned long flags; 140897b2e202SAlex Deucher int usec_timeout; 140997b2e202SAlex Deucher const struct amdgpu_asic_funcs *asic_funcs; 141097b2e202SAlex Deucher bool shutdown; 141197b2e202SAlex Deucher bool need_dma32; 141297b2e202SAlex Deucher bool accel_working; 141397b2e202SAlex Deucher struct work_struct reset_work; 141497b2e202SAlex Deucher struct notifier_block acpi_nb; 141597b2e202SAlex Deucher struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 141697b2e202SAlex Deucher struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 141797b2e202SAlex Deucher unsigned debugfs_count; 141897b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS) 1419adcec288STom St Denis struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 142097b2e202SAlex Deucher #endif 142197b2e202SAlex Deucher struct amdgpu_atif atif; 142297b2e202SAlex Deucher struct amdgpu_atcs atcs; 142397b2e202SAlex Deucher struct mutex srbm_mutex; 142497b2e202SAlex Deucher /* GRBM index mutex. Protects concurrent access to GRBM index */ 142597b2e202SAlex Deucher struct mutex grbm_idx_mutex; 142697b2e202SAlex Deucher struct dev_pm_domain vga_pm_domain; 142797b2e202SAlex Deucher bool have_disp_power_ref; 142897b2e202SAlex Deucher 142997b2e202SAlex Deucher /* BIOS */ 14300cdd5005SAlex Deucher bool is_atom_fw; 143197b2e202SAlex Deucher uint8_t *bios; 1432a9f5db9cSEvan Quan uint32_t bios_size; 14335af2c10dSKent Russell struct amdgpu_bo *stolen_vga_memory; 1434a5bde2f9SAlex Deucher uint32_t bios_scratch_reg_offset; 143597b2e202SAlex Deucher uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 143697b2e202SAlex Deucher 143797b2e202SAlex Deucher /* Register/doorbell mmio */ 143897b2e202SAlex Deucher resource_size_t rmmio_base; 143997b2e202SAlex Deucher resource_size_t rmmio_size; 144097b2e202SAlex Deucher void __iomem *rmmio; 144197b2e202SAlex Deucher /* protects concurrent MM_INDEX/DATA based register access */ 144297b2e202SAlex Deucher spinlock_t mmio_idx_lock; 144397b2e202SAlex Deucher /* protects concurrent SMC based register access */ 144497b2e202SAlex Deucher spinlock_t smc_idx_lock; 144597b2e202SAlex Deucher amdgpu_rreg_t smc_rreg; 144697b2e202SAlex Deucher amdgpu_wreg_t smc_wreg; 144797b2e202SAlex Deucher /* protects concurrent PCIE register access */ 144897b2e202SAlex Deucher spinlock_t pcie_idx_lock; 144997b2e202SAlex Deucher amdgpu_rreg_t pcie_rreg; 145097b2e202SAlex Deucher amdgpu_wreg_t pcie_wreg; 145136b9a952SHuang Rui amdgpu_rreg_t pciep_rreg; 145236b9a952SHuang Rui amdgpu_wreg_t pciep_wreg; 145397b2e202SAlex Deucher /* protects concurrent UVD register access */ 145497b2e202SAlex Deucher spinlock_t uvd_ctx_idx_lock; 145597b2e202SAlex Deucher amdgpu_rreg_t uvd_ctx_rreg; 145697b2e202SAlex Deucher amdgpu_wreg_t uvd_ctx_wreg; 145797b2e202SAlex Deucher /* protects concurrent DIDT register access */ 145897b2e202SAlex Deucher spinlock_t didt_idx_lock; 145997b2e202SAlex Deucher amdgpu_rreg_t didt_rreg; 146097b2e202SAlex Deucher amdgpu_wreg_t didt_wreg; 1461ccdbb20aSRex Zhu /* protects concurrent gc_cac register access */ 1462ccdbb20aSRex Zhu spinlock_t gc_cac_idx_lock; 1463ccdbb20aSRex Zhu amdgpu_rreg_t gc_cac_rreg; 1464ccdbb20aSRex Zhu amdgpu_wreg_t gc_cac_wreg; 146516abb5d2SEvan Quan /* protects concurrent se_cac register access */ 146616abb5d2SEvan Quan spinlock_t se_cac_idx_lock; 146716abb5d2SEvan Quan amdgpu_rreg_t se_cac_rreg; 146816abb5d2SEvan Quan amdgpu_wreg_t se_cac_wreg; 146997b2e202SAlex Deucher /* protects concurrent ENDPOINT (audio) register access */ 147097b2e202SAlex Deucher spinlock_t audio_endpt_idx_lock; 147197b2e202SAlex Deucher amdgpu_block_rreg_t audio_endpt_rreg; 147297b2e202SAlex Deucher amdgpu_block_wreg_t audio_endpt_wreg; 147397b2e202SAlex Deucher void __iomem *rio_mem; 147497b2e202SAlex Deucher resource_size_t rio_mem_size; 147597b2e202SAlex Deucher struct amdgpu_doorbell doorbell; 147697b2e202SAlex Deucher 147797b2e202SAlex Deucher /* clock/pll info */ 147897b2e202SAlex Deucher struct amdgpu_clock clock; 147997b2e202SAlex Deucher 148097b2e202SAlex Deucher /* MC */ 148197b2e202SAlex Deucher struct amdgpu_mc mc; 148297b2e202SAlex Deucher struct amdgpu_gart gart; 148397b2e202SAlex Deucher struct amdgpu_dummy_page dummy_page; 148497b2e202SAlex Deucher struct amdgpu_vm_manager vm_manager; 1485e60f8db5SAlex Xie struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 148697b2e202SAlex Deucher 148797b2e202SAlex Deucher /* memory management */ 148897b2e202SAlex Deucher struct amdgpu_mman mman; 148997b2e202SAlex Deucher struct amdgpu_vram_scratch vram_scratch; 149097b2e202SAlex Deucher struct amdgpu_wb wb; 149197b2e202SAlex Deucher atomic64_t num_bytes_moved; 1492dbd5ed60SChristian König atomic64_t num_evictions; 149368e2c5ffSMarek Olšák atomic64_t num_vram_cpu_page_faults; 1494d94aed5aSMarek Olšák atomic_t gpu_reset_counter; 1495f1892138SChunming Zhou atomic_t vram_lost_counter; 149697b2e202SAlex Deucher 149795844d20SMarek Olšák /* data for buffer migration throttling */ 149895844d20SMarek Olšák struct { 149995844d20SMarek Olšák spinlock_t lock; 150095844d20SMarek Olšák s64 last_update_us; 150195844d20SMarek Olšák s64 accum_us; /* accumulated microseconds */ 150200f06b24SJohn Brooks s64 accum_us_vis; /* for visible VRAM */ 150395844d20SMarek Olšák u32 log2_max_MBps; 150495844d20SMarek Olšák } mm_stats; 150595844d20SMarek Olšák 150697b2e202SAlex Deucher /* display */ 15079accf2fdSEmily Deng bool enable_virtual_display; 150897b2e202SAlex Deucher struct amdgpu_mode_info mode_info; 150997b2e202SAlex Deucher struct work_struct hotplug_work; 151097b2e202SAlex Deucher struct amdgpu_irq_src crtc_irq; 151197b2e202SAlex Deucher struct amdgpu_irq_src pageflip_irq; 151297b2e202SAlex Deucher struct amdgpu_irq_src hpd_irq; 151397b2e202SAlex Deucher 151497b2e202SAlex Deucher /* rings */ 151576bf0db5SChristian König u64 fence_context; 151697b2e202SAlex Deucher unsigned num_rings; 151797b2e202SAlex Deucher struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 151897b2e202SAlex Deucher bool ib_pool_ready; 151997b2e202SAlex Deucher struct amdgpu_sa_manager ring_tmp_bo; 152097b2e202SAlex Deucher 152197b2e202SAlex Deucher /* interrupts */ 152297b2e202SAlex Deucher struct amdgpu_irq irq; 152397b2e202SAlex Deucher 15241f7371b2SAlex Deucher /* powerplay */ 15251f7371b2SAlex Deucher struct amd_powerplay powerplay; 1526e61710c5SJammy Zhou bool pp_enabled; 1527f3898ea1SEric Huang bool pp_force_state_enabled; 15281f7371b2SAlex Deucher 152997b2e202SAlex Deucher /* dpm */ 153097b2e202SAlex Deucher struct amdgpu_pm pm; 153197b2e202SAlex Deucher u32 cg_flags; 153297b2e202SAlex Deucher u32 pg_flags; 153397b2e202SAlex Deucher 153497b2e202SAlex Deucher /* amdgpu smumgr */ 153597b2e202SAlex Deucher struct amdgpu_smumgr smu; 153697b2e202SAlex Deucher 153797b2e202SAlex Deucher /* gfx */ 153897b2e202SAlex Deucher struct amdgpu_gfx gfx; 153997b2e202SAlex Deucher 154097b2e202SAlex Deucher /* sdma */ 1541c113ea1cSAlex Deucher struct amdgpu_sdma sdma; 154297b2e202SAlex Deucher 154395d0906fSLeo Liu union { 154495d0906fSLeo Liu struct { 154597b2e202SAlex Deucher /* uvd */ 154697b2e202SAlex Deucher struct amdgpu_uvd uvd; 154797b2e202SAlex Deucher 154897b2e202SAlex Deucher /* vce */ 154997b2e202SAlex Deucher struct amdgpu_vce vce; 155095d0906fSLeo Liu }; 155195d0906fSLeo Liu 155295d0906fSLeo Liu /* vcn */ 155395d0906fSLeo Liu struct amdgpu_vcn vcn; 155495d0906fSLeo Liu }; 155597b2e202SAlex Deucher 155697b2e202SAlex Deucher /* firmwares */ 155797b2e202SAlex Deucher struct amdgpu_firmware firmware; 155897b2e202SAlex Deucher 15590e5ca0d1SHuang Rui /* PSP */ 15600e5ca0d1SHuang Rui struct psp_context psp; 15610e5ca0d1SHuang Rui 156297b2e202SAlex Deucher /* GDS */ 156397b2e202SAlex Deucher struct amdgpu_gds gds; 156497b2e202SAlex Deucher 1565a1255107SAlex Deucher struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 156697b2e202SAlex Deucher int num_ip_blocks; 156797b2e202SAlex Deucher struct mutex mn_lock; 156897b2e202SAlex Deucher DECLARE_HASHTABLE(mn_hash, 7); 156997b2e202SAlex Deucher 157097b2e202SAlex Deucher /* tracking pinned memory */ 157197b2e202SAlex Deucher u64 vram_pin_size; 1572e131b914SChunming Zhou u64 invisible_pin_size; 157397b2e202SAlex Deucher u64 gart_pin_size; 1574130e0371SOded Gabbay 1575130e0371SOded Gabbay /* amdkfd interface */ 1576130e0371SOded Gabbay struct kfd_dev *kfd; 157723ca0e4eSChunming Zhou 15782dc80b00SShirish S /* delayed work_func for deferring clockgating during resume */ 15792dc80b00SShirish S struct delayed_work late_init_work; 15802dc80b00SShirish S 15815a5099cbSXiangliang Yu struct amdgpu_virt virt; 15820c4e7fa5SChunming Zhou 15830c4e7fa5SChunming Zhou /* link all shadow bo */ 15840c4e7fa5SChunming Zhou struct list_head shadow_list; 15850c4e7fa5SChunming Zhou struct mutex shadow_list_lock; 15865c1354bdSChunming Zhou /* link all gtt */ 15875c1354bdSChunming Zhou spinlock_t gtt_list_lock; 15885c1354bdSChunming Zhou struct list_head gtt_list; 1589795f2813SAndres Rodriguez /* keep an lru list of rings by HW IP */ 1590795f2813SAndres Rodriguez struct list_head ring_lru_list; 1591795f2813SAndres Rodriguez spinlock_t ring_lru_list_lock; 15925c1354bdSChunming Zhou 1593c836fec5SJim Qu /* record hw reset is performed */ 1594c836fec5SJim Qu bool has_hw_reset; 15950c49e0b8SChunming Zhou u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1596c836fec5SJim Qu 159747ed4e1cSKen Wang /* record last mm index being written through WREG32*/ 159847ed4e1cSKen Wang unsigned long last_mm_index; 15993224a12bSMonk Liu bool in_sriov_reset; 160097b2e202SAlex Deucher }; 160197b2e202SAlex Deucher 1602a7d64de6SChristian König static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1603a7d64de6SChristian König { 1604a7d64de6SChristian König return container_of(bdev, struct amdgpu_device, mman.bdev); 1605a7d64de6SChristian König } 1606a7d64de6SChristian König 160797b2e202SAlex Deucher int amdgpu_device_init(struct amdgpu_device *adev, 160897b2e202SAlex Deucher struct drm_device *ddev, 160997b2e202SAlex Deucher struct pci_dev *pdev, 161097b2e202SAlex Deucher uint32_t flags); 161197b2e202SAlex Deucher void amdgpu_device_fini(struct amdgpu_device *adev); 161297b2e202SAlex Deucher int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 161397b2e202SAlex Deucher 161497b2e202SAlex Deucher uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 161515d72fd7SMonk Liu uint32_t acc_flags); 161697b2e202SAlex Deucher void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 161715d72fd7SMonk Liu uint32_t acc_flags); 161897b2e202SAlex Deucher u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 161997b2e202SAlex Deucher void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 162097b2e202SAlex Deucher 162197b2e202SAlex Deucher u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 162297b2e202SAlex Deucher void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1623832be404SKen Wang u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 1624832be404SKen Wang void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 162597b2e202SAlex Deucher 162697b2e202SAlex Deucher /* 162797b2e202SAlex Deucher * Registers read & write functions. 162897b2e202SAlex Deucher */ 162915d72fd7SMonk Liu 163015d72fd7SMonk Liu #define AMDGPU_REGS_IDX (1<<0) 163115d72fd7SMonk Liu #define AMDGPU_REGS_NO_KIQ (1<<1) 163215d72fd7SMonk Liu 163315d72fd7SMonk Liu #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 163415d72fd7SMonk Liu #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 163515d72fd7SMonk Liu 163615d72fd7SMonk Liu #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 163715d72fd7SMonk Liu #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 163815d72fd7SMonk Liu #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 163915d72fd7SMonk Liu #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 164015d72fd7SMonk Liu #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 164197b2e202SAlex Deucher #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 164297b2e202SAlex Deucher #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 164397b2e202SAlex Deucher #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 164497b2e202SAlex Deucher #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 164536b9a952SHuang Rui #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 164636b9a952SHuang Rui #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 164797b2e202SAlex Deucher #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 164897b2e202SAlex Deucher #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 164997b2e202SAlex Deucher #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 165097b2e202SAlex Deucher #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 165197b2e202SAlex Deucher #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 165297b2e202SAlex Deucher #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1653ccdbb20aSRex Zhu #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1654ccdbb20aSRex Zhu #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 165516abb5d2SEvan Quan #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 165616abb5d2SEvan Quan #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 165797b2e202SAlex Deucher #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 165897b2e202SAlex Deucher #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 165997b2e202SAlex Deucher #define WREG32_P(reg, val, mask) \ 166097b2e202SAlex Deucher do { \ 166197b2e202SAlex Deucher uint32_t tmp_ = RREG32(reg); \ 166297b2e202SAlex Deucher tmp_ &= (mask); \ 166397b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 166497b2e202SAlex Deucher WREG32(reg, tmp_); \ 166597b2e202SAlex Deucher } while (0) 166697b2e202SAlex Deucher #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 166797b2e202SAlex Deucher #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 166897b2e202SAlex Deucher #define WREG32_PLL_P(reg, val, mask) \ 166997b2e202SAlex Deucher do { \ 167097b2e202SAlex Deucher uint32_t tmp_ = RREG32_PLL(reg); \ 167197b2e202SAlex Deucher tmp_ &= (mask); \ 167297b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 167397b2e202SAlex Deucher WREG32_PLL(reg, tmp_); \ 167497b2e202SAlex Deucher } while (0) 167597b2e202SAlex Deucher #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 167697b2e202SAlex Deucher #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 167797b2e202SAlex Deucher #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 167897b2e202SAlex Deucher 167997b2e202SAlex Deucher #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 168097b2e202SAlex Deucher #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1681832be404SKen Wang #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 1682832be404SKen Wang #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 168397b2e202SAlex Deucher 168497b2e202SAlex Deucher #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 168597b2e202SAlex Deucher #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 168697b2e202SAlex Deucher 168797b2e202SAlex Deucher #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 168897b2e202SAlex Deucher (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 168997b2e202SAlex Deucher (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 169097b2e202SAlex Deucher 169197b2e202SAlex Deucher #define REG_GET_FIELD(value, reg, field) \ 169297b2e202SAlex Deucher (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 169397b2e202SAlex Deucher 169461cb8cefSTom St Denis #define WREG32_FIELD(reg, field, val) \ 169561cb8cefSTom St Denis WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 169661cb8cefSTom St Denis 1697ccaf3574STom St Denis #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1698ccaf3574STom St Denis WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1699ccaf3574STom St Denis 170097b2e202SAlex Deucher /* 170197b2e202SAlex Deucher * BIOS helpers. 170297b2e202SAlex Deucher */ 170397b2e202SAlex Deucher #define RBIOS8(i) (adev->bios[i]) 170497b2e202SAlex Deucher #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 170597b2e202SAlex Deucher #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 170697b2e202SAlex Deucher 1707c113ea1cSAlex Deucher static inline struct amdgpu_sdma_instance * 1708c113ea1cSAlex Deucher amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 17094b2f7e2cSJammy Zhou { 17104b2f7e2cSJammy Zhou struct amdgpu_device *adev = ring->adev; 17114b2f7e2cSJammy Zhou int i; 17124b2f7e2cSJammy Zhou 1713c113ea1cSAlex Deucher for (i = 0; i < adev->sdma.num_instances; i++) 1714c113ea1cSAlex Deucher if (&adev->sdma.instance[i].ring == ring) 17154b2f7e2cSJammy Zhou break; 17164b2f7e2cSJammy Zhou 17174b2f7e2cSJammy Zhou if (i < AMDGPU_MAX_SDMA_INSTANCES) 1718c113ea1cSAlex Deucher return &adev->sdma.instance[i]; 17194b2f7e2cSJammy Zhou else 17204b2f7e2cSJammy Zhou return NULL; 17214b2f7e2cSJammy Zhou } 17224b2f7e2cSJammy Zhou 172397b2e202SAlex Deucher /* 172497b2e202SAlex Deucher * ASICs macro. 172597b2e202SAlex Deucher */ 172697b2e202SAlex Deucher #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 172797b2e202SAlex Deucher #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 172897b2e202SAlex Deucher #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 172997b2e202SAlex Deucher #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 173097b2e202SAlex Deucher #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1731841686dfSMaruthi Bayyavarapu #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1732841686dfSMaruthi Bayyavarapu #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1733841686dfSMaruthi Bayyavarapu #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 173497b2e202SAlex Deucher #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 17357946b878SAlex Deucher #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 173697b2e202SAlex Deucher #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1737bbf282d8SAlex Deucher #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 173897b2e202SAlex Deucher #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 173997b2e202SAlex Deucher #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 1740b1166325SChristian König #define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr)) 174197b2e202SAlex Deucher #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 1742de9ea7bdSChristian König #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 174397b2e202SAlex Deucher #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 17445463545bSAlex Xie #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags)) 174597b2e202SAlex Deucher #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 174697b2e202SAlex Deucher #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 1747bbec97aaSChristian König #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 174897b2e202SAlex Deucher #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 174997b2e202SAlex Deucher #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 175097b2e202SAlex Deucher #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 1751d88bf583SChristian König #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 1752b8c7b39eSChristian König #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 175397b2e202SAlex Deucher #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 1754890ee23fSChunming Zhou #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 175597b2e202SAlex Deucher #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 1756d2edb07bSChristian König #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 175711afbde8SChunming Zhou #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 1758c2167a65SMonk Liu #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 1759753ad49cSMonk Liu #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 1760b6091c12SXiangliang Yu #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) 1761b6091c12SXiangliang Yu #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 17623b4d68e9SMonk Liu #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b)) 17639e5d5309SChristian König #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 176403ccf481SMonk Liu #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 176503ccf481SMonk Liu #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 176697b2e202SAlex Deucher #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 176700ecd8a2SFelix Kuehling #define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev)) 176897b2e202SAlex Deucher #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 176997b2e202SAlex Deucher #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 177097b2e202SAlex Deucher #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 177197b2e202SAlex Deucher #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 177297b2e202SAlex Deucher #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 177397b2e202SAlex Deucher #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 177497b2e202SAlex Deucher #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 177597b2e202SAlex Deucher #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 177697b2e202SAlex Deucher #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 177797b2e202SAlex Deucher #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 1778cb9e59d7SAlex Deucher #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 177997b2e202SAlex Deucher #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 178097b2e202SAlex Deucher #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 178197b2e202SAlex Deucher #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 1782c7ae72c0SChunming Zhou #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 17836e7a3840SChunming Zhou #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 1784b95e31fdSAlex Deucher #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 17859559ef5bSTom St Denis #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 178697b2e202SAlex Deucher #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 17870e5ca0d1SHuang Rui #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) 178897b2e202SAlex Deucher 178997b2e202SAlex Deucher /* Common functions */ 179097b2e202SAlex Deucher int amdgpu_gpu_reset(struct amdgpu_device *adev); 17913ad81f16SChunming Zhou bool amdgpu_need_backup(struct amdgpu_device *adev); 179297b2e202SAlex Deucher void amdgpu_pci_config_reset(struct amdgpu_device *adev); 1793c836fec5SJim Qu bool amdgpu_need_post(struct amdgpu_device *adev); 179497b2e202SAlex Deucher void amdgpu_update_display_priority(struct amdgpu_device *adev); 1795d5fc5e82SChunming Zhou 179600f06b24SJohn Brooks void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 179700f06b24SJohn Brooks u64 num_vis_bytes); 1798765e7fbfSChristian König void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 179997b2e202SAlex Deucher bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 180097b2e202SAlex Deucher void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 18016f02a696SChristian König void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 180297b2e202SAlex Deucher void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 18039f31a0b0SBaoyou Xie int amdgpu_ttm_init(struct amdgpu_device *adev); 18049f31a0b0SBaoyou Xie void amdgpu_ttm_fini(struct amdgpu_device *adev); 180597b2e202SAlex Deucher void amdgpu_program_register_sequence(struct amdgpu_device *adev, 180697b2e202SAlex Deucher const u32 *registers, 180797b2e202SAlex Deucher const u32 array_size); 180897b2e202SAlex Deucher 180997b2e202SAlex Deucher bool amdgpu_device_is_px(struct drm_device *dev); 181097b2e202SAlex Deucher /* atpx handler */ 181197b2e202SAlex Deucher #if defined(CONFIG_VGA_SWITCHEROO) 181297b2e202SAlex Deucher void amdgpu_register_atpx_handler(void); 181397b2e202SAlex Deucher void amdgpu_unregister_atpx_handler(void); 1814a78fe133SAlex Deucher bool amdgpu_has_atpx_dgpu_power_cntl(void); 18152f5af82eSAlex Deucher bool amdgpu_is_atpx_hybrid(void); 1816efc83cf4SAlex Deucher bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1817714f88e0SAlex Xie bool amdgpu_has_atpx(void); 181897b2e202SAlex Deucher #else 181997b2e202SAlex Deucher static inline void amdgpu_register_atpx_handler(void) {} 182097b2e202SAlex Deucher static inline void amdgpu_unregister_atpx_handler(void) {} 1821a78fe133SAlex Deucher static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 18222f5af82eSAlex Deucher static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1823efc83cf4SAlex Deucher static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1824714f88e0SAlex Xie static inline bool amdgpu_has_atpx(void) { return false; } 182597b2e202SAlex Deucher #endif 182697b2e202SAlex Deucher 182797b2e202SAlex Deucher /* 182897b2e202SAlex Deucher * KMS 182997b2e202SAlex Deucher */ 183097b2e202SAlex Deucher extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1831f498d9edSNils Wallménius extern const int amdgpu_max_kms_ioctl; 183297b2e202SAlex Deucher 1833f1892138SChunming Zhou bool amdgpu_kms_vram_lost(struct amdgpu_device *adev, 1834f1892138SChunming Zhou struct amdgpu_fpriv *fpriv); 183597b2e202SAlex Deucher int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 183611b3c20bSGabriel Krisman Bertazi void amdgpu_driver_unload_kms(struct drm_device *dev); 183797b2e202SAlex Deucher void amdgpu_driver_lastclose_kms(struct drm_device *dev); 183897b2e202SAlex Deucher int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 183997b2e202SAlex Deucher void amdgpu_driver_postclose_kms(struct drm_device *dev, 184097b2e202SAlex Deucher struct drm_file *file_priv); 1841faefba95SAlex Deucher int amdgpu_suspend(struct amdgpu_device *adev); 1842810ddc3aSAlex Deucher int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1843810ddc3aSAlex Deucher int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 184488e72717SThierry Reding u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 184588e72717SThierry Reding int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 184688e72717SThierry Reding void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 184797b2e202SAlex Deucher long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 184897b2e202SAlex Deucher unsigned long arg); 184997b2e202SAlex Deucher 185097b2e202SAlex Deucher /* 185197b2e202SAlex Deucher * functions used by amdgpu_encoder.c 185297b2e202SAlex Deucher */ 185397b2e202SAlex Deucher struct amdgpu_afmt_acr { 185497b2e202SAlex Deucher u32 clock; 185597b2e202SAlex Deucher 185697b2e202SAlex Deucher int n_32khz; 185797b2e202SAlex Deucher int cts_32khz; 185897b2e202SAlex Deucher 185997b2e202SAlex Deucher int n_44_1khz; 186097b2e202SAlex Deucher int cts_44_1khz; 186197b2e202SAlex Deucher 186297b2e202SAlex Deucher int n_48khz; 186397b2e202SAlex Deucher int cts_48khz; 186497b2e202SAlex Deucher 186597b2e202SAlex Deucher }; 186697b2e202SAlex Deucher 186797b2e202SAlex Deucher struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 186897b2e202SAlex Deucher 186997b2e202SAlex Deucher /* amdgpu_acpi.c */ 187097b2e202SAlex Deucher #if defined(CONFIG_ACPI) 187197b2e202SAlex Deucher int amdgpu_acpi_init(struct amdgpu_device *adev); 187297b2e202SAlex Deucher void amdgpu_acpi_fini(struct amdgpu_device *adev); 187397b2e202SAlex Deucher bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 187497b2e202SAlex Deucher int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 187597b2e202SAlex Deucher u8 perf_req, bool advertise); 187697b2e202SAlex Deucher int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 187797b2e202SAlex Deucher #else 187897b2e202SAlex Deucher static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 187997b2e202SAlex Deucher static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 188097b2e202SAlex Deucher #endif 188197b2e202SAlex Deucher 18829cca0b8eSChristian König int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 18839cca0b8eSChristian König uint64_t addr, struct amdgpu_bo **bo, 18849cca0b8eSChristian König struct amdgpu_bo_va_mapping **mapping); 188597b2e202SAlex Deucher 188697b2e202SAlex Deucher #include "amdgpu_object.h" 188797b2e202SAlex Deucher #endif 1888