xref: /openbmc/linux/drivers/gpu/drm/amd/amdgpu/amdgpu.h (revision ccaf3574)
197b2e202SAlex Deucher /*
297b2e202SAlex Deucher  * Copyright 2008 Advanced Micro Devices, Inc.
397b2e202SAlex Deucher  * Copyright 2008 Red Hat Inc.
497b2e202SAlex Deucher  * Copyright 2009 Jerome Glisse.
597b2e202SAlex Deucher  *
697b2e202SAlex Deucher  * Permission is hereby granted, free of charge, to any person obtaining a
797b2e202SAlex Deucher  * copy of this software and associated documentation files (the "Software"),
897b2e202SAlex Deucher  * to deal in the Software without restriction, including without limitation
997b2e202SAlex Deucher  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1097b2e202SAlex Deucher  * and/or sell copies of the Software, and to permit persons to whom the
1197b2e202SAlex Deucher  * Software is furnished to do so, subject to the following conditions:
1297b2e202SAlex Deucher  *
1397b2e202SAlex Deucher  * The above copyright notice and this permission notice shall be included in
1497b2e202SAlex Deucher  * all copies or substantial portions of the Software.
1597b2e202SAlex Deucher  *
1697b2e202SAlex Deucher  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1797b2e202SAlex Deucher  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1897b2e202SAlex Deucher  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1997b2e202SAlex Deucher  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
2097b2e202SAlex Deucher  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
2197b2e202SAlex Deucher  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2297b2e202SAlex Deucher  * OTHER DEALINGS IN THE SOFTWARE.
2397b2e202SAlex Deucher  *
2497b2e202SAlex Deucher  * Authors: Dave Airlie
2597b2e202SAlex Deucher  *          Alex Deucher
2697b2e202SAlex Deucher  *          Jerome Glisse
2797b2e202SAlex Deucher  */
2897b2e202SAlex Deucher #ifndef __AMDGPU_H__
2997b2e202SAlex Deucher #define __AMDGPU_H__
3097b2e202SAlex Deucher 
3197b2e202SAlex Deucher #include <linux/atomic.h>
3297b2e202SAlex Deucher #include <linux/wait.h>
3397b2e202SAlex Deucher #include <linux/list.h>
3497b2e202SAlex Deucher #include <linux/kref.h>
35a9f87f64SChristian König #include <linux/rbtree.h>
3697b2e202SAlex Deucher #include <linux/hashtable.h>
37f54d1867SChris Wilson #include <linux/dma-fence.h>
3897b2e202SAlex Deucher 
3997b2e202SAlex Deucher #include <ttm/ttm_bo_api.h>
4097b2e202SAlex Deucher #include <ttm/ttm_bo_driver.h>
4197b2e202SAlex Deucher #include <ttm/ttm_placement.h>
4297b2e202SAlex Deucher #include <ttm/ttm_module.h>
4397b2e202SAlex Deucher #include <ttm/ttm_execbuf_util.h>
4497b2e202SAlex Deucher 
45d03846afSChunming Zhou #include <drm/drmP.h>
4697b2e202SAlex Deucher #include <drm/drm_gem.h>
477e5a547fSChunming Zhou #include <drm/amdgpu_drm.h>
4897b2e202SAlex Deucher 
495fc3aeebSyanyang1 #include "amd_shared.h"
5097b2e202SAlex Deucher #include "amdgpu_mode.h"
5197b2e202SAlex Deucher #include "amdgpu_ih.h"
5297b2e202SAlex Deucher #include "amdgpu_irq.h"
5397b2e202SAlex Deucher #include "amdgpu_ucode.h"
54c632d799SFlora Cui #include "amdgpu_ttm.h"
550e5ca0d1SHuang Rui #include "amdgpu_psp.h"
5697b2e202SAlex Deucher #include "amdgpu_gds.h"
5756113504SChristian König #include "amdgpu_sync.h"
5878023016SChristian König #include "amdgpu_ring.h"
59073440d2SChristian König #include "amdgpu_vm.h"
601f7371b2SAlex Deucher #include "amd_powerplay.h"
61cf097881SAlex Deucher #include "amdgpu_dpm.h"
62a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h"
634df654d2SLeo Liu #include "amdgpu_uvd.h"
645e568178SLeo Liu #include "amdgpu_vce.h"
6597b2e202SAlex Deucher 
66b80d8475SAlex Deucher #include "gpu_scheduler.h"
67ceeb50edSMonk Liu #include "amdgpu_virt.h"
68b80d8475SAlex Deucher 
6997b2e202SAlex Deucher /*
7097b2e202SAlex Deucher  * Modules parameters.
7197b2e202SAlex Deucher  */
7297b2e202SAlex Deucher extern int amdgpu_modeset;
7397b2e202SAlex Deucher extern int amdgpu_vram_limit;
7497b2e202SAlex Deucher extern int amdgpu_gart_size;
7595844d20SMarek Olšák extern int amdgpu_moverate;
7697b2e202SAlex Deucher extern int amdgpu_benchmarking;
7797b2e202SAlex Deucher extern int amdgpu_testing;
7897b2e202SAlex Deucher extern int amdgpu_audio;
7997b2e202SAlex Deucher extern int amdgpu_disp_priority;
8097b2e202SAlex Deucher extern int amdgpu_hw_i2c;
8197b2e202SAlex Deucher extern int amdgpu_pcie_gen2;
8297b2e202SAlex Deucher extern int amdgpu_msi;
8397b2e202SAlex Deucher extern int amdgpu_lockup_timeout;
8497b2e202SAlex Deucher extern int amdgpu_dpm;
85e635ee07SHuang Rui extern int amdgpu_fw_load_type;
8697b2e202SAlex Deucher extern int amdgpu_aspm;
8797b2e202SAlex Deucher extern int amdgpu_runtime_pm;
8897b2e202SAlex Deucher extern unsigned amdgpu_ip_block_mask;
8997b2e202SAlex Deucher extern int amdgpu_bapm;
9097b2e202SAlex Deucher extern int amdgpu_deep_color;
9197b2e202SAlex Deucher extern int amdgpu_vm_size;
9297b2e202SAlex Deucher extern int amdgpu_vm_block_size;
93d9c13156SChristian König extern int amdgpu_vm_fault_stop;
94b495bd3aSChristian König extern int amdgpu_vm_debug;
951333f723SJammy Zhou extern int amdgpu_sched_jobs;
964afcb303SJammy Zhou extern int amdgpu_sched_hw_submission;
973ca67300SRex Zhu extern int amdgpu_no_evict;
983ca67300SRex Zhu extern int amdgpu_direct_gma_size;
99cd474ba0SAlex Deucher extern unsigned amdgpu_pcie_gen_cap;
100cd474ba0SAlex Deucher extern unsigned amdgpu_pcie_lane_cap;
101395d1fb9SNicolai Hähnle extern unsigned amdgpu_cg_mask;
102395d1fb9SNicolai Hähnle extern unsigned amdgpu_pg_mask;
1036f8941a2SNicolai Hähnle extern char *amdgpu_disable_cu;
1049accf2fdSEmily Deng extern char *amdgpu_virtual_display;
1055141e9d2SRex Zhu extern unsigned amdgpu_pp_feature_mask;
1066a7f76e7SChristian König extern int amdgpu_vram_page_split;
107bce23e00SAlex Deucher extern int amdgpu_ngg;
108bce23e00SAlex Deucher extern int amdgpu_prim_buf_per_se;
109bce23e00SAlex Deucher extern int amdgpu_pos_buf_per_se;
110bce23e00SAlex Deucher extern int amdgpu_cntl_sb_buf_per_se;
111bce23e00SAlex Deucher extern int amdgpu_param_buf_per_se;
11297b2e202SAlex Deucher 
1134b559c90SChunming Zhou #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000
11497b2e202SAlex Deucher #define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */
11597b2e202SAlex Deucher #define AMDGPU_FENCE_JIFFIES_TIMEOUT		(HZ / 2)
11697b2e202SAlex Deucher /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
11797b2e202SAlex Deucher #define AMDGPU_IB_POOL_SIZE			16
11897b2e202SAlex Deucher #define AMDGPU_DEBUGFS_MAX_COMPONENTS		32
11997b2e202SAlex Deucher #define AMDGPUFB_CONN_LIMIT			4
120a5bde2f9SAlex Deucher #define AMDGPU_BIOS_NUM_SCRATCH			16
12197b2e202SAlex Deucher 
12236f523a7SJammy Zhou /* max number of IP instances */
12336f523a7SJammy Zhou #define AMDGPU_MAX_SDMA_INSTANCES		2
12436f523a7SJammy Zhou 
12597b2e202SAlex Deucher /* hard reset data */
12697b2e202SAlex Deucher #define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b
12797b2e202SAlex Deucher 
12897b2e202SAlex Deucher /* reset flags */
12997b2e202SAlex Deucher #define AMDGPU_RESET_GFX			(1 << 0)
13097b2e202SAlex Deucher #define AMDGPU_RESET_COMPUTE			(1 << 1)
13197b2e202SAlex Deucher #define AMDGPU_RESET_DMA			(1 << 2)
13297b2e202SAlex Deucher #define AMDGPU_RESET_CP				(1 << 3)
13397b2e202SAlex Deucher #define AMDGPU_RESET_GRBM			(1 << 4)
13497b2e202SAlex Deucher #define AMDGPU_RESET_DMA1			(1 << 5)
13597b2e202SAlex Deucher #define AMDGPU_RESET_RLC			(1 << 6)
13697b2e202SAlex Deucher #define AMDGPU_RESET_SEM			(1 << 7)
13797b2e202SAlex Deucher #define AMDGPU_RESET_IH				(1 << 8)
13897b2e202SAlex Deucher #define AMDGPU_RESET_VMC			(1 << 9)
13997b2e202SAlex Deucher #define AMDGPU_RESET_MC				(1 << 10)
14097b2e202SAlex Deucher #define AMDGPU_RESET_DISPLAY			(1 << 11)
14197b2e202SAlex Deucher #define AMDGPU_RESET_UVD			(1 << 12)
14297b2e202SAlex Deucher #define AMDGPU_RESET_VCE			(1 << 13)
14397b2e202SAlex Deucher #define AMDGPU_RESET_VCE1			(1 << 14)
14497b2e202SAlex Deucher 
14597b2e202SAlex Deucher /* GFX current status */
14697b2e202SAlex Deucher #define AMDGPU_GFX_NORMAL_MODE			0x00000000L
14797b2e202SAlex Deucher #define AMDGPU_GFX_SAFE_MODE			0x00000001L
14897b2e202SAlex Deucher #define AMDGPU_GFX_PG_DISABLED_MODE		0x00000002L
14997b2e202SAlex Deucher #define AMDGPU_GFX_CG_DISABLED_MODE		0x00000004L
15097b2e202SAlex Deucher #define AMDGPU_GFX_LBPW_DISABLED_MODE		0x00000008L
15197b2e202SAlex Deucher 
15297b2e202SAlex Deucher /* max cursor sizes (in pixels) */
15397b2e202SAlex Deucher #define CIK_CURSOR_WIDTH 128
15497b2e202SAlex Deucher #define CIK_CURSOR_HEIGHT 128
15597b2e202SAlex Deucher 
15697b2e202SAlex Deucher struct amdgpu_device;
15797b2e202SAlex Deucher struct amdgpu_ib;
15897b2e202SAlex Deucher struct amdgpu_cs_parser;
159bb977d37SChunming Zhou struct amdgpu_job;
16097b2e202SAlex Deucher struct amdgpu_irq_src;
1610b492a4cSAlex Deucher struct amdgpu_fpriv;
16297b2e202SAlex Deucher 
16397b2e202SAlex Deucher enum amdgpu_cp_irq {
16497b2e202SAlex Deucher 	AMDGPU_CP_IRQ_GFX_EOP = 0,
16597b2e202SAlex Deucher 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
16697b2e202SAlex Deucher 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
16797b2e202SAlex Deucher 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
16897b2e202SAlex Deucher 	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
16997b2e202SAlex Deucher 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
17097b2e202SAlex Deucher 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
17197b2e202SAlex Deucher 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
17297b2e202SAlex Deucher 	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
17397b2e202SAlex Deucher 
17497b2e202SAlex Deucher 	AMDGPU_CP_IRQ_LAST
17597b2e202SAlex Deucher };
17697b2e202SAlex Deucher 
17797b2e202SAlex Deucher enum amdgpu_sdma_irq {
17897b2e202SAlex Deucher 	AMDGPU_SDMA_IRQ_TRAP0 = 0,
17997b2e202SAlex Deucher 	AMDGPU_SDMA_IRQ_TRAP1,
18097b2e202SAlex Deucher 
18197b2e202SAlex Deucher 	AMDGPU_SDMA_IRQ_LAST
18297b2e202SAlex Deucher };
18397b2e202SAlex Deucher 
18497b2e202SAlex Deucher enum amdgpu_thermal_irq {
18597b2e202SAlex Deucher 	AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
18697b2e202SAlex Deucher 	AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
18797b2e202SAlex Deucher 
18897b2e202SAlex Deucher 	AMDGPU_THERMAL_IRQ_LAST
18997b2e202SAlex Deucher };
19097b2e202SAlex Deucher 
1914e638ae9SXiangliang Yu enum amdgpu_kiq_irq {
1924e638ae9SXiangliang Yu 	AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
1934e638ae9SXiangliang Yu 	AMDGPU_CP_KIQ_IRQ_LAST
1944e638ae9SXiangliang Yu };
1954e638ae9SXiangliang Yu 
19697b2e202SAlex Deucher int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1975fc3aeebSyanyang1 				  enum amd_ip_block_type block_type,
1985fc3aeebSyanyang1 				  enum amd_clockgating_state state);
19997b2e202SAlex Deucher int amdgpu_set_powergating_state(struct amdgpu_device *adev,
2005fc3aeebSyanyang1 				  enum amd_ip_block_type block_type,
2015fc3aeebSyanyang1 				  enum amd_powergating_state state);
2026cb2d4e4SHuang Rui void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
2035dbbb60bSAlex Deucher int amdgpu_wait_for_idle(struct amdgpu_device *adev,
2045dbbb60bSAlex Deucher 			 enum amd_ip_block_type block_type);
2055dbbb60bSAlex Deucher bool amdgpu_is_idle(struct amdgpu_device *adev,
2065dbbb60bSAlex Deucher 		    enum amd_ip_block_type block_type);
20797b2e202SAlex Deucher 
208a1255107SAlex Deucher #define AMDGPU_MAX_IP_NUM 16
209a1255107SAlex Deucher 
210a1255107SAlex Deucher struct amdgpu_ip_block_status {
211a1255107SAlex Deucher 	bool valid;
212a1255107SAlex Deucher 	bool sw;
213a1255107SAlex Deucher 	bool hw;
214a1255107SAlex Deucher 	bool late_initialized;
215a1255107SAlex Deucher 	bool hang;
216a1255107SAlex Deucher };
217a1255107SAlex Deucher 
21897b2e202SAlex Deucher struct amdgpu_ip_block_version {
219a1255107SAlex Deucher 	const enum amd_ip_block_type type;
220a1255107SAlex Deucher 	const u32 major;
221a1255107SAlex Deucher 	const u32 minor;
222a1255107SAlex Deucher 	const u32 rev;
2235fc3aeebSyanyang1 	const struct amd_ip_funcs *funcs;
22497b2e202SAlex Deucher };
22597b2e202SAlex Deucher 
226a1255107SAlex Deucher struct amdgpu_ip_block {
227a1255107SAlex Deucher 	struct amdgpu_ip_block_status status;
228a1255107SAlex Deucher 	const struct amdgpu_ip_block_version *version;
229a1255107SAlex Deucher };
230a1255107SAlex Deucher 
23197b2e202SAlex Deucher int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
2325fc3aeebSyanyang1 				enum amd_ip_block_type type,
23397b2e202SAlex Deucher 				u32 major, u32 minor);
23497b2e202SAlex Deucher 
235a1255107SAlex Deucher struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
2365fc3aeebSyanyang1 					     enum amd_ip_block_type type);
23797b2e202SAlex Deucher 
238a1255107SAlex Deucher int amdgpu_ip_block_add(struct amdgpu_device *adev,
239a1255107SAlex Deucher 			const struct amdgpu_ip_block_version *ip_block_version);
240a1255107SAlex Deucher 
24197b2e202SAlex Deucher /* provided by hw blocks that can move/clear data.  e.g., gfx or sdma */
24297b2e202SAlex Deucher struct amdgpu_buffer_funcs {
24397b2e202SAlex Deucher 	/* maximum bytes in a single operation */
24497b2e202SAlex Deucher 	uint32_t	copy_max_bytes;
24597b2e202SAlex Deucher 
24697b2e202SAlex Deucher 	/* number of dw to reserve per operation */
24797b2e202SAlex Deucher 	unsigned	copy_num_dw;
24897b2e202SAlex Deucher 
24997b2e202SAlex Deucher 	/* used for buffer migration */
250c7ae72c0SChunming Zhou 	void (*emit_copy_buffer)(struct amdgpu_ib *ib,
25197b2e202SAlex Deucher 				 /* src addr in bytes */
25297b2e202SAlex Deucher 				 uint64_t src_offset,
25397b2e202SAlex Deucher 				 /* dst addr in bytes */
25497b2e202SAlex Deucher 				 uint64_t dst_offset,
25597b2e202SAlex Deucher 				 /* number of byte to transfer */
25697b2e202SAlex Deucher 				 uint32_t byte_count);
25797b2e202SAlex Deucher 
25897b2e202SAlex Deucher 	/* maximum bytes in a single operation */
25997b2e202SAlex Deucher 	uint32_t	fill_max_bytes;
26097b2e202SAlex Deucher 
26197b2e202SAlex Deucher 	/* number of dw to reserve per operation */
26297b2e202SAlex Deucher 	unsigned	fill_num_dw;
26397b2e202SAlex Deucher 
26497b2e202SAlex Deucher 	/* used for buffer clearing */
2656e7a3840SChunming Zhou 	void (*emit_fill_buffer)(struct amdgpu_ib *ib,
26697b2e202SAlex Deucher 				 /* value to write to memory */
26797b2e202SAlex Deucher 				 uint32_t src_data,
26897b2e202SAlex Deucher 				 /* dst addr in bytes */
26997b2e202SAlex Deucher 				 uint64_t dst_offset,
27097b2e202SAlex Deucher 				 /* number of byte to fill */
27197b2e202SAlex Deucher 				 uint32_t byte_count);
27297b2e202SAlex Deucher };
27397b2e202SAlex Deucher 
27497b2e202SAlex Deucher /* provided by hw blocks that can write ptes, e.g., sdma */
27597b2e202SAlex Deucher struct amdgpu_vm_pte_funcs {
27697b2e202SAlex Deucher 	/* copy pte entries from GART */
27797b2e202SAlex Deucher 	void (*copy_pte)(struct amdgpu_ib *ib,
27897b2e202SAlex Deucher 			 uint64_t pe, uint64_t src,
27997b2e202SAlex Deucher 			 unsigned count);
28097b2e202SAlex Deucher 	/* write pte one entry at a time with addr mapping */
281de9ea7bdSChristian König 	void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
282de9ea7bdSChristian König 			  uint64_t value, unsigned count,
283de9ea7bdSChristian König 			  uint32_t incr);
28497b2e202SAlex Deucher 	/* for linear pte/pde updates without addr mapping */
28597b2e202SAlex Deucher 	void (*set_pte_pde)(struct amdgpu_ib *ib,
28697b2e202SAlex Deucher 			    uint64_t pe,
28797b2e202SAlex Deucher 			    uint64_t addr, unsigned count,
2886b777607SChunming Zhou 			    uint32_t incr, uint64_t flags);
28997b2e202SAlex Deucher };
29097b2e202SAlex Deucher 
29197b2e202SAlex Deucher /* provided by the gmc block */
29297b2e202SAlex Deucher struct amdgpu_gart_funcs {
29397b2e202SAlex Deucher 	/* flush the vm tlb via mmio */
29497b2e202SAlex Deucher 	void (*flush_gpu_tlb)(struct amdgpu_device *adev,
29597b2e202SAlex Deucher 			      uint32_t vmid);
29697b2e202SAlex Deucher 	/* write pte/pde updates using the cpu */
29797b2e202SAlex Deucher 	int (*set_pte_pde)(struct amdgpu_device *adev,
29897b2e202SAlex Deucher 			   void *cpu_pt_addr, /* cpu addr of page table */
29997b2e202SAlex Deucher 			   uint32_t gpu_page_idx, /* pte/pde to update */
30097b2e202SAlex Deucher 			   uint64_t addr, /* addr to write into pte/pde */
3016b777607SChunming Zhou 			   uint64_t flags); /* access flags */
302284710faSChristian König 	/* enable/disable PRT support */
303284710faSChristian König 	void (*set_prt)(struct amdgpu_device *adev, bool enable);
3045463545bSAlex Xie 	/* set pte flags based per asic */
3055463545bSAlex Xie 	uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
3065463545bSAlex Xie 				     uint32_t flags);
307e60f8db5SAlex Xie 	/* adjust mc addr in fb for APU case */
308e60f8db5SAlex Xie 	u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);
309e60f8db5SAlex Xie };
310e60f8db5SAlex Xie 
31197b2e202SAlex Deucher /* provided by the ih block */
31297b2e202SAlex Deucher struct amdgpu_ih_funcs {
31397b2e202SAlex Deucher 	/* ring read/write ptr handling, called from interrupt context */
31497b2e202SAlex Deucher 	u32 (*get_wptr)(struct amdgpu_device *adev);
31597b2e202SAlex Deucher 	void (*decode_iv)(struct amdgpu_device *adev,
31697b2e202SAlex Deucher 			  struct amdgpu_iv_entry *entry);
31797b2e202SAlex Deucher 	void (*set_rptr)(struct amdgpu_device *adev);
31897b2e202SAlex Deucher };
31997b2e202SAlex Deucher 
32097b2e202SAlex Deucher /*
32197b2e202SAlex Deucher  * BIOS.
32297b2e202SAlex Deucher  */
32397b2e202SAlex Deucher bool amdgpu_get_bios(struct amdgpu_device *adev);
32497b2e202SAlex Deucher bool amdgpu_read_bios(struct amdgpu_device *adev);
32597b2e202SAlex Deucher 
32697b2e202SAlex Deucher /*
32797b2e202SAlex Deucher  * Dummy page
32897b2e202SAlex Deucher  */
32997b2e202SAlex Deucher struct amdgpu_dummy_page {
33097b2e202SAlex Deucher 	struct page	*page;
33197b2e202SAlex Deucher 	dma_addr_t	addr;
33297b2e202SAlex Deucher };
33397b2e202SAlex Deucher int amdgpu_dummy_page_init(struct amdgpu_device *adev);
33497b2e202SAlex Deucher void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
33597b2e202SAlex Deucher 
33697b2e202SAlex Deucher 
33797b2e202SAlex Deucher /*
33897b2e202SAlex Deucher  * Clocks
33997b2e202SAlex Deucher  */
34097b2e202SAlex Deucher 
34197b2e202SAlex Deucher #define AMDGPU_MAX_PPLL 3
34297b2e202SAlex Deucher 
34397b2e202SAlex Deucher struct amdgpu_clock {
34497b2e202SAlex Deucher 	struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
34597b2e202SAlex Deucher 	struct amdgpu_pll spll;
34697b2e202SAlex Deucher 	struct amdgpu_pll mpll;
34797b2e202SAlex Deucher 	/* 10 Khz units */
34897b2e202SAlex Deucher 	uint32_t default_mclk;
34997b2e202SAlex Deucher 	uint32_t default_sclk;
35097b2e202SAlex Deucher 	uint32_t default_dispclk;
35197b2e202SAlex Deucher 	uint32_t current_dispclk;
35297b2e202SAlex Deucher 	uint32_t dp_extclk;
35397b2e202SAlex Deucher 	uint32_t max_pixel_clock;
35497b2e202SAlex Deucher };
35597b2e202SAlex Deucher 
35697b2e202SAlex Deucher /*
357c632d799SFlora Cui  * BO.
35897b2e202SAlex Deucher  */
35997b2e202SAlex Deucher struct amdgpu_bo_list_entry {
36097b2e202SAlex Deucher 	struct amdgpu_bo		*robj;
36197b2e202SAlex Deucher 	struct ttm_validate_buffer	tv;
36297b2e202SAlex Deucher 	struct amdgpu_bo_va		*bo_va;
36397b2e202SAlex Deucher 	uint32_t			priority;
3642f568dbdSChristian König 	struct page			**user_pages;
3652f568dbdSChristian König 	int				user_invalidated;
36697b2e202SAlex Deucher };
36797b2e202SAlex Deucher 
36897b2e202SAlex Deucher struct amdgpu_bo_va_mapping {
36997b2e202SAlex Deucher 	struct list_head		list;
370a9f87f64SChristian König 	struct rb_node			rb;
371a9f87f64SChristian König 	uint64_t			start;
372a9f87f64SChristian König 	uint64_t			last;
373a9f87f64SChristian König 	uint64_t			__subtree_last;
37497b2e202SAlex Deucher 	uint64_t			offset;
375268c3001SChristian König 	uint64_t			flags;
37697b2e202SAlex Deucher };
37797b2e202SAlex Deucher 
37897b2e202SAlex Deucher /* bo virtual addresses in a specific vm */
37997b2e202SAlex Deucher struct amdgpu_bo_va {
38097b2e202SAlex Deucher 	/* protected by bo being reserved */
38197b2e202SAlex Deucher 	struct list_head		bo_list;
382f54d1867SChris Wilson 	struct dma_fence	        *last_pt_update;
38397b2e202SAlex Deucher 	unsigned			ref_count;
38497b2e202SAlex Deucher 
3857fc11959SChristian König 	/* protected by vm mutex and spinlock */
38697b2e202SAlex Deucher 	struct list_head		vm_status;
38797b2e202SAlex Deucher 
3887fc11959SChristian König 	/* mappings for this bo_va */
3897fc11959SChristian König 	struct list_head		invalids;
3907fc11959SChristian König 	struct list_head		valids;
3917fc11959SChristian König 
39297b2e202SAlex Deucher 	/* constant after initialization */
39397b2e202SAlex Deucher 	struct amdgpu_vm		*vm;
39497b2e202SAlex Deucher 	struct amdgpu_bo		*bo;
39597b2e202SAlex Deucher };
39697b2e202SAlex Deucher 
3977e5a547fSChunming Zhou #define AMDGPU_GEM_DOMAIN_MAX		0x3
3987e5a547fSChunming Zhou 
39997b2e202SAlex Deucher struct amdgpu_bo {
40097b2e202SAlex Deucher 	/* Protected by tbo.reserved */
4011ea863fdSChristian König 	u32				prefered_domains;
4021ea863fdSChristian König 	u32				allowed_domains;
4037e5a547fSChunming Zhou 	struct ttm_place		placements[AMDGPU_GEM_DOMAIN_MAX + 1];
40497b2e202SAlex Deucher 	struct ttm_placement		placement;
40597b2e202SAlex Deucher 	struct ttm_buffer_object	tbo;
40697b2e202SAlex Deucher 	struct ttm_bo_kmap_obj		kmap;
40797b2e202SAlex Deucher 	u64				flags;
40897b2e202SAlex Deucher 	unsigned			pin_count;
40997b2e202SAlex Deucher 	void				*kptr;
41097b2e202SAlex Deucher 	u64				tiling_flags;
41197b2e202SAlex Deucher 	u64				metadata_flags;
41297b2e202SAlex Deucher 	void				*metadata;
41397b2e202SAlex Deucher 	u32				metadata_size;
4148e94a46cSMario Kleiner 	unsigned			prime_shared_count;
41597b2e202SAlex Deucher 	/* list of all virtual address to which this bo
41697b2e202SAlex Deucher 	 * is associated to
41797b2e202SAlex Deucher 	 */
41897b2e202SAlex Deucher 	struct list_head		va;
41997b2e202SAlex Deucher 	/* Constant after initialization */
42097b2e202SAlex Deucher 	struct drm_gem_object		gem_base;
42182b9c55bSChristian König 	struct amdgpu_bo		*parent;
422e7893c4bSChunming Zhou 	struct amdgpu_bo		*shadow;
42397b2e202SAlex Deucher 
42497b2e202SAlex Deucher 	struct ttm_bo_kmap_obj		dma_buf_vmap;
42597b2e202SAlex Deucher 	struct amdgpu_mn		*mn;
42697b2e202SAlex Deucher 	struct list_head		mn_list;
4270c4e7fa5SChunming Zhou 	struct list_head		shadow_list;
42897b2e202SAlex Deucher };
42997b2e202SAlex Deucher #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
43097b2e202SAlex Deucher 
43197b2e202SAlex Deucher void amdgpu_gem_object_free(struct drm_gem_object *obj);
43297b2e202SAlex Deucher int amdgpu_gem_object_open(struct drm_gem_object *obj,
43397b2e202SAlex Deucher 				struct drm_file *file_priv);
43497b2e202SAlex Deucher void amdgpu_gem_object_close(struct drm_gem_object *obj,
43597b2e202SAlex Deucher 				struct drm_file *file_priv);
43697b2e202SAlex Deucher unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
43797b2e202SAlex Deucher struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
4384d9c514dSChristian König struct drm_gem_object *
4394d9c514dSChristian König amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
44097b2e202SAlex Deucher 				 struct dma_buf_attachment *attach,
44197b2e202SAlex Deucher 				 struct sg_table *sg);
44297b2e202SAlex Deucher struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
44397b2e202SAlex Deucher 					struct drm_gem_object *gobj,
44497b2e202SAlex Deucher 					int flags);
44597b2e202SAlex Deucher int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
44697b2e202SAlex Deucher void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
44797b2e202SAlex Deucher struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
44897b2e202SAlex Deucher void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
44997b2e202SAlex Deucher void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
45097b2e202SAlex Deucher int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
45197b2e202SAlex Deucher 
45297b2e202SAlex Deucher /* sub-allocation manager, it has to be protected by another lock.
45397b2e202SAlex Deucher  * By conception this is an helper for other part of the driver
45497b2e202SAlex Deucher  * like the indirect buffer or semaphore, which both have their
45597b2e202SAlex Deucher  * locking.
45697b2e202SAlex Deucher  *
45797b2e202SAlex Deucher  * Principe is simple, we keep a list of sub allocation in offset
45897b2e202SAlex Deucher  * order (first entry has offset == 0, last entry has the highest
45997b2e202SAlex Deucher  * offset).
46097b2e202SAlex Deucher  *
46197b2e202SAlex Deucher  * When allocating new object we first check if there is room at
46297b2e202SAlex Deucher  * the end total_size - (last_object_offset + last_object_size) >=
46397b2e202SAlex Deucher  * alloc_size. If so we allocate new object there.
46497b2e202SAlex Deucher  *
46597b2e202SAlex Deucher  * When there is not enough room at the end, we start waiting for
46697b2e202SAlex Deucher  * each sub object until we reach object_offset+object_size >=
46797b2e202SAlex Deucher  * alloc_size, this object then become the sub object we return.
46897b2e202SAlex Deucher  *
46997b2e202SAlex Deucher  * Alignment can't be bigger than page size.
47097b2e202SAlex Deucher  *
47197b2e202SAlex Deucher  * Hole are not considered for allocation to keep things simple.
47297b2e202SAlex Deucher  * Assumption is that there won't be hole (all object on same
47397b2e202SAlex Deucher  * alignment).
47497b2e202SAlex Deucher  */
4756ba60b89SChristian König 
4766ba60b89SChristian König #define AMDGPU_SA_NUM_FENCE_LISTS	32
4776ba60b89SChristian König 
47897b2e202SAlex Deucher struct amdgpu_sa_manager {
47997b2e202SAlex Deucher 	wait_queue_head_t	wq;
48097b2e202SAlex Deucher 	struct amdgpu_bo	*bo;
48197b2e202SAlex Deucher 	struct list_head	*hole;
4826ba60b89SChristian König 	struct list_head	flist[AMDGPU_SA_NUM_FENCE_LISTS];
48397b2e202SAlex Deucher 	struct list_head	olist;
48497b2e202SAlex Deucher 	unsigned		size;
48597b2e202SAlex Deucher 	uint64_t		gpu_addr;
48697b2e202SAlex Deucher 	void			*cpu_ptr;
48797b2e202SAlex Deucher 	uint32_t		domain;
48897b2e202SAlex Deucher 	uint32_t		align;
48997b2e202SAlex Deucher };
49097b2e202SAlex Deucher 
49197b2e202SAlex Deucher /* sub-allocation buffer */
49297b2e202SAlex Deucher struct amdgpu_sa_bo {
49397b2e202SAlex Deucher 	struct list_head		olist;
49497b2e202SAlex Deucher 	struct list_head		flist;
49597b2e202SAlex Deucher 	struct amdgpu_sa_manager	*manager;
49697b2e202SAlex Deucher 	unsigned			soffset;
49797b2e202SAlex Deucher 	unsigned			eoffset;
498f54d1867SChris Wilson 	struct dma_fence	        *fence;
49997b2e202SAlex Deucher };
50097b2e202SAlex Deucher 
50197b2e202SAlex Deucher /*
50297b2e202SAlex Deucher  * GEM objects.
50397b2e202SAlex Deucher  */
504418aa0c2SChristian König void amdgpu_gem_force_release(struct amdgpu_device *adev);
50597b2e202SAlex Deucher int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
50697b2e202SAlex Deucher 				int alignment, u32 initial_domain,
50797b2e202SAlex Deucher 				u64 flags, bool kernel,
50897b2e202SAlex Deucher 				struct drm_gem_object **obj);
50997b2e202SAlex Deucher 
51097b2e202SAlex Deucher int amdgpu_mode_dumb_create(struct drm_file *file_priv,
51197b2e202SAlex Deucher 			    struct drm_device *dev,
51297b2e202SAlex Deucher 			    struct drm_mode_create_dumb *args);
51397b2e202SAlex Deucher int amdgpu_mode_dumb_mmap(struct drm_file *filp,
51497b2e202SAlex Deucher 			  struct drm_device *dev,
51597b2e202SAlex Deucher 			  uint32_t handle, uint64_t *offset_p);
516d573de2dSRex Zhu int amdgpu_fence_slab_init(void);
517d573de2dSRex Zhu void amdgpu_fence_slab_fini(void);
51897b2e202SAlex Deucher 
51997b2e202SAlex Deucher /*
52097b2e202SAlex Deucher  * GART structures, functions & helpers
52197b2e202SAlex Deucher  */
52297b2e202SAlex Deucher struct amdgpu_mc;
52397b2e202SAlex Deucher 
52497b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_SIZE 4096
52597b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
52697b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_SHIFT 12
52797b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
52897b2e202SAlex Deucher 
52997b2e202SAlex Deucher struct amdgpu_gart {
53097b2e202SAlex Deucher 	dma_addr_t			table_addr;
53197b2e202SAlex Deucher 	struct amdgpu_bo		*robj;
53297b2e202SAlex Deucher 	void				*ptr;
53397b2e202SAlex Deucher 	unsigned			num_gpu_pages;
53497b2e202SAlex Deucher 	unsigned			num_cpu_pages;
53597b2e202SAlex Deucher 	unsigned			table_size;
536a1d29476SChristian König #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
53797b2e202SAlex Deucher 	struct page			**pages;
538a1d29476SChristian König #endif
53997b2e202SAlex Deucher 	bool				ready;
5404b98e0c4SAlex Xie 
5414b98e0c4SAlex Xie 	/* Asic default pte flags */
5424b98e0c4SAlex Xie 	uint64_t			gart_pte_flags;
5434b98e0c4SAlex Xie 
54497b2e202SAlex Deucher 	const struct amdgpu_gart_funcs *gart_funcs;
54597b2e202SAlex Deucher };
54697b2e202SAlex Deucher 
54797b2e202SAlex Deucher int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
54897b2e202SAlex Deucher void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
54997b2e202SAlex Deucher int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
55097b2e202SAlex Deucher void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
55197b2e202SAlex Deucher int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
55297b2e202SAlex Deucher void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
55397b2e202SAlex Deucher int amdgpu_gart_init(struct amdgpu_device *adev);
55497b2e202SAlex Deucher void amdgpu_gart_fini(struct amdgpu_device *adev);
555cab0b8d5SFelix Kuehling void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
55697b2e202SAlex Deucher 			int pages);
557cab0b8d5SFelix Kuehling int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
55897b2e202SAlex Deucher 		     int pages, struct page **pagelist,
5596b777607SChunming Zhou 		     dma_addr_t *dma_addr, uint64_t flags);
5602c0d7318SChunming Zhou int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
56197b2e202SAlex Deucher 
56297b2e202SAlex Deucher /*
563e60f8db5SAlex Xie  * VMHUB structures, functions & helpers
564e60f8db5SAlex Xie  */
565e60f8db5SAlex Xie struct amdgpu_vmhub {
566e60f8db5SAlex Xie 	uint32_t	ctx0_ptb_addr_lo32;
567e60f8db5SAlex Xie 	uint32_t	ctx0_ptb_addr_hi32;
568e60f8db5SAlex Xie 	uint32_t	vm_inv_eng0_req;
569e60f8db5SAlex Xie 	uint32_t	vm_inv_eng0_ack;
570e60f8db5SAlex Xie 	uint32_t	vm_context0_cntl;
571e60f8db5SAlex Xie 	uint32_t	vm_l2_pro_fault_status;
572e60f8db5SAlex Xie 	uint32_t	vm_l2_pro_fault_cntl;
573e60f8db5SAlex Xie 	uint32_t	(*get_invalidate_req)(unsigned int vm_id);
574e60f8db5SAlex Xie };
575e60f8db5SAlex Xie 
576e60f8db5SAlex Xie /*
57797b2e202SAlex Deucher  * GPU MC structures, functions & helpers
57897b2e202SAlex Deucher  */
57997b2e202SAlex Deucher struct amdgpu_mc {
58097b2e202SAlex Deucher 	resource_size_t		aper_size;
58197b2e202SAlex Deucher 	resource_size_t		aper_base;
58297b2e202SAlex Deucher 	resource_size_t		agp_base;
58397b2e202SAlex Deucher 	/* for some chips with <= 32MB we need to lie
58497b2e202SAlex Deucher 	 * about vram size near mc fb location */
58597b2e202SAlex Deucher 	u64			mc_vram_size;
58697b2e202SAlex Deucher 	u64			visible_vram_size;
58797b2e202SAlex Deucher 	u64			gtt_size;
58897b2e202SAlex Deucher 	u64			gtt_start;
58997b2e202SAlex Deucher 	u64			gtt_end;
59097b2e202SAlex Deucher 	u64			vram_start;
59197b2e202SAlex Deucher 	u64			vram_end;
59297b2e202SAlex Deucher 	unsigned		vram_width;
59397b2e202SAlex Deucher 	u64			real_vram_size;
59497b2e202SAlex Deucher 	int			vram_mtrr;
59597b2e202SAlex Deucher 	u64                     gtt_base_align;
59697b2e202SAlex Deucher 	u64                     mc_mask;
59797b2e202SAlex Deucher 	const struct firmware   *fw;	/* MC firmware */
59897b2e202SAlex Deucher 	uint32_t                fw_version;
59997b2e202SAlex Deucher 	struct amdgpu_irq_src	vm_fault;
60081c59f54SKen Wang 	uint32_t		vram_type;
60150b0197aSChunming Zhou 	uint32_t                srbm_soft_reset;
60250b0197aSChunming Zhou 	struct amdgpu_mode_mc_save save;
603f7c35abeSChristian König 	bool			prt_warning;
6048fe73328SJunwei Zhang 	/* apertures */
6058fe73328SJunwei Zhang 	u64					shared_aperture_start;
6068fe73328SJunwei Zhang 	u64					shared_aperture_end;
6078fe73328SJunwei Zhang 	u64					private_aperture_start;
6088fe73328SJunwei Zhang 	u64					private_aperture_end;
609e60f8db5SAlex Xie 	/* protects concurrent invalidation */
610e60f8db5SAlex Xie 	spinlock_t		invalidate_lock;
61197b2e202SAlex Deucher };
61297b2e202SAlex Deucher 
61397b2e202SAlex Deucher /*
61497b2e202SAlex Deucher  * GPU doorbell structures, functions & helpers
61597b2e202SAlex Deucher  */
61697b2e202SAlex Deucher typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
61797b2e202SAlex Deucher {
61897b2e202SAlex Deucher 	AMDGPU_DOORBELL_KIQ                     = 0x000,
61997b2e202SAlex Deucher 	AMDGPU_DOORBELL_HIQ                     = 0x001,
62097b2e202SAlex Deucher 	AMDGPU_DOORBELL_DIQ                     = 0x002,
62197b2e202SAlex Deucher 	AMDGPU_DOORBELL_MEC_RING0               = 0x010,
62297b2e202SAlex Deucher 	AMDGPU_DOORBELL_MEC_RING1               = 0x011,
62397b2e202SAlex Deucher 	AMDGPU_DOORBELL_MEC_RING2               = 0x012,
62497b2e202SAlex Deucher 	AMDGPU_DOORBELL_MEC_RING3               = 0x013,
62597b2e202SAlex Deucher 	AMDGPU_DOORBELL_MEC_RING4               = 0x014,
62697b2e202SAlex Deucher 	AMDGPU_DOORBELL_MEC_RING5               = 0x015,
62797b2e202SAlex Deucher 	AMDGPU_DOORBELL_MEC_RING6               = 0x016,
62897b2e202SAlex Deucher 	AMDGPU_DOORBELL_MEC_RING7               = 0x017,
62997b2e202SAlex Deucher 	AMDGPU_DOORBELL_GFX_RING0               = 0x020,
63097b2e202SAlex Deucher 	AMDGPU_DOORBELL_sDMA_ENGINE0            = 0x1E0,
63197b2e202SAlex Deucher 	AMDGPU_DOORBELL_sDMA_ENGINE1            = 0x1E1,
63297b2e202SAlex Deucher 	AMDGPU_DOORBELL_IH                      = 0x1E8,
63397b2e202SAlex Deucher 	AMDGPU_DOORBELL_MAX_ASSIGNMENT          = 0x3FF,
63497b2e202SAlex Deucher 	AMDGPU_DOORBELL_INVALID                 = 0xFFFF
63597b2e202SAlex Deucher } AMDGPU_DOORBELL_ASSIGNMENT;
63697b2e202SAlex Deucher 
63797b2e202SAlex Deucher struct amdgpu_doorbell {
63897b2e202SAlex Deucher 	/* doorbell mmio */
63997b2e202SAlex Deucher 	resource_size_t		base;
64097b2e202SAlex Deucher 	resource_size_t		size;
64197b2e202SAlex Deucher 	u32 __iomem		*ptr;
64297b2e202SAlex Deucher 	u32			num_doorbells;	/* Number of doorbells actually reserved for amdgpu. */
64397b2e202SAlex Deucher };
64497b2e202SAlex Deucher 
64539807b93SKen Wang /*
64639807b93SKen Wang  * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
64739807b93SKen Wang  */
64839807b93SKen Wang typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
64939807b93SKen Wang {
65039807b93SKen Wang 	/*
65139807b93SKen Wang 	 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
65239807b93SKen Wang 	 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
65339807b93SKen Wang 	 *  Compute related doorbells are allocated from 0x00 to 0x8a
65439807b93SKen Wang 	 */
65539807b93SKen Wang 
65639807b93SKen Wang 
65739807b93SKen Wang 	/* kernel scheduling */
65839807b93SKen Wang 	AMDGPU_DOORBELL64_KIQ                     = 0x00,
65939807b93SKen Wang 
66039807b93SKen Wang 	/* HSA interface queue and debug queue */
66139807b93SKen Wang 	AMDGPU_DOORBELL64_HIQ                     = 0x01,
66239807b93SKen Wang 	AMDGPU_DOORBELL64_DIQ                     = 0x02,
66339807b93SKen Wang 
66439807b93SKen Wang 	/* Compute engines */
66539807b93SKen Wang 	AMDGPU_DOORBELL64_MEC_RING0               = 0x03,
66639807b93SKen Wang 	AMDGPU_DOORBELL64_MEC_RING1               = 0x04,
66739807b93SKen Wang 	AMDGPU_DOORBELL64_MEC_RING2               = 0x05,
66839807b93SKen Wang 	AMDGPU_DOORBELL64_MEC_RING3               = 0x06,
66939807b93SKen Wang 	AMDGPU_DOORBELL64_MEC_RING4               = 0x07,
67039807b93SKen Wang 	AMDGPU_DOORBELL64_MEC_RING5               = 0x08,
67139807b93SKen Wang 	AMDGPU_DOORBELL64_MEC_RING6               = 0x09,
67239807b93SKen Wang 	AMDGPU_DOORBELL64_MEC_RING7               = 0x0a,
67339807b93SKen Wang 
67439807b93SKen Wang 	/* User queue doorbell range (128 doorbells) */
67539807b93SKen Wang 	AMDGPU_DOORBELL64_USERQUEUE_START         = 0x0b,
67639807b93SKen Wang 	AMDGPU_DOORBELL64_USERQUEUE_END           = 0x8a,
67739807b93SKen Wang 
67839807b93SKen Wang 	/* Graphics engine */
67939807b93SKen Wang 	AMDGPU_DOORBELL64_GFX_RING0               = 0x8b,
68039807b93SKen Wang 
68139807b93SKen Wang 	/*
68239807b93SKen Wang 	 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
68339807b93SKen Wang 	 * Graphics voltage island aperture 1
68439807b93SKen Wang 	 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
68539807b93SKen Wang 	 */
68639807b93SKen Wang 
68739807b93SKen Wang 	/* sDMA engines */
68839807b93SKen Wang 	AMDGPU_DOORBELL64_sDMA_ENGINE0            = 0xF0,
68939807b93SKen Wang 	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,
69039807b93SKen Wang 	AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xF2,
69139807b93SKen Wang 	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,
69239807b93SKen Wang 
69339807b93SKen Wang 	/* Interrupt handler */
69439807b93SKen Wang 	AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */
69539807b93SKen Wang 	AMDGPU_DOORBELL64_IH_RING1                = 0xF5,  /* For page migration request log */
69639807b93SKen Wang 	AMDGPU_DOORBELL64_IH_RING2                = 0xF6,  /* For page migration translation/invalidation log */
69739807b93SKen Wang 
698e6b3ecb4SMonk Liu 	/* VCN engine use 32 bits doorbell  */
699e6b3ecb4SMonk Liu 	AMDGPU_DOORBELL64_VCN0_1                  = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
700e6b3ecb4SMonk Liu 	AMDGPU_DOORBELL64_VCN2_3                  = 0xF9,
701e6b3ecb4SMonk Liu 	AMDGPU_DOORBELL64_VCN4_5                  = 0xFA,
702e6b3ecb4SMonk Liu 	AMDGPU_DOORBELL64_VCN6_7                  = 0xFB,
703e6b3ecb4SMonk Liu 
704e6b3ecb4SMonk Liu 	/* overlap the doorbell assignment with VCN as they are  mutually exclusive
705e6b3ecb4SMonk Liu 	 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
706e6b3ecb4SMonk Liu 	 */
707e6b3ecb4SMonk Liu 	AMDGPU_DOORBELL64_RING0_1                 = 0xF8,
708e6b3ecb4SMonk Liu 	AMDGPU_DOORBELL64_RING2_3                 = 0xF9,
709e6b3ecb4SMonk Liu 	AMDGPU_DOORBELL64_RING4_5                 = 0xFA,
710e6b3ecb4SMonk Liu 	AMDGPU_DOORBELL64_RING6_7                 = 0xFB,
711e6b3ecb4SMonk Liu 
712e6b3ecb4SMonk Liu 	AMDGPU_DOORBELL64_UVD_RING0_1             = 0xFC,
713e6b3ecb4SMonk Liu 	AMDGPU_DOORBELL64_UVD_RING2_3             = 0xFD,
714e6b3ecb4SMonk Liu 	AMDGPU_DOORBELL64_UVD_RING4_5             = 0xFE,
715e6b3ecb4SMonk Liu 	AMDGPU_DOORBELL64_UVD_RING6_7             = 0xFF,
71639807b93SKen Wang 
71739807b93SKen Wang 	AMDGPU_DOORBELL64_MAX_ASSIGNMENT          = 0xFF,
71839807b93SKen Wang 	AMDGPU_DOORBELL64_INVALID                 = 0xFFFF
71939807b93SKen Wang } AMDGPU_DOORBELL64_ASSIGNMENT;
72039807b93SKen Wang 
72139807b93SKen Wang 
72297b2e202SAlex Deucher void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
72397b2e202SAlex Deucher 				phys_addr_t *aperture_base,
72497b2e202SAlex Deucher 				size_t *aperture_size,
72597b2e202SAlex Deucher 				size_t *start_offset);
72697b2e202SAlex Deucher 
72797b2e202SAlex Deucher /*
72897b2e202SAlex Deucher  * IRQS.
72997b2e202SAlex Deucher  */
73097b2e202SAlex Deucher 
73197b2e202SAlex Deucher struct amdgpu_flip_work {
732325cbba1SMichel Dänzer 	struct delayed_work		flip_work;
73397b2e202SAlex Deucher 	struct work_struct		unpin_work;
73497b2e202SAlex Deucher 	struct amdgpu_device		*adev;
73597b2e202SAlex Deucher 	int				crtc_id;
736325cbba1SMichel Dänzer 	u32				target_vblank;
73797b2e202SAlex Deucher 	uint64_t			base;
73897b2e202SAlex Deucher 	struct drm_pending_vblank_event *event;
739765e7fbfSChristian König 	struct amdgpu_bo		*old_abo;
740f54d1867SChris Wilson 	struct dma_fence		*excl;
7411ffd2652SChristian König 	unsigned			shared_count;
742f54d1867SChris Wilson 	struct dma_fence		**shared;
743f54d1867SChris Wilson 	struct dma_fence_cb		cb;
744cb9e59d7SAlex Deucher 	bool				async;
74597b2e202SAlex Deucher };
74697b2e202SAlex Deucher 
74797b2e202SAlex Deucher 
74897b2e202SAlex Deucher /*
74997b2e202SAlex Deucher  * CP & rings.
75097b2e202SAlex Deucher  */
75197b2e202SAlex Deucher 
75297b2e202SAlex Deucher struct amdgpu_ib {
75397b2e202SAlex Deucher 	struct amdgpu_sa_bo		*sa_bo;
75497b2e202SAlex Deucher 	uint32_t			length_dw;
75597b2e202SAlex Deucher 	uint64_t			gpu_addr;
75697b2e202SAlex Deucher 	uint32_t			*ptr;
757de807f81SJammy Zhou 	uint32_t			flags;
75897b2e202SAlex Deucher };
75997b2e202SAlex Deucher 
76062250a91SNils Wallménius extern const struct amd_sched_backend_ops amdgpu_sched_ops;
761c1b69ed0SChunming Zhou 
76250838c8cSChristian König int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
763c5637837SMonk Liu 		     struct amdgpu_job **job, struct amdgpu_vm *vm);
764d71518b5SChristian König int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
765d71518b5SChristian König 			     struct amdgpu_job **job);
766b6723c8dSMonk Liu 
767a5fb4ec2SChristian König void amdgpu_job_free_resources(struct amdgpu_job *job);
76850838c8cSChristian König void amdgpu_job_free(struct amdgpu_job *job);
769d71518b5SChristian König int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
7702bd9ccfaSChristian König 		      struct amd_sched_entity *entity, void *owner,
771f54d1867SChris Wilson 		      struct dma_fence **f);
7728b4fb00bSChristian König 
77397b2e202SAlex Deucher /*
77497b2e202SAlex Deucher  * context related structures
77597b2e202SAlex Deucher  */
77697b2e202SAlex Deucher 
77721c16bf6SChristian König struct amdgpu_ctx_ring {
77821c16bf6SChristian König 	uint64_t		sequence;
779f54d1867SChris Wilson 	struct dma_fence	**fences;
78091404fb2SChristian König 	struct amd_sched_entity	entity;
78121c16bf6SChristian König };
78221c16bf6SChristian König 
78397b2e202SAlex Deucher struct amdgpu_ctx {
78497b2e202SAlex Deucher 	struct kref		refcount;
7859cb7e5a9SChunming Zhou 	struct amdgpu_device    *adev;
786d94aed5aSMarek Olšák 	unsigned		reset_counter;
78721c16bf6SChristian König 	spinlock_t		ring_lock;
788f54d1867SChris Wilson 	struct dma_fence	**fences;
78921c16bf6SChristian König 	struct amdgpu_ctx_ring	rings[AMDGPU_MAX_RINGS];
790753ad49cSMonk Liu 	bool preamble_presented;
79197b2e202SAlex Deucher };
79297b2e202SAlex Deucher 
79397b2e202SAlex Deucher struct amdgpu_ctx_mgr {
79497b2e202SAlex Deucher 	struct amdgpu_device	*adev;
7950147ee0fSMarek Olšák 	struct mutex		lock;
7960b492a4cSAlex Deucher 	/* protected by lock */
7970b492a4cSAlex Deucher 	struct idr		ctx_handles;
79897b2e202SAlex Deucher };
79997b2e202SAlex Deucher 
8000b492a4cSAlex Deucher struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
8010b492a4cSAlex Deucher int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
8020b492a4cSAlex Deucher 
80321c16bf6SChristian König uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
804f54d1867SChris Wilson 			      struct dma_fence *fence);
805f54d1867SChris Wilson struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
80621c16bf6SChristian König 				   struct amdgpu_ring *ring, uint64_t seq);
80721c16bf6SChristian König 
8080b492a4cSAlex Deucher int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
8090b492a4cSAlex Deucher 		     struct drm_file *filp);
8100b492a4cSAlex Deucher 
811efd4ccb5SChristian König void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
812efd4ccb5SChristian König void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
8130b492a4cSAlex Deucher 
81497b2e202SAlex Deucher /*
81597b2e202SAlex Deucher  * file private structure
81697b2e202SAlex Deucher  */
81797b2e202SAlex Deucher 
81897b2e202SAlex Deucher struct amdgpu_fpriv {
81997b2e202SAlex Deucher 	struct amdgpu_vm	vm;
820b85891bdSJunwei Zhang 	struct amdgpu_bo_va	*prt_va;
82197b2e202SAlex Deucher 	struct mutex		bo_list_lock;
82297b2e202SAlex Deucher 	struct idr		bo_list_handles;
82397b2e202SAlex Deucher 	struct amdgpu_ctx_mgr	ctx_mgr;
82497b2e202SAlex Deucher };
82597b2e202SAlex Deucher 
82697b2e202SAlex Deucher /*
82797b2e202SAlex Deucher  * residency list
82897b2e202SAlex Deucher  */
82997b2e202SAlex Deucher 
83097b2e202SAlex Deucher struct amdgpu_bo_list {
83197b2e202SAlex Deucher 	struct mutex lock;
83297b2e202SAlex Deucher 	struct amdgpu_bo *gds_obj;
83397b2e202SAlex Deucher 	struct amdgpu_bo *gws_obj;
83497b2e202SAlex Deucher 	struct amdgpu_bo *oa_obj;
835211dff55SChristian König 	unsigned first_userptr;
83697b2e202SAlex Deucher 	unsigned num_entries;
83797b2e202SAlex Deucher 	struct amdgpu_bo_list_entry *array;
83897b2e202SAlex Deucher };
83997b2e202SAlex Deucher 
84097b2e202SAlex Deucher struct amdgpu_bo_list *
84197b2e202SAlex Deucher amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
842636ce25cSChristian König void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
843636ce25cSChristian König 			     struct list_head *validated);
84497b2e202SAlex Deucher void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
84597b2e202SAlex Deucher void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
84697b2e202SAlex Deucher 
84797b2e202SAlex Deucher /*
84897b2e202SAlex Deucher  * GFX stuff
84997b2e202SAlex Deucher  */
85097b2e202SAlex Deucher #include "clearstate_defs.h"
85197b2e202SAlex Deucher 
85279e5412cSAlex Deucher struct amdgpu_rlc_funcs {
85379e5412cSAlex Deucher 	void (*enter_safe_mode)(struct amdgpu_device *adev);
85479e5412cSAlex Deucher 	void (*exit_safe_mode)(struct amdgpu_device *adev);
85579e5412cSAlex Deucher };
85679e5412cSAlex Deucher 
85797b2e202SAlex Deucher struct amdgpu_rlc {
85897b2e202SAlex Deucher 	/* for power gating */
85997b2e202SAlex Deucher 	struct amdgpu_bo	*save_restore_obj;
86097b2e202SAlex Deucher 	uint64_t		save_restore_gpu_addr;
86197b2e202SAlex Deucher 	volatile uint32_t	*sr_ptr;
86297b2e202SAlex Deucher 	const u32               *reg_list;
86397b2e202SAlex Deucher 	u32                     reg_list_size;
86497b2e202SAlex Deucher 	/* for clear state */
86597b2e202SAlex Deucher 	struct amdgpu_bo	*clear_state_obj;
86697b2e202SAlex Deucher 	uint64_t		clear_state_gpu_addr;
86797b2e202SAlex Deucher 	volatile uint32_t	*cs_ptr;
86897b2e202SAlex Deucher 	const struct cs_section_def   *cs_data;
86997b2e202SAlex Deucher 	u32                     clear_state_size;
87097b2e202SAlex Deucher 	/* for cp tables */
87197b2e202SAlex Deucher 	struct amdgpu_bo	*cp_table_obj;
87297b2e202SAlex Deucher 	uint64_t		cp_table_gpu_addr;
87397b2e202SAlex Deucher 	volatile uint32_t	*cp_table_ptr;
87497b2e202SAlex Deucher 	u32                     cp_table_size;
87579e5412cSAlex Deucher 
87679e5412cSAlex Deucher 	/* safe mode for updating CG/PG state */
87779e5412cSAlex Deucher 	bool in_safe_mode;
87879e5412cSAlex Deucher 	const struct amdgpu_rlc_funcs *funcs;
8792b6cd977SEric Huang 
8802b6cd977SEric Huang 	/* for firmware data */
8812b6cd977SEric Huang 	u32 save_and_restore_offset;
8822b6cd977SEric Huang 	u32 clear_state_descriptor_offset;
8832b6cd977SEric Huang 	u32 avail_scratch_ram_locations;
8842b6cd977SEric Huang 	u32 reg_restore_list_size;
8852b6cd977SEric Huang 	u32 reg_list_format_start;
8862b6cd977SEric Huang 	u32 reg_list_format_separate_start;
8872b6cd977SEric Huang 	u32 starting_offsets_start;
8882b6cd977SEric Huang 	u32 reg_list_format_size_bytes;
8892b6cd977SEric Huang 	u32 reg_list_size_bytes;
8902b6cd977SEric Huang 
8912b6cd977SEric Huang 	u32 *register_list_format;
8922b6cd977SEric Huang 	u32 *register_restore;
89397b2e202SAlex Deucher };
89497b2e202SAlex Deucher 
89597b2e202SAlex Deucher struct amdgpu_mec {
89697b2e202SAlex Deucher 	struct amdgpu_bo	*hpd_eop_obj;
89797b2e202SAlex Deucher 	u64			hpd_eop_gpu_addr;
898b1023571SKen Wang 	struct amdgpu_bo	*mec_fw_obj;
899b1023571SKen Wang 	u64			mec_fw_gpu_addr;
90097b2e202SAlex Deucher 	u32 num_pipe;
90197b2e202SAlex Deucher 	u32 num_mec;
90297b2e202SAlex Deucher 	u32 num_queue;
90359a82d7dSXiangliang Yu 	void			*mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
90497b2e202SAlex Deucher };
90597b2e202SAlex Deucher 
9064e638ae9SXiangliang Yu struct amdgpu_kiq {
9074e638ae9SXiangliang Yu 	u64			eop_gpu_addr;
9084e638ae9SXiangliang Yu 	struct amdgpu_bo	*eop_obj;
9094e638ae9SXiangliang Yu 	struct amdgpu_ring	ring;
9104e638ae9SXiangliang Yu 	struct amdgpu_irq_src	irq;
9114e638ae9SXiangliang Yu };
9124e638ae9SXiangliang Yu 
91397b2e202SAlex Deucher /*
91497b2e202SAlex Deucher  * GPU scratch registers structures, functions & helpers
91597b2e202SAlex Deucher  */
91697b2e202SAlex Deucher struct amdgpu_scratch {
91797b2e202SAlex Deucher 	unsigned		num_reg;
91897b2e202SAlex Deucher 	uint32_t                reg_base;
91950261151SNils Wallménius 	uint32_t		free_mask;
92097b2e202SAlex Deucher };
92197b2e202SAlex Deucher 
92297b2e202SAlex Deucher /*
92397b2e202SAlex Deucher  * GFX configurations
92497b2e202SAlex Deucher  */
925e3fa7630SAlex Deucher #define AMDGPU_GFX_MAX_SE 4
926e3fa7630SAlex Deucher #define AMDGPU_GFX_MAX_SH_PER_SE 2
927e3fa7630SAlex Deucher 
928e3fa7630SAlex Deucher struct amdgpu_rb_config {
929e3fa7630SAlex Deucher 	uint32_t rb_backend_disable;
930e3fa7630SAlex Deucher 	uint32_t user_rb_backend_disable;
931e3fa7630SAlex Deucher 	uint32_t raster_config;
932e3fa7630SAlex Deucher 	uint32_t raster_config_1;
933e3fa7630SAlex Deucher };
934e3fa7630SAlex Deucher 
935d0e95758SAndrey Grodzovsky struct gb_addr_config {
936d0e95758SAndrey Grodzovsky 	uint16_t pipe_interleave_size;
937d0e95758SAndrey Grodzovsky 	uint8_t num_pipes;
938d0e95758SAndrey Grodzovsky 	uint8_t max_compress_frags;
939d0e95758SAndrey Grodzovsky 	uint8_t num_banks;
940d0e95758SAndrey Grodzovsky 	uint8_t num_se;
941d0e95758SAndrey Grodzovsky 	uint8_t num_rb_per_se;
942d0e95758SAndrey Grodzovsky };
943d0e95758SAndrey Grodzovsky 
944ea323f88SJunwei Zhang struct amdgpu_gfx_config {
94597b2e202SAlex Deucher 	unsigned max_shader_engines;
94697b2e202SAlex Deucher 	unsigned max_tile_pipes;
94797b2e202SAlex Deucher 	unsigned max_cu_per_sh;
94897b2e202SAlex Deucher 	unsigned max_sh_per_se;
94997b2e202SAlex Deucher 	unsigned max_backends_per_se;
95097b2e202SAlex Deucher 	unsigned max_texture_channel_caches;
95197b2e202SAlex Deucher 	unsigned max_gprs;
95297b2e202SAlex Deucher 	unsigned max_gs_threads;
95397b2e202SAlex Deucher 	unsigned max_hw_contexts;
95497b2e202SAlex Deucher 	unsigned sc_prim_fifo_size_frontend;
95597b2e202SAlex Deucher 	unsigned sc_prim_fifo_size_backend;
95697b2e202SAlex Deucher 	unsigned sc_hiz_tile_fifo_size;
95797b2e202SAlex Deucher 	unsigned sc_earlyz_tile_fifo_size;
95897b2e202SAlex Deucher 
95997b2e202SAlex Deucher 	unsigned num_tile_pipes;
96097b2e202SAlex Deucher 	unsigned backend_enable_mask;
96197b2e202SAlex Deucher 	unsigned mem_max_burst_length_bytes;
96297b2e202SAlex Deucher 	unsigned mem_row_size_in_kb;
96397b2e202SAlex Deucher 	unsigned shader_engine_tile_size;
96497b2e202SAlex Deucher 	unsigned num_gpus;
96597b2e202SAlex Deucher 	unsigned multi_gpu_tile_size;
96697b2e202SAlex Deucher 	unsigned mc_arb_ramcfg;
96797b2e202SAlex Deucher 	unsigned gb_addr_config;
9688f8e00c1SAlex Deucher 	unsigned num_rbs;
96997b2e202SAlex Deucher 
97097b2e202SAlex Deucher 	uint32_t tile_mode_array[32];
97197b2e202SAlex Deucher 	uint32_t macrotile_mode_array[16];
972e3fa7630SAlex Deucher 
973d0e95758SAndrey Grodzovsky 	struct gb_addr_config gb_addr_config_fields;
974e3fa7630SAlex Deucher 	struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
975df6e2c4aSJunwei Zhang 
976df6e2c4aSJunwei Zhang 	/* gfx configure feature */
977df6e2c4aSJunwei Zhang 	uint32_t double_offchip_lds_buf;
97897b2e202SAlex Deucher };
97997b2e202SAlex Deucher 
9807dae69a2SAlex Deucher struct amdgpu_cu_info {
9817dae69a2SAlex Deucher 	uint32_t number; /* total active CU number */
9827dae69a2SAlex Deucher 	uint32_t ao_cu_mask;
9837dae69a2SAlex Deucher 	uint32_t bitmap[4][4];
9847dae69a2SAlex Deucher };
9857dae69a2SAlex Deucher 
986b95e31fdSAlex Deucher struct amdgpu_gfx_funcs {
987b95e31fdSAlex Deucher 	/* get the gpu clock counter */
988b95e31fdSAlex Deucher 	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
9899559ef5bSTom St Denis 	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
990472259f0STom St Denis 	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
991c5a60ce8STom St Denis 	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
992c5a60ce8STom St Denis 	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
993b95e31fdSAlex Deucher };
994b95e31fdSAlex Deucher 
995bce23e00SAlex Deucher struct amdgpu_ngg_buf {
996bce23e00SAlex Deucher 	struct amdgpu_bo	*bo;
997bce23e00SAlex Deucher 	uint64_t		gpu_addr;
998bce23e00SAlex Deucher 	uint32_t		size;
999bce23e00SAlex Deucher 	uint32_t		bo_size;
1000bce23e00SAlex Deucher };
1001bce23e00SAlex Deucher 
1002bce23e00SAlex Deucher enum {
1003bce23e00SAlex Deucher 	PRIM = 0,
1004bce23e00SAlex Deucher 	POS,
1005bce23e00SAlex Deucher 	CNTL,
1006bce23e00SAlex Deucher 	PARAM,
1007bce23e00SAlex Deucher 	NGG_BUF_MAX
1008bce23e00SAlex Deucher };
1009bce23e00SAlex Deucher 
1010bce23e00SAlex Deucher struct amdgpu_ngg {
1011bce23e00SAlex Deucher 	struct amdgpu_ngg_buf	buf[NGG_BUF_MAX];
1012bce23e00SAlex Deucher 	uint32_t		gds_reserve_addr;
1013bce23e00SAlex Deucher 	uint32_t		gds_reserve_size;
1014bce23e00SAlex Deucher 	bool			init;
1015bce23e00SAlex Deucher };
1016bce23e00SAlex Deucher 
101797b2e202SAlex Deucher struct amdgpu_gfx {
101897b2e202SAlex Deucher 	struct mutex			gpu_clock_mutex;
1019ea323f88SJunwei Zhang 	struct amdgpu_gfx_config	config;
102097b2e202SAlex Deucher 	struct amdgpu_rlc		rlc;
102197b2e202SAlex Deucher 	struct amdgpu_mec		mec;
10224e638ae9SXiangliang Yu 	struct amdgpu_kiq		kiq;
102397b2e202SAlex Deucher 	struct amdgpu_scratch		scratch;
102497b2e202SAlex Deucher 	const struct firmware		*me_fw;	/* ME firmware */
102597b2e202SAlex Deucher 	uint32_t			me_fw_version;
102697b2e202SAlex Deucher 	const struct firmware		*pfp_fw; /* PFP firmware */
102797b2e202SAlex Deucher 	uint32_t			pfp_fw_version;
102897b2e202SAlex Deucher 	const struct firmware		*ce_fw;	/* CE firmware */
102997b2e202SAlex Deucher 	uint32_t			ce_fw_version;
103097b2e202SAlex Deucher 	const struct firmware		*rlc_fw; /* RLC firmware */
103197b2e202SAlex Deucher 	uint32_t			rlc_fw_version;
103297b2e202SAlex Deucher 	const struct firmware		*mec_fw; /* MEC firmware */
103397b2e202SAlex Deucher 	uint32_t			mec_fw_version;
103497b2e202SAlex Deucher 	const struct firmware		*mec2_fw; /* MEC2 firmware */
103597b2e202SAlex Deucher 	uint32_t			mec2_fw_version;
103602558a00SKen Wang 	uint32_t			me_feature_version;
103702558a00SKen Wang 	uint32_t			ce_feature_version;
103802558a00SKen Wang 	uint32_t			pfp_feature_version;
1039351643d7SJammy Zhou 	uint32_t			rlc_feature_version;
1040351643d7SJammy Zhou 	uint32_t			mec_feature_version;
1041351643d7SJammy Zhou 	uint32_t			mec2_feature_version;
104297b2e202SAlex Deucher 	struct amdgpu_ring		gfx_ring[AMDGPU_MAX_GFX_RINGS];
104397b2e202SAlex Deucher 	unsigned			num_gfx_rings;
104497b2e202SAlex Deucher 	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
104597b2e202SAlex Deucher 	unsigned			num_compute_rings;
104697b2e202SAlex Deucher 	struct amdgpu_irq_src		eop_irq;
104797b2e202SAlex Deucher 	struct amdgpu_irq_src		priv_reg_irq;
104897b2e202SAlex Deucher 	struct amdgpu_irq_src		priv_inst_irq;
104997b2e202SAlex Deucher 	/* gfx status */
105097b2e202SAlex Deucher 	uint32_t			gfx_current_status;
1051a101a899SKen Wang 	/* ce ram size*/
1052a101a899SKen Wang 	unsigned			ce_ram_size;
10537dae69a2SAlex Deucher 	struct amdgpu_cu_info		cu_info;
1054b95e31fdSAlex Deucher 	const struct amdgpu_gfx_funcs	*funcs;
10553d7c6384SChunming Zhou 
10563d7c6384SChunming Zhou 	/* reset mask */
10573d7c6384SChunming Zhou 	uint32_t                        grbm_soft_reset;
10583d7c6384SChunming Zhou 	uint32_t                        srbm_soft_reset;
1059223049cdSMonk Liu 	bool                            in_reset;
1060bce23e00SAlex Deucher 	/* NGG */
1061bce23e00SAlex Deucher 	struct amdgpu_ngg		ngg;
106297b2e202SAlex Deucher };
106397b2e202SAlex Deucher 
1064b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
106597b2e202SAlex Deucher 		  unsigned size, struct amdgpu_ib *ib);
10664d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
1067f54d1867SChris Wilson 		    struct dma_fence *f);
1068b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
106950ddc75eSJunwei Zhang 		       struct amdgpu_ib *ibs, struct amdgpu_job *job,
107050ddc75eSJunwei Zhang 		       struct dma_fence **f);
107197b2e202SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev);
107297b2e202SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
107397b2e202SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
107497b2e202SAlex Deucher 
107597b2e202SAlex Deucher /*
107697b2e202SAlex Deucher  * CS.
107797b2e202SAlex Deucher  */
107897b2e202SAlex Deucher struct amdgpu_cs_chunk {
107997b2e202SAlex Deucher 	uint32_t		chunk_id;
108097b2e202SAlex Deucher 	uint32_t		length_dw;
1081758ac17fSChristian König 	void			*kdata;
108297b2e202SAlex Deucher };
108397b2e202SAlex Deucher 
108497b2e202SAlex Deucher struct amdgpu_cs_parser {
108597b2e202SAlex Deucher 	struct amdgpu_device	*adev;
108697b2e202SAlex Deucher 	struct drm_file		*filp;
10873cb485f3SChristian König 	struct amdgpu_ctx	*ctx;
1088c3cca41eSChristian König 
108997b2e202SAlex Deucher 	/* chunks */
109097b2e202SAlex Deucher 	unsigned		nchunks;
109197b2e202SAlex Deucher 	struct amdgpu_cs_chunk	*chunks;
1092c3cca41eSChristian König 
109350838c8cSChristian König 	/* scheduler job object */
109450838c8cSChristian König 	struct amdgpu_job	*job;
1095c3cca41eSChristian König 
1096c3cca41eSChristian König 	/* buffer objects */
1097c3cca41eSChristian König 	struct ww_acquire_ctx		ticket;
1098c3cca41eSChristian König 	struct amdgpu_bo_list		*bo_list;
109956467ebfSChristian König 	struct amdgpu_bo_list_entry	vm_pd;
110097b2e202SAlex Deucher 	struct list_head		validated;
1101f54d1867SChris Wilson 	struct dma_fence		*fence;
1102f69f90a1SChristian König 	uint64_t			bytes_moved_threshold;
1103f69f90a1SChristian König 	uint64_t			bytes_moved;
1104662bfa61SChristian König 	struct amdgpu_bo_list_entry	*evictable;
110597b2e202SAlex Deucher 
110697b2e202SAlex Deucher 	/* user fence */
110791acbeb6SChristian König 	struct amdgpu_bo_list_entry	uf_entry;
110897b2e202SAlex Deucher };
110997b2e202SAlex Deucher 
1110753ad49cSMonk Liu #define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0) /* bit set means command submit involves a preamble IB */
1111753ad49cSMonk Liu #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1112753ad49cSMonk Liu #define AMDGPU_HAVE_CTX_SWITCH              (1 << 2) /* bit set means context switch occured */
11137e6bf80fSMonk Liu #define AMDGPU_VM_DOMAIN                    (1 << 3) /* bit set means in virtual memory context */
1114753ad49cSMonk Liu 
1115bb977d37SChunming Zhou struct amdgpu_job {
1116bb977d37SChunming Zhou 	struct amd_sched_job    base;
1117bb977d37SChunming Zhou 	struct amdgpu_device	*adev;
1118c5637837SMonk Liu 	struct amdgpu_vm	*vm;
1119b07c60c0SChristian König 	struct amdgpu_ring	*ring;
1120e86f9ceeSChristian König 	struct amdgpu_sync	sync;
1121bb977d37SChunming Zhou 	struct amdgpu_ib	*ibs;
1122f54d1867SChris Wilson 	struct dma_fence	*fence; /* the hw fence */
1123753ad49cSMonk Liu 	uint32_t		preamble_status;
1124bb977d37SChunming Zhou 	uint32_t		num_ibs;
1125e2840221SChristian König 	void			*owner;
11263aecd24cSMonk Liu 	uint64_t		fence_ctx; /* the fence_context this job uses */
1127fd53be30SChunming Zhou 	bool                    vm_needs_flush;
1128d88bf583SChristian König 	unsigned		vm_id;
1129d88bf583SChristian König 	uint64_t		vm_pd_addr;
1130d88bf583SChristian König 	uint32_t		gds_base, gds_size;
1131d88bf583SChristian König 	uint32_t		gws_base, gws_size;
1132d88bf583SChristian König 	uint32_t		oa_base, oa_size;
1133758ac17fSChristian König 
1134758ac17fSChristian König 	/* user fence handling */
1135b5f5acbcSChristian König 	uint64_t		uf_addr;
1136758ac17fSChristian König 	uint64_t		uf_sequence;
1137758ac17fSChristian König 
1138bb977d37SChunming Zhou };
1139a6db8a33SJunwei Zhang #define to_amdgpu_job(sched_job)		\
1140a6db8a33SJunwei Zhang 		container_of((sched_job), struct amdgpu_job, base)
1141bb977d37SChunming Zhou 
11427270f839SChristian König static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
11437270f839SChristian König 				      uint32_t ib_idx, int idx)
114497b2e202SAlex Deucher {
114550838c8cSChristian König 	return p->job->ibs[ib_idx].ptr[idx];
114697b2e202SAlex Deucher }
114797b2e202SAlex Deucher 
11487270f839SChristian König static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
11497270f839SChristian König 				       uint32_t ib_idx, int idx,
11507270f839SChristian König 				       uint32_t value)
11517270f839SChristian König {
115250838c8cSChristian König 	p->job->ibs[ib_idx].ptr[idx] = value;
11537270f839SChristian König }
11547270f839SChristian König 
115597b2e202SAlex Deucher /*
115697b2e202SAlex Deucher  * Writeback
115797b2e202SAlex Deucher  */
115897b2e202SAlex Deucher #define AMDGPU_MAX_WB 1024	/* Reserve at most 1024 WB slots for amdgpu-owned rings. */
115997b2e202SAlex Deucher 
116097b2e202SAlex Deucher struct amdgpu_wb {
116197b2e202SAlex Deucher 	struct amdgpu_bo	*wb_obj;
116297b2e202SAlex Deucher 	volatile uint32_t	*wb;
116397b2e202SAlex Deucher 	uint64_t		gpu_addr;
116497b2e202SAlex Deucher 	u32			num_wb;	/* Number of wb slots actually reserved for amdgpu. */
116597b2e202SAlex Deucher 	unsigned long		used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
116697b2e202SAlex Deucher };
116797b2e202SAlex Deucher 
116897b2e202SAlex Deucher int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
116997b2e202SAlex Deucher void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
11707014285aSKen Wang int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
11717014285aSKen Wang void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
117297b2e202SAlex Deucher 
1173d0dd7f0cSAlex Deucher void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1174d0dd7f0cSAlex Deucher 
117597b2e202SAlex Deucher /*
117697b2e202SAlex Deucher  * SDMA
117797b2e202SAlex Deucher  */
1178c113ea1cSAlex Deucher struct amdgpu_sdma_instance {
117997b2e202SAlex Deucher 	/* SDMA firmware */
118097b2e202SAlex Deucher 	const struct firmware	*fw;
118197b2e202SAlex Deucher 	uint32_t		fw_version;
1182cfa2104fSJammy Zhou 	uint32_t		feature_version;
118397b2e202SAlex Deucher 
118497b2e202SAlex Deucher 	struct amdgpu_ring	ring;
118518111de0SJammy Zhou 	bool			burst_nop;
118697b2e202SAlex Deucher };
118797b2e202SAlex Deucher 
1188c113ea1cSAlex Deucher struct amdgpu_sdma {
1189c113ea1cSAlex Deucher 	struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
119030d1574fSKen Wang #ifdef CONFIG_DRM_AMDGPU_SI
119130d1574fSKen Wang 	//SI DMA has a difference trap irq number for the second engine
119230d1574fSKen Wang 	struct amdgpu_irq_src	trap_irq_1;
119330d1574fSKen Wang #endif
1194c113ea1cSAlex Deucher 	struct amdgpu_irq_src	trap_irq;
1195c113ea1cSAlex Deucher 	struct amdgpu_irq_src	illegal_inst_irq;
1196c113ea1cSAlex Deucher 	int			num_instances;
1197e702a680SChunming Zhou 	uint32_t                    srbm_soft_reset;
1198c113ea1cSAlex Deucher };
1199c113ea1cSAlex Deucher 
120097b2e202SAlex Deucher /*
120197b2e202SAlex Deucher  * Firmware
120297b2e202SAlex Deucher  */
1203e635ee07SHuang Rui enum amdgpu_firmware_load_type {
1204e635ee07SHuang Rui 	AMDGPU_FW_LOAD_DIRECT = 0,
1205e635ee07SHuang Rui 	AMDGPU_FW_LOAD_SMU,
1206e635ee07SHuang Rui 	AMDGPU_FW_LOAD_PSP,
1207e635ee07SHuang Rui };
1208e635ee07SHuang Rui 
120997b2e202SAlex Deucher struct amdgpu_firmware {
121097b2e202SAlex Deucher 	struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1211e635ee07SHuang Rui 	enum amdgpu_firmware_load_type load_type;
121297b2e202SAlex Deucher 	struct amdgpu_bo *fw_buf;
121397b2e202SAlex Deucher 	unsigned int fw_size;
12142445b227SHuang Rui 	unsigned int max_ucodes;
12150e5ca0d1SHuang Rui 	/* firmwares are loaded by psp instead of smu from vega10 */
12160e5ca0d1SHuang Rui 	const struct amdgpu_psp_funcs *funcs;
12170e5ca0d1SHuang Rui 	struct amdgpu_bo *rbuf;
12180e5ca0d1SHuang Rui 	struct mutex mutex;
121997b2e202SAlex Deucher };
122097b2e202SAlex Deucher 
122197b2e202SAlex Deucher /*
122297b2e202SAlex Deucher  * Benchmarking
122397b2e202SAlex Deucher  */
122497b2e202SAlex Deucher void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
122597b2e202SAlex Deucher 
122697b2e202SAlex Deucher 
122797b2e202SAlex Deucher /*
122897b2e202SAlex Deucher  * Testing
122997b2e202SAlex Deucher  */
123097b2e202SAlex Deucher void amdgpu_test_moves(struct amdgpu_device *adev);
123197b2e202SAlex Deucher 
123297b2e202SAlex Deucher /*
123397b2e202SAlex Deucher  * MMU Notifier
123497b2e202SAlex Deucher  */
123597b2e202SAlex Deucher #if defined(CONFIG_MMU_NOTIFIER)
123697b2e202SAlex Deucher int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
123797b2e202SAlex Deucher void amdgpu_mn_unregister(struct amdgpu_bo *bo);
123897b2e202SAlex Deucher #else
12391d1106b0SHarry Wentland static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
124097b2e202SAlex Deucher {
124197b2e202SAlex Deucher 	return -ENODEV;
124297b2e202SAlex Deucher }
12431d1106b0SHarry Wentland static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
124497b2e202SAlex Deucher #endif
124597b2e202SAlex Deucher 
124697b2e202SAlex Deucher /*
124797b2e202SAlex Deucher  * Debugfs
124897b2e202SAlex Deucher  */
124997b2e202SAlex Deucher struct amdgpu_debugfs {
125006ab6832SNils Wallménius 	const struct drm_info_list	*files;
125197b2e202SAlex Deucher 	unsigned		num_files;
125297b2e202SAlex Deucher };
125397b2e202SAlex Deucher 
125497b2e202SAlex Deucher int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
125506ab6832SNils Wallménius 			     const struct drm_info_list *files,
125697b2e202SAlex Deucher 			     unsigned nfiles);
125797b2e202SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
125897b2e202SAlex Deucher 
125997b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS)
126097b2e202SAlex Deucher int amdgpu_debugfs_init(struct drm_minor *minor);
126197b2e202SAlex Deucher #endif
126297b2e202SAlex Deucher 
126350ab2533SHuang Rui int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
126450ab2533SHuang Rui 
126597b2e202SAlex Deucher /*
126697b2e202SAlex Deucher  * amdgpu smumgr functions
126797b2e202SAlex Deucher  */
126897b2e202SAlex Deucher struct amdgpu_smumgr_funcs {
126997b2e202SAlex Deucher 	int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
127097b2e202SAlex Deucher 	int (*request_smu_load_fw)(struct amdgpu_device *adev);
127197b2e202SAlex Deucher 	int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
127297b2e202SAlex Deucher };
127397b2e202SAlex Deucher 
127497b2e202SAlex Deucher /*
127597b2e202SAlex Deucher  * amdgpu smumgr
127697b2e202SAlex Deucher  */
127797b2e202SAlex Deucher struct amdgpu_smumgr {
127897b2e202SAlex Deucher 	struct amdgpu_bo *toc_buf;
127997b2e202SAlex Deucher 	struct amdgpu_bo *smu_buf;
128097b2e202SAlex Deucher 	/* asic priv smu data */
128197b2e202SAlex Deucher 	void *priv;
128297b2e202SAlex Deucher 	spinlock_t smu_lock;
128397b2e202SAlex Deucher 	/* smumgr functions */
128497b2e202SAlex Deucher 	const struct amdgpu_smumgr_funcs *smumgr_funcs;
128597b2e202SAlex Deucher 	/* ucode loading complete flag */
128697b2e202SAlex Deucher 	uint32_t fw_flags;
128797b2e202SAlex Deucher };
128897b2e202SAlex Deucher 
128997b2e202SAlex Deucher /*
129097b2e202SAlex Deucher  * ASIC specific register table accessible by UMD
129197b2e202SAlex Deucher  */
129297b2e202SAlex Deucher struct amdgpu_allowed_register_entry {
129397b2e202SAlex Deucher 	uint32_t reg_offset;
129497b2e202SAlex Deucher 	bool untouched;
129597b2e202SAlex Deucher 	bool grbm_indexed;
129697b2e202SAlex Deucher };
129797b2e202SAlex Deucher 
129897b2e202SAlex Deucher /*
129997b2e202SAlex Deucher  * ASIC specific functions.
130097b2e202SAlex Deucher  */
130197b2e202SAlex Deucher struct amdgpu_asic_funcs {
130297b2e202SAlex Deucher 	bool (*read_disabled_bios)(struct amdgpu_device *adev);
13037946b878SAlex Deucher 	bool (*read_bios_from_rom)(struct amdgpu_device *adev,
13047946b878SAlex Deucher 				   u8 *bios, u32 length_bytes);
130597b2e202SAlex Deucher 	int (*read_register)(struct amdgpu_device *adev, u32 se_num,
130697b2e202SAlex Deucher 			     u32 sh_num, u32 reg_offset, u32 *value);
130797b2e202SAlex Deucher 	void (*set_vga_state)(struct amdgpu_device *adev, bool state);
130897b2e202SAlex Deucher 	int (*reset)(struct amdgpu_device *adev);
130997b2e202SAlex Deucher 	/* get the reference clock */
131097b2e202SAlex Deucher 	u32 (*get_xclk)(struct amdgpu_device *adev);
131197b2e202SAlex Deucher 	/* MM block clocks */
131297b2e202SAlex Deucher 	int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
131397b2e202SAlex Deucher 	int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1314841686dfSMaruthi Bayyavarapu 	/* static power management */
1315841686dfSMaruthi Bayyavarapu 	int (*get_pcie_lanes)(struct amdgpu_device *adev);
1316841686dfSMaruthi Bayyavarapu 	void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
1317bbf282d8SAlex Deucher 	/* get config memsize register */
1318bbf282d8SAlex Deucher 	u32 (*get_config_memsize)(struct amdgpu_device *adev);
131997b2e202SAlex Deucher };
132097b2e202SAlex Deucher 
132197b2e202SAlex Deucher /*
132297b2e202SAlex Deucher  * IOCTL.
132397b2e202SAlex Deucher  */
132497b2e202SAlex Deucher int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
132597b2e202SAlex Deucher 			    struct drm_file *filp);
132697b2e202SAlex Deucher int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
132797b2e202SAlex Deucher 				struct drm_file *filp);
132897b2e202SAlex Deucher 
132997b2e202SAlex Deucher int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
133097b2e202SAlex Deucher 			  struct drm_file *filp);
133197b2e202SAlex Deucher int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
133297b2e202SAlex Deucher 			struct drm_file *filp);
133397b2e202SAlex Deucher int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
133497b2e202SAlex Deucher 			  struct drm_file *filp);
133597b2e202SAlex Deucher int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
133697b2e202SAlex Deucher 			      struct drm_file *filp);
133797b2e202SAlex Deucher int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
133897b2e202SAlex Deucher 			  struct drm_file *filp);
133997b2e202SAlex Deucher int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
134097b2e202SAlex Deucher 			struct drm_file *filp);
134197b2e202SAlex Deucher int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
134297b2e202SAlex Deucher int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1343eef18a82SJunwei Zhang int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1344eef18a82SJunwei Zhang 				struct drm_file *filp);
134597b2e202SAlex Deucher 
134697b2e202SAlex Deucher int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
134797b2e202SAlex Deucher 				struct drm_file *filp);
134897b2e202SAlex Deucher 
134997b2e202SAlex Deucher /* VRAM scratch page for HDP bug, default vram page */
135097b2e202SAlex Deucher struct amdgpu_vram_scratch {
135197b2e202SAlex Deucher 	struct amdgpu_bo		*robj;
135297b2e202SAlex Deucher 	volatile uint32_t		*ptr;
135397b2e202SAlex Deucher 	u64				gpu_addr;
135497b2e202SAlex Deucher };
135597b2e202SAlex Deucher 
135697b2e202SAlex Deucher /*
135797b2e202SAlex Deucher  * ACPI
135897b2e202SAlex Deucher  */
135997b2e202SAlex Deucher struct amdgpu_atif_notification_cfg {
136097b2e202SAlex Deucher 	bool enabled;
136197b2e202SAlex Deucher 	int command_code;
136297b2e202SAlex Deucher };
136397b2e202SAlex Deucher 
136497b2e202SAlex Deucher struct amdgpu_atif_notifications {
136597b2e202SAlex Deucher 	bool display_switch;
136697b2e202SAlex Deucher 	bool expansion_mode_change;
136797b2e202SAlex Deucher 	bool thermal_state;
136897b2e202SAlex Deucher 	bool forced_power_state;
136997b2e202SAlex Deucher 	bool system_power_state;
137097b2e202SAlex Deucher 	bool display_conf_change;
137197b2e202SAlex Deucher 	bool px_gfx_switch;
137297b2e202SAlex Deucher 	bool brightness_change;
137397b2e202SAlex Deucher 	bool dgpu_display_event;
137497b2e202SAlex Deucher };
137597b2e202SAlex Deucher 
137697b2e202SAlex Deucher struct amdgpu_atif_functions {
137797b2e202SAlex Deucher 	bool system_params;
137897b2e202SAlex Deucher 	bool sbios_requests;
137997b2e202SAlex Deucher 	bool select_active_disp;
138097b2e202SAlex Deucher 	bool lid_state;
138197b2e202SAlex Deucher 	bool get_tv_standard;
138297b2e202SAlex Deucher 	bool set_tv_standard;
138397b2e202SAlex Deucher 	bool get_panel_expansion_mode;
138497b2e202SAlex Deucher 	bool set_panel_expansion_mode;
138597b2e202SAlex Deucher 	bool temperature_change;
138697b2e202SAlex Deucher 	bool graphics_device_types;
138797b2e202SAlex Deucher };
138897b2e202SAlex Deucher 
138997b2e202SAlex Deucher struct amdgpu_atif {
139097b2e202SAlex Deucher 	struct amdgpu_atif_notifications notifications;
139197b2e202SAlex Deucher 	struct amdgpu_atif_functions functions;
139297b2e202SAlex Deucher 	struct amdgpu_atif_notification_cfg notification_cfg;
139397b2e202SAlex Deucher 	struct amdgpu_encoder *encoder_for_bl;
139497b2e202SAlex Deucher };
139597b2e202SAlex Deucher 
139697b2e202SAlex Deucher struct amdgpu_atcs_functions {
139797b2e202SAlex Deucher 	bool get_ext_state;
139897b2e202SAlex Deucher 	bool pcie_perf_req;
139997b2e202SAlex Deucher 	bool pcie_dev_rdy;
140097b2e202SAlex Deucher 	bool pcie_bus_width;
140197b2e202SAlex Deucher };
140297b2e202SAlex Deucher 
140397b2e202SAlex Deucher struct amdgpu_atcs {
140497b2e202SAlex Deucher 	struct amdgpu_atcs_functions functions;
140597b2e202SAlex Deucher };
140697b2e202SAlex Deucher 
140797b2e202SAlex Deucher /*
1408d03846afSChunming Zhou  * CGS
1409d03846afSChunming Zhou  */
1410110e6f26SDave Airlie struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1411110e6f26SDave Airlie void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
1412a8fe58ceSMaruthi Bayyavarapu 
1413a8fe58ceSMaruthi Bayyavarapu /*
141497b2e202SAlex Deucher  * Core structure, functions and helpers.
141597b2e202SAlex Deucher  */
141697b2e202SAlex Deucher typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
141797b2e202SAlex Deucher typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
141897b2e202SAlex Deucher 
141997b2e202SAlex Deucher typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
142097b2e202SAlex Deucher typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
142197b2e202SAlex Deucher 
142297b2e202SAlex Deucher struct amdgpu_device {
142397b2e202SAlex Deucher 	struct device			*dev;
142497b2e202SAlex Deucher 	struct drm_device		*ddev;
142597b2e202SAlex Deucher 	struct pci_dev			*pdev;
142697b2e202SAlex Deucher 
1427a8fe58ceSMaruthi Bayyavarapu #ifdef CONFIG_DRM_AMD_ACP
1428a8fe58ceSMaruthi Bayyavarapu 	struct amdgpu_acp		acp;
1429a8fe58ceSMaruthi Bayyavarapu #endif
1430a8fe58ceSMaruthi Bayyavarapu 
143197b2e202SAlex Deucher 	/* ASIC */
14322f7d10b3SJammy Zhou 	enum amd_asic_type		asic_type;
143397b2e202SAlex Deucher 	uint32_t			family;
143497b2e202SAlex Deucher 	uint32_t			rev_id;
143597b2e202SAlex Deucher 	uint32_t			external_rev_id;
143697b2e202SAlex Deucher 	unsigned long			flags;
143797b2e202SAlex Deucher 	int				usec_timeout;
143897b2e202SAlex Deucher 	const struct amdgpu_asic_funcs	*asic_funcs;
143997b2e202SAlex Deucher 	bool				shutdown;
144097b2e202SAlex Deucher 	bool				need_dma32;
144197b2e202SAlex Deucher 	bool				accel_working;
144297b2e202SAlex Deucher 	struct work_struct		reset_work;
144397b2e202SAlex Deucher 	struct notifier_block		acpi_nb;
144497b2e202SAlex Deucher 	struct amdgpu_i2c_chan		*i2c_bus[AMDGPU_MAX_I2C_BUS];
144597b2e202SAlex Deucher 	struct amdgpu_debugfs		debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
144697b2e202SAlex Deucher 	unsigned			debugfs_count;
144797b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS)
1448adcec288STom St Denis 	struct dentry			*debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
144997b2e202SAlex Deucher #endif
145097b2e202SAlex Deucher 	struct amdgpu_atif		atif;
145197b2e202SAlex Deucher 	struct amdgpu_atcs		atcs;
145297b2e202SAlex Deucher 	struct mutex			srbm_mutex;
145397b2e202SAlex Deucher 	/* GRBM index mutex. Protects concurrent access to GRBM index */
145497b2e202SAlex Deucher 	struct mutex                    grbm_idx_mutex;
145597b2e202SAlex Deucher 	struct dev_pm_domain		vga_pm_domain;
145697b2e202SAlex Deucher 	bool				have_disp_power_ref;
145797b2e202SAlex Deucher 
145897b2e202SAlex Deucher 	/* BIOS */
14590cdd5005SAlex Deucher 	bool				is_atom_fw;
146097b2e202SAlex Deucher 	uint8_t				*bios;
1461a9f5db9cSEvan Quan 	uint32_t			bios_size;
146297b2e202SAlex Deucher 	struct amdgpu_bo		*stollen_vga_memory;
1463a5bde2f9SAlex Deucher 	uint32_t			bios_scratch_reg_offset;
146497b2e202SAlex Deucher 	uint32_t			bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
146597b2e202SAlex Deucher 
146697b2e202SAlex Deucher 	/* Register/doorbell mmio */
146797b2e202SAlex Deucher 	resource_size_t			rmmio_base;
146897b2e202SAlex Deucher 	resource_size_t			rmmio_size;
146997b2e202SAlex Deucher 	void __iomem			*rmmio;
147097b2e202SAlex Deucher 	/* protects concurrent MM_INDEX/DATA based register access */
147197b2e202SAlex Deucher 	spinlock_t mmio_idx_lock;
147297b2e202SAlex Deucher 	/* protects concurrent SMC based register access */
147397b2e202SAlex Deucher 	spinlock_t smc_idx_lock;
147497b2e202SAlex Deucher 	amdgpu_rreg_t			smc_rreg;
147597b2e202SAlex Deucher 	amdgpu_wreg_t			smc_wreg;
147697b2e202SAlex Deucher 	/* protects concurrent PCIE register access */
147797b2e202SAlex Deucher 	spinlock_t pcie_idx_lock;
147897b2e202SAlex Deucher 	amdgpu_rreg_t			pcie_rreg;
147997b2e202SAlex Deucher 	amdgpu_wreg_t			pcie_wreg;
148036b9a952SHuang Rui 	amdgpu_rreg_t			pciep_rreg;
148136b9a952SHuang Rui 	amdgpu_wreg_t			pciep_wreg;
148297b2e202SAlex Deucher 	/* protects concurrent UVD register access */
148397b2e202SAlex Deucher 	spinlock_t uvd_ctx_idx_lock;
148497b2e202SAlex Deucher 	amdgpu_rreg_t			uvd_ctx_rreg;
148597b2e202SAlex Deucher 	amdgpu_wreg_t			uvd_ctx_wreg;
148697b2e202SAlex Deucher 	/* protects concurrent DIDT register access */
148797b2e202SAlex Deucher 	spinlock_t didt_idx_lock;
148897b2e202SAlex Deucher 	amdgpu_rreg_t			didt_rreg;
148997b2e202SAlex Deucher 	amdgpu_wreg_t			didt_wreg;
1490ccdbb20aSRex Zhu 	/* protects concurrent gc_cac register access */
1491ccdbb20aSRex Zhu 	spinlock_t gc_cac_idx_lock;
1492ccdbb20aSRex Zhu 	amdgpu_rreg_t			gc_cac_rreg;
1493ccdbb20aSRex Zhu 	amdgpu_wreg_t			gc_cac_wreg;
149497b2e202SAlex Deucher 	/* protects concurrent ENDPOINT (audio) register access */
149597b2e202SAlex Deucher 	spinlock_t audio_endpt_idx_lock;
149697b2e202SAlex Deucher 	amdgpu_block_rreg_t		audio_endpt_rreg;
149797b2e202SAlex Deucher 	amdgpu_block_wreg_t		audio_endpt_wreg;
149897b2e202SAlex Deucher 	void __iomem                    *rio_mem;
149997b2e202SAlex Deucher 	resource_size_t			rio_mem_size;
150097b2e202SAlex Deucher 	struct amdgpu_doorbell		doorbell;
150197b2e202SAlex Deucher 
150297b2e202SAlex Deucher 	/* clock/pll info */
150397b2e202SAlex Deucher 	struct amdgpu_clock            clock;
150497b2e202SAlex Deucher 
150597b2e202SAlex Deucher 	/* MC */
150697b2e202SAlex Deucher 	struct amdgpu_mc		mc;
150797b2e202SAlex Deucher 	struct amdgpu_gart		gart;
150897b2e202SAlex Deucher 	struct amdgpu_dummy_page	dummy_page;
150997b2e202SAlex Deucher 	struct amdgpu_vm_manager	vm_manager;
1510e60f8db5SAlex Xie 	struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];
151197b2e202SAlex Deucher 
151297b2e202SAlex Deucher 	/* memory management */
151397b2e202SAlex Deucher 	struct amdgpu_mman		mman;
151497b2e202SAlex Deucher 	struct amdgpu_vram_scratch	vram_scratch;
151597b2e202SAlex Deucher 	struct amdgpu_wb		wb;
151697b2e202SAlex Deucher 	atomic64_t			vram_usage;
151797b2e202SAlex Deucher 	atomic64_t			vram_vis_usage;
151897b2e202SAlex Deucher 	atomic64_t			gtt_usage;
151997b2e202SAlex Deucher 	atomic64_t			num_bytes_moved;
1520dbd5ed60SChristian König 	atomic64_t			num_evictions;
1521d94aed5aSMarek Olšák 	atomic_t			gpu_reset_counter;
152297b2e202SAlex Deucher 
152395844d20SMarek Olšák 	/* data for buffer migration throttling */
152495844d20SMarek Olšák 	struct {
152595844d20SMarek Olšák 		spinlock_t		lock;
152695844d20SMarek Olšák 		s64			last_update_us;
152795844d20SMarek Olšák 		s64			accum_us; /* accumulated microseconds */
152895844d20SMarek Olšák 		u32			log2_max_MBps;
152995844d20SMarek Olšák 	} mm_stats;
153095844d20SMarek Olšák 
153197b2e202SAlex Deucher 	/* display */
15329accf2fdSEmily Deng 	bool				enable_virtual_display;
153397b2e202SAlex Deucher 	struct amdgpu_mode_info		mode_info;
153497b2e202SAlex Deucher 	struct work_struct		hotplug_work;
153597b2e202SAlex Deucher 	struct amdgpu_irq_src		crtc_irq;
153697b2e202SAlex Deucher 	struct amdgpu_irq_src		pageflip_irq;
153797b2e202SAlex Deucher 	struct amdgpu_irq_src		hpd_irq;
153897b2e202SAlex Deucher 
153997b2e202SAlex Deucher 	/* rings */
154076bf0db5SChristian König 	u64				fence_context;
154197b2e202SAlex Deucher 	unsigned			num_rings;
154297b2e202SAlex Deucher 	struct amdgpu_ring		*rings[AMDGPU_MAX_RINGS];
154397b2e202SAlex Deucher 	bool				ib_pool_ready;
154497b2e202SAlex Deucher 	struct amdgpu_sa_manager	ring_tmp_bo;
154597b2e202SAlex Deucher 
154697b2e202SAlex Deucher 	/* interrupts */
154797b2e202SAlex Deucher 	struct amdgpu_irq		irq;
154897b2e202SAlex Deucher 
15491f7371b2SAlex Deucher 	/* powerplay */
15501f7371b2SAlex Deucher 	struct amd_powerplay		powerplay;
1551e61710c5SJammy Zhou 	bool				pp_enabled;
1552f3898ea1SEric Huang 	bool				pp_force_state_enabled;
15531f7371b2SAlex Deucher 
155497b2e202SAlex Deucher 	/* dpm */
155597b2e202SAlex Deucher 	struct amdgpu_pm		pm;
155697b2e202SAlex Deucher 	u32				cg_flags;
155797b2e202SAlex Deucher 	u32				pg_flags;
155897b2e202SAlex Deucher 
155997b2e202SAlex Deucher 	/* amdgpu smumgr */
156097b2e202SAlex Deucher 	struct amdgpu_smumgr smu;
156197b2e202SAlex Deucher 
156297b2e202SAlex Deucher 	/* gfx */
156397b2e202SAlex Deucher 	struct amdgpu_gfx		gfx;
156497b2e202SAlex Deucher 
156597b2e202SAlex Deucher 	/* sdma */
1566c113ea1cSAlex Deucher 	struct amdgpu_sdma		sdma;
156797b2e202SAlex Deucher 
156897b2e202SAlex Deucher 	/* uvd */
156997b2e202SAlex Deucher 	struct amdgpu_uvd		uvd;
157097b2e202SAlex Deucher 
157197b2e202SAlex Deucher 	/* vce */
157297b2e202SAlex Deucher 	struct amdgpu_vce		vce;
157397b2e202SAlex Deucher 
157497b2e202SAlex Deucher 	/* firmwares */
157597b2e202SAlex Deucher 	struct amdgpu_firmware		firmware;
157697b2e202SAlex Deucher 
15770e5ca0d1SHuang Rui 	/* PSP */
15780e5ca0d1SHuang Rui 	struct psp_context		psp;
15790e5ca0d1SHuang Rui 
158097b2e202SAlex Deucher 	/* GDS */
158197b2e202SAlex Deucher 	struct amdgpu_gds		gds;
158297b2e202SAlex Deucher 
1583a1255107SAlex Deucher 	struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];
158497b2e202SAlex Deucher 	int				num_ip_blocks;
158597b2e202SAlex Deucher 	struct mutex	mn_lock;
158697b2e202SAlex Deucher 	DECLARE_HASHTABLE(mn_hash, 7);
158797b2e202SAlex Deucher 
158897b2e202SAlex Deucher 	/* tracking pinned memory */
158997b2e202SAlex Deucher 	u64 vram_pin_size;
1590e131b914SChunming Zhou 	u64 invisible_pin_size;
159197b2e202SAlex Deucher 	u64 gart_pin_size;
1592130e0371SOded Gabbay 
1593130e0371SOded Gabbay 	/* amdkfd interface */
1594130e0371SOded Gabbay 	struct kfd_dev          *kfd;
159523ca0e4eSChunming Zhou 
15965a5099cbSXiangliang Yu 	struct amdgpu_virt	virt;
15970c4e7fa5SChunming Zhou 
15980c4e7fa5SChunming Zhou 	/* link all shadow bo */
15990c4e7fa5SChunming Zhou 	struct list_head                shadow_list;
16000c4e7fa5SChunming Zhou 	struct mutex                    shadow_list_lock;
16015c1354bdSChunming Zhou 	/* link all gtt */
16025c1354bdSChunming Zhou 	spinlock_t			gtt_list_lock;
16035c1354bdSChunming Zhou 	struct list_head                gtt_list;
16045c1354bdSChunming Zhou 
1605c836fec5SJim Qu 	/* record hw reset is performed */
1606c836fec5SJim Qu 	bool has_hw_reset;
1607c836fec5SJim Qu 
160897b2e202SAlex Deucher };
160997b2e202SAlex Deucher 
1610a7d64de6SChristian König static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1611a7d64de6SChristian König {
1612a7d64de6SChristian König 	return container_of(bdev, struct amdgpu_device, mman.bdev);
1613a7d64de6SChristian König }
1614a7d64de6SChristian König 
161597b2e202SAlex Deucher bool amdgpu_device_is_px(struct drm_device *dev);
161697b2e202SAlex Deucher int amdgpu_device_init(struct amdgpu_device *adev,
161797b2e202SAlex Deucher 		       struct drm_device *ddev,
161897b2e202SAlex Deucher 		       struct pci_dev *pdev,
161997b2e202SAlex Deucher 		       uint32_t flags);
162097b2e202SAlex Deucher void amdgpu_device_fini(struct amdgpu_device *adev);
162197b2e202SAlex Deucher int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
162297b2e202SAlex Deucher 
162397b2e202SAlex Deucher uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
162415d72fd7SMonk Liu 			uint32_t acc_flags);
162597b2e202SAlex Deucher void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
162615d72fd7SMonk Liu 		    uint32_t acc_flags);
162797b2e202SAlex Deucher u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
162897b2e202SAlex Deucher void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
162997b2e202SAlex Deucher 
163097b2e202SAlex Deucher u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
163197b2e202SAlex Deucher void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
1632832be404SKen Wang u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1633832be404SKen Wang void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
163497b2e202SAlex Deucher 
163597b2e202SAlex Deucher /*
163697b2e202SAlex Deucher  * Registers read & write functions.
163797b2e202SAlex Deucher  */
163815d72fd7SMonk Liu 
163915d72fd7SMonk Liu #define AMDGPU_REGS_IDX       (1<<0)
164015d72fd7SMonk Liu #define AMDGPU_REGS_NO_KIQ    (1<<1)
164115d72fd7SMonk Liu 
164215d72fd7SMonk Liu #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
164315d72fd7SMonk Liu #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
164415d72fd7SMonk Liu 
164515d72fd7SMonk Liu #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
164615d72fd7SMonk Liu #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
164715d72fd7SMonk Liu #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
164815d72fd7SMonk Liu #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
164915d72fd7SMonk Liu #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
165097b2e202SAlex Deucher #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
165197b2e202SAlex Deucher #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
165297b2e202SAlex Deucher #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
165397b2e202SAlex Deucher #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
165436b9a952SHuang Rui #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
165536b9a952SHuang Rui #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
165697b2e202SAlex Deucher #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
165797b2e202SAlex Deucher #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
165897b2e202SAlex Deucher #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
165997b2e202SAlex Deucher #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
166097b2e202SAlex Deucher #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
166197b2e202SAlex Deucher #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1662ccdbb20aSRex Zhu #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1663ccdbb20aSRex Zhu #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
166497b2e202SAlex Deucher #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
166597b2e202SAlex Deucher #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
166697b2e202SAlex Deucher #define WREG32_P(reg, val, mask)				\
166797b2e202SAlex Deucher 	do {							\
166897b2e202SAlex Deucher 		uint32_t tmp_ = RREG32(reg);			\
166997b2e202SAlex Deucher 		tmp_ &= (mask);					\
167097b2e202SAlex Deucher 		tmp_ |= ((val) & ~(mask));			\
167197b2e202SAlex Deucher 		WREG32(reg, tmp_);				\
167297b2e202SAlex Deucher 	} while (0)
167397b2e202SAlex Deucher #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
167497b2e202SAlex Deucher #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
167597b2e202SAlex Deucher #define WREG32_PLL_P(reg, val, mask)				\
167697b2e202SAlex Deucher 	do {							\
167797b2e202SAlex Deucher 		uint32_t tmp_ = RREG32_PLL(reg);		\
167897b2e202SAlex Deucher 		tmp_ &= (mask);					\
167997b2e202SAlex Deucher 		tmp_ |= ((val) & ~(mask));			\
168097b2e202SAlex Deucher 		WREG32_PLL(reg, tmp_);				\
168197b2e202SAlex Deucher 	} while (0)
168297b2e202SAlex Deucher #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
168397b2e202SAlex Deucher #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
168497b2e202SAlex Deucher #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
168597b2e202SAlex Deucher 
168697b2e202SAlex Deucher #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
168797b2e202SAlex Deucher #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
1688832be404SKen Wang #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1689832be404SKen Wang #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
169097b2e202SAlex Deucher 
169197b2e202SAlex Deucher #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
169297b2e202SAlex Deucher #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
169397b2e202SAlex Deucher 
169497b2e202SAlex Deucher #define REG_SET_FIELD(orig_val, reg, field, field_val)			\
169597b2e202SAlex Deucher 	(((orig_val) & ~REG_FIELD_MASK(reg, field)) |			\
169697b2e202SAlex Deucher 	 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
169797b2e202SAlex Deucher 
169897b2e202SAlex Deucher #define REG_GET_FIELD(value, reg, field)				\
169997b2e202SAlex Deucher 	(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
170097b2e202SAlex Deucher 
170161cb8cefSTom St Denis #define WREG32_FIELD(reg, field, val)	\
170261cb8cefSTom St Denis 	WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
170361cb8cefSTom St Denis 
1704ccaf3574STom St Denis #define WREG32_FIELD_OFFSET(reg, offset, field, val)	\
1705ccaf3574STom St Denis 	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1706ccaf3574STom St Denis 
170797b2e202SAlex Deucher /*
170897b2e202SAlex Deucher  * BIOS helpers.
170997b2e202SAlex Deucher  */
171097b2e202SAlex Deucher #define RBIOS8(i) (adev->bios[i])
171197b2e202SAlex Deucher #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
171297b2e202SAlex Deucher #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
171397b2e202SAlex Deucher 
171497b2e202SAlex Deucher /*
171597b2e202SAlex Deucher  * RING helpers.
171697b2e202SAlex Deucher  */
171797b2e202SAlex Deucher static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
171897b2e202SAlex Deucher {
171997b2e202SAlex Deucher 	if (ring->count_dw <= 0)
172086c2b790SJammy Zhou 		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
1721536fbf94SKen Wang 	ring->ring[ring->wptr++ & ring->buf_mask] = v;
172297b2e202SAlex Deucher 	ring->wptr &= ring->ptr_mask;
172397b2e202SAlex Deucher 	ring->count_dw--;
172497b2e202SAlex Deucher }
172597b2e202SAlex Deucher 
17260a8e1473SMonk Liu static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw)
17270a8e1473SMonk Liu {
17280a8e1473SMonk Liu 	unsigned occupied, chunk1, chunk2;
17290a8e1473SMonk Liu 	void *dst;
17300a8e1473SMonk Liu 
17310a8e1473SMonk Liu 	if (ring->count_dw < count_dw) {
17320a8e1473SMonk Liu 		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
17330a8e1473SMonk Liu 	} else {
17345846e355SMonk Liu 		occupied = ring->wptr & ring->buf_mask;
17350a8e1473SMonk Liu 		dst = (void *)&ring->ring[occupied];
17365846e355SMonk Liu 		chunk1 = ring->buf_mask + 1 - occupied;
17370a8e1473SMonk Liu 		chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
17380a8e1473SMonk Liu 		chunk2 = count_dw - chunk1;
17390a8e1473SMonk Liu 		chunk1 <<= 2;
17400a8e1473SMonk Liu 		chunk2 <<= 2;
17410a8e1473SMonk Liu 
17420a8e1473SMonk Liu 		if (chunk1)
17430a8e1473SMonk Liu 			memcpy(dst, src, chunk1);
17440a8e1473SMonk Liu 
17450a8e1473SMonk Liu 		if (chunk2) {
17460a8e1473SMonk Liu 			src += chunk1;
17470a8e1473SMonk Liu 			dst = (void *)ring->ring;
17480a8e1473SMonk Liu 			memcpy(dst, src, chunk2);
17490a8e1473SMonk Liu 		}
17500a8e1473SMonk Liu 
17510a8e1473SMonk Liu 		ring->wptr += count_dw;
17520a8e1473SMonk Liu 		ring->wptr &= ring->ptr_mask;
17530a8e1473SMonk Liu 		ring->count_dw -= count_dw;
17540a8e1473SMonk Liu 	}
17550a8e1473SMonk Liu }
17560a8e1473SMonk Liu 
1757c113ea1cSAlex Deucher static inline struct amdgpu_sdma_instance *
1758c113ea1cSAlex Deucher amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
17594b2f7e2cSJammy Zhou {
17604b2f7e2cSJammy Zhou 	struct amdgpu_device *adev = ring->adev;
17614b2f7e2cSJammy Zhou 	int i;
17624b2f7e2cSJammy Zhou 
1763c113ea1cSAlex Deucher 	for (i = 0; i < adev->sdma.num_instances; i++)
1764c113ea1cSAlex Deucher 		if (&adev->sdma.instance[i].ring == ring)
17654b2f7e2cSJammy Zhou 			break;
17664b2f7e2cSJammy Zhou 
17674b2f7e2cSJammy Zhou 	if (i < AMDGPU_MAX_SDMA_INSTANCES)
1768c113ea1cSAlex Deucher 		return &adev->sdma.instance[i];
17694b2f7e2cSJammy Zhou 	else
17704b2f7e2cSJammy Zhou 		return NULL;
17714b2f7e2cSJammy Zhou }
17724b2f7e2cSJammy Zhou 
177397b2e202SAlex Deucher /*
177497b2e202SAlex Deucher  * ASICs macro.
177597b2e202SAlex Deucher  */
177697b2e202SAlex Deucher #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
177797b2e202SAlex Deucher #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
177897b2e202SAlex Deucher #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
177997b2e202SAlex Deucher #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
178097b2e202SAlex Deucher #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1781841686dfSMaruthi Bayyavarapu #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1782841686dfSMaruthi Bayyavarapu #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1783841686dfSMaruthi Bayyavarapu #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
178497b2e202SAlex Deucher #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
17857946b878SAlex Deucher #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
178697b2e202SAlex Deucher #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1787bbf282d8SAlex Deucher #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
178897b2e202SAlex Deucher #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
178997b2e202SAlex Deucher #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
179097b2e202SAlex Deucher #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
1791de9ea7bdSChristian König #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
179297b2e202SAlex Deucher #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
17935463545bSAlex Xie #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
179497b2e202SAlex Deucher #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
179597b2e202SAlex Deucher #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
1796bbec97aaSChristian König #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
179797b2e202SAlex Deucher #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
179897b2e202SAlex Deucher #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
179997b2e202SAlex Deucher #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
1800d88bf583SChristian König #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
1801b8c7b39eSChristian König #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
180297b2e202SAlex Deucher #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
1803890ee23fSChunming Zhou #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
180497b2e202SAlex Deucher #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
1805d2edb07bSChristian König #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
180611afbde8SChunming Zhou #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
1807c2167a65SMonk Liu #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
1808753ad49cSMonk Liu #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
1809b6091c12SXiangliang Yu #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1810b6091c12SXiangliang Yu #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
18119e5d5309SChristian König #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
181203ccf481SMonk Liu #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
181303ccf481SMonk Liu #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
181497b2e202SAlex Deucher #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
181597b2e202SAlex Deucher #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
181697b2e202SAlex Deucher #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
181797b2e202SAlex Deucher #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
181897b2e202SAlex Deucher #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
181997b2e202SAlex Deucher #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
182097b2e202SAlex Deucher #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
182197b2e202SAlex Deucher #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
182297b2e202SAlex Deucher #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
182397b2e202SAlex Deucher #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
182497b2e202SAlex Deucher #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
182597b2e202SAlex Deucher #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
1826cb9e59d7SAlex Deucher #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
182797b2e202SAlex Deucher #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
182897b2e202SAlex Deucher #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
182997b2e202SAlex Deucher #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
183097b2e202SAlex Deucher #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
183197b2e202SAlex Deucher #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
1832c7ae72c0SChunming Zhou #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b))
18336e7a3840SChunming Zhou #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
1834b95e31fdSAlex Deucher #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
18359559ef5bSTom St Denis #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
183697b2e202SAlex Deucher #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
18370e5ca0d1SHuang Rui #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
183897b2e202SAlex Deucher 
183997b2e202SAlex Deucher /* Common functions */
184097b2e202SAlex Deucher int amdgpu_gpu_reset(struct amdgpu_device *adev);
18413ad81f16SChunming Zhou bool amdgpu_need_backup(struct amdgpu_device *adev);
184297b2e202SAlex Deucher void amdgpu_pci_config_reset(struct amdgpu_device *adev);
1843c836fec5SJim Qu bool amdgpu_need_post(struct amdgpu_device *adev);
184497b2e202SAlex Deucher void amdgpu_update_display_priority(struct amdgpu_device *adev);
1845d5fc5e82SChunming Zhou 
184697b2e202SAlex Deucher int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
184797b2e202SAlex Deucher int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
184897b2e202SAlex Deucher 		       u32 ip_instance, u32 ring,
184997b2e202SAlex Deucher 		       struct amdgpu_ring **out_ring);
1850fad06127SSamuel Pitoiset void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes);
1851765e7fbfSChristian König void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
185297b2e202SAlex Deucher bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
18532f568dbdSChristian König int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
185497b2e202SAlex Deucher int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
185597b2e202SAlex Deucher 				     uint32_t flags);
185697b2e202SAlex Deucher bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
1857cc325d19SChristian König struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
1858d7006964SChristian König bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1859d7006964SChristian König 				  unsigned long end);
18602f568dbdSChristian König bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
18612f568dbdSChristian König 				       int *last_invalidated);
186297b2e202SAlex Deucher bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
18636b777607SChunming Zhou uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
186497b2e202SAlex Deucher 				 struct ttm_mem_reg *mem);
186597b2e202SAlex Deucher void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
186697b2e202SAlex Deucher void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
186797b2e202SAlex Deucher void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
18689f31a0b0SBaoyou Xie int amdgpu_ttm_init(struct amdgpu_device *adev);
18699f31a0b0SBaoyou Xie void amdgpu_ttm_fini(struct amdgpu_device *adev);
187097b2e202SAlex Deucher void amdgpu_program_register_sequence(struct amdgpu_device *adev,
187197b2e202SAlex Deucher 					     const u32 *registers,
187297b2e202SAlex Deucher 					     const u32 array_size);
187397b2e202SAlex Deucher 
187497b2e202SAlex Deucher bool amdgpu_device_is_px(struct drm_device *dev);
187597b2e202SAlex Deucher /* atpx handler */
187697b2e202SAlex Deucher #if defined(CONFIG_VGA_SWITCHEROO)
187797b2e202SAlex Deucher void amdgpu_register_atpx_handler(void);
187897b2e202SAlex Deucher void amdgpu_unregister_atpx_handler(void);
1879a78fe133SAlex Deucher bool amdgpu_has_atpx_dgpu_power_cntl(void);
18802f5af82eSAlex Deucher bool amdgpu_is_atpx_hybrid(void);
1881efc83cf4SAlex Deucher bool amdgpu_atpx_dgpu_req_power_for_displays(void);
188297b2e202SAlex Deucher #else
188397b2e202SAlex Deucher static inline void amdgpu_register_atpx_handler(void) {}
188497b2e202SAlex Deucher static inline void amdgpu_unregister_atpx_handler(void) {}
1885a78fe133SAlex Deucher static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
18862f5af82eSAlex Deucher static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1887efc83cf4SAlex Deucher static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
188897b2e202SAlex Deucher #endif
188997b2e202SAlex Deucher 
189097b2e202SAlex Deucher /*
189197b2e202SAlex Deucher  * KMS
189297b2e202SAlex Deucher  */
189397b2e202SAlex Deucher extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1894f498d9edSNils Wallménius extern const int amdgpu_max_kms_ioctl;
189597b2e202SAlex Deucher 
189697b2e202SAlex Deucher int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
189711b3c20bSGabriel Krisman Bertazi void amdgpu_driver_unload_kms(struct drm_device *dev);
189897b2e202SAlex Deucher void amdgpu_driver_lastclose_kms(struct drm_device *dev);
189997b2e202SAlex Deucher int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
190097b2e202SAlex Deucher void amdgpu_driver_postclose_kms(struct drm_device *dev,
190197b2e202SAlex Deucher 				 struct drm_file *file_priv);
1902faefba95SAlex Deucher int amdgpu_suspend(struct amdgpu_device *adev);
1903810ddc3aSAlex Deucher int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1904810ddc3aSAlex Deucher int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
190588e72717SThierry Reding u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
190688e72717SThierry Reding int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
190788e72717SThierry Reding void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
190888e72717SThierry Reding int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
190997b2e202SAlex Deucher 				    int *max_error,
191097b2e202SAlex Deucher 				    struct timeval *vblank_time,
191197b2e202SAlex Deucher 				    unsigned flags);
191297b2e202SAlex Deucher long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
191397b2e202SAlex Deucher 			     unsigned long arg);
191497b2e202SAlex Deucher 
191597b2e202SAlex Deucher /*
191697b2e202SAlex Deucher  * functions used by amdgpu_encoder.c
191797b2e202SAlex Deucher  */
191897b2e202SAlex Deucher struct amdgpu_afmt_acr {
191997b2e202SAlex Deucher 	u32 clock;
192097b2e202SAlex Deucher 
192197b2e202SAlex Deucher 	int n_32khz;
192297b2e202SAlex Deucher 	int cts_32khz;
192397b2e202SAlex Deucher 
192497b2e202SAlex Deucher 	int n_44_1khz;
192597b2e202SAlex Deucher 	int cts_44_1khz;
192697b2e202SAlex Deucher 
192797b2e202SAlex Deucher 	int n_48khz;
192897b2e202SAlex Deucher 	int cts_48khz;
192997b2e202SAlex Deucher 
193097b2e202SAlex Deucher };
193197b2e202SAlex Deucher 
193297b2e202SAlex Deucher struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
193397b2e202SAlex Deucher 
193497b2e202SAlex Deucher /* amdgpu_acpi.c */
193597b2e202SAlex Deucher #if defined(CONFIG_ACPI)
193697b2e202SAlex Deucher int amdgpu_acpi_init(struct amdgpu_device *adev);
193797b2e202SAlex Deucher void amdgpu_acpi_fini(struct amdgpu_device *adev);
193897b2e202SAlex Deucher bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
193997b2e202SAlex Deucher int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
194097b2e202SAlex Deucher 						u8 perf_req, bool advertise);
194197b2e202SAlex Deucher int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
194297b2e202SAlex Deucher #else
194397b2e202SAlex Deucher static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
194497b2e202SAlex Deucher static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
194597b2e202SAlex Deucher #endif
194697b2e202SAlex Deucher 
194797b2e202SAlex Deucher struct amdgpu_bo_va_mapping *
194897b2e202SAlex Deucher amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
194997b2e202SAlex Deucher 		       uint64_t addr, struct amdgpu_bo **bo);
1950c855e250SChristian König int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
195197b2e202SAlex Deucher 
195297b2e202SAlex Deucher #include "amdgpu_object.h"
195397b2e202SAlex Deucher #endif
1954