197b2e202SAlex Deucher /* 297b2e202SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 397b2e202SAlex Deucher * Copyright 2008 Red Hat Inc. 497b2e202SAlex Deucher * Copyright 2009 Jerome Glisse. 597b2e202SAlex Deucher * 697b2e202SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 797b2e202SAlex Deucher * copy of this software and associated documentation files (the "Software"), 897b2e202SAlex Deucher * to deal in the Software without restriction, including without limitation 997b2e202SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1097b2e202SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1197b2e202SAlex Deucher * Software is furnished to do so, subject to the following conditions: 1297b2e202SAlex Deucher * 1397b2e202SAlex Deucher * The above copyright notice and this permission notice shall be included in 1497b2e202SAlex Deucher * all copies or substantial portions of the Software. 1597b2e202SAlex Deucher * 1697b2e202SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1797b2e202SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1897b2e202SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1997b2e202SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2097b2e202SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2197b2e202SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2297b2e202SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2397b2e202SAlex Deucher * 2497b2e202SAlex Deucher * Authors: Dave Airlie 2597b2e202SAlex Deucher * Alex Deucher 2697b2e202SAlex Deucher * Jerome Glisse 2797b2e202SAlex Deucher */ 2897b2e202SAlex Deucher #ifndef __AMDGPU_H__ 2997b2e202SAlex Deucher #define __AMDGPU_H__ 3097b2e202SAlex Deucher 3197b2e202SAlex Deucher #include <linux/atomic.h> 3297b2e202SAlex Deucher #include <linux/wait.h> 3397b2e202SAlex Deucher #include <linux/list.h> 3497b2e202SAlex Deucher #include <linux/kref.h> 3597b2e202SAlex Deucher #include <linux/interval_tree.h> 3697b2e202SAlex Deucher #include <linux/hashtable.h> 3797b2e202SAlex Deucher #include <linux/fence.h> 3897b2e202SAlex Deucher 3997b2e202SAlex Deucher #include <ttm/ttm_bo_api.h> 4097b2e202SAlex Deucher #include <ttm/ttm_bo_driver.h> 4197b2e202SAlex Deucher #include <ttm/ttm_placement.h> 4297b2e202SAlex Deucher #include <ttm/ttm_module.h> 4397b2e202SAlex Deucher #include <ttm/ttm_execbuf_util.h> 4497b2e202SAlex Deucher 45d03846afSChunming Zhou #include <drm/drmP.h> 4697b2e202SAlex Deucher #include <drm/drm_gem.h> 477e5a547fSChunming Zhou #include <drm/amdgpu_drm.h> 4897b2e202SAlex Deucher 495fc3aeebSyanyang1 #include "amd_shared.h" 5097b2e202SAlex Deucher #include "amdgpu_mode.h" 5197b2e202SAlex Deucher #include "amdgpu_ih.h" 5297b2e202SAlex Deucher #include "amdgpu_irq.h" 5397b2e202SAlex Deucher #include "amdgpu_ucode.h" 54c632d799SFlora Cui #include "amdgpu_ttm.h" 5597b2e202SAlex Deucher #include "amdgpu_gds.h" 561f7371b2SAlex Deucher #include "amd_powerplay.h" 57a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h" 5897b2e202SAlex Deucher 59b80d8475SAlex Deucher #include "gpu_scheduler.h" 60b80d8475SAlex Deucher 6197b2e202SAlex Deucher /* 6297b2e202SAlex Deucher * Modules parameters. 6397b2e202SAlex Deucher */ 6497b2e202SAlex Deucher extern int amdgpu_modeset; 6597b2e202SAlex Deucher extern int amdgpu_vram_limit; 6697b2e202SAlex Deucher extern int amdgpu_gart_size; 6795844d20SMarek Olšák extern int amdgpu_moverate; 6897b2e202SAlex Deucher extern int amdgpu_benchmarking; 6997b2e202SAlex Deucher extern int amdgpu_testing; 7097b2e202SAlex Deucher extern int amdgpu_audio; 7197b2e202SAlex Deucher extern int amdgpu_disp_priority; 7297b2e202SAlex Deucher extern int amdgpu_hw_i2c; 7397b2e202SAlex Deucher extern int amdgpu_pcie_gen2; 7497b2e202SAlex Deucher extern int amdgpu_msi; 7597b2e202SAlex Deucher extern int amdgpu_lockup_timeout; 7697b2e202SAlex Deucher extern int amdgpu_dpm; 7797b2e202SAlex Deucher extern int amdgpu_smc_load_fw; 7897b2e202SAlex Deucher extern int amdgpu_aspm; 7997b2e202SAlex Deucher extern int amdgpu_runtime_pm; 8097b2e202SAlex Deucher extern unsigned amdgpu_ip_block_mask; 8197b2e202SAlex Deucher extern int amdgpu_bapm; 8297b2e202SAlex Deucher extern int amdgpu_deep_color; 8397b2e202SAlex Deucher extern int amdgpu_vm_size; 8497b2e202SAlex Deucher extern int amdgpu_vm_block_size; 85d9c13156SChristian König extern int amdgpu_vm_fault_stop; 86b495bd3aSChristian König extern int amdgpu_vm_debug; 871333f723SJammy Zhou extern int amdgpu_sched_jobs; 884afcb303SJammy Zhou extern int amdgpu_sched_hw_submission; 891f7371b2SAlex Deucher extern int amdgpu_powerplay; 906bb6b297SHuang Rui extern int amdgpu_powercontainment; 91cd474ba0SAlex Deucher extern unsigned amdgpu_pcie_gen_cap; 92cd474ba0SAlex Deucher extern unsigned amdgpu_pcie_lane_cap; 93395d1fb9SNicolai Hähnle extern unsigned amdgpu_cg_mask; 94395d1fb9SNicolai Hähnle extern unsigned amdgpu_pg_mask; 956f8941a2SNicolai Hähnle extern char *amdgpu_disable_cu; 9666bc3f7fSRex Zhu extern int amdgpu_sclk_deep_sleep_en; 979accf2fdSEmily Deng extern char *amdgpu_virtual_display; 9897b2e202SAlex Deucher 994b559c90SChunming Zhou #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 10097b2e202SAlex Deucher #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 10197b2e202SAlex Deucher #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 10297b2e202SAlex Deucher /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 10397b2e202SAlex Deucher #define AMDGPU_IB_POOL_SIZE 16 10497b2e202SAlex Deucher #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 10597b2e202SAlex Deucher #define AMDGPUFB_CONN_LIMIT 4 10697b2e202SAlex Deucher #define AMDGPU_BIOS_NUM_SCRATCH 8 10797b2e202SAlex Deucher 10897b2e202SAlex Deucher /* max number of rings */ 10997b2e202SAlex Deucher #define AMDGPU_MAX_RINGS 16 11097b2e202SAlex Deucher #define AMDGPU_MAX_GFX_RINGS 1 11197b2e202SAlex Deucher #define AMDGPU_MAX_COMPUTE_RINGS 8 1126f0359ffSAlex Deucher #define AMDGPU_MAX_VCE_RINGS 3 11397b2e202SAlex Deucher 11436f523a7SJammy Zhou /* max number of IP instances */ 11536f523a7SJammy Zhou #define AMDGPU_MAX_SDMA_INSTANCES 2 11636f523a7SJammy Zhou 11797b2e202SAlex Deucher /* hardcode that limit for now */ 11897b2e202SAlex Deucher #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 11997b2e202SAlex Deucher 12097b2e202SAlex Deucher /* hard reset data */ 12197b2e202SAlex Deucher #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 12297b2e202SAlex Deucher 12397b2e202SAlex Deucher /* reset flags */ 12497b2e202SAlex Deucher #define AMDGPU_RESET_GFX (1 << 0) 12597b2e202SAlex Deucher #define AMDGPU_RESET_COMPUTE (1 << 1) 12697b2e202SAlex Deucher #define AMDGPU_RESET_DMA (1 << 2) 12797b2e202SAlex Deucher #define AMDGPU_RESET_CP (1 << 3) 12897b2e202SAlex Deucher #define AMDGPU_RESET_GRBM (1 << 4) 12997b2e202SAlex Deucher #define AMDGPU_RESET_DMA1 (1 << 5) 13097b2e202SAlex Deucher #define AMDGPU_RESET_RLC (1 << 6) 13197b2e202SAlex Deucher #define AMDGPU_RESET_SEM (1 << 7) 13297b2e202SAlex Deucher #define AMDGPU_RESET_IH (1 << 8) 13397b2e202SAlex Deucher #define AMDGPU_RESET_VMC (1 << 9) 13497b2e202SAlex Deucher #define AMDGPU_RESET_MC (1 << 10) 13597b2e202SAlex Deucher #define AMDGPU_RESET_DISPLAY (1 << 11) 13697b2e202SAlex Deucher #define AMDGPU_RESET_UVD (1 << 12) 13797b2e202SAlex Deucher #define AMDGPU_RESET_VCE (1 << 13) 13897b2e202SAlex Deucher #define AMDGPU_RESET_VCE1 (1 << 14) 13997b2e202SAlex Deucher 14097b2e202SAlex Deucher /* GFX current status */ 14197b2e202SAlex Deucher #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 14297b2e202SAlex Deucher #define AMDGPU_GFX_SAFE_MODE 0x00000001L 14397b2e202SAlex Deucher #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 14497b2e202SAlex Deucher #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 14597b2e202SAlex Deucher #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 14697b2e202SAlex Deucher 14797b2e202SAlex Deucher /* max cursor sizes (in pixels) */ 14897b2e202SAlex Deucher #define CIK_CURSOR_WIDTH 128 14997b2e202SAlex Deucher #define CIK_CURSOR_HEIGHT 128 15097b2e202SAlex Deucher 15197b2e202SAlex Deucher struct amdgpu_device; 15297b2e202SAlex Deucher struct amdgpu_ib; 15397b2e202SAlex Deucher struct amdgpu_vm; 15497b2e202SAlex Deucher struct amdgpu_ring; 15597b2e202SAlex Deucher struct amdgpu_cs_parser; 156bb977d37SChunming Zhou struct amdgpu_job; 15797b2e202SAlex Deucher struct amdgpu_irq_src; 1580b492a4cSAlex Deucher struct amdgpu_fpriv; 15997b2e202SAlex Deucher 16097b2e202SAlex Deucher enum amdgpu_cp_irq { 16197b2e202SAlex Deucher AMDGPU_CP_IRQ_GFX_EOP = 0, 16297b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 16397b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 16497b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 16597b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 16697b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 16797b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 16897b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 16997b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 17097b2e202SAlex Deucher 17197b2e202SAlex Deucher AMDGPU_CP_IRQ_LAST 17297b2e202SAlex Deucher }; 17397b2e202SAlex Deucher 17497b2e202SAlex Deucher enum amdgpu_sdma_irq { 17597b2e202SAlex Deucher AMDGPU_SDMA_IRQ_TRAP0 = 0, 17697b2e202SAlex Deucher AMDGPU_SDMA_IRQ_TRAP1, 17797b2e202SAlex Deucher 17897b2e202SAlex Deucher AMDGPU_SDMA_IRQ_LAST 17997b2e202SAlex Deucher }; 18097b2e202SAlex Deucher 18197b2e202SAlex Deucher enum amdgpu_thermal_irq { 18297b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 18397b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 18497b2e202SAlex Deucher 18597b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LAST 18697b2e202SAlex Deucher }; 18797b2e202SAlex Deucher 18897b2e202SAlex Deucher int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 1895fc3aeebSyanyang1 enum amd_ip_block_type block_type, 1905fc3aeebSyanyang1 enum amd_clockgating_state state); 19197b2e202SAlex Deucher int amdgpu_set_powergating_state(struct amdgpu_device *adev, 1925fc3aeebSyanyang1 enum amd_ip_block_type block_type, 1935fc3aeebSyanyang1 enum amd_powergating_state state); 1945dbbb60bSAlex Deucher int amdgpu_wait_for_idle(struct amdgpu_device *adev, 1955dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 1965dbbb60bSAlex Deucher bool amdgpu_is_idle(struct amdgpu_device *adev, 1975dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 19897b2e202SAlex Deucher 19997b2e202SAlex Deucher struct amdgpu_ip_block_version { 2005fc3aeebSyanyang1 enum amd_ip_block_type type; 20197b2e202SAlex Deucher u32 major; 20297b2e202SAlex Deucher u32 minor; 20397b2e202SAlex Deucher u32 rev; 2045fc3aeebSyanyang1 const struct amd_ip_funcs *funcs; 20597b2e202SAlex Deucher }; 20697b2e202SAlex Deucher 20797b2e202SAlex Deucher int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 2085fc3aeebSyanyang1 enum amd_ip_block_type type, 20997b2e202SAlex Deucher u32 major, u32 minor); 21097b2e202SAlex Deucher 21197b2e202SAlex Deucher const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 21297b2e202SAlex Deucher struct amdgpu_device *adev, 2135fc3aeebSyanyang1 enum amd_ip_block_type type); 21497b2e202SAlex Deucher 21597b2e202SAlex Deucher /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 21697b2e202SAlex Deucher struct amdgpu_buffer_funcs { 21797b2e202SAlex Deucher /* maximum bytes in a single operation */ 21897b2e202SAlex Deucher uint32_t copy_max_bytes; 21997b2e202SAlex Deucher 22097b2e202SAlex Deucher /* number of dw to reserve per operation */ 22197b2e202SAlex Deucher unsigned copy_num_dw; 22297b2e202SAlex Deucher 22397b2e202SAlex Deucher /* used for buffer migration */ 224c7ae72c0SChunming Zhou void (*emit_copy_buffer)(struct amdgpu_ib *ib, 22597b2e202SAlex Deucher /* src addr in bytes */ 22697b2e202SAlex Deucher uint64_t src_offset, 22797b2e202SAlex Deucher /* dst addr in bytes */ 22897b2e202SAlex Deucher uint64_t dst_offset, 22997b2e202SAlex Deucher /* number of byte to transfer */ 23097b2e202SAlex Deucher uint32_t byte_count); 23197b2e202SAlex Deucher 23297b2e202SAlex Deucher /* maximum bytes in a single operation */ 23397b2e202SAlex Deucher uint32_t fill_max_bytes; 23497b2e202SAlex Deucher 23597b2e202SAlex Deucher /* number of dw to reserve per operation */ 23697b2e202SAlex Deucher unsigned fill_num_dw; 23797b2e202SAlex Deucher 23897b2e202SAlex Deucher /* used for buffer clearing */ 2396e7a3840SChunming Zhou void (*emit_fill_buffer)(struct amdgpu_ib *ib, 24097b2e202SAlex Deucher /* value to write to memory */ 24197b2e202SAlex Deucher uint32_t src_data, 24297b2e202SAlex Deucher /* dst addr in bytes */ 24397b2e202SAlex Deucher uint64_t dst_offset, 24497b2e202SAlex Deucher /* number of byte to fill */ 24597b2e202SAlex Deucher uint32_t byte_count); 24697b2e202SAlex Deucher }; 24797b2e202SAlex Deucher 24897b2e202SAlex Deucher /* provided by hw blocks that can write ptes, e.g., sdma */ 24997b2e202SAlex Deucher struct amdgpu_vm_pte_funcs { 25097b2e202SAlex Deucher /* copy pte entries from GART */ 25197b2e202SAlex Deucher void (*copy_pte)(struct amdgpu_ib *ib, 25297b2e202SAlex Deucher uint64_t pe, uint64_t src, 25397b2e202SAlex Deucher unsigned count); 25497b2e202SAlex Deucher /* write pte one entry at a time with addr mapping */ 255de9ea7bdSChristian König void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 256de9ea7bdSChristian König uint64_t value, unsigned count, 257de9ea7bdSChristian König uint32_t incr); 25897b2e202SAlex Deucher /* for linear pte/pde updates without addr mapping */ 25997b2e202SAlex Deucher void (*set_pte_pde)(struct amdgpu_ib *ib, 26097b2e202SAlex Deucher uint64_t pe, 26197b2e202SAlex Deucher uint64_t addr, unsigned count, 26297b2e202SAlex Deucher uint32_t incr, uint32_t flags); 26397b2e202SAlex Deucher }; 26497b2e202SAlex Deucher 26597b2e202SAlex Deucher /* provided by the gmc block */ 26697b2e202SAlex Deucher struct amdgpu_gart_funcs { 26797b2e202SAlex Deucher /* flush the vm tlb via mmio */ 26897b2e202SAlex Deucher void (*flush_gpu_tlb)(struct amdgpu_device *adev, 26997b2e202SAlex Deucher uint32_t vmid); 27097b2e202SAlex Deucher /* write pte/pde updates using the cpu */ 27197b2e202SAlex Deucher int (*set_pte_pde)(struct amdgpu_device *adev, 27297b2e202SAlex Deucher void *cpu_pt_addr, /* cpu addr of page table */ 27397b2e202SAlex Deucher uint32_t gpu_page_idx, /* pte/pde to update */ 27497b2e202SAlex Deucher uint64_t addr, /* addr to write into pte/pde */ 27597b2e202SAlex Deucher uint32_t flags); /* access flags */ 27697b2e202SAlex Deucher }; 27797b2e202SAlex Deucher 27897b2e202SAlex Deucher /* provided by the ih block */ 27997b2e202SAlex Deucher struct amdgpu_ih_funcs { 28097b2e202SAlex Deucher /* ring read/write ptr handling, called from interrupt context */ 28197b2e202SAlex Deucher u32 (*get_wptr)(struct amdgpu_device *adev); 28297b2e202SAlex Deucher void (*decode_iv)(struct amdgpu_device *adev, 28397b2e202SAlex Deucher struct amdgpu_iv_entry *entry); 28497b2e202SAlex Deucher void (*set_rptr)(struct amdgpu_device *adev); 28597b2e202SAlex Deucher }; 28697b2e202SAlex Deucher 28797b2e202SAlex Deucher /* provided by hw blocks that expose a ring buffer for commands */ 28897b2e202SAlex Deucher struct amdgpu_ring_funcs { 28997b2e202SAlex Deucher /* ring read/write ptr handling */ 29097b2e202SAlex Deucher u32 (*get_rptr)(struct amdgpu_ring *ring); 29197b2e202SAlex Deucher u32 (*get_wptr)(struct amdgpu_ring *ring); 29297b2e202SAlex Deucher void (*set_wptr)(struct amdgpu_ring *ring); 29397b2e202SAlex Deucher /* validating and patching of IBs */ 29497b2e202SAlex Deucher int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 29597b2e202SAlex Deucher /* command emit functions */ 29697b2e202SAlex Deucher void (*emit_ib)(struct amdgpu_ring *ring, 297d88bf583SChristian König struct amdgpu_ib *ib, 298d88bf583SChristian König unsigned vm_id, bool ctx_switch); 29997b2e202SAlex Deucher void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 300890ee23fSChunming Zhou uint64_t seq, unsigned flags); 301b8c7b39eSChristian König void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 30297b2e202SAlex Deucher void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 30397b2e202SAlex Deucher uint64_t pd_addr); 304d2edb07bSChristian König void (*emit_hdp_flush)(struct amdgpu_ring *ring); 30511afbde8SChunming Zhou void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); 30697b2e202SAlex Deucher void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 30797b2e202SAlex Deucher uint32_t gds_base, uint32_t gds_size, 30897b2e202SAlex Deucher uint32_t gws_base, uint32_t gws_size, 30997b2e202SAlex Deucher uint32_t oa_base, uint32_t oa_size); 31097b2e202SAlex Deucher /* testing functions */ 31197b2e202SAlex Deucher int (*test_ring)(struct amdgpu_ring *ring); 312bbec97aaSChristian König int (*test_ib)(struct amdgpu_ring *ring, long timeout); 313edff0e28SJammy Zhou /* insert NOP packets */ 314edff0e28SJammy Zhou void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 3159e5d5309SChristian König /* pad the indirect buffer to the necessary number of dw */ 3169e5d5309SChristian König void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 31703ccf481SMonk Liu unsigned (*init_cond_exec)(struct amdgpu_ring *ring); 31803ccf481SMonk Liu void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); 319f06505b8SChristian König /* note usage for clock and power gating */ 320f06505b8SChristian König void (*begin_use)(struct amdgpu_ring *ring); 321f06505b8SChristian König void (*end_use)(struct amdgpu_ring *ring); 322c2167a65SMonk Liu void (*emit_switch_buffer) (struct amdgpu_ring *ring); 32397b2e202SAlex Deucher }; 32497b2e202SAlex Deucher 32597b2e202SAlex Deucher /* 32697b2e202SAlex Deucher * BIOS. 32797b2e202SAlex Deucher */ 32897b2e202SAlex Deucher bool amdgpu_get_bios(struct amdgpu_device *adev); 32997b2e202SAlex Deucher bool amdgpu_read_bios(struct amdgpu_device *adev); 33097b2e202SAlex Deucher 33197b2e202SAlex Deucher /* 33297b2e202SAlex Deucher * Dummy page 33397b2e202SAlex Deucher */ 33497b2e202SAlex Deucher struct amdgpu_dummy_page { 33597b2e202SAlex Deucher struct page *page; 33697b2e202SAlex Deucher dma_addr_t addr; 33797b2e202SAlex Deucher }; 33897b2e202SAlex Deucher int amdgpu_dummy_page_init(struct amdgpu_device *adev); 33997b2e202SAlex Deucher void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 34097b2e202SAlex Deucher 34197b2e202SAlex Deucher 34297b2e202SAlex Deucher /* 34397b2e202SAlex Deucher * Clocks 34497b2e202SAlex Deucher */ 34597b2e202SAlex Deucher 34697b2e202SAlex Deucher #define AMDGPU_MAX_PPLL 3 34797b2e202SAlex Deucher 34897b2e202SAlex Deucher struct amdgpu_clock { 34997b2e202SAlex Deucher struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 35097b2e202SAlex Deucher struct amdgpu_pll spll; 35197b2e202SAlex Deucher struct amdgpu_pll mpll; 35297b2e202SAlex Deucher /* 10 Khz units */ 35397b2e202SAlex Deucher uint32_t default_mclk; 35497b2e202SAlex Deucher uint32_t default_sclk; 35597b2e202SAlex Deucher uint32_t default_dispclk; 35697b2e202SAlex Deucher uint32_t current_dispclk; 35797b2e202SAlex Deucher uint32_t dp_extclk; 35897b2e202SAlex Deucher uint32_t max_pixel_clock; 35997b2e202SAlex Deucher }; 36097b2e202SAlex Deucher 36197b2e202SAlex Deucher /* 36297b2e202SAlex Deucher * Fences. 36397b2e202SAlex Deucher */ 36497b2e202SAlex Deucher struct amdgpu_fence_driver { 36597b2e202SAlex Deucher uint64_t gpu_addr; 36697b2e202SAlex Deucher volatile uint32_t *cpu_addr; 36797b2e202SAlex Deucher /* sync_seq is protected by ring emission lock */ 368742c085fSChristian König uint32_t sync_seq; 369742c085fSChristian König atomic_t last_seq; 37097b2e202SAlex Deucher bool initialized; 37197b2e202SAlex Deucher struct amdgpu_irq_src *irq_src; 37297b2e202SAlex Deucher unsigned irq_type; 373c2776afeSChristian König struct timer_list fallback_timer; 374c89377d1SChristian König unsigned num_fences_mask; 3754a7d74f1SChristian König spinlock_t lock; 376c89377d1SChristian König struct fence **fences; 37797b2e202SAlex Deucher }; 37897b2e202SAlex Deucher 37997b2e202SAlex Deucher /* some special values for the owner field */ 38097b2e202SAlex Deucher #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 38197b2e202SAlex Deucher #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 38297b2e202SAlex Deucher 383890ee23fSChunming Zhou #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 384890ee23fSChunming Zhou #define AMDGPU_FENCE_FLAG_INT (1 << 1) 385890ee23fSChunming Zhou 38697b2e202SAlex Deucher int amdgpu_fence_driver_init(struct amdgpu_device *adev); 38797b2e202SAlex Deucher void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 38897b2e202SAlex Deucher void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 38997b2e202SAlex Deucher 390e6151a08SChristian König int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 391e6151a08SChristian König unsigned num_hw_submission); 39297b2e202SAlex Deucher int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 39397b2e202SAlex Deucher struct amdgpu_irq_src *irq_src, 39497b2e202SAlex Deucher unsigned irq_type); 3955ceb54c6SAlex Deucher void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 3965ceb54c6SAlex Deucher void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 397364beb2cSChristian König int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence); 39897b2e202SAlex Deucher void amdgpu_fence_process(struct amdgpu_ring *ring); 39997b2e202SAlex Deucher int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 40097b2e202SAlex Deucher unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 40197b2e202SAlex Deucher 40297b2e202SAlex Deucher /* 403c632d799SFlora Cui * BO. 40497b2e202SAlex Deucher */ 40529b3259aSChristian König 40697b2e202SAlex Deucher struct amdgpu_bo_list_entry { 40797b2e202SAlex Deucher struct amdgpu_bo *robj; 40897b2e202SAlex Deucher struct ttm_validate_buffer tv; 40997b2e202SAlex Deucher struct amdgpu_bo_va *bo_va; 41097b2e202SAlex Deucher uint32_t priority; 4112f568dbdSChristian König struct page **user_pages; 4122f568dbdSChristian König int user_invalidated; 41397b2e202SAlex Deucher }; 41497b2e202SAlex Deucher 41597b2e202SAlex Deucher struct amdgpu_bo_va_mapping { 41697b2e202SAlex Deucher struct list_head list; 41797b2e202SAlex Deucher struct interval_tree_node it; 41897b2e202SAlex Deucher uint64_t offset; 41997b2e202SAlex Deucher uint32_t flags; 42097b2e202SAlex Deucher }; 42197b2e202SAlex Deucher 42297b2e202SAlex Deucher /* bo virtual addresses in a specific vm */ 42397b2e202SAlex Deucher struct amdgpu_bo_va { 42497b2e202SAlex Deucher /* protected by bo being reserved */ 42597b2e202SAlex Deucher struct list_head bo_list; 426bb1e38a4SChunming Zhou struct fence *last_pt_update; 42797b2e202SAlex Deucher unsigned ref_count; 42897b2e202SAlex Deucher 4297fc11959SChristian König /* protected by vm mutex and spinlock */ 43097b2e202SAlex Deucher struct list_head vm_status; 43197b2e202SAlex Deucher 4327fc11959SChristian König /* mappings for this bo_va */ 4337fc11959SChristian König struct list_head invalids; 4347fc11959SChristian König struct list_head valids; 4357fc11959SChristian König 43697b2e202SAlex Deucher /* constant after initialization */ 43797b2e202SAlex Deucher struct amdgpu_vm *vm; 43897b2e202SAlex Deucher struct amdgpu_bo *bo; 43997b2e202SAlex Deucher }; 44097b2e202SAlex Deucher 4417e5a547fSChunming Zhou #define AMDGPU_GEM_DOMAIN_MAX 0x3 4427e5a547fSChunming Zhou 44397b2e202SAlex Deucher struct amdgpu_bo { 44497b2e202SAlex Deucher /* Protected by gem.mutex */ 44597b2e202SAlex Deucher struct list_head list; 44697b2e202SAlex Deucher /* Protected by tbo.reserved */ 4471ea863fdSChristian König u32 prefered_domains; 4481ea863fdSChristian König u32 allowed_domains; 4497e5a547fSChunming Zhou struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 45097b2e202SAlex Deucher struct ttm_placement placement; 45197b2e202SAlex Deucher struct ttm_buffer_object tbo; 45297b2e202SAlex Deucher struct ttm_bo_kmap_obj kmap; 45397b2e202SAlex Deucher u64 flags; 45497b2e202SAlex Deucher unsigned pin_count; 45597b2e202SAlex Deucher void *kptr; 45697b2e202SAlex Deucher u64 tiling_flags; 45797b2e202SAlex Deucher u64 metadata_flags; 45897b2e202SAlex Deucher void *metadata; 45997b2e202SAlex Deucher u32 metadata_size; 46097b2e202SAlex Deucher /* list of all virtual address to which this bo 46197b2e202SAlex Deucher * is associated to 46297b2e202SAlex Deucher */ 46397b2e202SAlex Deucher struct list_head va; 46497b2e202SAlex Deucher /* Constant after initialization */ 46597b2e202SAlex Deucher struct amdgpu_device *adev; 46697b2e202SAlex Deucher struct drm_gem_object gem_base; 46782b9c55bSChristian König struct amdgpu_bo *parent; 468e7893c4bSChunming Zhou struct amdgpu_bo *shadow; 46997b2e202SAlex Deucher 47097b2e202SAlex Deucher struct ttm_bo_kmap_obj dma_buf_vmap; 47197b2e202SAlex Deucher struct amdgpu_mn *mn; 47297b2e202SAlex Deucher struct list_head mn_list; 4730c4e7fa5SChunming Zhou struct list_head shadow_list; 47497b2e202SAlex Deucher }; 47597b2e202SAlex Deucher #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 47697b2e202SAlex Deucher 47797b2e202SAlex Deucher void amdgpu_gem_object_free(struct drm_gem_object *obj); 47897b2e202SAlex Deucher int amdgpu_gem_object_open(struct drm_gem_object *obj, 47997b2e202SAlex Deucher struct drm_file *file_priv); 48097b2e202SAlex Deucher void amdgpu_gem_object_close(struct drm_gem_object *obj, 48197b2e202SAlex Deucher struct drm_file *file_priv); 48297b2e202SAlex Deucher unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 48397b2e202SAlex Deucher struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 4844d9c514dSChristian König struct drm_gem_object * 4854d9c514dSChristian König amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 48697b2e202SAlex Deucher struct dma_buf_attachment *attach, 48797b2e202SAlex Deucher struct sg_table *sg); 48897b2e202SAlex Deucher struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 48997b2e202SAlex Deucher struct drm_gem_object *gobj, 49097b2e202SAlex Deucher int flags); 49197b2e202SAlex Deucher int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 49297b2e202SAlex Deucher void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 49397b2e202SAlex Deucher struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 49497b2e202SAlex Deucher void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 49597b2e202SAlex Deucher void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 49697b2e202SAlex Deucher int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 49797b2e202SAlex Deucher 49897b2e202SAlex Deucher /* sub-allocation manager, it has to be protected by another lock. 49997b2e202SAlex Deucher * By conception this is an helper for other part of the driver 50097b2e202SAlex Deucher * like the indirect buffer or semaphore, which both have their 50197b2e202SAlex Deucher * locking. 50297b2e202SAlex Deucher * 50397b2e202SAlex Deucher * Principe is simple, we keep a list of sub allocation in offset 50497b2e202SAlex Deucher * order (first entry has offset == 0, last entry has the highest 50597b2e202SAlex Deucher * offset). 50697b2e202SAlex Deucher * 50797b2e202SAlex Deucher * When allocating new object we first check if there is room at 50897b2e202SAlex Deucher * the end total_size - (last_object_offset + last_object_size) >= 50997b2e202SAlex Deucher * alloc_size. If so we allocate new object there. 51097b2e202SAlex Deucher * 51197b2e202SAlex Deucher * When there is not enough room at the end, we start waiting for 51297b2e202SAlex Deucher * each sub object until we reach object_offset+object_size >= 51397b2e202SAlex Deucher * alloc_size, this object then become the sub object we return. 51497b2e202SAlex Deucher * 51597b2e202SAlex Deucher * Alignment can't be bigger than page size. 51697b2e202SAlex Deucher * 51797b2e202SAlex Deucher * Hole are not considered for allocation to keep things simple. 51897b2e202SAlex Deucher * Assumption is that there won't be hole (all object on same 51997b2e202SAlex Deucher * alignment). 52097b2e202SAlex Deucher */ 5216ba60b89SChristian König 5226ba60b89SChristian König #define AMDGPU_SA_NUM_FENCE_LISTS 32 5236ba60b89SChristian König 52497b2e202SAlex Deucher struct amdgpu_sa_manager { 52597b2e202SAlex Deucher wait_queue_head_t wq; 52697b2e202SAlex Deucher struct amdgpu_bo *bo; 52797b2e202SAlex Deucher struct list_head *hole; 5286ba60b89SChristian König struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 52997b2e202SAlex Deucher struct list_head olist; 53097b2e202SAlex Deucher unsigned size; 53197b2e202SAlex Deucher uint64_t gpu_addr; 53297b2e202SAlex Deucher void *cpu_ptr; 53397b2e202SAlex Deucher uint32_t domain; 53497b2e202SAlex Deucher uint32_t align; 53597b2e202SAlex Deucher }; 53697b2e202SAlex Deucher 53797b2e202SAlex Deucher /* sub-allocation buffer */ 53897b2e202SAlex Deucher struct amdgpu_sa_bo { 53997b2e202SAlex Deucher struct list_head olist; 54097b2e202SAlex Deucher struct list_head flist; 54197b2e202SAlex Deucher struct amdgpu_sa_manager *manager; 54297b2e202SAlex Deucher unsigned soffset; 54397b2e202SAlex Deucher unsigned eoffset; 5444ce9891eSChunming Zhou struct fence *fence; 54597b2e202SAlex Deucher }; 54697b2e202SAlex Deucher 54797b2e202SAlex Deucher /* 54897b2e202SAlex Deucher * GEM objects. 54997b2e202SAlex Deucher */ 550418aa0c2SChristian König void amdgpu_gem_force_release(struct amdgpu_device *adev); 55197b2e202SAlex Deucher int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 55297b2e202SAlex Deucher int alignment, u32 initial_domain, 55397b2e202SAlex Deucher u64 flags, bool kernel, 55497b2e202SAlex Deucher struct drm_gem_object **obj); 55597b2e202SAlex Deucher 55697b2e202SAlex Deucher int amdgpu_mode_dumb_create(struct drm_file *file_priv, 55797b2e202SAlex Deucher struct drm_device *dev, 55897b2e202SAlex Deucher struct drm_mode_create_dumb *args); 55997b2e202SAlex Deucher int amdgpu_mode_dumb_mmap(struct drm_file *filp, 56097b2e202SAlex Deucher struct drm_device *dev, 56197b2e202SAlex Deucher uint32_t handle, uint64_t *offset_p); 56297b2e202SAlex Deucher /* 56397b2e202SAlex Deucher * Synchronization 56497b2e202SAlex Deucher */ 56597b2e202SAlex Deucher struct amdgpu_sync { 566f91b3a69SChristian König DECLARE_HASHTABLE(fences, 4); 5673c62338cSChunming Zhou struct fence *last_vm_update; 56897b2e202SAlex Deucher }; 56997b2e202SAlex Deucher 57097b2e202SAlex Deucher void amdgpu_sync_create(struct amdgpu_sync *sync); 57191e1a520SChristian König int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 57291e1a520SChristian König struct fence *f); 57397b2e202SAlex Deucher int amdgpu_sync_resv(struct amdgpu_device *adev, 57497b2e202SAlex Deucher struct amdgpu_sync *sync, 57597b2e202SAlex Deucher struct reservation_object *resv, 57697b2e202SAlex Deucher void *owner); 5771fbb2e92SChristian König struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, 57835420238SChristian König struct amdgpu_ring *ring); 579e61235dbSChristian König struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 5808a8f0b48SChristian König void amdgpu_sync_free(struct amdgpu_sync *sync); 581257bf15aSChristian König int amdgpu_sync_init(void); 582257bf15aSChristian König void amdgpu_sync_fini(void); 583d573de2dSRex Zhu int amdgpu_fence_slab_init(void); 584d573de2dSRex Zhu void amdgpu_fence_slab_fini(void); 58597b2e202SAlex Deucher 58697b2e202SAlex Deucher /* 58797b2e202SAlex Deucher * GART structures, functions & helpers 58897b2e202SAlex Deucher */ 58997b2e202SAlex Deucher struct amdgpu_mc; 59097b2e202SAlex Deucher 59197b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_SIZE 4096 59297b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 59397b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_SHIFT 12 59497b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 59597b2e202SAlex Deucher 59697b2e202SAlex Deucher struct amdgpu_gart { 59797b2e202SAlex Deucher dma_addr_t table_addr; 59897b2e202SAlex Deucher struct amdgpu_bo *robj; 59997b2e202SAlex Deucher void *ptr; 60097b2e202SAlex Deucher unsigned num_gpu_pages; 60197b2e202SAlex Deucher unsigned num_cpu_pages; 60297b2e202SAlex Deucher unsigned table_size; 603a1d29476SChristian König #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 60497b2e202SAlex Deucher struct page **pages; 605a1d29476SChristian König #endif 60697b2e202SAlex Deucher bool ready; 60797b2e202SAlex Deucher const struct amdgpu_gart_funcs *gart_funcs; 60897b2e202SAlex Deucher }; 60997b2e202SAlex Deucher 61097b2e202SAlex Deucher int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 61197b2e202SAlex Deucher void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 61297b2e202SAlex Deucher int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 61397b2e202SAlex Deucher void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 61497b2e202SAlex Deucher int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 61597b2e202SAlex Deucher void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 61697b2e202SAlex Deucher int amdgpu_gart_init(struct amdgpu_device *adev); 61797b2e202SAlex Deucher void amdgpu_gart_fini(struct amdgpu_device *adev); 61897b2e202SAlex Deucher void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 61997b2e202SAlex Deucher int pages); 62097b2e202SAlex Deucher int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 62197b2e202SAlex Deucher int pages, struct page **pagelist, 62297b2e202SAlex Deucher dma_addr_t *dma_addr, uint32_t flags); 62397b2e202SAlex Deucher 62497b2e202SAlex Deucher /* 62597b2e202SAlex Deucher * GPU MC structures, functions & helpers 62697b2e202SAlex Deucher */ 62797b2e202SAlex Deucher struct amdgpu_mc { 62897b2e202SAlex Deucher resource_size_t aper_size; 62997b2e202SAlex Deucher resource_size_t aper_base; 63097b2e202SAlex Deucher resource_size_t agp_base; 63197b2e202SAlex Deucher /* for some chips with <= 32MB we need to lie 63297b2e202SAlex Deucher * about vram size near mc fb location */ 63397b2e202SAlex Deucher u64 mc_vram_size; 63497b2e202SAlex Deucher u64 visible_vram_size; 63597b2e202SAlex Deucher u64 gtt_size; 63697b2e202SAlex Deucher u64 gtt_start; 63797b2e202SAlex Deucher u64 gtt_end; 63897b2e202SAlex Deucher u64 vram_start; 63997b2e202SAlex Deucher u64 vram_end; 64097b2e202SAlex Deucher unsigned vram_width; 64197b2e202SAlex Deucher u64 real_vram_size; 64297b2e202SAlex Deucher int vram_mtrr; 64397b2e202SAlex Deucher u64 gtt_base_align; 64497b2e202SAlex Deucher u64 mc_mask; 64597b2e202SAlex Deucher const struct firmware *fw; /* MC firmware */ 64697b2e202SAlex Deucher uint32_t fw_version; 64797b2e202SAlex Deucher struct amdgpu_irq_src vm_fault; 64881c59f54SKen Wang uint32_t vram_type; 64950b0197aSChunming Zhou uint32_t srbm_soft_reset; 65050b0197aSChunming Zhou struct amdgpu_mode_mc_save save; 65197b2e202SAlex Deucher }; 65297b2e202SAlex Deucher 65397b2e202SAlex Deucher /* 65497b2e202SAlex Deucher * GPU doorbell structures, functions & helpers 65597b2e202SAlex Deucher */ 65697b2e202SAlex Deucher typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 65797b2e202SAlex Deucher { 65897b2e202SAlex Deucher AMDGPU_DOORBELL_KIQ = 0x000, 65997b2e202SAlex Deucher AMDGPU_DOORBELL_HIQ = 0x001, 66097b2e202SAlex Deucher AMDGPU_DOORBELL_DIQ = 0x002, 66197b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING0 = 0x010, 66297b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING1 = 0x011, 66397b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING2 = 0x012, 66497b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING3 = 0x013, 66597b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING4 = 0x014, 66697b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING5 = 0x015, 66797b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING6 = 0x016, 66897b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING7 = 0x017, 66997b2e202SAlex Deucher AMDGPU_DOORBELL_GFX_RING0 = 0x020, 67097b2e202SAlex Deucher AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 67197b2e202SAlex Deucher AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 67297b2e202SAlex Deucher AMDGPU_DOORBELL_IH = 0x1E8, 67397b2e202SAlex Deucher AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 67497b2e202SAlex Deucher AMDGPU_DOORBELL_INVALID = 0xFFFF 67597b2e202SAlex Deucher } AMDGPU_DOORBELL_ASSIGNMENT; 67697b2e202SAlex Deucher 67797b2e202SAlex Deucher struct amdgpu_doorbell { 67897b2e202SAlex Deucher /* doorbell mmio */ 67997b2e202SAlex Deucher resource_size_t base; 68097b2e202SAlex Deucher resource_size_t size; 68197b2e202SAlex Deucher u32 __iomem *ptr; 68297b2e202SAlex Deucher u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 68397b2e202SAlex Deucher }; 68497b2e202SAlex Deucher 68597b2e202SAlex Deucher void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 68697b2e202SAlex Deucher phys_addr_t *aperture_base, 68797b2e202SAlex Deucher size_t *aperture_size, 68897b2e202SAlex Deucher size_t *start_offset); 68997b2e202SAlex Deucher 69097b2e202SAlex Deucher /* 69197b2e202SAlex Deucher * IRQS. 69297b2e202SAlex Deucher */ 69397b2e202SAlex Deucher 69497b2e202SAlex Deucher struct amdgpu_flip_work { 695325cbba1SMichel Dänzer struct delayed_work flip_work; 69697b2e202SAlex Deucher struct work_struct unpin_work; 69797b2e202SAlex Deucher struct amdgpu_device *adev; 69897b2e202SAlex Deucher int crtc_id; 699325cbba1SMichel Dänzer u32 target_vblank; 70097b2e202SAlex Deucher uint64_t base; 70197b2e202SAlex Deucher struct drm_pending_vblank_event *event; 70297b2e202SAlex Deucher struct amdgpu_bo *old_rbo; 7031ffd2652SChristian König struct fence *excl; 7041ffd2652SChristian König unsigned shared_count; 7051ffd2652SChristian König struct fence **shared; 706c3874b75SChristian König struct fence_cb cb; 707cb9e59d7SAlex Deucher bool async; 70897b2e202SAlex Deucher }; 70997b2e202SAlex Deucher 71097b2e202SAlex Deucher 71197b2e202SAlex Deucher /* 71297b2e202SAlex Deucher * CP & rings. 71397b2e202SAlex Deucher */ 71497b2e202SAlex Deucher 71597b2e202SAlex Deucher struct amdgpu_ib { 71697b2e202SAlex Deucher struct amdgpu_sa_bo *sa_bo; 71797b2e202SAlex Deucher uint32_t length_dw; 71897b2e202SAlex Deucher uint64_t gpu_addr; 71997b2e202SAlex Deucher uint32_t *ptr; 720de807f81SJammy Zhou uint32_t flags; 72197b2e202SAlex Deucher }; 72297b2e202SAlex Deucher 72397b2e202SAlex Deucher enum amdgpu_ring_type { 72497b2e202SAlex Deucher AMDGPU_RING_TYPE_GFX, 72597b2e202SAlex Deucher AMDGPU_RING_TYPE_COMPUTE, 72697b2e202SAlex Deucher AMDGPU_RING_TYPE_SDMA, 72797b2e202SAlex Deucher AMDGPU_RING_TYPE_UVD, 72897b2e202SAlex Deucher AMDGPU_RING_TYPE_VCE 72997b2e202SAlex Deucher }; 73097b2e202SAlex Deucher 73162250a91SNils Wallménius extern const struct amd_sched_backend_ops amdgpu_sched_ops; 732c1b69ed0SChunming Zhou 73350838c8cSChristian König int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 734c5637837SMonk Liu struct amdgpu_job **job, struct amdgpu_vm *vm); 735d71518b5SChristian König int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 736d71518b5SChristian König struct amdgpu_job **job); 737b6723c8dSMonk Liu 738a5fb4ec2SChristian König void amdgpu_job_free_resources(struct amdgpu_job *job); 73950838c8cSChristian König void amdgpu_job_free(struct amdgpu_job *job); 740d71518b5SChristian König int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 7412bd9ccfaSChristian König struct amd_sched_entity *entity, void *owner, 7422bd9ccfaSChristian König struct fence **f); 7433c704e93SChunming Zhou 74497b2e202SAlex Deucher struct amdgpu_ring { 74597b2e202SAlex Deucher struct amdgpu_device *adev; 74697b2e202SAlex Deucher const struct amdgpu_ring_funcs *funcs; 74797b2e202SAlex Deucher struct amdgpu_fence_driver fence_drv; 7484f839a24SChristian König struct amd_gpu_scheduler sched; 74997b2e202SAlex Deucher 75097b2e202SAlex Deucher struct amdgpu_bo *ring_obj; 75197b2e202SAlex Deucher volatile uint32_t *ring; 75297b2e202SAlex Deucher unsigned rptr_offs; 75397b2e202SAlex Deucher unsigned wptr; 75497b2e202SAlex Deucher unsigned wptr_old; 75597b2e202SAlex Deucher unsigned ring_size; 756c7e6be23SChristian König unsigned max_dw; 75797b2e202SAlex Deucher int count_dw; 75897b2e202SAlex Deucher uint64_t gpu_addr; 75997b2e202SAlex Deucher uint32_t align_mask; 76097b2e202SAlex Deucher uint32_t ptr_mask; 76197b2e202SAlex Deucher bool ready; 76297b2e202SAlex Deucher u32 nop; 76397b2e202SAlex Deucher u32 idx; 76497b2e202SAlex Deucher u32 me; 76597b2e202SAlex Deucher u32 pipe; 76697b2e202SAlex Deucher u32 queue; 76797b2e202SAlex Deucher struct amdgpu_bo *mqd_obj; 76897b2e202SAlex Deucher u32 doorbell_index; 76997b2e202SAlex Deucher bool use_doorbell; 77097b2e202SAlex Deucher unsigned wptr_offs; 77197b2e202SAlex Deucher unsigned fence_offs; 772aa3b73f6SChristian König uint64_t current_ctx; 77397b2e202SAlex Deucher enum amdgpu_ring_type type; 77497b2e202SAlex Deucher char name[16]; 775128cff1aSMonk Liu unsigned cond_exe_offs; 776128cff1aSMonk Liu u64 cond_exe_gpu_addr; 777128cff1aSMonk Liu volatile u32 *cond_exe_cpu_addr; 778a909c6bdSMonk Liu #if defined(CONFIG_DEBUG_FS) 779a909c6bdSMonk Liu struct dentry *ent; 780a909c6bdSMonk Liu #endif 78197b2e202SAlex Deucher }; 78297b2e202SAlex Deucher 78397b2e202SAlex Deucher /* 78497b2e202SAlex Deucher * VM 78597b2e202SAlex Deucher */ 78697b2e202SAlex Deucher 78797b2e202SAlex Deucher /* maximum number of VMIDs */ 78897b2e202SAlex Deucher #define AMDGPU_NUM_VM 16 78997b2e202SAlex Deucher 79096105e53SChristian König /* Maximum number of PTEs the hardware can write with one command */ 79196105e53SChristian König #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 79296105e53SChristian König 79397b2e202SAlex Deucher /* number of entries in page table */ 79497b2e202SAlex Deucher #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 79597b2e202SAlex Deucher 79697b2e202SAlex Deucher /* PTBs (Page Table Blocks) need to be aligned to 32K */ 79797b2e202SAlex Deucher #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 79897b2e202SAlex Deucher 7991303c73cSChristian König /* LOG2 number of continuous pages for the fragment field */ 8001303c73cSChristian König #define AMDGPU_LOG2_PAGES_PER_FRAG 4 8011303c73cSChristian König 80297b2e202SAlex Deucher #define AMDGPU_PTE_VALID (1 << 0) 80397b2e202SAlex Deucher #define AMDGPU_PTE_SYSTEM (1 << 1) 80497b2e202SAlex Deucher #define AMDGPU_PTE_SNOOPED (1 << 2) 80597b2e202SAlex Deucher 80697b2e202SAlex Deucher /* VI only */ 80797b2e202SAlex Deucher #define AMDGPU_PTE_EXECUTABLE (1 << 4) 80897b2e202SAlex Deucher 80997b2e202SAlex Deucher #define AMDGPU_PTE_READABLE (1 << 5) 81097b2e202SAlex Deucher #define AMDGPU_PTE_WRITEABLE (1 << 6) 81197b2e202SAlex Deucher 8121303c73cSChristian König #define AMDGPU_PTE_FRAG(x) ((x & 0x1f) << 7) 81397b2e202SAlex Deucher 814d9c13156SChristian König /* How to programm VM fault handling */ 815d9c13156SChristian König #define AMDGPU_VM_FAULT_STOP_NEVER 0 816d9c13156SChristian König #define AMDGPU_VM_FAULT_STOP_FIRST 1 817d9c13156SChristian König #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 818d9c13156SChristian König 81997b2e202SAlex Deucher struct amdgpu_vm_pt { 820ee1782c3SChristian König struct amdgpu_bo_list_entry entry; 82197b2e202SAlex Deucher uint64_t addr; 8226557e3d2SChunming Zhou uint64_t shadow_addr; 82397b2e202SAlex Deucher }; 82497b2e202SAlex Deucher 82597b2e202SAlex Deucher struct amdgpu_vm { 82625cfc3c2SChristian König /* tree of virtual addresses mapped */ 82797b2e202SAlex Deucher struct rb_root va; 82897b2e202SAlex Deucher 8297fc11959SChristian König /* protecting invalidated */ 83097b2e202SAlex Deucher spinlock_t status_lock; 83197b2e202SAlex Deucher 83297b2e202SAlex Deucher /* BOs moved, but not yet updated in the PT */ 83397b2e202SAlex Deucher struct list_head invalidated; 83497b2e202SAlex Deucher 8357fc11959SChristian König /* BOs cleared in the PT because of a move */ 8367fc11959SChristian König struct list_head cleared; 8377fc11959SChristian König 8387fc11959SChristian König /* BO mappings freed, but not yet updated in the PT */ 83997b2e202SAlex Deucher struct list_head freed; 84097b2e202SAlex Deucher 84197b2e202SAlex Deucher /* contains the page directory */ 84297b2e202SAlex Deucher struct amdgpu_bo *page_directory; 84397b2e202SAlex Deucher unsigned max_pde_used; 84405906decSBas Nieuwenhuizen struct fence *page_directory_fence; 8455a712a87SChristian König uint64_t last_eviction_counter; 84697b2e202SAlex Deucher 84797b2e202SAlex Deucher /* array of page tables, one for each page directory entry */ 84897b2e202SAlex Deucher struct amdgpu_vm_pt *page_tables; 84997b2e202SAlex Deucher 85097b2e202SAlex Deucher /* for id and flush management per ring */ 851bcb1ba35SChristian König struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS]; 85225cfc3c2SChristian König 85381d75a30Sjimqu /* protecting freed */ 85481d75a30Sjimqu spinlock_t freed_lock; 8552bd9ccfaSChristian König 8562bd9ccfaSChristian König /* Scheduler entity for page table updates */ 8572bd9ccfaSChristian König struct amd_sched_entity entity; 858031e2983SChunming Zhou 859031e2983SChunming Zhou /* client id */ 860031e2983SChunming Zhou u64 client_id; 86197b2e202SAlex Deucher }; 86297b2e202SAlex Deucher 863bcb1ba35SChristian König struct amdgpu_vm_id { 864a9a78b32SChristian König struct list_head list; 865832a902fSChristian König struct fence *first; 866832a902fSChristian König struct amdgpu_sync active; 86741d9eb2cSChristian König struct fence *last_flush; 8680ea54b9bSChristian König atomic64_t owner; 869971fe9a9SChristian König 870bcb1ba35SChristian König uint64_t pd_gpu_addr; 871bcb1ba35SChristian König /* last flushed PD/PT update */ 872bcb1ba35SChristian König struct fence *flushed_updates; 873bcb1ba35SChristian König 8746adb0513SChunming Zhou uint32_t current_gpu_reset_count; 8756adb0513SChunming Zhou 876971fe9a9SChristian König uint32_t gds_base; 877971fe9a9SChristian König uint32_t gds_size; 878971fe9a9SChristian König uint32_t gws_base; 879971fe9a9SChristian König uint32_t gws_size; 880971fe9a9SChristian König uint32_t oa_base; 881971fe9a9SChristian König uint32_t oa_size; 882a9a78b32SChristian König }; 883a9a78b32SChristian König 884a9a78b32SChristian König struct amdgpu_vm_manager { 885a9a78b32SChristian König /* Handling of VMIDs */ 886a9a78b32SChristian König struct mutex lock; 887a9a78b32SChristian König unsigned num_ids; 888a9a78b32SChristian König struct list_head ids_lru; 889bcb1ba35SChristian König struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; 8901c16c0a7SChristian König 8911fbb2e92SChristian König /* Handling of VM fences */ 8921fbb2e92SChristian König u64 fence_context; 8931fbb2e92SChristian König unsigned seqno[AMDGPU_MAX_RINGS]; 8941fbb2e92SChristian König 89597b2e202SAlex Deucher uint32_t max_pfn; 89697b2e202SAlex Deucher /* vram base address for page table entry */ 89797b2e202SAlex Deucher u64 vram_base_offset; 89897b2e202SAlex Deucher /* is vm enabled? */ 89997b2e202SAlex Deucher bool enabled; 90097b2e202SAlex Deucher /* vm pte handling */ 90197b2e202SAlex Deucher const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 9022d55e45aSChristian König struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; 9032d55e45aSChristian König unsigned vm_pte_num_rings; 9042d55e45aSChristian König atomic_t vm_pte_next_ring; 905031e2983SChunming Zhou /* client id counter */ 906031e2983SChunming Zhou atomic64_t client_counter; 90797b2e202SAlex Deucher }; 90897b2e202SAlex Deucher 909a9a78b32SChristian König void amdgpu_vm_manager_init(struct amdgpu_device *adev); 910ea89f8c9SChristian König void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 9118b4fb00bSChristian König int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 9128b4fb00bSChristian König void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 91356467ebfSChristian König void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 9143c0eea6cSChristian König struct list_head *validated, 91556467ebfSChristian König struct amdgpu_bo_list_entry *entry); 9165a712a87SChristian König void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, 9175a712a87SChristian König struct list_head *duplicates); 918eceb8a15SChristian König void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, 919eceb8a15SChristian König struct amdgpu_vm *vm); 9208b4fb00bSChristian König int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 9214ff37a83SChristian König struct amdgpu_sync *sync, struct fence *fence, 922fd53be30SChunming Zhou struct amdgpu_job *job); 923fd53be30SChunming Zhou int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job); 924971fe9a9SChristian König void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); 9258b4fb00bSChristian König int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 9268b4fb00bSChristian König struct amdgpu_vm *vm); 9278b4fb00bSChristian König int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 9288b4fb00bSChristian König struct amdgpu_vm *vm); 9298b4fb00bSChristian König int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, 9308b4fb00bSChristian König struct amdgpu_sync *sync); 9318b4fb00bSChristian König int amdgpu_vm_bo_update(struct amdgpu_device *adev, 9328b4fb00bSChristian König struct amdgpu_bo_va *bo_va, 93399e124f4SChristian König bool clear); 9348b4fb00bSChristian König void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 9358b4fb00bSChristian König struct amdgpu_bo *bo); 9368b4fb00bSChristian König struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 9378b4fb00bSChristian König struct amdgpu_bo *bo); 9388b4fb00bSChristian König struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 9398b4fb00bSChristian König struct amdgpu_vm *vm, 9408b4fb00bSChristian König struct amdgpu_bo *bo); 9418b4fb00bSChristian König int amdgpu_vm_bo_map(struct amdgpu_device *adev, 9428b4fb00bSChristian König struct amdgpu_bo_va *bo_va, 9438b4fb00bSChristian König uint64_t addr, uint64_t offset, 9448b4fb00bSChristian König uint64_t size, uint32_t flags); 9458b4fb00bSChristian König int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 9468b4fb00bSChristian König struct amdgpu_bo_va *bo_va, 9478b4fb00bSChristian König uint64_t addr); 9488b4fb00bSChristian König void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 9498b4fb00bSChristian König struct amdgpu_bo_va *bo_va); 9508b4fb00bSChristian König 95197b2e202SAlex Deucher /* 95297b2e202SAlex Deucher * context related structures 95397b2e202SAlex Deucher */ 95497b2e202SAlex Deucher 95521c16bf6SChristian König struct amdgpu_ctx_ring { 95621c16bf6SChristian König uint64_t sequence; 95737cd0ca2SChunming Zhou struct fence **fences; 95891404fb2SChristian König struct amd_sched_entity entity; 95921c16bf6SChristian König }; 96021c16bf6SChristian König 96197b2e202SAlex Deucher struct amdgpu_ctx { 96297b2e202SAlex Deucher struct kref refcount; 9639cb7e5a9SChunming Zhou struct amdgpu_device *adev; 964d94aed5aSMarek Olšák unsigned reset_counter; 96521c16bf6SChristian König spinlock_t ring_lock; 96637cd0ca2SChunming Zhou struct fence **fences; 96721c16bf6SChristian König struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 96897b2e202SAlex Deucher }; 96997b2e202SAlex Deucher 97097b2e202SAlex Deucher struct amdgpu_ctx_mgr { 97197b2e202SAlex Deucher struct amdgpu_device *adev; 9720147ee0fSMarek Olšák struct mutex lock; 9730b492a4cSAlex Deucher /* protected by lock */ 9740b492a4cSAlex Deucher struct idr ctx_handles; 97597b2e202SAlex Deucher }; 97697b2e202SAlex Deucher 9770b492a4cSAlex Deucher struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 9780b492a4cSAlex Deucher int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 9790b492a4cSAlex Deucher 98021c16bf6SChristian König uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 981ce882e6dSChristian König struct fence *fence); 98221c16bf6SChristian König struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 98321c16bf6SChristian König struct amdgpu_ring *ring, uint64_t seq); 98421c16bf6SChristian König 9850b492a4cSAlex Deucher int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 9860b492a4cSAlex Deucher struct drm_file *filp); 9870b492a4cSAlex Deucher 988efd4ccb5SChristian König void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 989efd4ccb5SChristian König void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 9900b492a4cSAlex Deucher 99197b2e202SAlex Deucher /* 99297b2e202SAlex Deucher * file private structure 99397b2e202SAlex Deucher */ 99497b2e202SAlex Deucher 99597b2e202SAlex Deucher struct amdgpu_fpriv { 99697b2e202SAlex Deucher struct amdgpu_vm vm; 99797b2e202SAlex Deucher struct mutex bo_list_lock; 99897b2e202SAlex Deucher struct idr bo_list_handles; 99997b2e202SAlex Deucher struct amdgpu_ctx_mgr ctx_mgr; 100097b2e202SAlex Deucher }; 100197b2e202SAlex Deucher 100297b2e202SAlex Deucher /* 100397b2e202SAlex Deucher * residency list 100497b2e202SAlex Deucher */ 100597b2e202SAlex Deucher 100697b2e202SAlex Deucher struct amdgpu_bo_list { 100797b2e202SAlex Deucher struct mutex lock; 100897b2e202SAlex Deucher struct amdgpu_bo *gds_obj; 100997b2e202SAlex Deucher struct amdgpu_bo *gws_obj; 101097b2e202SAlex Deucher struct amdgpu_bo *oa_obj; 1011211dff55SChristian König unsigned first_userptr; 101297b2e202SAlex Deucher unsigned num_entries; 101397b2e202SAlex Deucher struct amdgpu_bo_list_entry *array; 101497b2e202SAlex Deucher }; 101597b2e202SAlex Deucher 101697b2e202SAlex Deucher struct amdgpu_bo_list * 101797b2e202SAlex Deucher amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1018636ce25cSChristian König void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 1019636ce25cSChristian König struct list_head *validated); 102097b2e202SAlex Deucher void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 102197b2e202SAlex Deucher void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 102297b2e202SAlex Deucher 102397b2e202SAlex Deucher /* 102497b2e202SAlex Deucher * GFX stuff 102597b2e202SAlex Deucher */ 102697b2e202SAlex Deucher #include "clearstate_defs.h" 102797b2e202SAlex Deucher 102879e5412cSAlex Deucher struct amdgpu_rlc_funcs { 102979e5412cSAlex Deucher void (*enter_safe_mode)(struct amdgpu_device *adev); 103079e5412cSAlex Deucher void (*exit_safe_mode)(struct amdgpu_device *adev); 103179e5412cSAlex Deucher }; 103279e5412cSAlex Deucher 103397b2e202SAlex Deucher struct amdgpu_rlc { 103497b2e202SAlex Deucher /* for power gating */ 103597b2e202SAlex Deucher struct amdgpu_bo *save_restore_obj; 103697b2e202SAlex Deucher uint64_t save_restore_gpu_addr; 103797b2e202SAlex Deucher volatile uint32_t *sr_ptr; 103897b2e202SAlex Deucher const u32 *reg_list; 103997b2e202SAlex Deucher u32 reg_list_size; 104097b2e202SAlex Deucher /* for clear state */ 104197b2e202SAlex Deucher struct amdgpu_bo *clear_state_obj; 104297b2e202SAlex Deucher uint64_t clear_state_gpu_addr; 104397b2e202SAlex Deucher volatile uint32_t *cs_ptr; 104497b2e202SAlex Deucher const struct cs_section_def *cs_data; 104597b2e202SAlex Deucher u32 clear_state_size; 104697b2e202SAlex Deucher /* for cp tables */ 104797b2e202SAlex Deucher struct amdgpu_bo *cp_table_obj; 104897b2e202SAlex Deucher uint64_t cp_table_gpu_addr; 104997b2e202SAlex Deucher volatile uint32_t *cp_table_ptr; 105097b2e202SAlex Deucher u32 cp_table_size; 105179e5412cSAlex Deucher 105279e5412cSAlex Deucher /* safe mode for updating CG/PG state */ 105379e5412cSAlex Deucher bool in_safe_mode; 105479e5412cSAlex Deucher const struct amdgpu_rlc_funcs *funcs; 10552b6cd977SEric Huang 10562b6cd977SEric Huang /* for firmware data */ 10572b6cd977SEric Huang u32 save_and_restore_offset; 10582b6cd977SEric Huang u32 clear_state_descriptor_offset; 10592b6cd977SEric Huang u32 avail_scratch_ram_locations; 10602b6cd977SEric Huang u32 reg_restore_list_size; 10612b6cd977SEric Huang u32 reg_list_format_start; 10622b6cd977SEric Huang u32 reg_list_format_separate_start; 10632b6cd977SEric Huang u32 starting_offsets_start; 10642b6cd977SEric Huang u32 reg_list_format_size_bytes; 10652b6cd977SEric Huang u32 reg_list_size_bytes; 10662b6cd977SEric Huang 10672b6cd977SEric Huang u32 *register_list_format; 10682b6cd977SEric Huang u32 *register_restore; 106997b2e202SAlex Deucher }; 107097b2e202SAlex Deucher 107197b2e202SAlex Deucher struct amdgpu_mec { 107297b2e202SAlex Deucher struct amdgpu_bo *hpd_eop_obj; 107397b2e202SAlex Deucher u64 hpd_eop_gpu_addr; 107497b2e202SAlex Deucher u32 num_pipe; 107597b2e202SAlex Deucher u32 num_mec; 107697b2e202SAlex Deucher u32 num_queue; 107797b2e202SAlex Deucher }; 107897b2e202SAlex Deucher 107997b2e202SAlex Deucher /* 108097b2e202SAlex Deucher * GPU scratch registers structures, functions & helpers 108197b2e202SAlex Deucher */ 108297b2e202SAlex Deucher struct amdgpu_scratch { 108397b2e202SAlex Deucher unsigned num_reg; 108497b2e202SAlex Deucher uint32_t reg_base; 108597b2e202SAlex Deucher bool free[32]; 108697b2e202SAlex Deucher uint32_t reg[32]; 108797b2e202SAlex Deucher }; 108897b2e202SAlex Deucher 108997b2e202SAlex Deucher /* 109097b2e202SAlex Deucher * GFX configurations 109197b2e202SAlex Deucher */ 109297b2e202SAlex Deucher struct amdgpu_gca_config { 109397b2e202SAlex Deucher unsigned max_shader_engines; 109497b2e202SAlex Deucher unsigned max_tile_pipes; 109597b2e202SAlex Deucher unsigned max_cu_per_sh; 109697b2e202SAlex Deucher unsigned max_sh_per_se; 109797b2e202SAlex Deucher unsigned max_backends_per_se; 109897b2e202SAlex Deucher unsigned max_texture_channel_caches; 109997b2e202SAlex Deucher unsigned max_gprs; 110097b2e202SAlex Deucher unsigned max_gs_threads; 110197b2e202SAlex Deucher unsigned max_hw_contexts; 110297b2e202SAlex Deucher unsigned sc_prim_fifo_size_frontend; 110397b2e202SAlex Deucher unsigned sc_prim_fifo_size_backend; 110497b2e202SAlex Deucher unsigned sc_hiz_tile_fifo_size; 110597b2e202SAlex Deucher unsigned sc_earlyz_tile_fifo_size; 110697b2e202SAlex Deucher 110797b2e202SAlex Deucher unsigned num_tile_pipes; 110897b2e202SAlex Deucher unsigned backend_enable_mask; 110997b2e202SAlex Deucher unsigned mem_max_burst_length_bytes; 111097b2e202SAlex Deucher unsigned mem_row_size_in_kb; 111197b2e202SAlex Deucher unsigned shader_engine_tile_size; 111297b2e202SAlex Deucher unsigned num_gpus; 111397b2e202SAlex Deucher unsigned multi_gpu_tile_size; 111497b2e202SAlex Deucher unsigned mc_arb_ramcfg; 111597b2e202SAlex Deucher unsigned gb_addr_config; 11168f8e00c1SAlex Deucher unsigned num_rbs; 111797b2e202SAlex Deucher 111897b2e202SAlex Deucher uint32_t tile_mode_array[32]; 111997b2e202SAlex Deucher uint32_t macrotile_mode_array[16]; 112097b2e202SAlex Deucher }; 112197b2e202SAlex Deucher 11227dae69a2SAlex Deucher struct amdgpu_cu_info { 11237dae69a2SAlex Deucher uint32_t number; /* total active CU number */ 11247dae69a2SAlex Deucher uint32_t ao_cu_mask; 11257dae69a2SAlex Deucher uint32_t bitmap[4][4]; 11267dae69a2SAlex Deucher }; 11277dae69a2SAlex Deucher 1128b95e31fdSAlex Deucher struct amdgpu_gfx_funcs { 1129b95e31fdSAlex Deucher /* get the gpu clock counter */ 1130b95e31fdSAlex Deucher uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 11319559ef5bSTom St Denis void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 1132b95e31fdSAlex Deucher }; 1133b95e31fdSAlex Deucher 113497b2e202SAlex Deucher struct amdgpu_gfx { 113597b2e202SAlex Deucher struct mutex gpu_clock_mutex; 113697b2e202SAlex Deucher struct amdgpu_gca_config config; 113797b2e202SAlex Deucher struct amdgpu_rlc rlc; 113897b2e202SAlex Deucher struct amdgpu_mec mec; 113997b2e202SAlex Deucher struct amdgpu_scratch scratch; 114097b2e202SAlex Deucher const struct firmware *me_fw; /* ME firmware */ 114197b2e202SAlex Deucher uint32_t me_fw_version; 114297b2e202SAlex Deucher const struct firmware *pfp_fw; /* PFP firmware */ 114397b2e202SAlex Deucher uint32_t pfp_fw_version; 114497b2e202SAlex Deucher const struct firmware *ce_fw; /* CE firmware */ 114597b2e202SAlex Deucher uint32_t ce_fw_version; 114697b2e202SAlex Deucher const struct firmware *rlc_fw; /* RLC firmware */ 114797b2e202SAlex Deucher uint32_t rlc_fw_version; 114897b2e202SAlex Deucher const struct firmware *mec_fw; /* MEC firmware */ 114997b2e202SAlex Deucher uint32_t mec_fw_version; 115097b2e202SAlex Deucher const struct firmware *mec2_fw; /* MEC2 firmware */ 115197b2e202SAlex Deucher uint32_t mec2_fw_version; 115202558a00SKen Wang uint32_t me_feature_version; 115302558a00SKen Wang uint32_t ce_feature_version; 115402558a00SKen Wang uint32_t pfp_feature_version; 1155351643d7SJammy Zhou uint32_t rlc_feature_version; 1156351643d7SJammy Zhou uint32_t mec_feature_version; 1157351643d7SJammy Zhou uint32_t mec2_feature_version; 115897b2e202SAlex Deucher struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 115997b2e202SAlex Deucher unsigned num_gfx_rings; 116097b2e202SAlex Deucher struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 116197b2e202SAlex Deucher unsigned num_compute_rings; 116297b2e202SAlex Deucher struct amdgpu_irq_src eop_irq; 116397b2e202SAlex Deucher struct amdgpu_irq_src priv_reg_irq; 116497b2e202SAlex Deucher struct amdgpu_irq_src priv_inst_irq; 116597b2e202SAlex Deucher /* gfx status */ 116697b2e202SAlex Deucher uint32_t gfx_current_status; 1167a101a899SKen Wang /* ce ram size*/ 1168a101a899SKen Wang unsigned ce_ram_size; 11697dae69a2SAlex Deucher struct amdgpu_cu_info cu_info; 1170b95e31fdSAlex Deucher const struct amdgpu_gfx_funcs *funcs; 11713d7c6384SChunming Zhou 11723d7c6384SChunming Zhou /* reset mask */ 11733d7c6384SChunming Zhou uint32_t grbm_soft_reset; 11743d7c6384SChunming Zhou uint32_t srbm_soft_reset; 117597b2e202SAlex Deucher }; 117697b2e202SAlex Deucher 1177b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 117897b2e202SAlex Deucher unsigned size, struct amdgpu_ib *ib); 11794d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 11804d9c514dSChristian König struct fence *f); 1181b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 1182336d1f5eSChristian König struct amdgpu_ib *ib, struct fence *last_vm_update, 1183c5637837SMonk Liu struct amdgpu_job *job, struct fence **f); 118497b2e202SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev); 118597b2e202SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 118697b2e202SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 118797b2e202SAlex Deucher int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1188edff0e28SJammy Zhou void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 11899e5d5309SChristian König void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 119097b2e202SAlex Deucher void amdgpu_ring_commit(struct amdgpu_ring *ring); 119197b2e202SAlex Deucher void amdgpu_ring_undo(struct amdgpu_ring *ring); 119297b2e202SAlex Deucher int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 119397b2e202SAlex Deucher unsigned ring_size, u32 nop, u32 align_mask, 119497b2e202SAlex Deucher struct amdgpu_irq_src *irq_src, unsigned irq_type, 119597b2e202SAlex Deucher enum amdgpu_ring_type ring_type); 119697b2e202SAlex Deucher void amdgpu_ring_fini(struct amdgpu_ring *ring); 119797b2e202SAlex Deucher 119897b2e202SAlex Deucher /* 119997b2e202SAlex Deucher * CS. 120097b2e202SAlex Deucher */ 120197b2e202SAlex Deucher struct amdgpu_cs_chunk { 120297b2e202SAlex Deucher uint32_t chunk_id; 120397b2e202SAlex Deucher uint32_t length_dw; 1204758ac17fSChristian König void *kdata; 120597b2e202SAlex Deucher }; 120697b2e202SAlex Deucher 120797b2e202SAlex Deucher struct amdgpu_cs_parser { 120897b2e202SAlex Deucher struct amdgpu_device *adev; 120997b2e202SAlex Deucher struct drm_file *filp; 12103cb485f3SChristian König struct amdgpu_ctx *ctx; 1211c3cca41eSChristian König 121297b2e202SAlex Deucher /* chunks */ 121397b2e202SAlex Deucher unsigned nchunks; 121497b2e202SAlex Deucher struct amdgpu_cs_chunk *chunks; 1215c3cca41eSChristian König 121650838c8cSChristian König /* scheduler job object */ 121750838c8cSChristian König struct amdgpu_job *job; 1218c3cca41eSChristian König 1219c3cca41eSChristian König /* buffer objects */ 1220c3cca41eSChristian König struct ww_acquire_ctx ticket; 1221c3cca41eSChristian König struct amdgpu_bo_list *bo_list; 122256467ebfSChristian König struct amdgpu_bo_list_entry vm_pd; 122397b2e202SAlex Deucher struct list_head validated; 1224984810fcSChristian König struct fence *fence; 1225f69f90a1SChristian König uint64_t bytes_moved_threshold; 1226f69f90a1SChristian König uint64_t bytes_moved; 122797b2e202SAlex Deucher 122897b2e202SAlex Deucher /* user fence */ 122991acbeb6SChristian König struct amdgpu_bo_list_entry uf_entry; 123097b2e202SAlex Deucher }; 123197b2e202SAlex Deucher 1232bb977d37SChunming Zhou struct amdgpu_job { 1233bb977d37SChunming Zhou struct amd_sched_job base; 1234bb977d37SChunming Zhou struct amdgpu_device *adev; 1235c5637837SMonk Liu struct amdgpu_vm *vm; 1236b07c60c0SChristian König struct amdgpu_ring *ring; 1237e86f9ceeSChristian König struct amdgpu_sync sync; 1238bb977d37SChunming Zhou struct amdgpu_ib *ibs; 123973cfa5f5SMonk Liu struct fence *fence; /* the hw fence */ 1240bb977d37SChunming Zhou uint32_t num_ibs; 1241e2840221SChristian König void *owner; 124292f25098SChristian König uint64_t ctx; 1243fd53be30SChunming Zhou bool vm_needs_flush; 1244d88bf583SChristian König unsigned vm_id; 1245d88bf583SChristian König uint64_t vm_pd_addr; 1246d88bf583SChristian König uint32_t gds_base, gds_size; 1247d88bf583SChristian König uint32_t gws_base, gws_size; 1248d88bf583SChristian König uint32_t oa_base, oa_size; 1249758ac17fSChristian König 1250758ac17fSChristian König /* user fence handling */ 1251b5f5acbcSChristian König uint64_t uf_addr; 1252758ac17fSChristian König uint64_t uf_sequence; 1253758ac17fSChristian König 1254bb977d37SChunming Zhou }; 1255a6db8a33SJunwei Zhang #define to_amdgpu_job(sched_job) \ 1256a6db8a33SJunwei Zhang container_of((sched_job), struct amdgpu_job, base) 1257bb977d37SChunming Zhou 12587270f839SChristian König static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 12597270f839SChristian König uint32_t ib_idx, int idx) 126097b2e202SAlex Deucher { 126150838c8cSChristian König return p->job->ibs[ib_idx].ptr[idx]; 126297b2e202SAlex Deucher } 126397b2e202SAlex Deucher 12647270f839SChristian König static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 12657270f839SChristian König uint32_t ib_idx, int idx, 12667270f839SChristian König uint32_t value) 12677270f839SChristian König { 126850838c8cSChristian König p->job->ibs[ib_idx].ptr[idx] = value; 12697270f839SChristian König } 12707270f839SChristian König 127197b2e202SAlex Deucher /* 127297b2e202SAlex Deucher * Writeback 127397b2e202SAlex Deucher */ 127497b2e202SAlex Deucher #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 127597b2e202SAlex Deucher 127697b2e202SAlex Deucher struct amdgpu_wb { 127797b2e202SAlex Deucher struct amdgpu_bo *wb_obj; 127897b2e202SAlex Deucher volatile uint32_t *wb; 127997b2e202SAlex Deucher uint64_t gpu_addr; 128097b2e202SAlex Deucher u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 128197b2e202SAlex Deucher unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 128297b2e202SAlex Deucher }; 128397b2e202SAlex Deucher 128497b2e202SAlex Deucher int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 128597b2e202SAlex Deucher void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 128697b2e202SAlex Deucher 128797b2e202SAlex Deucher 128897b2e202SAlex Deucher 128997b2e202SAlex Deucher enum amdgpu_int_thermal_type { 129097b2e202SAlex Deucher THERMAL_TYPE_NONE, 129197b2e202SAlex Deucher THERMAL_TYPE_EXTERNAL, 129297b2e202SAlex Deucher THERMAL_TYPE_EXTERNAL_GPIO, 129397b2e202SAlex Deucher THERMAL_TYPE_RV6XX, 129497b2e202SAlex Deucher THERMAL_TYPE_RV770, 129597b2e202SAlex Deucher THERMAL_TYPE_ADT7473_WITH_INTERNAL, 129697b2e202SAlex Deucher THERMAL_TYPE_EVERGREEN, 129797b2e202SAlex Deucher THERMAL_TYPE_SUMO, 129897b2e202SAlex Deucher THERMAL_TYPE_NI, 129997b2e202SAlex Deucher THERMAL_TYPE_SI, 130097b2e202SAlex Deucher THERMAL_TYPE_EMC2103_WITH_INTERNAL, 130197b2e202SAlex Deucher THERMAL_TYPE_CI, 130297b2e202SAlex Deucher THERMAL_TYPE_KV, 130397b2e202SAlex Deucher }; 130497b2e202SAlex Deucher 130597b2e202SAlex Deucher enum amdgpu_dpm_auto_throttle_src { 130697b2e202SAlex Deucher AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 130797b2e202SAlex Deucher AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 130897b2e202SAlex Deucher }; 130997b2e202SAlex Deucher 131097b2e202SAlex Deucher enum amdgpu_dpm_event_src { 131197b2e202SAlex Deucher AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 131297b2e202SAlex Deucher AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 131397b2e202SAlex Deucher AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 131497b2e202SAlex Deucher AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 131597b2e202SAlex Deucher AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 131697b2e202SAlex Deucher }; 131797b2e202SAlex Deucher 131897b2e202SAlex Deucher #define AMDGPU_MAX_VCE_LEVELS 6 131997b2e202SAlex Deucher 132097b2e202SAlex Deucher enum amdgpu_vce_level { 132197b2e202SAlex Deucher AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 132297b2e202SAlex Deucher AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 132397b2e202SAlex Deucher AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 132497b2e202SAlex Deucher AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 132597b2e202SAlex Deucher AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 132697b2e202SAlex Deucher AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 132797b2e202SAlex Deucher }; 132897b2e202SAlex Deucher 132997b2e202SAlex Deucher struct amdgpu_ps { 133097b2e202SAlex Deucher u32 caps; /* vbios flags */ 133197b2e202SAlex Deucher u32 class; /* vbios flags */ 133297b2e202SAlex Deucher u32 class2; /* vbios flags */ 133397b2e202SAlex Deucher /* UVD clocks */ 133497b2e202SAlex Deucher u32 vclk; 133597b2e202SAlex Deucher u32 dclk; 133697b2e202SAlex Deucher /* VCE clocks */ 133797b2e202SAlex Deucher u32 evclk; 133897b2e202SAlex Deucher u32 ecclk; 133997b2e202SAlex Deucher bool vce_active; 134097b2e202SAlex Deucher enum amdgpu_vce_level vce_level; 134197b2e202SAlex Deucher /* asic priv */ 134297b2e202SAlex Deucher void *ps_priv; 134397b2e202SAlex Deucher }; 134497b2e202SAlex Deucher 134597b2e202SAlex Deucher struct amdgpu_dpm_thermal { 134697b2e202SAlex Deucher /* thermal interrupt work */ 134797b2e202SAlex Deucher struct work_struct work; 134897b2e202SAlex Deucher /* low temperature threshold */ 134997b2e202SAlex Deucher int min_temp; 135097b2e202SAlex Deucher /* high temperature threshold */ 135197b2e202SAlex Deucher int max_temp; 135297b2e202SAlex Deucher /* was last interrupt low to high or high to low */ 135397b2e202SAlex Deucher bool high_to_low; 135497b2e202SAlex Deucher /* interrupt source */ 135597b2e202SAlex Deucher struct amdgpu_irq_src irq; 135697b2e202SAlex Deucher }; 135797b2e202SAlex Deucher 135897b2e202SAlex Deucher enum amdgpu_clk_action 135997b2e202SAlex Deucher { 136097b2e202SAlex Deucher AMDGPU_SCLK_UP = 1, 136197b2e202SAlex Deucher AMDGPU_SCLK_DOWN 136297b2e202SAlex Deucher }; 136397b2e202SAlex Deucher 136497b2e202SAlex Deucher struct amdgpu_blacklist_clocks 136597b2e202SAlex Deucher { 136697b2e202SAlex Deucher u32 sclk; 136797b2e202SAlex Deucher u32 mclk; 136897b2e202SAlex Deucher enum amdgpu_clk_action action; 136997b2e202SAlex Deucher }; 137097b2e202SAlex Deucher 137197b2e202SAlex Deucher struct amdgpu_clock_and_voltage_limits { 137297b2e202SAlex Deucher u32 sclk; 137397b2e202SAlex Deucher u32 mclk; 137497b2e202SAlex Deucher u16 vddc; 137597b2e202SAlex Deucher u16 vddci; 137697b2e202SAlex Deucher }; 137797b2e202SAlex Deucher 137897b2e202SAlex Deucher struct amdgpu_clock_array { 137997b2e202SAlex Deucher u32 count; 138097b2e202SAlex Deucher u32 *values; 138197b2e202SAlex Deucher }; 138297b2e202SAlex Deucher 138397b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_entry { 138497b2e202SAlex Deucher u32 clk; 138597b2e202SAlex Deucher u16 v; 138697b2e202SAlex Deucher }; 138797b2e202SAlex Deucher 138897b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table { 138997b2e202SAlex Deucher u32 count; 139097b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_entry *entries; 139197b2e202SAlex Deucher }; 139297b2e202SAlex Deucher 139397b2e202SAlex Deucher union amdgpu_cac_leakage_entry { 139497b2e202SAlex Deucher struct { 139597b2e202SAlex Deucher u16 vddc; 139697b2e202SAlex Deucher u32 leakage; 139797b2e202SAlex Deucher }; 139897b2e202SAlex Deucher struct { 139997b2e202SAlex Deucher u16 vddc1; 140097b2e202SAlex Deucher u16 vddc2; 140197b2e202SAlex Deucher u16 vddc3; 140297b2e202SAlex Deucher }; 140397b2e202SAlex Deucher }; 140497b2e202SAlex Deucher 140597b2e202SAlex Deucher struct amdgpu_cac_leakage_table { 140697b2e202SAlex Deucher u32 count; 140797b2e202SAlex Deucher union amdgpu_cac_leakage_entry *entries; 140897b2e202SAlex Deucher }; 140997b2e202SAlex Deucher 141097b2e202SAlex Deucher struct amdgpu_phase_shedding_limits_entry { 141197b2e202SAlex Deucher u16 voltage; 141297b2e202SAlex Deucher u32 sclk; 141397b2e202SAlex Deucher u32 mclk; 141497b2e202SAlex Deucher }; 141597b2e202SAlex Deucher 141697b2e202SAlex Deucher struct amdgpu_phase_shedding_limits_table { 141797b2e202SAlex Deucher u32 count; 141897b2e202SAlex Deucher struct amdgpu_phase_shedding_limits_entry *entries; 141997b2e202SAlex Deucher }; 142097b2e202SAlex Deucher 142197b2e202SAlex Deucher struct amdgpu_uvd_clock_voltage_dependency_entry { 142297b2e202SAlex Deucher u32 vclk; 142397b2e202SAlex Deucher u32 dclk; 142497b2e202SAlex Deucher u16 v; 142597b2e202SAlex Deucher }; 142697b2e202SAlex Deucher 142797b2e202SAlex Deucher struct amdgpu_uvd_clock_voltage_dependency_table { 142897b2e202SAlex Deucher u8 count; 142997b2e202SAlex Deucher struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 143097b2e202SAlex Deucher }; 143197b2e202SAlex Deucher 143297b2e202SAlex Deucher struct amdgpu_vce_clock_voltage_dependency_entry { 143397b2e202SAlex Deucher u32 ecclk; 143497b2e202SAlex Deucher u32 evclk; 143597b2e202SAlex Deucher u16 v; 143697b2e202SAlex Deucher }; 143797b2e202SAlex Deucher 143897b2e202SAlex Deucher struct amdgpu_vce_clock_voltage_dependency_table { 143997b2e202SAlex Deucher u8 count; 144097b2e202SAlex Deucher struct amdgpu_vce_clock_voltage_dependency_entry *entries; 144197b2e202SAlex Deucher }; 144297b2e202SAlex Deucher 144397b2e202SAlex Deucher struct amdgpu_ppm_table { 144497b2e202SAlex Deucher u8 ppm_design; 144597b2e202SAlex Deucher u16 cpu_core_number; 144697b2e202SAlex Deucher u32 platform_tdp; 144797b2e202SAlex Deucher u32 small_ac_platform_tdp; 144897b2e202SAlex Deucher u32 platform_tdc; 144997b2e202SAlex Deucher u32 small_ac_platform_tdc; 145097b2e202SAlex Deucher u32 apu_tdp; 145197b2e202SAlex Deucher u32 dgpu_tdp; 145297b2e202SAlex Deucher u32 dgpu_ulv_power; 145397b2e202SAlex Deucher u32 tj_max; 145497b2e202SAlex Deucher }; 145597b2e202SAlex Deucher 145697b2e202SAlex Deucher struct amdgpu_cac_tdp_table { 145797b2e202SAlex Deucher u16 tdp; 145897b2e202SAlex Deucher u16 configurable_tdp; 145997b2e202SAlex Deucher u16 tdc; 146097b2e202SAlex Deucher u16 battery_power_limit; 146197b2e202SAlex Deucher u16 small_power_limit; 146297b2e202SAlex Deucher u16 low_cac_leakage; 146397b2e202SAlex Deucher u16 high_cac_leakage; 146497b2e202SAlex Deucher u16 maximum_power_delivery_limit; 146597b2e202SAlex Deucher }; 146697b2e202SAlex Deucher 146797b2e202SAlex Deucher struct amdgpu_dpm_dynamic_state { 146897b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 146997b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 147097b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 147197b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 147297b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 147397b2e202SAlex Deucher struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 147497b2e202SAlex Deucher struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 147597b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 147697b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 147797b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 147897b2e202SAlex Deucher struct amdgpu_clock_array valid_sclk_values; 147997b2e202SAlex Deucher struct amdgpu_clock_array valid_mclk_values; 148097b2e202SAlex Deucher struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 148197b2e202SAlex Deucher struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 148297b2e202SAlex Deucher u32 mclk_sclk_ratio; 148397b2e202SAlex Deucher u32 sclk_mclk_delta; 148497b2e202SAlex Deucher u16 vddc_vddci_delta; 148597b2e202SAlex Deucher u16 min_vddc_for_pcie_gen2; 148697b2e202SAlex Deucher struct amdgpu_cac_leakage_table cac_leakage_table; 148797b2e202SAlex Deucher struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 148897b2e202SAlex Deucher struct amdgpu_ppm_table *ppm_table; 148997b2e202SAlex Deucher struct amdgpu_cac_tdp_table *cac_tdp_table; 149097b2e202SAlex Deucher }; 149197b2e202SAlex Deucher 149297b2e202SAlex Deucher struct amdgpu_dpm_fan { 149397b2e202SAlex Deucher u16 t_min; 149497b2e202SAlex Deucher u16 t_med; 149597b2e202SAlex Deucher u16 t_high; 149697b2e202SAlex Deucher u16 pwm_min; 149797b2e202SAlex Deucher u16 pwm_med; 149897b2e202SAlex Deucher u16 pwm_high; 149997b2e202SAlex Deucher u8 t_hyst; 150097b2e202SAlex Deucher u32 cycle_delay; 150197b2e202SAlex Deucher u16 t_max; 150297b2e202SAlex Deucher u8 control_mode; 150397b2e202SAlex Deucher u16 default_max_fan_pwm; 150497b2e202SAlex Deucher u16 default_fan_output_sensitivity; 150597b2e202SAlex Deucher u16 fan_output_sensitivity; 150697b2e202SAlex Deucher bool ucode_fan_control; 150797b2e202SAlex Deucher }; 150897b2e202SAlex Deucher 150997b2e202SAlex Deucher enum amdgpu_pcie_gen { 151097b2e202SAlex Deucher AMDGPU_PCIE_GEN1 = 0, 151197b2e202SAlex Deucher AMDGPU_PCIE_GEN2 = 1, 151297b2e202SAlex Deucher AMDGPU_PCIE_GEN3 = 2, 151397b2e202SAlex Deucher AMDGPU_PCIE_GEN_INVALID = 0xffff 151497b2e202SAlex Deucher }; 151597b2e202SAlex Deucher 151697b2e202SAlex Deucher enum amdgpu_dpm_forced_level { 151797b2e202SAlex Deucher AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 151897b2e202SAlex Deucher AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 151997b2e202SAlex Deucher AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1520f3898ea1SEric Huang AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3, 152197b2e202SAlex Deucher }; 152297b2e202SAlex Deucher 152397b2e202SAlex Deucher struct amdgpu_vce_state { 152497b2e202SAlex Deucher /* vce clocks */ 152597b2e202SAlex Deucher u32 evclk; 152697b2e202SAlex Deucher u32 ecclk; 152797b2e202SAlex Deucher /* gpu clocks */ 152897b2e202SAlex Deucher u32 sclk; 152997b2e202SAlex Deucher u32 mclk; 153097b2e202SAlex Deucher u8 clk_idx; 153197b2e202SAlex Deucher u8 pstate; 153297b2e202SAlex Deucher }; 153397b2e202SAlex Deucher 153497b2e202SAlex Deucher struct amdgpu_dpm_funcs { 153597b2e202SAlex Deucher int (*get_temperature)(struct amdgpu_device *adev); 153697b2e202SAlex Deucher int (*pre_set_power_state)(struct amdgpu_device *adev); 153797b2e202SAlex Deucher int (*set_power_state)(struct amdgpu_device *adev); 153897b2e202SAlex Deucher void (*post_set_power_state)(struct amdgpu_device *adev); 153997b2e202SAlex Deucher void (*display_configuration_changed)(struct amdgpu_device *adev); 154097b2e202SAlex Deucher u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 154197b2e202SAlex Deucher u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 154297b2e202SAlex Deucher void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 154397b2e202SAlex Deucher void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 154497b2e202SAlex Deucher int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 154597b2e202SAlex Deucher bool (*vblank_too_short)(struct amdgpu_device *adev); 154697b2e202SAlex Deucher void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1547b7a07769SSonny Jiang void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 154897b2e202SAlex Deucher void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 154997b2e202SAlex Deucher void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 155097b2e202SAlex Deucher u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 155197b2e202SAlex Deucher int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 155297b2e202SAlex Deucher int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1553c85e299fSEric Huang int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask); 1554c85e299fSEric Huang int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf); 15558b2e574dSEric Huang int (*get_sclk_od)(struct amdgpu_device *adev); 15568b2e574dSEric Huang int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value); 1557f2bdc05fSEric Huang int (*get_mclk_od)(struct amdgpu_device *adev); 1558f2bdc05fSEric Huang int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value); 155997b2e202SAlex Deucher }; 156097b2e202SAlex Deucher 156197b2e202SAlex Deucher struct amdgpu_dpm { 156297b2e202SAlex Deucher struct amdgpu_ps *ps; 156397b2e202SAlex Deucher /* number of valid power states */ 156497b2e202SAlex Deucher int num_ps; 156597b2e202SAlex Deucher /* current power state that is active */ 156697b2e202SAlex Deucher struct amdgpu_ps *current_ps; 156797b2e202SAlex Deucher /* requested power state */ 156897b2e202SAlex Deucher struct amdgpu_ps *requested_ps; 156997b2e202SAlex Deucher /* boot up power state */ 157097b2e202SAlex Deucher struct amdgpu_ps *boot_ps; 157197b2e202SAlex Deucher /* default uvd power state */ 157297b2e202SAlex Deucher struct amdgpu_ps *uvd_ps; 157397b2e202SAlex Deucher /* vce requirements */ 157497b2e202SAlex Deucher struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 157597b2e202SAlex Deucher enum amdgpu_vce_level vce_level; 15763a2c788dSRex Zhu enum amd_pm_state_type state; 15773a2c788dSRex Zhu enum amd_pm_state_type user_state; 157897b2e202SAlex Deucher u32 platform_caps; 157997b2e202SAlex Deucher u32 voltage_response_time; 158097b2e202SAlex Deucher u32 backbias_response_time; 158197b2e202SAlex Deucher void *priv; 158297b2e202SAlex Deucher u32 new_active_crtcs; 158397b2e202SAlex Deucher int new_active_crtc_count; 158497b2e202SAlex Deucher u32 current_active_crtcs; 158597b2e202SAlex Deucher int current_active_crtc_count; 158697b2e202SAlex Deucher struct amdgpu_dpm_dynamic_state dyn_state; 158797b2e202SAlex Deucher struct amdgpu_dpm_fan fan; 158897b2e202SAlex Deucher u32 tdp_limit; 158997b2e202SAlex Deucher u32 near_tdp_limit; 159097b2e202SAlex Deucher u32 near_tdp_limit_adjusted; 159197b2e202SAlex Deucher u32 sq_ramping_threshold; 159297b2e202SAlex Deucher u32 cac_leakage; 159397b2e202SAlex Deucher u16 tdp_od_limit; 159497b2e202SAlex Deucher u32 tdp_adjustment; 159597b2e202SAlex Deucher u16 load_line_slope; 159697b2e202SAlex Deucher bool power_control; 159797b2e202SAlex Deucher bool ac_power; 159897b2e202SAlex Deucher /* special states active */ 159997b2e202SAlex Deucher bool thermal_active; 160097b2e202SAlex Deucher bool uvd_active; 160197b2e202SAlex Deucher bool vce_active; 160297b2e202SAlex Deucher /* thermal handling */ 160397b2e202SAlex Deucher struct amdgpu_dpm_thermal thermal; 160497b2e202SAlex Deucher /* forced levels */ 160597b2e202SAlex Deucher enum amdgpu_dpm_forced_level forced_level; 160697b2e202SAlex Deucher }; 160797b2e202SAlex Deucher 160897b2e202SAlex Deucher struct amdgpu_pm { 160997b2e202SAlex Deucher struct mutex mutex; 161097b2e202SAlex Deucher u32 current_sclk; 161197b2e202SAlex Deucher u32 current_mclk; 161297b2e202SAlex Deucher u32 default_sclk; 161397b2e202SAlex Deucher u32 default_mclk; 161497b2e202SAlex Deucher struct amdgpu_i2c_chan *i2c_bus; 161597b2e202SAlex Deucher /* internal thermal controller on rv6xx+ */ 161697b2e202SAlex Deucher enum amdgpu_int_thermal_type int_thermal_type; 161797b2e202SAlex Deucher struct device *int_hwmon_dev; 161897b2e202SAlex Deucher /* fan control parameters */ 161997b2e202SAlex Deucher bool no_fan; 162097b2e202SAlex Deucher u8 fan_pulses_per_revolution; 162197b2e202SAlex Deucher u8 fan_min_rpm; 162297b2e202SAlex Deucher u8 fan_max_rpm; 162397b2e202SAlex Deucher /* dpm */ 162497b2e202SAlex Deucher bool dpm_enabled; 1625c86f5ebfSAlex Deucher bool sysfs_initialized; 162697b2e202SAlex Deucher struct amdgpu_dpm dpm; 162797b2e202SAlex Deucher const struct firmware *fw; /* SMC firmware */ 162897b2e202SAlex Deucher uint32_t fw_version; 162997b2e202SAlex Deucher const struct amdgpu_dpm_funcs *funcs; 1630d0dd7f0cSAlex Deucher uint32_t pcie_gen_mask; 1631d0dd7f0cSAlex Deucher uint32_t pcie_mlw_mask; 16327fb72a1fSRex Zhu struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ 163397b2e202SAlex Deucher }; 163497b2e202SAlex Deucher 1635d0dd7f0cSAlex Deucher void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1636d0dd7f0cSAlex Deucher 163797b2e202SAlex Deucher /* 163897b2e202SAlex Deucher * UVD 163997b2e202SAlex Deucher */ 1640c0365541SArindam Nath #define AMDGPU_DEFAULT_UVD_HANDLES 10 1641c0365541SArindam Nath #define AMDGPU_MAX_UVD_HANDLES 40 1642c0365541SArindam Nath #define AMDGPU_UVD_STACK_SIZE (200*1024) 1643c0365541SArindam Nath #define AMDGPU_UVD_HEAP_SIZE (256*1024) 1644c0365541SArindam Nath #define AMDGPU_UVD_SESSION_SIZE (50*1024) 164597b2e202SAlex Deucher #define AMDGPU_UVD_FIRMWARE_OFFSET 256 164697b2e202SAlex Deucher 164797b2e202SAlex Deucher struct amdgpu_uvd { 164897b2e202SAlex Deucher struct amdgpu_bo *vcpu_bo; 164997b2e202SAlex Deucher void *cpu_addr; 165097b2e202SAlex Deucher uint64_t gpu_addr; 1651562e2689SSonny Jiang unsigned fw_version; 16523f99dd81SLeo Liu void *saved_bo; 1653c0365541SArindam Nath unsigned max_handles; 165497b2e202SAlex Deucher atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 165597b2e202SAlex Deucher struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 165697b2e202SAlex Deucher struct delayed_work idle_work; 165797b2e202SAlex Deucher const struct firmware *fw; /* UVD firmware */ 165897b2e202SAlex Deucher struct amdgpu_ring ring; 165997b2e202SAlex Deucher struct amdgpu_irq_src irq; 166097b2e202SAlex Deucher bool address_64_bit; 16614cb5877cSChristian König bool use_ctx_buf; 1662ead833ecSChristian König struct amd_sched_entity entity; 1663fc0b3b90SChunming Zhou uint32_t srbm_soft_reset; 166497b2e202SAlex Deucher }; 166597b2e202SAlex Deucher 166697b2e202SAlex Deucher /* 166797b2e202SAlex Deucher * VCE 166897b2e202SAlex Deucher */ 166997b2e202SAlex Deucher #define AMDGPU_MAX_VCE_HANDLES 16 167097b2e202SAlex Deucher #define AMDGPU_VCE_FIRMWARE_OFFSET 256 167197b2e202SAlex Deucher 16726a585777SAlex Deucher #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 16736a585777SAlex Deucher #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 16746a585777SAlex Deucher 167597b2e202SAlex Deucher struct amdgpu_vce { 167697b2e202SAlex Deucher struct amdgpu_bo *vcpu_bo; 167797b2e202SAlex Deucher uint64_t gpu_addr; 167897b2e202SAlex Deucher unsigned fw_version; 167997b2e202SAlex Deucher unsigned fb_version; 168097b2e202SAlex Deucher atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 168197b2e202SAlex Deucher struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1682f1689ec1SChristian König uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 168397b2e202SAlex Deucher struct delayed_work idle_work; 1684ebff485eSChristian König struct mutex idle_mutex; 168597b2e202SAlex Deucher const struct firmware *fw; /* VCE firmware */ 168697b2e202SAlex Deucher struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 168797b2e202SAlex Deucher struct amdgpu_irq_src irq; 16886a585777SAlex Deucher unsigned harvest_config; 1689c594989cSChristian König struct amd_sched_entity entity; 1690115933a5SChunming Zhou uint32_t srbm_soft_reset; 169175c65480SAlex Deucher unsigned num_rings; 169297b2e202SAlex Deucher }; 169397b2e202SAlex Deucher 169497b2e202SAlex Deucher /* 169597b2e202SAlex Deucher * SDMA 169697b2e202SAlex Deucher */ 1697c113ea1cSAlex Deucher struct amdgpu_sdma_instance { 169897b2e202SAlex Deucher /* SDMA firmware */ 169997b2e202SAlex Deucher const struct firmware *fw; 170097b2e202SAlex Deucher uint32_t fw_version; 1701cfa2104fSJammy Zhou uint32_t feature_version; 170297b2e202SAlex Deucher 170397b2e202SAlex Deucher struct amdgpu_ring ring; 170418111de0SJammy Zhou bool burst_nop; 170597b2e202SAlex Deucher }; 170697b2e202SAlex Deucher 1707c113ea1cSAlex Deucher struct amdgpu_sdma { 1708c113ea1cSAlex Deucher struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1709c113ea1cSAlex Deucher struct amdgpu_irq_src trap_irq; 1710c113ea1cSAlex Deucher struct amdgpu_irq_src illegal_inst_irq; 1711c113ea1cSAlex Deucher int num_instances; 1712e702a680SChunming Zhou uint32_t srbm_soft_reset; 1713c113ea1cSAlex Deucher }; 1714c113ea1cSAlex Deucher 171597b2e202SAlex Deucher /* 171697b2e202SAlex Deucher * Firmware 171797b2e202SAlex Deucher */ 171897b2e202SAlex Deucher struct amdgpu_firmware { 171997b2e202SAlex Deucher struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 172097b2e202SAlex Deucher bool smu_load; 172197b2e202SAlex Deucher struct amdgpu_bo *fw_buf; 172297b2e202SAlex Deucher unsigned int fw_size; 172397b2e202SAlex Deucher }; 172497b2e202SAlex Deucher 172597b2e202SAlex Deucher /* 172697b2e202SAlex Deucher * Benchmarking 172797b2e202SAlex Deucher */ 172897b2e202SAlex Deucher void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 172997b2e202SAlex Deucher 173097b2e202SAlex Deucher 173197b2e202SAlex Deucher /* 173297b2e202SAlex Deucher * Testing 173397b2e202SAlex Deucher */ 173497b2e202SAlex Deucher void amdgpu_test_moves(struct amdgpu_device *adev); 173597b2e202SAlex Deucher void amdgpu_test_ring_sync(struct amdgpu_device *adev, 173697b2e202SAlex Deucher struct amdgpu_ring *cpA, 173797b2e202SAlex Deucher struct amdgpu_ring *cpB); 173897b2e202SAlex Deucher void amdgpu_test_syncing(struct amdgpu_device *adev); 173997b2e202SAlex Deucher 174097b2e202SAlex Deucher /* 174197b2e202SAlex Deucher * MMU Notifier 174297b2e202SAlex Deucher */ 174397b2e202SAlex Deucher #if defined(CONFIG_MMU_NOTIFIER) 174497b2e202SAlex Deucher int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 174597b2e202SAlex Deucher void amdgpu_mn_unregister(struct amdgpu_bo *bo); 174697b2e202SAlex Deucher #else 17471d1106b0SHarry Wentland static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 174897b2e202SAlex Deucher { 174997b2e202SAlex Deucher return -ENODEV; 175097b2e202SAlex Deucher } 17511d1106b0SHarry Wentland static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 175297b2e202SAlex Deucher #endif 175397b2e202SAlex Deucher 175497b2e202SAlex Deucher /* 175597b2e202SAlex Deucher * Debugfs 175697b2e202SAlex Deucher */ 175797b2e202SAlex Deucher struct amdgpu_debugfs { 175806ab6832SNils Wallménius const struct drm_info_list *files; 175997b2e202SAlex Deucher unsigned num_files; 176097b2e202SAlex Deucher }; 176197b2e202SAlex Deucher 176297b2e202SAlex Deucher int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 176306ab6832SNils Wallménius const struct drm_info_list *files, 176497b2e202SAlex Deucher unsigned nfiles); 176597b2e202SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 176697b2e202SAlex Deucher 176797b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS) 176897b2e202SAlex Deucher int amdgpu_debugfs_init(struct drm_minor *minor); 176997b2e202SAlex Deucher void amdgpu_debugfs_cleanup(struct drm_minor *minor); 177097b2e202SAlex Deucher #endif 177197b2e202SAlex Deucher 177250ab2533SHuang Rui int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); 177350ab2533SHuang Rui 177497b2e202SAlex Deucher /* 177597b2e202SAlex Deucher * amdgpu smumgr functions 177697b2e202SAlex Deucher */ 177797b2e202SAlex Deucher struct amdgpu_smumgr_funcs { 177897b2e202SAlex Deucher int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 177997b2e202SAlex Deucher int (*request_smu_load_fw)(struct amdgpu_device *adev); 178097b2e202SAlex Deucher int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 178197b2e202SAlex Deucher }; 178297b2e202SAlex Deucher 178397b2e202SAlex Deucher /* 178497b2e202SAlex Deucher * amdgpu smumgr 178597b2e202SAlex Deucher */ 178697b2e202SAlex Deucher struct amdgpu_smumgr { 178797b2e202SAlex Deucher struct amdgpu_bo *toc_buf; 178897b2e202SAlex Deucher struct amdgpu_bo *smu_buf; 178997b2e202SAlex Deucher /* asic priv smu data */ 179097b2e202SAlex Deucher void *priv; 179197b2e202SAlex Deucher spinlock_t smu_lock; 179297b2e202SAlex Deucher /* smumgr functions */ 179397b2e202SAlex Deucher const struct amdgpu_smumgr_funcs *smumgr_funcs; 179497b2e202SAlex Deucher /* ucode loading complete flag */ 179597b2e202SAlex Deucher uint32_t fw_flags; 179697b2e202SAlex Deucher }; 179797b2e202SAlex Deucher 179897b2e202SAlex Deucher /* 179997b2e202SAlex Deucher * ASIC specific register table accessible by UMD 180097b2e202SAlex Deucher */ 180197b2e202SAlex Deucher struct amdgpu_allowed_register_entry { 180297b2e202SAlex Deucher uint32_t reg_offset; 180397b2e202SAlex Deucher bool untouched; 180497b2e202SAlex Deucher bool grbm_indexed; 180597b2e202SAlex Deucher }; 180697b2e202SAlex Deucher 180797b2e202SAlex Deucher /* 180897b2e202SAlex Deucher * ASIC specific functions. 180997b2e202SAlex Deucher */ 181097b2e202SAlex Deucher struct amdgpu_asic_funcs { 181197b2e202SAlex Deucher bool (*read_disabled_bios)(struct amdgpu_device *adev); 18127946b878SAlex Deucher bool (*read_bios_from_rom)(struct amdgpu_device *adev, 18137946b878SAlex Deucher u8 *bios, u32 length_bytes); 181497b2e202SAlex Deucher int (*read_register)(struct amdgpu_device *adev, u32 se_num, 181597b2e202SAlex Deucher u32 sh_num, u32 reg_offset, u32 *value); 181697b2e202SAlex Deucher void (*set_vga_state)(struct amdgpu_device *adev, bool state); 181797b2e202SAlex Deucher int (*reset)(struct amdgpu_device *adev); 181897b2e202SAlex Deucher /* get the reference clock */ 181997b2e202SAlex Deucher u32 (*get_xclk)(struct amdgpu_device *adev); 182097b2e202SAlex Deucher /* MM block clocks */ 182197b2e202SAlex Deucher int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 182297b2e202SAlex Deucher int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1823048765adSAndres Rodriguez /* query virtual capabilities */ 1824048765adSAndres Rodriguez u32 (*get_virtual_caps)(struct amdgpu_device *adev); 182597b2e202SAlex Deucher }; 182697b2e202SAlex Deucher 182797b2e202SAlex Deucher /* 182897b2e202SAlex Deucher * IOCTL. 182997b2e202SAlex Deucher */ 183097b2e202SAlex Deucher int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 183197b2e202SAlex Deucher struct drm_file *filp); 183297b2e202SAlex Deucher int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 183397b2e202SAlex Deucher struct drm_file *filp); 183497b2e202SAlex Deucher 183597b2e202SAlex Deucher int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 183697b2e202SAlex Deucher struct drm_file *filp); 183797b2e202SAlex Deucher int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 183897b2e202SAlex Deucher struct drm_file *filp); 183997b2e202SAlex Deucher int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 184097b2e202SAlex Deucher struct drm_file *filp); 184197b2e202SAlex Deucher int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 184297b2e202SAlex Deucher struct drm_file *filp); 184397b2e202SAlex Deucher int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 184497b2e202SAlex Deucher struct drm_file *filp); 184597b2e202SAlex Deucher int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 184697b2e202SAlex Deucher struct drm_file *filp); 184797b2e202SAlex Deucher int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 184897b2e202SAlex Deucher int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 184997b2e202SAlex Deucher 185097b2e202SAlex Deucher int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 185197b2e202SAlex Deucher struct drm_file *filp); 185297b2e202SAlex Deucher 185397b2e202SAlex Deucher /* VRAM scratch page for HDP bug, default vram page */ 185497b2e202SAlex Deucher struct amdgpu_vram_scratch { 185597b2e202SAlex Deucher struct amdgpu_bo *robj; 185697b2e202SAlex Deucher volatile uint32_t *ptr; 185797b2e202SAlex Deucher u64 gpu_addr; 185897b2e202SAlex Deucher }; 185997b2e202SAlex Deucher 186097b2e202SAlex Deucher /* 186197b2e202SAlex Deucher * ACPI 186297b2e202SAlex Deucher */ 186397b2e202SAlex Deucher struct amdgpu_atif_notification_cfg { 186497b2e202SAlex Deucher bool enabled; 186597b2e202SAlex Deucher int command_code; 186697b2e202SAlex Deucher }; 186797b2e202SAlex Deucher 186897b2e202SAlex Deucher struct amdgpu_atif_notifications { 186997b2e202SAlex Deucher bool display_switch; 187097b2e202SAlex Deucher bool expansion_mode_change; 187197b2e202SAlex Deucher bool thermal_state; 187297b2e202SAlex Deucher bool forced_power_state; 187397b2e202SAlex Deucher bool system_power_state; 187497b2e202SAlex Deucher bool display_conf_change; 187597b2e202SAlex Deucher bool px_gfx_switch; 187697b2e202SAlex Deucher bool brightness_change; 187797b2e202SAlex Deucher bool dgpu_display_event; 187897b2e202SAlex Deucher }; 187997b2e202SAlex Deucher 188097b2e202SAlex Deucher struct amdgpu_atif_functions { 188197b2e202SAlex Deucher bool system_params; 188297b2e202SAlex Deucher bool sbios_requests; 188397b2e202SAlex Deucher bool select_active_disp; 188497b2e202SAlex Deucher bool lid_state; 188597b2e202SAlex Deucher bool get_tv_standard; 188697b2e202SAlex Deucher bool set_tv_standard; 188797b2e202SAlex Deucher bool get_panel_expansion_mode; 188897b2e202SAlex Deucher bool set_panel_expansion_mode; 188997b2e202SAlex Deucher bool temperature_change; 189097b2e202SAlex Deucher bool graphics_device_types; 189197b2e202SAlex Deucher }; 189297b2e202SAlex Deucher 189397b2e202SAlex Deucher struct amdgpu_atif { 189497b2e202SAlex Deucher struct amdgpu_atif_notifications notifications; 189597b2e202SAlex Deucher struct amdgpu_atif_functions functions; 189697b2e202SAlex Deucher struct amdgpu_atif_notification_cfg notification_cfg; 189797b2e202SAlex Deucher struct amdgpu_encoder *encoder_for_bl; 189897b2e202SAlex Deucher }; 189997b2e202SAlex Deucher 190097b2e202SAlex Deucher struct amdgpu_atcs_functions { 190197b2e202SAlex Deucher bool get_ext_state; 190297b2e202SAlex Deucher bool pcie_perf_req; 190397b2e202SAlex Deucher bool pcie_dev_rdy; 190497b2e202SAlex Deucher bool pcie_bus_width; 190597b2e202SAlex Deucher }; 190697b2e202SAlex Deucher 190797b2e202SAlex Deucher struct amdgpu_atcs { 190897b2e202SAlex Deucher struct amdgpu_atcs_functions functions; 190997b2e202SAlex Deucher }; 191097b2e202SAlex Deucher 191197b2e202SAlex Deucher /* 1912d03846afSChunming Zhou * CGS 1913d03846afSChunming Zhou */ 1914110e6f26SDave Airlie struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1915110e6f26SDave Airlie void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1916a8fe58ceSMaruthi Bayyavarapu 1917a8fe58ceSMaruthi Bayyavarapu 19187e471e6fSAlex Deucher /* GPU virtualization */ 1919048765adSAndres Rodriguez #define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0) 1920048765adSAndres Rodriguez #define AMDGPU_VIRT_CAPS_IS_VF (1 << 1) 19217e471e6fSAlex Deucher struct amdgpu_virtualization { 19227e471e6fSAlex Deucher bool supports_sr_iov; 1923048765adSAndres Rodriguez bool is_virtual; 1924048765adSAndres Rodriguez u32 caps; 19257e471e6fSAlex Deucher }; 19267e471e6fSAlex Deucher 1927a8fe58ceSMaruthi Bayyavarapu /* 192897b2e202SAlex Deucher * Core structure, functions and helpers. 192997b2e202SAlex Deucher */ 193097b2e202SAlex Deucher typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 193197b2e202SAlex Deucher typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 193297b2e202SAlex Deucher 193397b2e202SAlex Deucher typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 193497b2e202SAlex Deucher typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 193597b2e202SAlex Deucher 19368faf0e08SAlex Deucher struct amdgpu_ip_block_status { 19378faf0e08SAlex Deucher bool valid; 19388faf0e08SAlex Deucher bool sw; 19398faf0e08SAlex Deucher bool hw; 194063fbf42fSChunming Zhou bool hang; 19418faf0e08SAlex Deucher }; 19428faf0e08SAlex Deucher 194397b2e202SAlex Deucher struct amdgpu_device { 194497b2e202SAlex Deucher struct device *dev; 194597b2e202SAlex Deucher struct drm_device *ddev; 194697b2e202SAlex Deucher struct pci_dev *pdev; 194797b2e202SAlex Deucher 1948a8fe58ceSMaruthi Bayyavarapu #ifdef CONFIG_DRM_AMD_ACP 1949a8fe58ceSMaruthi Bayyavarapu struct amdgpu_acp acp; 1950a8fe58ceSMaruthi Bayyavarapu #endif 1951a8fe58ceSMaruthi Bayyavarapu 195297b2e202SAlex Deucher /* ASIC */ 19532f7d10b3SJammy Zhou enum amd_asic_type asic_type; 195497b2e202SAlex Deucher uint32_t family; 195597b2e202SAlex Deucher uint32_t rev_id; 195697b2e202SAlex Deucher uint32_t external_rev_id; 195797b2e202SAlex Deucher unsigned long flags; 195897b2e202SAlex Deucher int usec_timeout; 195997b2e202SAlex Deucher const struct amdgpu_asic_funcs *asic_funcs; 196097b2e202SAlex Deucher bool shutdown; 196197b2e202SAlex Deucher bool need_dma32; 196297b2e202SAlex Deucher bool accel_working; 196397b2e202SAlex Deucher struct work_struct reset_work; 196497b2e202SAlex Deucher struct notifier_block acpi_nb; 196597b2e202SAlex Deucher struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 196697b2e202SAlex Deucher struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 196797b2e202SAlex Deucher unsigned debugfs_count; 196897b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS) 1969adcec288STom St Denis struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 197097b2e202SAlex Deucher #endif 197197b2e202SAlex Deucher struct amdgpu_atif atif; 197297b2e202SAlex Deucher struct amdgpu_atcs atcs; 197397b2e202SAlex Deucher struct mutex srbm_mutex; 197497b2e202SAlex Deucher /* GRBM index mutex. Protects concurrent access to GRBM index */ 197597b2e202SAlex Deucher struct mutex grbm_idx_mutex; 197697b2e202SAlex Deucher struct dev_pm_domain vga_pm_domain; 197797b2e202SAlex Deucher bool have_disp_power_ref; 197897b2e202SAlex Deucher 197997b2e202SAlex Deucher /* BIOS */ 198097b2e202SAlex Deucher uint8_t *bios; 198197b2e202SAlex Deucher bool is_atom_bios; 198297b2e202SAlex Deucher struct amdgpu_bo *stollen_vga_memory; 198397b2e202SAlex Deucher uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 198497b2e202SAlex Deucher 198597b2e202SAlex Deucher /* Register/doorbell mmio */ 198697b2e202SAlex Deucher resource_size_t rmmio_base; 198797b2e202SAlex Deucher resource_size_t rmmio_size; 198897b2e202SAlex Deucher void __iomem *rmmio; 198997b2e202SAlex Deucher /* protects concurrent MM_INDEX/DATA based register access */ 199097b2e202SAlex Deucher spinlock_t mmio_idx_lock; 199197b2e202SAlex Deucher /* protects concurrent SMC based register access */ 199297b2e202SAlex Deucher spinlock_t smc_idx_lock; 199397b2e202SAlex Deucher amdgpu_rreg_t smc_rreg; 199497b2e202SAlex Deucher amdgpu_wreg_t smc_wreg; 199597b2e202SAlex Deucher /* protects concurrent PCIE register access */ 199697b2e202SAlex Deucher spinlock_t pcie_idx_lock; 199797b2e202SAlex Deucher amdgpu_rreg_t pcie_rreg; 199897b2e202SAlex Deucher amdgpu_wreg_t pcie_wreg; 199997b2e202SAlex Deucher /* protects concurrent UVD register access */ 200097b2e202SAlex Deucher spinlock_t uvd_ctx_idx_lock; 200197b2e202SAlex Deucher amdgpu_rreg_t uvd_ctx_rreg; 200297b2e202SAlex Deucher amdgpu_wreg_t uvd_ctx_wreg; 200397b2e202SAlex Deucher /* protects concurrent DIDT register access */ 200497b2e202SAlex Deucher spinlock_t didt_idx_lock; 200597b2e202SAlex Deucher amdgpu_rreg_t didt_rreg; 200697b2e202SAlex Deucher amdgpu_wreg_t didt_wreg; 2007ccdbb20aSRex Zhu /* protects concurrent gc_cac register access */ 2008ccdbb20aSRex Zhu spinlock_t gc_cac_idx_lock; 2009ccdbb20aSRex Zhu amdgpu_rreg_t gc_cac_rreg; 2010ccdbb20aSRex Zhu amdgpu_wreg_t gc_cac_wreg; 201197b2e202SAlex Deucher /* protects concurrent ENDPOINT (audio) register access */ 201297b2e202SAlex Deucher spinlock_t audio_endpt_idx_lock; 201397b2e202SAlex Deucher amdgpu_block_rreg_t audio_endpt_rreg; 201497b2e202SAlex Deucher amdgpu_block_wreg_t audio_endpt_wreg; 201597b2e202SAlex Deucher void __iomem *rio_mem; 201697b2e202SAlex Deucher resource_size_t rio_mem_size; 201797b2e202SAlex Deucher struct amdgpu_doorbell doorbell; 201897b2e202SAlex Deucher 201997b2e202SAlex Deucher /* clock/pll info */ 202097b2e202SAlex Deucher struct amdgpu_clock clock; 202197b2e202SAlex Deucher 202297b2e202SAlex Deucher /* MC */ 202397b2e202SAlex Deucher struct amdgpu_mc mc; 202497b2e202SAlex Deucher struct amdgpu_gart gart; 202597b2e202SAlex Deucher struct amdgpu_dummy_page dummy_page; 202697b2e202SAlex Deucher struct amdgpu_vm_manager vm_manager; 202797b2e202SAlex Deucher 202897b2e202SAlex Deucher /* memory management */ 202997b2e202SAlex Deucher struct amdgpu_mman mman; 203097b2e202SAlex Deucher struct amdgpu_vram_scratch vram_scratch; 203197b2e202SAlex Deucher struct amdgpu_wb wb; 203297b2e202SAlex Deucher atomic64_t vram_usage; 203397b2e202SAlex Deucher atomic64_t vram_vis_usage; 203497b2e202SAlex Deucher atomic64_t gtt_usage; 203597b2e202SAlex Deucher atomic64_t num_bytes_moved; 2036dbd5ed60SChristian König atomic64_t num_evictions; 2037d94aed5aSMarek Olšák atomic_t gpu_reset_counter; 203897b2e202SAlex Deucher 203995844d20SMarek Olšák /* data for buffer migration throttling */ 204095844d20SMarek Olšák struct { 204195844d20SMarek Olšák spinlock_t lock; 204295844d20SMarek Olšák s64 last_update_us; 204395844d20SMarek Olšák s64 accum_us; /* accumulated microseconds */ 204495844d20SMarek Olšák u32 log2_max_MBps; 204595844d20SMarek Olšák } mm_stats; 204695844d20SMarek Olšák 204797b2e202SAlex Deucher /* display */ 20489accf2fdSEmily Deng bool enable_virtual_display; 204997b2e202SAlex Deucher struct amdgpu_mode_info mode_info; 205097b2e202SAlex Deucher struct work_struct hotplug_work; 205197b2e202SAlex Deucher struct amdgpu_irq_src crtc_irq; 205297b2e202SAlex Deucher struct amdgpu_irq_src pageflip_irq; 205397b2e202SAlex Deucher struct amdgpu_irq_src hpd_irq; 205497b2e202SAlex Deucher 205597b2e202SAlex Deucher /* rings */ 205676bf0db5SChristian König u64 fence_context; 205797b2e202SAlex Deucher unsigned num_rings; 205897b2e202SAlex Deucher struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 205997b2e202SAlex Deucher bool ib_pool_ready; 206097b2e202SAlex Deucher struct amdgpu_sa_manager ring_tmp_bo; 206197b2e202SAlex Deucher 206297b2e202SAlex Deucher /* interrupts */ 206397b2e202SAlex Deucher struct amdgpu_irq irq; 206497b2e202SAlex Deucher 20651f7371b2SAlex Deucher /* powerplay */ 20661f7371b2SAlex Deucher struct amd_powerplay powerplay; 2067e61710c5SJammy Zhou bool pp_enabled; 2068f3898ea1SEric Huang bool pp_force_state_enabled; 20691f7371b2SAlex Deucher 207097b2e202SAlex Deucher /* dpm */ 207197b2e202SAlex Deucher struct amdgpu_pm pm; 207297b2e202SAlex Deucher u32 cg_flags; 207397b2e202SAlex Deucher u32 pg_flags; 207497b2e202SAlex Deucher 207597b2e202SAlex Deucher /* amdgpu smumgr */ 207697b2e202SAlex Deucher struct amdgpu_smumgr smu; 207797b2e202SAlex Deucher 207897b2e202SAlex Deucher /* gfx */ 207997b2e202SAlex Deucher struct amdgpu_gfx gfx; 208097b2e202SAlex Deucher 208197b2e202SAlex Deucher /* sdma */ 2082c113ea1cSAlex Deucher struct amdgpu_sdma sdma; 208397b2e202SAlex Deucher 208497b2e202SAlex Deucher /* uvd */ 208597b2e202SAlex Deucher struct amdgpu_uvd uvd; 208697b2e202SAlex Deucher 208797b2e202SAlex Deucher /* vce */ 208897b2e202SAlex Deucher struct amdgpu_vce vce; 208997b2e202SAlex Deucher 209097b2e202SAlex Deucher /* firmwares */ 209197b2e202SAlex Deucher struct amdgpu_firmware firmware; 209297b2e202SAlex Deucher 209397b2e202SAlex Deucher /* GDS */ 209497b2e202SAlex Deucher struct amdgpu_gds gds; 209597b2e202SAlex Deucher 209697b2e202SAlex Deucher const struct amdgpu_ip_block_version *ip_blocks; 209797b2e202SAlex Deucher int num_ip_blocks; 20988faf0e08SAlex Deucher struct amdgpu_ip_block_status *ip_block_status; 209997b2e202SAlex Deucher struct mutex mn_lock; 210097b2e202SAlex Deucher DECLARE_HASHTABLE(mn_hash, 7); 210197b2e202SAlex Deucher 210297b2e202SAlex Deucher /* tracking pinned memory */ 210397b2e202SAlex Deucher u64 vram_pin_size; 2104e131b914SChunming Zhou u64 invisible_pin_size; 210597b2e202SAlex Deucher u64 gart_pin_size; 2106130e0371SOded Gabbay 2107130e0371SOded Gabbay /* amdkfd interface */ 2108130e0371SOded Gabbay struct kfd_dev *kfd; 210923ca0e4eSChunming Zhou 21107e471e6fSAlex Deucher struct amdgpu_virtualization virtualization; 21110c4e7fa5SChunming Zhou 21120c4e7fa5SChunming Zhou /* link all shadow bo */ 21130c4e7fa5SChunming Zhou struct list_head shadow_list; 21140c4e7fa5SChunming Zhou struct mutex shadow_list_lock; 211597b2e202SAlex Deucher }; 211697b2e202SAlex Deucher 211797b2e202SAlex Deucher bool amdgpu_device_is_px(struct drm_device *dev); 211897b2e202SAlex Deucher int amdgpu_device_init(struct amdgpu_device *adev, 211997b2e202SAlex Deucher struct drm_device *ddev, 212097b2e202SAlex Deucher struct pci_dev *pdev, 212197b2e202SAlex Deucher uint32_t flags); 212297b2e202SAlex Deucher void amdgpu_device_fini(struct amdgpu_device *adev); 212397b2e202SAlex Deucher int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 212497b2e202SAlex Deucher 212597b2e202SAlex Deucher uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 212697b2e202SAlex Deucher bool always_indirect); 212797b2e202SAlex Deucher void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 212897b2e202SAlex Deucher bool always_indirect); 212997b2e202SAlex Deucher u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 213097b2e202SAlex Deucher void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 213197b2e202SAlex Deucher 213297b2e202SAlex Deucher u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 213397b2e202SAlex Deucher void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 213497b2e202SAlex Deucher 213597b2e202SAlex Deucher /* 213697b2e202SAlex Deucher * Registers read & write functions. 213797b2e202SAlex Deucher */ 213897b2e202SAlex Deucher #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 213997b2e202SAlex Deucher #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 214097b2e202SAlex Deucher #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 214197b2e202SAlex Deucher #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 214297b2e202SAlex Deucher #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 214397b2e202SAlex Deucher #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 214497b2e202SAlex Deucher #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 214597b2e202SAlex Deucher #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 214697b2e202SAlex Deucher #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 214797b2e202SAlex Deucher #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 214897b2e202SAlex Deucher #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 214997b2e202SAlex Deucher #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 215097b2e202SAlex Deucher #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 215197b2e202SAlex Deucher #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 215297b2e202SAlex Deucher #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2153ccdbb20aSRex Zhu #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 2154ccdbb20aSRex Zhu #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 215597b2e202SAlex Deucher #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 215697b2e202SAlex Deucher #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 215797b2e202SAlex Deucher #define WREG32_P(reg, val, mask) \ 215897b2e202SAlex Deucher do { \ 215997b2e202SAlex Deucher uint32_t tmp_ = RREG32(reg); \ 216097b2e202SAlex Deucher tmp_ &= (mask); \ 216197b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 216297b2e202SAlex Deucher WREG32(reg, tmp_); \ 216397b2e202SAlex Deucher } while (0) 216497b2e202SAlex Deucher #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 216597b2e202SAlex Deucher #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 216697b2e202SAlex Deucher #define WREG32_PLL_P(reg, val, mask) \ 216797b2e202SAlex Deucher do { \ 216897b2e202SAlex Deucher uint32_t tmp_ = RREG32_PLL(reg); \ 216997b2e202SAlex Deucher tmp_ &= (mask); \ 217097b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 217197b2e202SAlex Deucher WREG32_PLL(reg, tmp_); \ 217297b2e202SAlex Deucher } while (0) 217397b2e202SAlex Deucher #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 217497b2e202SAlex Deucher #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 217597b2e202SAlex Deucher #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 217697b2e202SAlex Deucher 217797b2e202SAlex Deucher #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 217897b2e202SAlex Deucher #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 217997b2e202SAlex Deucher 218097b2e202SAlex Deucher #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 218197b2e202SAlex Deucher #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 218297b2e202SAlex Deucher 218397b2e202SAlex Deucher #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 218497b2e202SAlex Deucher (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 218597b2e202SAlex Deucher (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 218697b2e202SAlex Deucher 218797b2e202SAlex Deucher #define REG_GET_FIELD(value, reg, field) \ 218897b2e202SAlex Deucher (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 218997b2e202SAlex Deucher 219061cb8cefSTom St Denis #define WREG32_FIELD(reg, field, val) \ 219161cb8cefSTom St Denis WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 219261cb8cefSTom St Denis 219397b2e202SAlex Deucher /* 219497b2e202SAlex Deucher * BIOS helpers. 219597b2e202SAlex Deucher */ 219697b2e202SAlex Deucher #define RBIOS8(i) (adev->bios[i]) 219797b2e202SAlex Deucher #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 219897b2e202SAlex Deucher #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 219997b2e202SAlex Deucher 220097b2e202SAlex Deucher /* 220197b2e202SAlex Deucher * RING helpers. 220297b2e202SAlex Deucher */ 220397b2e202SAlex Deucher static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 220497b2e202SAlex Deucher { 220597b2e202SAlex Deucher if (ring->count_dw <= 0) 220686c2b790SJammy Zhou DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 220797b2e202SAlex Deucher ring->ring[ring->wptr++] = v; 220897b2e202SAlex Deucher ring->wptr &= ring->ptr_mask; 220997b2e202SAlex Deucher ring->count_dw--; 221097b2e202SAlex Deucher } 221197b2e202SAlex Deucher 2212c113ea1cSAlex Deucher static inline struct amdgpu_sdma_instance * 2213c113ea1cSAlex Deucher amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 22144b2f7e2cSJammy Zhou { 22154b2f7e2cSJammy Zhou struct amdgpu_device *adev = ring->adev; 22164b2f7e2cSJammy Zhou int i; 22174b2f7e2cSJammy Zhou 2218c113ea1cSAlex Deucher for (i = 0; i < adev->sdma.num_instances; i++) 2219c113ea1cSAlex Deucher if (&adev->sdma.instance[i].ring == ring) 22204b2f7e2cSJammy Zhou break; 22214b2f7e2cSJammy Zhou 22224b2f7e2cSJammy Zhou if (i < AMDGPU_MAX_SDMA_INSTANCES) 2223c113ea1cSAlex Deucher return &adev->sdma.instance[i]; 22244b2f7e2cSJammy Zhou else 22254b2f7e2cSJammy Zhou return NULL; 22264b2f7e2cSJammy Zhou } 22274b2f7e2cSJammy Zhou 222897b2e202SAlex Deucher /* 222997b2e202SAlex Deucher * ASICs macro. 223097b2e202SAlex Deucher */ 223197b2e202SAlex Deucher #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 223297b2e202SAlex Deucher #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 223397b2e202SAlex Deucher #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 223497b2e202SAlex Deucher #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 223597b2e202SAlex Deucher #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2236048765adSAndres Rodriguez #define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev))) 223797b2e202SAlex Deucher #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 22387946b878SAlex Deucher #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 223997b2e202SAlex Deucher #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 224097b2e202SAlex Deucher #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 224197b2e202SAlex Deucher #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 224297b2e202SAlex Deucher #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2243de9ea7bdSChristian König #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 224497b2e202SAlex Deucher #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 224597b2e202SAlex Deucher #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 224697b2e202SAlex Deucher #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2247bbec97aaSChristian König #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 224897b2e202SAlex Deucher #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 224997b2e202SAlex Deucher #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 225097b2e202SAlex Deucher #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2251d88bf583SChristian König #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 2252b8c7b39eSChristian König #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 225397b2e202SAlex Deucher #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2254890ee23fSChunming Zhou #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 225597b2e202SAlex Deucher #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2256d2edb07bSChristian König #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 225711afbde8SChunming Zhou #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 2258c2167a65SMonk Liu #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 22599e5d5309SChristian König #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 226003ccf481SMonk Liu #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 226103ccf481SMonk Liu #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 226297b2e202SAlex Deucher #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 226397b2e202SAlex Deucher #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 226497b2e202SAlex Deucher #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 226597b2e202SAlex Deucher #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 226697b2e202SAlex Deucher #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 226797b2e202SAlex Deucher #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 226897b2e202SAlex Deucher #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 226997b2e202SAlex Deucher #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 227097b2e202SAlex Deucher #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 227197b2e202SAlex Deucher #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 227297b2e202SAlex Deucher #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 227397b2e202SAlex Deucher #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 227497b2e202SAlex Deucher #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2275cb9e59d7SAlex Deucher #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 227697b2e202SAlex Deucher #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 227797b2e202SAlex Deucher #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 227897b2e202SAlex Deucher #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 227997b2e202SAlex Deucher #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 228097b2e202SAlex Deucher #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2281c7ae72c0SChunming Zhou #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 22826e7a3840SChunming Zhou #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 228397b2e202SAlex Deucher #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 228497b2e202SAlex Deucher #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 228597b2e202SAlex Deucher #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 228697b2e202SAlex Deucher #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 228797b2e202SAlex Deucher #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 228897b2e202SAlex Deucher #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 228997b2e202SAlex Deucher #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2290b95e31fdSAlex Deucher #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 22919559ef5bSTom St Denis #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 22923af76f23SRex Zhu 22933af76f23SRex Zhu #define amdgpu_dpm_get_temperature(adev) \ 22944b5ece24SEric Huang ((adev)->pp_enabled ? \ 22953af76f23SRex Zhu (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ 22964b5ece24SEric Huang (adev)->pm.funcs->get_temperature((adev))) 22973af76f23SRex Zhu 22983af76f23SRex Zhu #define amdgpu_dpm_set_fan_control_mode(adev, m) \ 22994b5ece24SEric Huang ((adev)->pp_enabled ? \ 23003af76f23SRex Zhu (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ 23014b5ece24SEric Huang (adev)->pm.funcs->set_fan_control_mode((adev), (m))) 23023af76f23SRex Zhu 23033af76f23SRex Zhu #define amdgpu_dpm_get_fan_control_mode(adev) \ 23044b5ece24SEric Huang ((adev)->pp_enabled ? \ 23053af76f23SRex Zhu (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ 23064b5ece24SEric Huang (adev)->pm.funcs->get_fan_control_mode((adev))) 23073af76f23SRex Zhu 23083af76f23SRex Zhu #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ 23094b5ece24SEric Huang ((adev)->pp_enabled ? \ 23103af76f23SRex Zhu (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 23114b5ece24SEric Huang (adev)->pm.funcs->set_fan_speed_percent((adev), (s))) 23123af76f23SRex Zhu 23133af76f23SRex Zhu #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ 23144b5ece24SEric Huang ((adev)->pp_enabled ? \ 23153af76f23SRex Zhu (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 23164b5ece24SEric Huang (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) 231797b2e202SAlex Deucher 23181b5708ffSRex Zhu #define amdgpu_dpm_get_sclk(adev, l) \ 23194b5ece24SEric Huang ((adev)->pp_enabled ? \ 23201b5708ffSRex Zhu (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ 23214b5ece24SEric Huang (adev)->pm.funcs->get_sclk((adev), (l))) 23221b5708ffSRex Zhu 23231b5708ffSRex Zhu #define amdgpu_dpm_get_mclk(adev, l) \ 23244b5ece24SEric Huang ((adev)->pp_enabled ? \ 23251b5708ffSRex Zhu (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ 23264b5ece24SEric Huang (adev)->pm.funcs->get_mclk((adev), (l))) 23271b5708ffSRex Zhu 23281b5708ffSRex Zhu 23291b5708ffSRex Zhu #define amdgpu_dpm_force_performance_level(adev, l) \ 23304b5ece24SEric Huang ((adev)->pp_enabled ? \ 23311b5708ffSRex Zhu (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ 23324b5ece24SEric Huang (adev)->pm.funcs->force_performance_level((adev), (l))) 23331b5708ffSRex Zhu 23341b5708ffSRex Zhu #define amdgpu_dpm_powergate_uvd(adev, g) \ 23354b5ece24SEric Huang ((adev)->pp_enabled ? \ 23361b5708ffSRex Zhu (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ 23374b5ece24SEric Huang (adev)->pm.funcs->powergate_uvd((adev), (g))) 23381b5708ffSRex Zhu 23391b5708ffSRex Zhu #define amdgpu_dpm_powergate_vce(adev, g) \ 23404b5ece24SEric Huang ((adev)->pp_enabled ? \ 23411b5708ffSRex Zhu (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ 23424b5ece24SEric Huang (adev)->pm.funcs->powergate_vce((adev), (g))) 23431b5708ffSRex Zhu 23441b5708ffSRex Zhu #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \ 23454b5ece24SEric Huang ((adev)->pp_enabled ? \ 23461b5708ffSRex Zhu (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \ 23474b5ece24SEric Huang (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))) 23481b5708ffSRex Zhu 23491b5708ffSRex Zhu #define amdgpu_dpm_get_current_power_state(adev) \ 23501b5708ffSRex Zhu (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) 23511b5708ffSRex Zhu 23521b5708ffSRex Zhu #define amdgpu_dpm_get_performance_level(adev) \ 23531b5708ffSRex Zhu (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) 23541b5708ffSRex Zhu 2355f3898ea1SEric Huang #define amdgpu_dpm_get_pp_num_states(adev, data) \ 2356f3898ea1SEric Huang (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data) 2357f3898ea1SEric Huang 2358f3898ea1SEric Huang #define amdgpu_dpm_get_pp_table(adev, table) \ 2359f3898ea1SEric Huang (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table) 2360f3898ea1SEric Huang 2361f3898ea1SEric Huang #define amdgpu_dpm_set_pp_table(adev, buf, size) \ 2362f3898ea1SEric Huang (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size) 2363f3898ea1SEric Huang 2364f3898ea1SEric Huang #define amdgpu_dpm_print_clock_levels(adev, type, buf) \ 2365f3898ea1SEric Huang (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf) 2366f3898ea1SEric Huang 2367f3898ea1SEric Huang #define amdgpu_dpm_force_clock_level(adev, type, level) \ 2368f3898ea1SEric Huang (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level) 2369f3898ea1SEric Huang 2370428bafa8SEric Huang #define amdgpu_dpm_get_sclk_od(adev) \ 2371428bafa8SEric Huang (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle) 2372428bafa8SEric Huang 2373428bafa8SEric Huang #define amdgpu_dpm_set_sclk_od(adev, value) \ 2374428bafa8SEric Huang (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value) 2375428bafa8SEric Huang 2376f2bdc05fSEric Huang #define amdgpu_dpm_get_mclk_od(adev) \ 2377f2bdc05fSEric Huang ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle)) 2378f2bdc05fSEric Huang 2379f2bdc05fSEric Huang #define amdgpu_dpm_set_mclk_od(adev, value) \ 2380f2bdc05fSEric Huang ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value)) 2381f2bdc05fSEric Huang 23821b5708ffSRex Zhu #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ 23831b5708ffSRex Zhu (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) 238497b2e202SAlex Deucher 238597b2e202SAlex Deucher #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 238697b2e202SAlex Deucher 238797b2e202SAlex Deucher /* Common functions */ 238897b2e202SAlex Deucher int amdgpu_gpu_reset(struct amdgpu_device *adev); 23893ad81f16SChunming Zhou bool amdgpu_need_backup(struct amdgpu_device *adev); 239097b2e202SAlex Deucher void amdgpu_pci_config_reset(struct amdgpu_device *adev); 239197b2e202SAlex Deucher bool amdgpu_card_posted(struct amdgpu_device *adev); 239297b2e202SAlex Deucher void amdgpu_update_display_priority(struct amdgpu_device *adev); 2393d5fc5e82SChunming Zhou 239497b2e202SAlex Deucher int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 239597b2e202SAlex Deucher int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 239697b2e202SAlex Deucher u32 ip_instance, u32 ring, 239797b2e202SAlex Deucher struct amdgpu_ring **out_ring); 239897b2e202SAlex Deucher void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 239997b2e202SAlex Deucher bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 24002f568dbdSChristian König int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 240197b2e202SAlex Deucher int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 240297b2e202SAlex Deucher uint32_t flags); 240397b2e202SAlex Deucher bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2404cc325d19SChristian König struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 2405d7006964SChristian König bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 2406d7006964SChristian König unsigned long end); 24072f568dbdSChristian König bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 24082f568dbdSChristian König int *last_invalidated); 240997b2e202SAlex Deucher bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 241097b2e202SAlex Deucher uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 241197b2e202SAlex Deucher struct ttm_mem_reg *mem); 241297b2e202SAlex Deucher void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 241397b2e202SAlex Deucher void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 241497b2e202SAlex Deucher void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2415a693e050SKen Wang u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev); 2416a693e050SKen Wang int amdgpu_ttm_global_init(struct amdgpu_device *adev); 241797b2e202SAlex Deucher void amdgpu_program_register_sequence(struct amdgpu_device *adev, 241897b2e202SAlex Deucher const u32 *registers, 241997b2e202SAlex Deucher const u32 array_size); 242097b2e202SAlex Deucher 242197b2e202SAlex Deucher bool amdgpu_device_is_px(struct drm_device *dev); 242297b2e202SAlex Deucher /* atpx handler */ 242397b2e202SAlex Deucher #if defined(CONFIG_VGA_SWITCHEROO) 242497b2e202SAlex Deucher void amdgpu_register_atpx_handler(void); 242597b2e202SAlex Deucher void amdgpu_unregister_atpx_handler(void); 2426a78fe133SAlex Deucher bool amdgpu_has_atpx_dgpu_power_cntl(void); 24272f5af82eSAlex Deucher bool amdgpu_is_atpx_hybrid(void); 242897b2e202SAlex Deucher #else 242997b2e202SAlex Deucher static inline void amdgpu_register_atpx_handler(void) {} 243097b2e202SAlex Deucher static inline void amdgpu_unregister_atpx_handler(void) {} 2431a78fe133SAlex Deucher static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 24322f5af82eSAlex Deucher static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 243397b2e202SAlex Deucher #endif 243497b2e202SAlex Deucher 243597b2e202SAlex Deucher /* 243697b2e202SAlex Deucher * KMS 243797b2e202SAlex Deucher */ 243897b2e202SAlex Deucher extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2439f498d9edSNils Wallménius extern const int amdgpu_max_kms_ioctl; 244097b2e202SAlex Deucher 244197b2e202SAlex Deucher int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 244297b2e202SAlex Deucher int amdgpu_driver_unload_kms(struct drm_device *dev); 244397b2e202SAlex Deucher void amdgpu_driver_lastclose_kms(struct drm_device *dev); 244497b2e202SAlex Deucher int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 244597b2e202SAlex Deucher void amdgpu_driver_postclose_kms(struct drm_device *dev, 244697b2e202SAlex Deucher struct drm_file *file_priv); 244797b2e202SAlex Deucher void amdgpu_driver_preclose_kms(struct drm_device *dev, 244897b2e202SAlex Deucher struct drm_file *file_priv); 2449810ddc3aSAlex Deucher int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 2450810ddc3aSAlex Deucher int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 245188e72717SThierry Reding u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 245288e72717SThierry Reding int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 245388e72717SThierry Reding void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 245488e72717SThierry Reding int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 245597b2e202SAlex Deucher int *max_error, 245697b2e202SAlex Deucher struct timeval *vblank_time, 245797b2e202SAlex Deucher unsigned flags); 245897b2e202SAlex Deucher long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 245997b2e202SAlex Deucher unsigned long arg); 246097b2e202SAlex Deucher 246197b2e202SAlex Deucher /* 246297b2e202SAlex Deucher * functions used by amdgpu_encoder.c 246397b2e202SAlex Deucher */ 246497b2e202SAlex Deucher struct amdgpu_afmt_acr { 246597b2e202SAlex Deucher u32 clock; 246697b2e202SAlex Deucher 246797b2e202SAlex Deucher int n_32khz; 246897b2e202SAlex Deucher int cts_32khz; 246997b2e202SAlex Deucher 247097b2e202SAlex Deucher int n_44_1khz; 247197b2e202SAlex Deucher int cts_44_1khz; 247297b2e202SAlex Deucher 247397b2e202SAlex Deucher int n_48khz; 247497b2e202SAlex Deucher int cts_48khz; 247597b2e202SAlex Deucher 247697b2e202SAlex Deucher }; 247797b2e202SAlex Deucher 247897b2e202SAlex Deucher struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 247997b2e202SAlex Deucher 248097b2e202SAlex Deucher /* amdgpu_acpi.c */ 248197b2e202SAlex Deucher #if defined(CONFIG_ACPI) 248297b2e202SAlex Deucher int amdgpu_acpi_init(struct amdgpu_device *adev); 248397b2e202SAlex Deucher void amdgpu_acpi_fini(struct amdgpu_device *adev); 248497b2e202SAlex Deucher bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 248597b2e202SAlex Deucher int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 248697b2e202SAlex Deucher u8 perf_req, bool advertise); 248797b2e202SAlex Deucher int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 248897b2e202SAlex Deucher #else 248997b2e202SAlex Deucher static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 249097b2e202SAlex Deucher static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 249197b2e202SAlex Deucher #endif 249297b2e202SAlex Deucher 249397b2e202SAlex Deucher struct amdgpu_bo_va_mapping * 249497b2e202SAlex Deucher amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 249597b2e202SAlex Deucher uint64_t addr, struct amdgpu_bo **bo); 249697b2e202SAlex Deucher 249797b2e202SAlex Deucher #include "amdgpu_object.h" 249897b2e202SAlex Deucher #endif 2499