197b2e202SAlex Deucher /* 297b2e202SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 397b2e202SAlex Deucher * Copyright 2008 Red Hat Inc. 497b2e202SAlex Deucher * Copyright 2009 Jerome Glisse. 597b2e202SAlex Deucher * 697b2e202SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 797b2e202SAlex Deucher * copy of this software and associated documentation files (the "Software"), 897b2e202SAlex Deucher * to deal in the Software without restriction, including without limitation 997b2e202SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1097b2e202SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1197b2e202SAlex Deucher * Software is furnished to do so, subject to the following conditions: 1297b2e202SAlex Deucher * 1397b2e202SAlex Deucher * The above copyright notice and this permission notice shall be included in 1497b2e202SAlex Deucher * all copies or substantial portions of the Software. 1597b2e202SAlex Deucher * 1697b2e202SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1797b2e202SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1897b2e202SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1997b2e202SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2097b2e202SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2197b2e202SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2297b2e202SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2397b2e202SAlex Deucher * 2497b2e202SAlex Deucher * Authors: Dave Airlie 2597b2e202SAlex Deucher * Alex Deucher 2697b2e202SAlex Deucher * Jerome Glisse 2797b2e202SAlex Deucher */ 2897b2e202SAlex Deucher #ifndef __AMDGPU_H__ 2997b2e202SAlex Deucher #define __AMDGPU_H__ 3097b2e202SAlex Deucher 31d57229b1SAurabindo Pillai #ifdef pr_fmt 32d57229b1SAurabindo Pillai #undef pr_fmt 33d57229b1SAurabindo Pillai #endif 34d57229b1SAurabindo Pillai 35d57229b1SAurabindo Pillai #define pr_fmt(fmt) "amdgpu: " fmt 36d57229b1SAurabindo Pillai 37539489fcSAurabindo Pillai #ifdef dev_fmt 38539489fcSAurabindo Pillai #undef dev_fmt 39539489fcSAurabindo Pillai #endif 40539489fcSAurabindo Pillai 41539489fcSAurabindo Pillai #define dev_fmt(fmt) "amdgpu: " fmt 42539489fcSAurabindo Pillai 438290268fSChristian König #include "amdgpu_ctx.h" 448290268fSChristian König 4597b2e202SAlex Deucher #include <linux/atomic.h> 4697b2e202SAlex Deucher #include <linux/wait.h> 4797b2e202SAlex Deucher #include <linux/list.h> 4897b2e202SAlex Deucher #include <linux/kref.h> 49a9f87f64SChristian König #include <linux/rbtree.h> 5097b2e202SAlex Deucher #include <linux/hashtable.h> 51f54d1867SChris Wilson #include <linux/dma-fence.h> 52c9a6b82fSAndrey Grodzovsky #include <linux/pci.h> 53c9a6b82fSAndrey Grodzovsky #include <linux/aer.h> 5497b2e202SAlex Deucher 55248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_bo_api.h> 56248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_bo_driver.h> 57248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_placement.h> 58248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_module.h> 59248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_execbuf_util.h> 6097b2e202SAlex Deucher 617e5a547fSChunming Zhou #include <drm/amdgpu_drm.h> 62f867723bSSam Ravnborg #include <drm/drm_gem.h> 63f867723bSSam Ravnborg #include <drm/drm_ioctl.h> 641b1f42d8SLucas Stach #include <drm/gpu_scheduler.h> 6597b2e202SAlex Deucher 6678c16834SAndres Rodriguez #include <kgd_kfd_interface.h> 67c79563a3SRex Zhu #include "dm_pp_interface.h" 68c79563a3SRex Zhu #include "kgd_pp_interface.h" 6978c16834SAndres Rodriguez 705fc3aeebSyanyang1 #include "amd_shared.h" 7197b2e202SAlex Deucher #include "amdgpu_mode.h" 7297b2e202SAlex Deucher #include "amdgpu_ih.h" 7397b2e202SAlex Deucher #include "amdgpu_irq.h" 7497b2e202SAlex Deucher #include "amdgpu_ucode.h" 75c632d799SFlora Cui #include "amdgpu_ttm.h" 760e5ca0d1SHuang Rui #include "amdgpu_psp.h" 7797b2e202SAlex Deucher #include "amdgpu_gds.h" 7856113504SChristian König #include "amdgpu_sync.h" 7978023016SChristian König #include "amdgpu_ring.h" 80073440d2SChristian König #include "amdgpu_vm.h" 81cf097881SAlex Deucher #include "amdgpu_dpm.h" 82a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h" 834df654d2SLeo Liu #include "amdgpu_uvd.h" 845e568178SLeo Liu #include "amdgpu_vce.h" 8595aa13f6SLeo Liu #include "amdgpu_vcn.h" 8688a1c40aSLeo Liu #include "amdgpu_jpeg.h" 879a189996SChristian König #include "amdgpu_mn.h" 88770d13b1SChristian König #include "amdgpu_gmc.h" 89448fe192SHuang Rui #include "amdgpu_gfx.h" 90bb7743bcSHuang Rui #include "amdgpu_sdma.h" 91bebc0762SHawking Zhang #include "amdgpu_nbio.h" 924562236bSHarry Wentland #include "amdgpu_dm.h" 93ceeb50edSMonk Liu #include "amdgpu_virt.h" 947946340fSRex Zhu #include "amdgpu_csa.h" 953490bdb5SChristian König #include "amdgpu_gart.h" 9675758255SAlex Deucher #include "amdgpu_debugfs.h" 97050d9d43SChristian König #include "amdgpu_job.h" 984a8c21a1SChristian König #include "amdgpu_bo_list.h" 992cddc50eSHuang Rui #include "amdgpu_gem.h" 100cde577bdSOak Zeng #include "amdgpu_doorbell.h" 101611736d8SFelix Kuehling #include "amdgpu_amdkfd.h" 102137d63abSHuang Rui #include "amdgpu_smu.h" 103f39f5bb1SXiaojie Yuan #include "amdgpu_discovery.h" 104a538bbe7SJack Xiao #include "amdgpu_mes.h" 1059e585a52SHawking Zhang #include "amdgpu_umc.h" 1063d093da0STao Zhou #include "amdgpu_mmhub.h" 107bdf84a80SJoseph Greathouse #include "amdgpu_df.h" 108c79563a3SRex Zhu 10962d73fbcSEvan Quan #define MAX_GPU_INSTANCE 16 11062d73fbcSEvan Quan 11162d73fbcSEvan Quan struct amdgpu_gpu_instance 11262d73fbcSEvan Quan { 11362d73fbcSEvan Quan struct amdgpu_device *adev; 11462d73fbcSEvan Quan int mgpu_fan_enabled; 11562d73fbcSEvan Quan }; 11662d73fbcSEvan Quan 11762d73fbcSEvan Quan struct amdgpu_mgpu_info 11862d73fbcSEvan Quan { 11962d73fbcSEvan Quan struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 12062d73fbcSEvan Quan struct mutex mutex; 12162d73fbcSEvan Quan uint32_t num_gpu; 12262d73fbcSEvan Quan uint32_t num_dgpu; 12362d73fbcSEvan Quan uint32_t num_apu; 12462d73fbcSEvan Quan }; 12562d73fbcSEvan Quan 126f440ff44SWambui Karuga #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 12771f98027SAlex Deucher 12897b2e202SAlex Deucher /* 12997b2e202SAlex Deucher * Modules parameters. 13097b2e202SAlex Deucher */ 13197b2e202SAlex Deucher extern int amdgpu_modeset; 13297b2e202SAlex Deucher extern int amdgpu_vram_limit; 133218b5dcdSJohn Brooks extern int amdgpu_vis_vram_limit; 13483e74db6SAlex Deucher extern int amdgpu_gart_size; 13536d38372SChristian König extern int amdgpu_gtt_size; 13695844d20SMarek Olšák extern int amdgpu_moverate; 13797b2e202SAlex Deucher extern int amdgpu_benchmarking; 13897b2e202SAlex Deucher extern int amdgpu_testing; 13997b2e202SAlex Deucher extern int amdgpu_audio; 14097b2e202SAlex Deucher extern int amdgpu_disp_priority; 14197b2e202SAlex Deucher extern int amdgpu_hw_i2c; 14297b2e202SAlex Deucher extern int amdgpu_pcie_gen2; 14397b2e202SAlex Deucher extern int amdgpu_msi; 144f440ff44SWambui Karuga extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 14597b2e202SAlex Deucher extern int amdgpu_dpm; 146e635ee07SHuang Rui extern int amdgpu_fw_load_type; 14797b2e202SAlex Deucher extern int amdgpu_aspm; 14897b2e202SAlex Deucher extern int amdgpu_runtime_pm; 1490b693f0bSRex Zhu extern uint amdgpu_ip_block_mask; 15097b2e202SAlex Deucher extern int amdgpu_bapm; 15197b2e202SAlex Deucher extern int amdgpu_deep_color; 15297b2e202SAlex Deucher extern int amdgpu_vm_size; 15397b2e202SAlex Deucher extern int amdgpu_vm_block_size; 154d07f14beSRoger He extern int amdgpu_vm_fragment_size; 155d9c13156SChristian König extern int amdgpu_vm_fault_stop; 156b495bd3aSChristian König extern int amdgpu_vm_debug; 1579a4b7d4cSHarish Kasiviswanathan extern int amdgpu_vm_update_mode; 1587e0ff20cSWambui Karuga extern int amdgpu_exp_hw_support; 1594562236bSHarry Wentland extern int amdgpu_dc; 1601333f723SJammy Zhou extern int amdgpu_sched_jobs; 1614afcb303SJammy Zhou extern int amdgpu_sched_hw_submission; 1620b693f0bSRex Zhu extern uint amdgpu_pcie_gen_cap; 1630b693f0bSRex Zhu extern uint amdgpu_pcie_lane_cap; 1640b693f0bSRex Zhu extern uint amdgpu_cg_mask; 1650b693f0bSRex Zhu extern uint amdgpu_pg_mask; 1660b693f0bSRex Zhu extern uint amdgpu_sdma_phase_quantum; 1676f8941a2SNicolai Hähnle extern char *amdgpu_disable_cu; 1689accf2fdSEmily Deng extern char *amdgpu_virtual_display; 1690b693f0bSRex Zhu extern uint amdgpu_pp_feature_mask; 170367039bfSTianci.Yin extern uint amdgpu_force_long_training; 17165781c78SMonk Liu extern int amdgpu_job_hang_limit; 172e8835e0eSHawking Zhang extern int amdgpu_lbpw; 1734a75aefeSAndres Rodriguez extern int amdgpu_compute_multipipe; 174dcebf026SAndrey Grodzovsky extern int amdgpu_gpu_recovery; 175bfca0289SShaoyun Liu extern int amdgpu_emu_mode; 1767951e376SRex Zhu extern uint amdgpu_smu_memory_pool_size; 1777875a226SAlex Deucher extern uint amdgpu_dc_feature_mask; 1788a791dabSHarry Wentland extern uint amdgpu_dc_debug_mask; 179ad4de27fSNicholas Kazlauskas extern uint amdgpu_dm_abm_level; 18062d73fbcSEvan Quan extern struct amdgpu_mgpu_info mgpu_info; 1811218252fSxinhui pan extern int amdgpu_ras_enable; 1821218252fSxinhui pan extern uint amdgpu_ras_mask; 183acc0204cSGuchun Chen extern int amdgpu_bad_page_threshold; 18451bcce46SHawking Zhang extern int amdgpu_async_gfx_ring; 185b239c017SJack Xiao extern int amdgpu_mcbp; 186a190d1c7SXiaojie Yuan extern int amdgpu_discovery; 18738487284SJack Xiao extern int amdgpu_mes; 18875ee6487SFelix Kuehling extern int amdgpu_noretry; 1894e66d7d2SYong Zhao extern int amdgpu_force_asic_type; 1908c9f69bcSShirish S #ifdef CONFIG_HSA_AMD 191aa978594SHuang Rui extern int sched_policy; 192b2057956SFelix Kuehling extern bool debug_evictions; 193b80f050fSPhilip Yang extern bool no_system_mem_limit; 194a35ad98bSShirish S #else 195a35ad98bSShirish S static const int sched_policy = KFD_SCHED_POLICY_HWS; 196b2057956SFelix Kuehling static const bool debug_evictions; /* = false */ 197b80f050fSPhilip Yang static const bool no_system_mem_limit; 1988c9f69bcSShirish S #endif 19997b2e202SAlex Deucher 200d7ccb38dSHuang Rui extern int amdgpu_tmz; 201273da6ffSWenhui Sheng extern int amdgpu_reset_method; 202d7ccb38dSHuang Rui 2036dd13096SFelix Kuehling #ifdef CONFIG_DRM_AMDGPU_SI 2046dd13096SFelix Kuehling extern int amdgpu_si_support; 2056dd13096SFelix Kuehling #endif 2067df28986SFelix Kuehling #ifdef CONFIG_DRM_AMDGPU_CIK 2077df28986SFelix Kuehling extern int amdgpu_cik_support; 2087df28986SFelix Kuehling #endif 209a300de40SMonk Liu extern int amdgpu_num_kcq; 21097b2e202SAlex Deucher 21108d1bdd4SRex Zhu #define AMDGPU_VM_MAX_NUM_CTX 4096 2126c8d74caSSamuel Li #define AMDGPU_SG_THRESHOLD (256*1024*1024) 21355ed8cafSChunming Zhou #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 2144b559c90SChunming Zhou #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 21597b2e202SAlex Deucher #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 2168c5e13ecSAndrey Grodzovsky #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 21797b2e202SAlex Deucher #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 21897b2e202SAlex Deucher #define AMDGPUFB_CONN_LIMIT 4 219a5bde2f9SAlex Deucher #define AMDGPU_BIOS_NUM_SCRATCH 16 22097b2e202SAlex Deucher 22181b54fb7SAlex Deucher #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 22281b54fb7SAlex Deucher 22397b2e202SAlex Deucher /* hard reset data */ 22497b2e202SAlex Deucher #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 22597b2e202SAlex Deucher 22697b2e202SAlex Deucher /* reset flags */ 22797b2e202SAlex Deucher #define AMDGPU_RESET_GFX (1 << 0) 22897b2e202SAlex Deucher #define AMDGPU_RESET_COMPUTE (1 << 1) 22997b2e202SAlex Deucher #define AMDGPU_RESET_DMA (1 << 2) 23097b2e202SAlex Deucher #define AMDGPU_RESET_CP (1 << 3) 23197b2e202SAlex Deucher #define AMDGPU_RESET_GRBM (1 << 4) 23297b2e202SAlex Deucher #define AMDGPU_RESET_DMA1 (1 << 5) 23397b2e202SAlex Deucher #define AMDGPU_RESET_RLC (1 << 6) 23497b2e202SAlex Deucher #define AMDGPU_RESET_SEM (1 << 7) 23597b2e202SAlex Deucher #define AMDGPU_RESET_IH (1 << 8) 23697b2e202SAlex Deucher #define AMDGPU_RESET_VMC (1 << 9) 23797b2e202SAlex Deucher #define AMDGPU_RESET_MC (1 << 10) 23897b2e202SAlex Deucher #define AMDGPU_RESET_DISPLAY (1 << 11) 23997b2e202SAlex Deucher #define AMDGPU_RESET_UVD (1 << 12) 24097b2e202SAlex Deucher #define AMDGPU_RESET_VCE (1 << 13) 24197b2e202SAlex Deucher #define AMDGPU_RESET_VCE1 (1 << 14) 24297b2e202SAlex Deucher 24397b2e202SAlex Deucher /* max cursor sizes (in pixels) */ 24497b2e202SAlex Deucher #define CIK_CURSOR_WIDTH 128 24597b2e202SAlex Deucher #define CIK_CURSOR_HEIGHT 128 24697b2e202SAlex Deucher 24797b2e202SAlex Deucher struct amdgpu_device; 24897b2e202SAlex Deucher struct amdgpu_ib; 24997b2e202SAlex Deucher struct amdgpu_cs_parser; 250bb977d37SChunming Zhou struct amdgpu_job; 25197b2e202SAlex Deucher struct amdgpu_irq_src; 2520b492a4cSAlex Deucher struct amdgpu_fpriv; 2539cca0b8eSChristian König struct amdgpu_bo_va_mapping; 254102c16a0SLyude Paul struct amdgpu_atif; 255992af942SJonathan Kim struct kfd_vm_fault_info; 256d95e8e97SDennis Li struct amdgpu_hive_info; 25797b2e202SAlex Deucher 25897b2e202SAlex Deucher enum amdgpu_cp_irq { 25953b2fe41SHawking Zhang AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 26053b2fe41SHawking Zhang AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 26197b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 26297b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 26397b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 26497b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 26597b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 26697b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 26797b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 26897b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 26997b2e202SAlex Deucher 27097b2e202SAlex Deucher AMDGPU_CP_IRQ_LAST 27197b2e202SAlex Deucher }; 27297b2e202SAlex Deucher 27397b2e202SAlex Deucher enum amdgpu_thermal_irq { 27497b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 27597b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 27697b2e202SAlex Deucher 27797b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LAST 27897b2e202SAlex Deucher }; 27997b2e202SAlex Deucher 2804e638ae9SXiangliang Yu enum amdgpu_kiq_irq { 2814e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 2824e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_LAST 2834e638ae9SXiangliang Yu }; 2844e638ae9SXiangliang Yu 2853890d111SEmily Deng #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 2863890d111SEmily Deng #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 2874944af67Swentalou #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 2883890d111SEmily Deng 28943fa561fSRex Zhu int amdgpu_device_ip_set_clockgating_state(void *dev, 2905fc3aeebSyanyang1 enum amd_ip_block_type block_type, 2915fc3aeebSyanyang1 enum amd_clockgating_state state); 29243fa561fSRex Zhu int amdgpu_device_ip_set_powergating_state(void *dev, 2935fc3aeebSyanyang1 enum amd_ip_block_type block_type, 2945fc3aeebSyanyang1 enum amd_powergating_state state); 2952990a1fcSAlex Deucher void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 2962990a1fcSAlex Deucher u32 *flags); 2972990a1fcSAlex Deucher int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 2985dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 2992990a1fcSAlex Deucher bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 3005dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 30197b2e202SAlex Deucher 302a1255107SAlex Deucher #define AMDGPU_MAX_IP_NUM 16 303a1255107SAlex Deucher 304a1255107SAlex Deucher struct amdgpu_ip_block_status { 305a1255107SAlex Deucher bool valid; 306a1255107SAlex Deucher bool sw; 307a1255107SAlex Deucher bool hw; 308a1255107SAlex Deucher bool late_initialized; 309a1255107SAlex Deucher bool hang; 310a1255107SAlex Deucher }; 311a1255107SAlex Deucher 31297b2e202SAlex Deucher struct amdgpu_ip_block_version { 313a1255107SAlex Deucher const enum amd_ip_block_type type; 314a1255107SAlex Deucher const u32 major; 315a1255107SAlex Deucher const u32 minor; 316a1255107SAlex Deucher const u32 rev; 3175fc3aeebSyanyang1 const struct amd_ip_funcs *funcs; 31897b2e202SAlex Deucher }; 31997b2e202SAlex Deucher 320efe4f000STianci.Yin #define HW_REV(_Major, _Minor, _Rev) \ 321efe4f000STianci.Yin ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 322efe4f000STianci.Yin 323a1255107SAlex Deucher struct amdgpu_ip_block { 324a1255107SAlex Deucher struct amdgpu_ip_block_status status; 325a1255107SAlex Deucher const struct amdgpu_ip_block_version *version; 326a1255107SAlex Deucher }; 327a1255107SAlex Deucher 3282990a1fcSAlex Deucher int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 3295fc3aeebSyanyang1 enum amd_ip_block_type type, 33097b2e202SAlex Deucher u32 major, u32 minor); 33197b2e202SAlex Deucher 3322990a1fcSAlex Deucher struct amdgpu_ip_block * 3332990a1fcSAlex Deucher amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 3345fc3aeebSyanyang1 enum amd_ip_block_type type); 33597b2e202SAlex Deucher 3362990a1fcSAlex Deucher int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 337a1255107SAlex Deucher const struct amdgpu_ip_block_version *ip_block_version); 338a1255107SAlex Deucher 33997b2e202SAlex Deucher /* 34097b2e202SAlex Deucher * BIOS. 34197b2e202SAlex Deucher */ 34297b2e202SAlex Deucher bool amdgpu_get_bios(struct amdgpu_device *adev); 34397b2e202SAlex Deucher bool amdgpu_read_bios(struct amdgpu_device *adev); 34497b2e202SAlex Deucher 34597b2e202SAlex Deucher /* 34697b2e202SAlex Deucher * Clocks 34797b2e202SAlex Deucher */ 34897b2e202SAlex Deucher 34997b2e202SAlex Deucher #define AMDGPU_MAX_PPLL 3 35097b2e202SAlex Deucher 35197b2e202SAlex Deucher struct amdgpu_clock { 35297b2e202SAlex Deucher struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 35397b2e202SAlex Deucher struct amdgpu_pll spll; 35497b2e202SAlex Deucher struct amdgpu_pll mpll; 35597b2e202SAlex Deucher /* 10 Khz units */ 35697b2e202SAlex Deucher uint32_t default_mclk; 35797b2e202SAlex Deucher uint32_t default_sclk; 35897b2e202SAlex Deucher uint32_t default_dispclk; 35997b2e202SAlex Deucher uint32_t current_dispclk; 36097b2e202SAlex Deucher uint32_t dp_extclk; 36197b2e202SAlex Deucher uint32_t max_pixel_clock; 36297b2e202SAlex Deucher }; 36397b2e202SAlex Deucher 36497b2e202SAlex Deucher /* sub-allocation manager, it has to be protected by another lock. 36597b2e202SAlex Deucher * By conception this is an helper for other part of the driver 36697b2e202SAlex Deucher * like the indirect buffer or semaphore, which both have their 36797b2e202SAlex Deucher * locking. 36897b2e202SAlex Deucher * 36997b2e202SAlex Deucher * Principe is simple, we keep a list of sub allocation in offset 37097b2e202SAlex Deucher * order (first entry has offset == 0, last entry has the highest 37197b2e202SAlex Deucher * offset). 37297b2e202SAlex Deucher * 37397b2e202SAlex Deucher * When allocating new object we first check if there is room at 37497b2e202SAlex Deucher * the end total_size - (last_object_offset + last_object_size) >= 37597b2e202SAlex Deucher * alloc_size. If so we allocate new object there. 37697b2e202SAlex Deucher * 37797b2e202SAlex Deucher * When there is not enough room at the end, we start waiting for 37897b2e202SAlex Deucher * each sub object until we reach object_offset+object_size >= 37997b2e202SAlex Deucher * alloc_size, this object then become the sub object we return. 38097b2e202SAlex Deucher * 38197b2e202SAlex Deucher * Alignment can't be bigger than page size. 38297b2e202SAlex Deucher * 38397b2e202SAlex Deucher * Hole are not considered for allocation to keep things simple. 38497b2e202SAlex Deucher * Assumption is that there won't be hole (all object on same 38597b2e202SAlex Deucher * alignment). 38697b2e202SAlex Deucher */ 3876ba60b89SChristian König 3886ba60b89SChristian König #define AMDGPU_SA_NUM_FENCE_LISTS 32 3896ba60b89SChristian König 39097b2e202SAlex Deucher struct amdgpu_sa_manager { 39197b2e202SAlex Deucher wait_queue_head_t wq; 39297b2e202SAlex Deucher struct amdgpu_bo *bo; 39397b2e202SAlex Deucher struct list_head *hole; 3946ba60b89SChristian König struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 39597b2e202SAlex Deucher struct list_head olist; 39697b2e202SAlex Deucher unsigned size; 39797b2e202SAlex Deucher uint64_t gpu_addr; 39897b2e202SAlex Deucher void *cpu_ptr; 39997b2e202SAlex Deucher uint32_t domain; 40097b2e202SAlex Deucher uint32_t align; 40197b2e202SAlex Deucher }; 40297b2e202SAlex Deucher 40397b2e202SAlex Deucher /* sub-allocation buffer */ 40497b2e202SAlex Deucher struct amdgpu_sa_bo { 40597b2e202SAlex Deucher struct list_head olist; 40697b2e202SAlex Deucher struct list_head flist; 40797b2e202SAlex Deucher struct amdgpu_sa_manager *manager; 40897b2e202SAlex Deucher unsigned soffset; 40997b2e202SAlex Deucher unsigned eoffset; 410f54d1867SChris Wilson struct dma_fence *fence; 41197b2e202SAlex Deucher }; 41297b2e202SAlex Deucher 413d573de2dSRex Zhu int amdgpu_fence_slab_init(void); 414d573de2dSRex Zhu void amdgpu_fence_slab_fini(void); 41597b2e202SAlex Deucher 41697b2e202SAlex Deucher /* 41797b2e202SAlex Deucher * IRQS. 41897b2e202SAlex Deucher */ 41997b2e202SAlex Deucher 42097b2e202SAlex Deucher struct amdgpu_flip_work { 421325cbba1SMichel Dänzer struct delayed_work flip_work; 42297b2e202SAlex Deucher struct work_struct unpin_work; 42397b2e202SAlex Deucher struct amdgpu_device *adev; 42497b2e202SAlex Deucher int crtc_id; 425325cbba1SMichel Dänzer u32 target_vblank; 42697b2e202SAlex Deucher uint64_t base; 42797b2e202SAlex Deucher struct drm_pending_vblank_event *event; 428765e7fbfSChristian König struct amdgpu_bo *old_abo; 429f54d1867SChris Wilson struct dma_fence *excl; 4301ffd2652SChristian König unsigned shared_count; 431f54d1867SChris Wilson struct dma_fence **shared; 432f54d1867SChris Wilson struct dma_fence_cb cb; 433cb9e59d7SAlex Deucher bool async; 43497b2e202SAlex Deucher }; 43597b2e202SAlex Deucher 43697b2e202SAlex Deucher 43797b2e202SAlex Deucher /* 43897b2e202SAlex Deucher * CP & rings. 43997b2e202SAlex Deucher */ 44097b2e202SAlex Deucher 44197b2e202SAlex Deucher struct amdgpu_ib { 44297b2e202SAlex Deucher struct amdgpu_sa_bo *sa_bo; 44397b2e202SAlex Deucher uint32_t length_dw; 44497b2e202SAlex Deucher uint64_t gpu_addr; 44597b2e202SAlex Deucher uint32_t *ptr; 446de807f81SJammy Zhou uint32_t flags; 44797b2e202SAlex Deucher }; 44897b2e202SAlex Deucher 4491b1f42d8SLucas Stach extern const struct drm_sched_backend_ops amdgpu_sched_ops; 450c1b69ed0SChunming Zhou 45197b2e202SAlex Deucher /* 45297b2e202SAlex Deucher * file private structure 45397b2e202SAlex Deucher */ 45497b2e202SAlex Deucher 45597b2e202SAlex Deucher struct amdgpu_fpriv { 45697b2e202SAlex Deucher struct amdgpu_vm vm; 457b85891bdSJunwei Zhang struct amdgpu_bo_va *prt_va; 4580f4b3c68SChristian König struct amdgpu_bo_va *csa_va; 45997b2e202SAlex Deucher struct mutex bo_list_lock; 46097b2e202SAlex Deucher struct idr bo_list_handles; 46197b2e202SAlex Deucher struct amdgpu_ctx_mgr ctx_mgr; 46297b2e202SAlex Deucher }; 46397b2e202SAlex Deucher 464021830d2SBas Nieuwenhuizen int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 465021830d2SBas Nieuwenhuizen 466b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 467c8e42d57Sxinhui pan unsigned size, 468c8e42d57Sxinhui pan enum amdgpu_ib_pool_type pool, 469c8e42d57Sxinhui pan struct amdgpu_ib *ib); 4704d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 471f54d1867SChris Wilson struct dma_fence *f); 472b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 47350ddc75eSJunwei Zhang struct amdgpu_ib *ibs, struct amdgpu_job *job, 47450ddc75eSJunwei Zhang struct dma_fence **f); 47597b2e202SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev); 47697b2e202SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 47797b2e202SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 47897b2e202SAlex Deucher 47997b2e202SAlex Deucher /* 48097b2e202SAlex Deucher * CS. 48197b2e202SAlex Deucher */ 48297b2e202SAlex Deucher struct amdgpu_cs_chunk { 48397b2e202SAlex Deucher uint32_t chunk_id; 48497b2e202SAlex Deucher uint32_t length_dw; 485758ac17fSChristian König void *kdata; 48697b2e202SAlex Deucher }; 48797b2e202SAlex Deucher 4882624dd15SChunming Zhou struct amdgpu_cs_post_dep { 4892624dd15SChunming Zhou struct drm_syncobj *syncobj; 4902624dd15SChunming Zhou struct dma_fence_chain *chain; 4912624dd15SChunming Zhou u64 point; 4922624dd15SChunming Zhou }; 4932624dd15SChunming Zhou 49497b2e202SAlex Deucher struct amdgpu_cs_parser { 49597b2e202SAlex Deucher struct amdgpu_device *adev; 49697b2e202SAlex Deucher struct drm_file *filp; 4973cb485f3SChristian König struct amdgpu_ctx *ctx; 498c3cca41eSChristian König 49997b2e202SAlex Deucher /* chunks */ 50097b2e202SAlex Deucher unsigned nchunks; 50197b2e202SAlex Deucher struct amdgpu_cs_chunk *chunks; 502c3cca41eSChristian König 50350838c8cSChristian König /* scheduler job object */ 50450838c8cSChristian König struct amdgpu_job *job; 5050d346a14SChristian König struct drm_sched_entity *entity; 506c3cca41eSChristian König 507c3cca41eSChristian König /* buffer objects */ 508c3cca41eSChristian König struct ww_acquire_ctx ticket; 509c3cca41eSChristian König struct amdgpu_bo_list *bo_list; 5103fe89771SChristian König struct amdgpu_mn *mn; 51156467ebfSChristian König struct amdgpu_bo_list_entry vm_pd; 51297b2e202SAlex Deucher struct list_head validated; 513f54d1867SChris Wilson struct dma_fence *fence; 514f69f90a1SChristian König uint64_t bytes_moved_threshold; 51500f06b24SJohn Brooks uint64_t bytes_moved_vis_threshold; 516f69f90a1SChristian König uint64_t bytes_moved; 51700f06b24SJohn Brooks uint64_t bytes_moved_vis; 51897b2e202SAlex Deucher 51997b2e202SAlex Deucher /* user fence */ 52091acbeb6SChristian König struct amdgpu_bo_list_entry uf_entry; 521660e8558SDave Airlie 5222624dd15SChunming Zhou unsigned num_post_deps; 5232624dd15SChunming Zhou struct amdgpu_cs_post_dep *post_deps; 52497b2e202SAlex Deucher }; 52597b2e202SAlex Deucher 5267270f839SChristian König static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 5277270f839SChristian König uint32_t ib_idx, int idx) 52897b2e202SAlex Deucher { 52950838c8cSChristian König return p->job->ibs[ib_idx].ptr[idx]; 53097b2e202SAlex Deucher } 53197b2e202SAlex Deucher 5327270f839SChristian König static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 5337270f839SChristian König uint32_t ib_idx, int idx, 5347270f839SChristian König uint32_t value) 5357270f839SChristian König { 53650838c8cSChristian König p->job->ibs[ib_idx].ptr[idx] = value; 5377270f839SChristian König } 5387270f839SChristian König 53997b2e202SAlex Deucher /* 54097b2e202SAlex Deucher * Writeback 54197b2e202SAlex Deucher */ 54254208194SYintian Tao #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 54397b2e202SAlex Deucher 54497b2e202SAlex Deucher struct amdgpu_wb { 54597b2e202SAlex Deucher struct amdgpu_bo *wb_obj; 54697b2e202SAlex Deucher volatile uint32_t *wb; 54797b2e202SAlex Deucher uint64_t gpu_addr; 54897b2e202SAlex Deucher u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 54997b2e202SAlex Deucher unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 55097b2e202SAlex Deucher }; 55197b2e202SAlex Deucher 552131b4b36SAlex Deucher int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 553131b4b36SAlex Deucher void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 55497b2e202SAlex Deucher 55597b2e202SAlex Deucher /* 55697b2e202SAlex Deucher * Benchmarking 55797b2e202SAlex Deucher */ 55897b2e202SAlex Deucher void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 55997b2e202SAlex Deucher 56097b2e202SAlex Deucher 56197b2e202SAlex Deucher /* 56297b2e202SAlex Deucher * Testing 56397b2e202SAlex Deucher */ 56497b2e202SAlex Deucher void amdgpu_test_moves(struct amdgpu_device *adev); 56597b2e202SAlex Deucher 56697b2e202SAlex Deucher /* 56797b2e202SAlex Deucher * ASIC specific register table accessible by UMD 56897b2e202SAlex Deucher */ 56997b2e202SAlex Deucher struct amdgpu_allowed_register_entry { 57097b2e202SAlex Deucher uint32_t reg_offset; 57197b2e202SAlex Deucher bool grbm_indexed; 57297b2e202SAlex Deucher }; 57397b2e202SAlex Deucher 5740cf3c64fSAlex Deucher enum amd_reset_method { 5750cf3c64fSAlex Deucher AMD_RESET_METHOD_LEGACY = 0, 5760cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE0, 5770cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE1, 5780cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE2, 5790cf3c64fSAlex Deucher AMD_RESET_METHOD_BACO 5800cf3c64fSAlex Deucher }; 5810cf3c64fSAlex Deucher 58297b2e202SAlex Deucher /* 58397b2e202SAlex Deucher * ASIC specific functions. 58497b2e202SAlex Deucher */ 58597b2e202SAlex Deucher struct amdgpu_asic_funcs { 58697b2e202SAlex Deucher bool (*read_disabled_bios)(struct amdgpu_device *adev); 5877946b878SAlex Deucher bool (*read_bios_from_rom)(struct amdgpu_device *adev, 5887946b878SAlex Deucher u8 *bios, u32 length_bytes); 58997b2e202SAlex Deucher int (*read_register)(struct amdgpu_device *adev, u32 se_num, 59097b2e202SAlex Deucher u32 sh_num, u32 reg_offset, u32 *value); 59197b2e202SAlex Deucher void (*set_vga_state)(struct amdgpu_device *adev, bool state); 59297b2e202SAlex Deucher int (*reset)(struct amdgpu_device *adev); 5930cf3c64fSAlex Deucher enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 59497b2e202SAlex Deucher /* get the reference clock */ 59597b2e202SAlex Deucher u32 (*get_xclk)(struct amdgpu_device *adev); 59697b2e202SAlex Deucher /* MM block clocks */ 59797b2e202SAlex Deucher int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 59897b2e202SAlex Deucher int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 599841686dfSMaruthi Bayyavarapu /* static power management */ 600841686dfSMaruthi Bayyavarapu int (*get_pcie_lanes)(struct amdgpu_device *adev); 601841686dfSMaruthi Bayyavarapu void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 602bbf282d8SAlex Deucher /* get config memsize register */ 603bbf282d8SAlex Deucher u32 (*get_config_memsize)(struct amdgpu_device *adev); 6042df1b8b6SAlex Deucher /* flush hdp write queue */ 60569882565SChristian König void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 6062df1b8b6SAlex Deucher /* invalidate hdp read cache */ 60769882565SChristian König void (*invalidate_hdp)(struct amdgpu_device *adev, 60869882565SChristian König struct amdgpu_ring *ring); 6094a89ad9bSHawking Zhang void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev); 61069070690SAlex Deucher /* check if the asic needs a full reset of if soft reset will work */ 61169070690SAlex Deucher bool (*need_full_reset)(struct amdgpu_device *adev); 6125253163aSOak Zeng /* initialize doorbell layout for specific asic*/ 6135253163aSOak Zeng void (*init_doorbell_index)(struct amdgpu_device *adev); 614b45e18acSKent Russell /* PCIe bandwidth usage */ 615b45e18acSKent Russell void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 616b45e18acSKent Russell uint64_t *count1); 61744401889SAlex Deucher /* do we need to reset the asic at init time (e.g., kexec) */ 61844401889SAlex Deucher bool (*need_reset_on_init)(struct amdgpu_device *adev); 619dcea6e65SKent Russell /* PCIe replay counter */ 620dcea6e65SKent Russell uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 62169d5436dSAlex Deucher /* device supports BACO */ 62269d5436dSAlex Deucher bool (*supports_baco)(struct amdgpu_device *adev); 6239737a923SAlex Deucher /* pre asic_init quirks */ 6249737a923SAlex Deucher void (*pre_asic_init)(struct amdgpu_device *adev); 62597b2e202SAlex Deucher }; 62697b2e202SAlex Deucher 62797b2e202SAlex Deucher /* 62897b2e202SAlex Deucher * IOCTL. 62997b2e202SAlex Deucher */ 63097b2e202SAlex Deucher int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 63197b2e202SAlex Deucher struct drm_file *filp); 63297b2e202SAlex Deucher 63397b2e202SAlex Deucher int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 6347ca24cf2SMarek Olšák int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 6357ca24cf2SMarek Olšák struct drm_file *filp); 63697b2e202SAlex Deucher int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 637eef18a82SJunwei Zhang int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 638eef18a82SJunwei Zhang struct drm_file *filp); 63997b2e202SAlex Deucher 64097b2e202SAlex Deucher /* VRAM scratch page for HDP bug, default vram page */ 64197b2e202SAlex Deucher struct amdgpu_vram_scratch { 64297b2e202SAlex Deucher struct amdgpu_bo *robj; 64397b2e202SAlex Deucher volatile uint32_t *ptr; 64497b2e202SAlex Deucher u64 gpu_addr; 64597b2e202SAlex Deucher }; 64697b2e202SAlex Deucher 64797b2e202SAlex Deucher /* 64897b2e202SAlex Deucher * ACPI 64997b2e202SAlex Deucher */ 65097b2e202SAlex Deucher struct amdgpu_atcs_functions { 65197b2e202SAlex Deucher bool get_ext_state; 65297b2e202SAlex Deucher bool pcie_perf_req; 65397b2e202SAlex Deucher bool pcie_dev_rdy; 65497b2e202SAlex Deucher bool pcie_bus_width; 65597b2e202SAlex Deucher }; 65697b2e202SAlex Deucher 65797b2e202SAlex Deucher struct amdgpu_atcs { 65897b2e202SAlex Deucher struct amdgpu_atcs_functions functions; 65997b2e202SAlex Deucher }; 66097b2e202SAlex Deucher 66197b2e202SAlex Deucher /* 662d03846afSChunming Zhou * CGS 663d03846afSChunming Zhou */ 664110e6f26SDave Airlie struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 665110e6f26SDave Airlie void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 666a8fe58ceSMaruthi Bayyavarapu 667a8fe58ceSMaruthi Bayyavarapu /* 66897b2e202SAlex Deucher * Core structure, functions and helpers. 66997b2e202SAlex Deucher */ 67097b2e202SAlex Deucher typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 67197b2e202SAlex Deucher typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 67297b2e202SAlex Deucher 6734fa1c6a6STao Zhou typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 6744fa1c6a6STao Zhou typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 6754fa1c6a6STao Zhou 67697b2e202SAlex Deucher typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 67797b2e202SAlex Deucher typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 67897b2e202SAlex Deucher 67988807dc8SOak Zeng struct amdgpu_mmio_remap { 68088807dc8SOak Zeng u32 reg_offset; 68188807dc8SOak Zeng resource_size_t bus_addr; 68288807dc8SOak Zeng }; 68388807dc8SOak Zeng 6844522824cSShaoyun Liu /* Define the HW IP blocks will be used in driver , add more if necessary */ 6854522824cSShaoyun Liu enum amd_hw_ip_block_type { 6864522824cSShaoyun Liu GC_HWIP = 1, 6874522824cSShaoyun Liu HDP_HWIP, 6884522824cSShaoyun Liu SDMA0_HWIP, 6894522824cSShaoyun Liu SDMA1_HWIP, 690fa5d2e6fSLe Ma SDMA2_HWIP, 691fa5d2e6fSLe Ma SDMA3_HWIP, 692fa5d2e6fSLe Ma SDMA4_HWIP, 693fa5d2e6fSLe Ma SDMA5_HWIP, 694fa5d2e6fSLe Ma SDMA6_HWIP, 695fa5d2e6fSLe Ma SDMA7_HWIP, 6964522824cSShaoyun Liu MMHUB_HWIP, 6974522824cSShaoyun Liu ATHUB_HWIP, 6984522824cSShaoyun Liu NBIO_HWIP, 6994522824cSShaoyun Liu MP0_HWIP, 700e6636ae1SEvan Quan MP1_HWIP, 7014522824cSShaoyun Liu UVD_HWIP, 7024522824cSShaoyun Liu VCN_HWIP = UVD_HWIP, 70388a1c40aSLeo Liu JPEG_HWIP = VCN_HWIP, 7044522824cSShaoyun Liu VCE_HWIP, 7054522824cSShaoyun Liu DF_HWIP, 7064522824cSShaoyun Liu DCE_HWIP, 7074522824cSShaoyun Liu OSSSYS_HWIP, 7084522824cSShaoyun Liu SMUIO_HWIP, 7094522824cSShaoyun Liu PWR_HWIP, 7104522824cSShaoyun Liu NBIF_HWIP, 711e6636ae1SEvan Quan THM_HWIP, 71273b19174SRex Zhu CLK_HWIP, 7136501a771SHawking Zhang UMC_HWIP, 7146501a771SHawking Zhang RSMU_HWIP, 7154522824cSShaoyun Liu MAX_HWIP 7164522824cSShaoyun Liu }; 7174522824cSShaoyun Liu 718113b47e7SLe Ma #define HWIP_MAX_INSTANCE 8 7194522824cSShaoyun Liu 72011dc9364SRex Zhu struct amd_powerplay { 72111dc9364SRex Zhu void *pp_handle; 72211dc9364SRex Zhu const struct amd_pm_funcs *pp_funcs; 72311dc9364SRex Zhu }; 72411dc9364SRex Zhu 7250c49e0b8SChunming Zhou #define AMDGPU_RESET_MAGIC_NUM 64 726e4cf4bf5SJonathan Kim #define AMDGPU_MAX_DF_PERFMONS 4 72797b2e202SAlex Deucher struct amdgpu_device { 72897b2e202SAlex Deucher struct device *dev; 72997b2e202SAlex Deucher struct pci_dev *pdev; 7308aba21b7SLuben Tuikov struct drm_device ddev; 73197b2e202SAlex Deucher 732a8fe58ceSMaruthi Bayyavarapu #ifdef CONFIG_DRM_AMD_ACP 733a8fe58ceSMaruthi Bayyavarapu struct amdgpu_acp acp; 734a8fe58ceSMaruthi Bayyavarapu #endif 735d95e8e97SDennis Li struct amdgpu_hive_info *hive; 73697b2e202SAlex Deucher /* ASIC */ 7372f7d10b3SJammy Zhou enum amd_asic_type asic_type; 73897b2e202SAlex Deucher uint32_t family; 73997b2e202SAlex Deucher uint32_t rev_id; 74097b2e202SAlex Deucher uint32_t external_rev_id; 74197b2e202SAlex Deucher unsigned long flags; 74254f78a76SAlex Deucher unsigned long apu_flags; 74397b2e202SAlex Deucher int usec_timeout; 74497b2e202SAlex Deucher const struct amdgpu_asic_funcs *asic_funcs; 74597b2e202SAlex Deucher bool shutdown; 746fd5fd480SChunming Zhou bool need_swiotlb; 74797b2e202SAlex Deucher bool accel_working; 74897b2e202SAlex Deucher struct notifier_block acpi_nb; 74997b2e202SAlex Deucher struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 75097b2e202SAlex Deucher struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 75197b2e202SAlex Deucher unsigned debugfs_count; 75297b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS) 7536698a3d0SJack Xiao struct dentry *debugfs_preempt; 754adcec288STom St Denis struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 75597b2e202SAlex Deucher #endif 756102c16a0SLyude Paul struct amdgpu_atif *atif; 75797b2e202SAlex Deucher struct amdgpu_atcs atcs; 75897b2e202SAlex Deucher struct mutex srbm_mutex; 75997b2e202SAlex Deucher /* GRBM index mutex. Protects concurrent access to GRBM index */ 76097b2e202SAlex Deucher struct mutex grbm_idx_mutex; 76197b2e202SAlex Deucher struct dev_pm_domain vga_pm_domain; 76297b2e202SAlex Deucher bool have_disp_power_ref; 763bae17d2aSJack Xiao bool have_atomics_support; 76497b2e202SAlex Deucher 76597b2e202SAlex Deucher /* BIOS */ 7660cdd5005SAlex Deucher bool is_atom_fw; 76797b2e202SAlex Deucher uint8_t *bios; 768a9f5db9cSEvan Quan uint32_t bios_size; 769a5bde2f9SAlex Deucher uint32_t bios_scratch_reg_offset; 77097b2e202SAlex Deucher uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 77197b2e202SAlex Deucher 77297b2e202SAlex Deucher /* Register/doorbell mmio */ 77397b2e202SAlex Deucher resource_size_t rmmio_base; 77497b2e202SAlex Deucher resource_size_t rmmio_size; 77597b2e202SAlex Deucher void __iomem *rmmio; 77697b2e202SAlex Deucher /* protects concurrent MM_INDEX/DATA based register access */ 77797b2e202SAlex Deucher spinlock_t mmio_idx_lock; 77888807dc8SOak Zeng struct amdgpu_mmio_remap rmmio_remap; 77997b2e202SAlex Deucher /* protects concurrent SMC based register access */ 78097b2e202SAlex Deucher spinlock_t smc_idx_lock; 78197b2e202SAlex Deucher amdgpu_rreg_t smc_rreg; 78297b2e202SAlex Deucher amdgpu_wreg_t smc_wreg; 78397b2e202SAlex Deucher /* protects concurrent PCIE register access */ 78497b2e202SAlex Deucher spinlock_t pcie_idx_lock; 78597b2e202SAlex Deucher amdgpu_rreg_t pcie_rreg; 78697b2e202SAlex Deucher amdgpu_wreg_t pcie_wreg; 78736b9a952SHuang Rui amdgpu_rreg_t pciep_rreg; 78836b9a952SHuang Rui amdgpu_wreg_t pciep_wreg; 7894fa1c6a6STao Zhou amdgpu_rreg64_t pcie_rreg64; 7904fa1c6a6STao Zhou amdgpu_wreg64_t pcie_wreg64; 79197b2e202SAlex Deucher /* protects concurrent UVD register access */ 79297b2e202SAlex Deucher spinlock_t uvd_ctx_idx_lock; 79397b2e202SAlex Deucher amdgpu_rreg_t uvd_ctx_rreg; 79497b2e202SAlex Deucher amdgpu_wreg_t uvd_ctx_wreg; 79597b2e202SAlex Deucher /* protects concurrent DIDT register access */ 79697b2e202SAlex Deucher spinlock_t didt_idx_lock; 79797b2e202SAlex Deucher amdgpu_rreg_t didt_rreg; 79897b2e202SAlex Deucher amdgpu_wreg_t didt_wreg; 799ccdbb20aSRex Zhu /* protects concurrent gc_cac register access */ 800ccdbb20aSRex Zhu spinlock_t gc_cac_idx_lock; 801ccdbb20aSRex Zhu amdgpu_rreg_t gc_cac_rreg; 802ccdbb20aSRex Zhu amdgpu_wreg_t gc_cac_wreg; 80316abb5d2SEvan Quan /* protects concurrent se_cac register access */ 80416abb5d2SEvan Quan spinlock_t se_cac_idx_lock; 80516abb5d2SEvan Quan amdgpu_rreg_t se_cac_rreg; 80616abb5d2SEvan Quan amdgpu_wreg_t se_cac_wreg; 80797b2e202SAlex Deucher /* protects concurrent ENDPOINT (audio) register access */ 80897b2e202SAlex Deucher spinlock_t audio_endpt_idx_lock; 80997b2e202SAlex Deucher amdgpu_block_rreg_t audio_endpt_rreg; 81097b2e202SAlex Deucher amdgpu_block_wreg_t audio_endpt_wreg; 81197b2e202SAlex Deucher void __iomem *rio_mem; 81297b2e202SAlex Deucher resource_size_t rio_mem_size; 81397b2e202SAlex Deucher struct amdgpu_doorbell doorbell; 81497b2e202SAlex Deucher 81597b2e202SAlex Deucher /* clock/pll info */ 81697b2e202SAlex Deucher struct amdgpu_clock clock; 81797b2e202SAlex Deucher 81897b2e202SAlex Deucher /* MC */ 819770d13b1SChristian König struct amdgpu_gmc gmc; 82097b2e202SAlex Deucher struct amdgpu_gart gart; 82192e71b06SChristian König dma_addr_t dummy_page_addr; 82297b2e202SAlex Deucher struct amdgpu_vm_manager vm_manager; 823e60f8db5SAlex Xie struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 8241daa2bfaSLe Ma unsigned num_vmhubs; 82597b2e202SAlex Deucher 82697b2e202SAlex Deucher /* memory management */ 82797b2e202SAlex Deucher struct amdgpu_mman mman; 82897b2e202SAlex Deucher struct amdgpu_vram_scratch vram_scratch; 82997b2e202SAlex Deucher struct amdgpu_wb wb; 83097b2e202SAlex Deucher atomic64_t num_bytes_moved; 831dbd5ed60SChristian König atomic64_t num_evictions; 83268e2c5ffSMarek Olšák atomic64_t num_vram_cpu_page_faults; 833d94aed5aSMarek Olšák atomic_t gpu_reset_counter; 834f1892138SChunming Zhou atomic_t vram_lost_counter; 83597b2e202SAlex Deucher 83695844d20SMarek Olšák /* data for buffer migration throttling */ 83795844d20SMarek Olšák struct { 83895844d20SMarek Olšák spinlock_t lock; 83995844d20SMarek Olšák s64 last_update_us; 84095844d20SMarek Olšák s64 accum_us; /* accumulated microseconds */ 84100f06b24SJohn Brooks s64 accum_us_vis; /* for visible VRAM */ 84295844d20SMarek Olšák u32 log2_max_MBps; 84395844d20SMarek Olšák } mm_stats; 84495844d20SMarek Olšák 84597b2e202SAlex Deucher /* display */ 8469accf2fdSEmily Deng bool enable_virtual_display; 84797b2e202SAlex Deucher struct amdgpu_mode_info mode_info; 8484562236bSHarry Wentland /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 84997b2e202SAlex Deucher struct work_struct hotplug_work; 85097b2e202SAlex Deucher struct amdgpu_irq_src crtc_irq; 851d2574c33SMario Kleiner struct amdgpu_irq_src vupdate_irq; 85297b2e202SAlex Deucher struct amdgpu_irq_src pageflip_irq; 85397b2e202SAlex Deucher struct amdgpu_irq_src hpd_irq; 85497b2e202SAlex Deucher 85597b2e202SAlex Deucher /* rings */ 85676bf0db5SChristian König u64 fence_context; 85797b2e202SAlex Deucher unsigned num_rings; 85897b2e202SAlex Deucher struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 85997b2e202SAlex Deucher bool ib_pool_ready; 8609ecefb19SChristian König struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 8611c6d567bSNirmoy Das struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 86297b2e202SAlex Deucher 86397b2e202SAlex Deucher /* interrupts */ 86497b2e202SAlex Deucher struct amdgpu_irq irq; 86597b2e202SAlex Deucher 8661f7371b2SAlex Deucher /* powerplay */ 8671f7371b2SAlex Deucher struct amd_powerplay powerplay; 868f3898ea1SEric Huang bool pp_force_state_enabled; 8691f7371b2SAlex Deucher 870137d63abSHuang Rui /* smu */ 871137d63abSHuang Rui struct smu_context smu; 872137d63abSHuang Rui 87397b2e202SAlex Deucher /* dpm */ 87497b2e202SAlex Deucher struct amdgpu_pm pm; 87597b2e202SAlex Deucher u32 cg_flags; 87697b2e202SAlex Deucher u32 pg_flags; 87797b2e202SAlex Deucher 878bebc0762SHawking Zhang /* nbio */ 879bebc0762SHawking Zhang struct amdgpu_nbio nbio; 880bebc0762SHawking Zhang 881d3a5a121STao Zhou /* mmhub */ 882d3a5a121STao Zhou struct amdgpu_mmhub mmhub; 883d3a5a121STao Zhou 88497b2e202SAlex Deucher /* gfx */ 88597b2e202SAlex Deucher struct amdgpu_gfx gfx; 88697b2e202SAlex Deucher 88797b2e202SAlex Deucher /* sdma */ 888c113ea1cSAlex Deucher struct amdgpu_sdma sdma; 88997b2e202SAlex Deucher 89097b2e202SAlex Deucher /* uvd */ 89197b2e202SAlex Deucher struct amdgpu_uvd uvd; 89297b2e202SAlex Deucher 89397b2e202SAlex Deucher /* vce */ 89497b2e202SAlex Deucher struct amdgpu_vce vce; 89595d0906fSLeo Liu 89695d0906fSLeo Liu /* vcn */ 89795d0906fSLeo Liu struct amdgpu_vcn vcn; 89897b2e202SAlex Deucher 89988a1c40aSLeo Liu /* jpeg */ 90088a1c40aSLeo Liu struct amdgpu_jpeg jpeg; 90188a1c40aSLeo Liu 90297b2e202SAlex Deucher /* firmwares */ 90397b2e202SAlex Deucher struct amdgpu_firmware firmware; 90497b2e202SAlex Deucher 9050e5ca0d1SHuang Rui /* PSP */ 9060e5ca0d1SHuang Rui struct psp_context psp; 9070e5ca0d1SHuang Rui 90897b2e202SAlex Deucher /* GDS */ 90997b2e202SAlex Deucher struct amdgpu_gds gds; 91097b2e202SAlex Deucher 911611736d8SFelix Kuehling /* KFD */ 912611736d8SFelix Kuehling struct amdgpu_kfd_dev kfd; 913611736d8SFelix Kuehling 914045c0216STao Zhou /* UMC */ 915045c0216STao Zhou struct amdgpu_umc umc; 916045c0216STao Zhou 9174562236bSHarry Wentland /* display related functionality */ 9184562236bSHarry Wentland struct amdgpu_display_manager dm; 9194562236bSHarry Wentland 920a538bbe7SJack Xiao /* mes */ 921a538bbe7SJack Xiao bool enable_mes; 922a538bbe7SJack Xiao struct amdgpu_mes mes; 923a538bbe7SJack Xiao 924bdf84a80SJoseph Greathouse /* df */ 925bdf84a80SJoseph Greathouse struct amdgpu_df df; 926bdf84a80SJoseph Greathouse 927a1255107SAlex Deucher struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 92897b2e202SAlex Deucher int num_ip_blocks; 92997b2e202SAlex Deucher struct mutex mn_lock; 93097b2e202SAlex Deucher DECLARE_HASHTABLE(mn_hash, 7); 93197b2e202SAlex Deucher 93297b2e202SAlex Deucher /* tracking pinned memory */ 933a5ccfe5cSMichel Dänzer atomic64_t vram_pin_size; 934a5ccfe5cSMichel Dänzer atomic64_t visible_pin_size; 935a5ccfe5cSMichel Dänzer atomic64_t gart_pin_size; 936130e0371SOded Gabbay 9374522824cSShaoyun Liu /* soc15 register offset based on ip, instance and segment */ 9384522824cSShaoyun Liu uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 9394522824cSShaoyun Liu 9402dc80b00SShirish S /* delayed work_func for deferring clockgating during resume */ 941beff74bcSAlex Deucher struct delayed_work delayed_init_work; 9422dc80b00SShirish S 9435a5099cbSXiangliang Yu struct amdgpu_virt virt; 9440c4e7fa5SChunming Zhou 9450c4e7fa5SChunming Zhou /* link all shadow bo */ 9460c4e7fa5SChunming Zhou struct list_head shadow_list; 9470c4e7fa5SChunming Zhou struct mutex shadow_list_lock; 9485c1354bdSChunming Zhou 949c836fec5SJim Qu /* record hw reset is performed */ 950c836fec5SJim Qu bool has_hw_reset; 9510c49e0b8SChunming Zhou u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 952c836fec5SJim Qu 95344779b43SRex Zhu /* s3/s4 mask */ 95444779b43SRex Zhu bool in_suspend; 95585625e64SEvan Quan bool in_hibernate; 95644779b43SRex Zhu 95753b3f8f4SDennis Li atomic_t in_gpu_reset; 958a3a09142SAlex Deucher enum pp_mp1_state mp1_state; 9596049db43SDennis Li struct rw_semaphore reset_sem; 960409c5191SOak Zeng struct amdgpu_doorbell_index doorbell_index; 961d4535e2cSAndrey Grodzovsky 96262914a99SJason Gunthorpe struct mutex notifier_lock; 96362914a99SJason Gunthorpe 96426bc5340SAndrey Grodzovsky int asic_reset_res; 965d4535e2cSAndrey Grodzovsky struct work_struct xgmi_reset_work; 9669b638f97Sshaoyunl 967912dfc84SEvan Quan long gfx_timeout; 968912dfc84SEvan Quan long sdma_timeout; 969912dfc84SEvan Quan long video_timeout; 970912dfc84SEvan Quan long compute_timeout; 971fb2dbfd2SKent Russell 972fb2dbfd2SKent Russell uint64_t unique_id; 973e4cf4bf5SJonathan Kim uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 9745c5b2ba0SEvan Quan 9756ae6c7d4SAlex Deucher /* enable runtime pm on the device */ 9766ae6c7d4SAlex Deucher bool runpm; 977f0f7ddfcSAlex Deucher bool in_runpm; 9787c868b59SYintian Tao 9797c868b59SYintian Tao bool pm_sysfs_en; 9807c868b59SYintian Tao bool ucode_sysfs_en; 981bd607166SKent Russell 982bd607166SKent Russell /* Chip product information */ 983bd607166SKent Russell char product_number[16]; 984bd607166SKent Russell char product_name[32]; 9858df1a28fSDan Carpenter char serial[20]; 986728e7e0cSJiange Zhao 987728e7e0cSJiange Zhao struct amdgpu_autodump autodump; 988b265bdbdSEvan Quan 989b265bdbdSEvan Quan atomic_t throttling_logging_enabled; 990b265bdbdSEvan Quan struct ratelimit_state throttling_logging_rs; 9915436ab94SStanley.Yang uint32_t ras_features; 992bf36b52eSAndrey Grodzovsky bool in_pci_err_recovery; 99397b2e202SAlex Deucher }; 99497b2e202SAlex Deucher 9951348969aSLuben Tuikov static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 9961348969aSLuben Tuikov { 9978aba21b7SLuben Tuikov return container_of(ddev, struct amdgpu_device, ddev); 9981348969aSLuben Tuikov } 9991348969aSLuben Tuikov 10004a580877SLuben Tuikov static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 10014a580877SLuben Tuikov { 10028aba21b7SLuben Tuikov return &adev->ddev; 10034a580877SLuben Tuikov } 10044a580877SLuben Tuikov 1005a7d64de6SChristian König static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1006a7d64de6SChristian König { 1007a7d64de6SChristian König return container_of(bdev, struct amdgpu_device, mman.bdev); 1008a7d64de6SChristian König } 1009a7d64de6SChristian König 101097b2e202SAlex Deucher int amdgpu_device_init(struct amdgpu_device *adev, 101197b2e202SAlex Deucher uint32_t flags); 101297b2e202SAlex Deucher void amdgpu_device_fini(struct amdgpu_device *adev); 101397b2e202SAlex Deucher int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 101497b2e202SAlex Deucher 1015e35e2b11STianci.Yin void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1016e35e2b11STianci.Yin uint32_t *buf, size_t size, bool write); 1017e78b579dSHawking Zhang uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 101815d72fd7SMonk Liu uint32_t acc_flags); 1019e78b579dSHawking Zhang void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 102015d72fd7SMonk Liu uint32_t acc_flags); 10212e0cc4d4SMonk Liu void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 10222e0cc4d4SMonk Liu uint32_t acc_flags); 1023421a2a30SMonk Liu void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1024421a2a30SMonk Liu uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1025421a2a30SMonk Liu 102697b2e202SAlex Deucher u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 102797b2e202SAlex Deucher void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 102897b2e202SAlex Deucher 10294562236bSHarry Wentland bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 10304562236bSHarry Wentland bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 10314562236bSHarry Wentland 10329475a943SShaoyun Liu int emu_soc_asic_init(struct amdgpu_device *adev); 10339475a943SShaoyun Liu 103497b2e202SAlex Deucher /* 103597b2e202SAlex Deucher * Registers read & write functions. 103697b2e202SAlex Deucher */ 103715d72fd7SMonk Liu #define AMDGPU_REGS_NO_KIQ (1<<1) 103815d72fd7SMonk Liu 1039e78b579dSHawking Zhang #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1040e78b579dSHawking Zhang #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 104115d72fd7SMonk Liu 1042f384ff95SHawking Zhang #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1043f384ff95SHawking Zhang #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1044c68dbcd8Schen gong 1045421a2a30SMonk Liu #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1046421a2a30SMonk Liu #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1047421a2a30SMonk Liu 1048e78b579dSHawking Zhang #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1049e78b579dSHawking Zhang #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1050e78b579dSHawking Zhang #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 105197b2e202SAlex Deucher #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 105297b2e202SAlex Deucher #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 105397b2e202SAlex Deucher #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 105497b2e202SAlex Deucher #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 105536b9a952SHuang Rui #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 105636b9a952SHuang Rui #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 10574fa1c6a6STao Zhou #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 10584fa1c6a6STao Zhou #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 105997b2e202SAlex Deucher #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 106097b2e202SAlex Deucher #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 106197b2e202SAlex Deucher #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 106297b2e202SAlex Deucher #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 106397b2e202SAlex Deucher #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 106497b2e202SAlex Deucher #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1065ccdbb20aSRex Zhu #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1066ccdbb20aSRex Zhu #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 106716abb5d2SEvan Quan #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 106816abb5d2SEvan Quan #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 106997b2e202SAlex Deucher #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 107097b2e202SAlex Deucher #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 107197b2e202SAlex Deucher #define WREG32_P(reg, val, mask) \ 107297b2e202SAlex Deucher do { \ 107397b2e202SAlex Deucher uint32_t tmp_ = RREG32(reg); \ 107497b2e202SAlex Deucher tmp_ &= (mask); \ 107597b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 107697b2e202SAlex Deucher WREG32(reg, tmp_); \ 107797b2e202SAlex Deucher } while (0) 107897b2e202SAlex Deucher #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 107997b2e202SAlex Deucher #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 108097b2e202SAlex Deucher #define WREG32_PLL_P(reg, val, mask) \ 108197b2e202SAlex Deucher do { \ 108297b2e202SAlex Deucher uint32_t tmp_ = RREG32_PLL(reg); \ 108397b2e202SAlex Deucher tmp_ &= (mask); \ 108497b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 108597b2e202SAlex Deucher WREG32_PLL(reg, tmp_); \ 108697b2e202SAlex Deucher } while (0) 1087fb40bcebSAlex Jivin 1088fb40bcebSAlex Jivin #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1089fb40bcebSAlex Jivin do { \ 1090fb40bcebSAlex Jivin u32 tmp = RREG32_SMC(_Reg); \ 1091fb40bcebSAlex Jivin tmp &= (_Mask); \ 1092fb40bcebSAlex Jivin tmp |= ((_Val) & ~(_Mask)); \ 1093fb40bcebSAlex Jivin WREG32_SMC(_Reg, tmp); \ 1094fb40bcebSAlex Jivin } while (0) 1095fb40bcebSAlex Jivin 1096e78b579dSHawking Zhang #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 109797b2e202SAlex Deucher #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 109897b2e202SAlex Deucher #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 109997b2e202SAlex Deucher 110097b2e202SAlex Deucher #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 110197b2e202SAlex Deucher #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 110297b2e202SAlex Deucher 110397b2e202SAlex Deucher #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 110497b2e202SAlex Deucher (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 110597b2e202SAlex Deucher (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 110697b2e202SAlex Deucher 110797b2e202SAlex Deucher #define REG_GET_FIELD(value, reg, field) \ 110897b2e202SAlex Deucher (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 110997b2e202SAlex Deucher 111061cb8cefSTom St Denis #define WREG32_FIELD(reg, field, val) \ 111161cb8cefSTom St Denis WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 111261cb8cefSTom St Denis 1113ccaf3574STom St Denis #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1114ccaf3574STom St Denis WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1115ccaf3574STom St Denis 111697b2e202SAlex Deucher /* 111797b2e202SAlex Deucher * BIOS helpers. 111897b2e202SAlex Deucher */ 111997b2e202SAlex Deucher #define RBIOS8(i) (adev->bios[i]) 112097b2e202SAlex Deucher #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 112197b2e202SAlex Deucher #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 112297b2e202SAlex Deucher 112397b2e202SAlex Deucher /* 112497b2e202SAlex Deucher * ASICs macro. 112597b2e202SAlex Deucher */ 112697b2e202SAlex Deucher #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 112797b2e202SAlex Deucher #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 11280cf3c64fSAlex Deucher #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 112997b2e202SAlex Deucher #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 113097b2e202SAlex Deucher #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 113197b2e202SAlex Deucher #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1132841686dfSMaruthi Bayyavarapu #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1133841686dfSMaruthi Bayyavarapu #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1134841686dfSMaruthi Bayyavarapu #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 113597b2e202SAlex Deucher #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 11367946b878SAlex Deucher #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 113797b2e202SAlex Deucher #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1138bbf282d8SAlex Deucher #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 113969882565SChristian König #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 114069882565SChristian König #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 114169070690SAlex Deucher #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 11425253163aSOak Zeng #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1143b45e18acSKent Russell #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 114444401889SAlex Deucher #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1145dcea6e65SKent Russell #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 114669d5436dSAlex Deucher #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 11479737a923SAlex Deucher #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 114869d5436dSAlex Deucher 1149e3526257SMonk Liu #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 115097b2e202SAlex Deucher 115197b2e202SAlex Deucher /* Common functions */ 11529a1cddd6Sjqdeng bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 115312938fadSChristian König bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 11545f152b5eSAlex Deucher int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 115512938fadSChristian König struct amdgpu_job* job); 11568111c387SAlex Deucher void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 115739c640c0SAlex Deucher bool amdgpu_device_need_post(struct amdgpu_device *adev); 1158d5fc5e82SChunming Zhou 115900f06b24SJohn Brooks void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 116000f06b24SJohn Brooks u64 num_vis_bytes); 1161d6895ad3SChristian König int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 11629c3f2b54SAlex Deucher void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 116397b2e202SAlex Deucher const u32 *registers, 116497b2e202SAlex Deucher const u32 array_size); 116597b2e202SAlex Deucher 116631af062aSAlex Deucher bool amdgpu_device_supports_boco(struct drm_device *dev); 1167a69cba42SAlex Deucher bool amdgpu_device_supports_baco(struct drm_device *dev); 1168992af942SJonathan Kim bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1169992af942SJonathan Kim struct amdgpu_device *peer_adev); 1170361dbd01SAlex Deucher int amdgpu_device_baco_enter(struct drm_device *dev); 1171361dbd01SAlex Deucher int amdgpu_device_baco_exit(struct drm_device *dev); 1172992af942SJonathan Kim 117397b2e202SAlex Deucher /* atpx handler */ 117497b2e202SAlex Deucher #if defined(CONFIG_VGA_SWITCHEROO) 117597b2e202SAlex Deucher void amdgpu_register_atpx_handler(void); 117697b2e202SAlex Deucher void amdgpu_unregister_atpx_handler(void); 1177a78fe133SAlex Deucher bool amdgpu_has_atpx_dgpu_power_cntl(void); 11782f5af82eSAlex Deucher bool amdgpu_is_atpx_hybrid(void); 1179efc83cf4SAlex Deucher bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1180714f88e0SAlex Xie bool amdgpu_has_atpx(void); 118197b2e202SAlex Deucher #else 118297b2e202SAlex Deucher static inline void amdgpu_register_atpx_handler(void) {} 118397b2e202SAlex Deucher static inline void amdgpu_unregister_atpx_handler(void) {} 1184a78fe133SAlex Deucher static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 11852f5af82eSAlex Deucher static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1186efc83cf4SAlex Deucher static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1187714f88e0SAlex Xie static inline bool amdgpu_has_atpx(void) { return false; } 118897b2e202SAlex Deucher #endif 118997b2e202SAlex Deucher 119024aeefcdSLyude Paul #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 119124aeefcdSLyude Paul void *amdgpu_atpx_get_dhandle(void); 119224aeefcdSLyude Paul #else 119324aeefcdSLyude Paul static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 119424aeefcdSLyude Paul #endif 119524aeefcdSLyude Paul 119697b2e202SAlex Deucher /* 119797b2e202SAlex Deucher * KMS 119897b2e202SAlex Deucher */ 119997b2e202SAlex Deucher extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1200f498d9edSNils Wallménius extern const int amdgpu_max_kms_ioctl; 120197b2e202SAlex Deucher 12028aba21b7SLuben Tuikov int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 120311b3c20bSGabriel Krisman Bertazi void amdgpu_driver_unload_kms(struct drm_device *dev); 120497b2e202SAlex Deucher void amdgpu_driver_lastclose_kms(struct drm_device *dev); 120597b2e202SAlex Deucher int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 120697b2e202SAlex Deucher void amdgpu_driver_postclose_kms(struct drm_device *dev, 120797b2e202SAlex Deucher struct drm_file *file_priv); 1208cdd61df6SAlex Deucher int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1209de185019SAlex Deucher int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1210de185019SAlex Deucher int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1211e3eff4b5SThomas Zimmermann u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1212e3eff4b5SThomas Zimmermann int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1213e3eff4b5SThomas Zimmermann void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 121497b2e202SAlex Deucher long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 121597b2e202SAlex Deucher unsigned long arg); 121697b2e202SAlex Deucher 121797b2e202SAlex Deucher /* 121897b2e202SAlex Deucher * functions used by amdgpu_encoder.c 121997b2e202SAlex Deucher */ 122097b2e202SAlex Deucher struct amdgpu_afmt_acr { 122197b2e202SAlex Deucher u32 clock; 122297b2e202SAlex Deucher 122397b2e202SAlex Deucher int n_32khz; 122497b2e202SAlex Deucher int cts_32khz; 122597b2e202SAlex Deucher 122697b2e202SAlex Deucher int n_44_1khz; 122797b2e202SAlex Deucher int cts_44_1khz; 122897b2e202SAlex Deucher 122997b2e202SAlex Deucher int n_48khz; 123097b2e202SAlex Deucher int cts_48khz; 123197b2e202SAlex Deucher 123297b2e202SAlex Deucher }; 123397b2e202SAlex Deucher 123497b2e202SAlex Deucher struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 123597b2e202SAlex Deucher 123697b2e202SAlex Deucher /* amdgpu_acpi.c */ 123797b2e202SAlex Deucher #if defined(CONFIG_ACPI) 123897b2e202SAlex Deucher int amdgpu_acpi_init(struct amdgpu_device *adev); 123997b2e202SAlex Deucher void amdgpu_acpi_fini(struct amdgpu_device *adev); 124097b2e202SAlex Deucher bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 124197b2e202SAlex Deucher int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 124297b2e202SAlex Deucher u8 perf_req, bool advertise); 124397b2e202SAlex Deucher int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1244206bbafeSDavid Francis 1245206bbafeSDavid Francis void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1246206bbafeSDavid Francis struct amdgpu_dm_backlight_caps *caps); 124797b2e202SAlex Deucher #else 124897b2e202SAlex Deucher static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 124997b2e202SAlex Deucher static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 125097b2e202SAlex Deucher #endif 125197b2e202SAlex Deucher 12529cca0b8eSChristian König int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 12539cca0b8eSChristian König uint64_t addr, struct amdgpu_bo **bo, 12549cca0b8eSChristian König struct amdgpu_bo_va_mapping **mapping); 125597b2e202SAlex Deucher 12564562236bSHarry Wentland #if defined(CONFIG_DRM_AMD_DC) 12574562236bSHarry Wentland int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 12584562236bSHarry Wentland #else 12594562236bSHarry Wentland static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 12604562236bSHarry Wentland #endif 12614562236bSHarry Wentland 1262fdafb359SEvan Quan 1263fdafb359SEvan Quan void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1264fdafb359SEvan Quan void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1265fdafb359SEvan Quan 1266c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1267c9a6b82fSAndrey Grodzovsky pci_channel_state_t state); 1268c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1269c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1270c9a6b82fSAndrey Grodzovsky void amdgpu_pci_resume(struct pci_dev *pdev); 1271c9a6b82fSAndrey Grodzovsky 127297b2e202SAlex Deucher #include "amdgpu_object.h" 1273e4cf4bf5SJonathan Kim 1274e4cf4bf5SJonathan Kim /* used by df_v3_6.c and amdgpu_pmu.c */ 1275e4cf4bf5SJonathan Kim #define AMDGPU_PMU_ATTR(_name, _object) \ 1276e4cf4bf5SJonathan Kim static ssize_t \ 1277e4cf4bf5SJonathan Kim _name##_show(struct device *dev, \ 1278e4cf4bf5SJonathan Kim struct device_attribute *attr, \ 1279e4cf4bf5SJonathan Kim char *page) \ 1280e4cf4bf5SJonathan Kim { \ 1281e4cf4bf5SJonathan Kim BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1282e4cf4bf5SJonathan Kim return sprintf(page, _object "\n"); \ 1283e4cf4bf5SJonathan Kim } \ 1284e4cf4bf5SJonathan Kim \ 1285e4cf4bf5SJonathan Kim static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1286e4cf4bf5SJonathan Kim 1287c6252390SLuben Tuikov static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1288c6252390SLuben Tuikov { 1289c6252390SLuben Tuikov return adev->gmc.tmz_enabled; 1290c6252390SLuben Tuikov } 1291e4cf4bf5SJonathan Kim 129253b3f8f4SDennis Li static inline int amdgpu_in_reset(struct amdgpu_device *adev) 129353b3f8f4SDennis Li { 129453b3f8f4SDennis Li return atomic_read(&adev->in_gpu_reset); 129553b3f8f4SDennis Li } 1296c6252390SLuben Tuikov #endif 1297