197b2e202SAlex Deucher /* 297b2e202SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 397b2e202SAlex Deucher * Copyright 2008 Red Hat Inc. 497b2e202SAlex Deucher * Copyright 2009 Jerome Glisse. 597b2e202SAlex Deucher * 697b2e202SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 797b2e202SAlex Deucher * copy of this software and associated documentation files (the "Software"), 897b2e202SAlex Deucher * to deal in the Software without restriction, including without limitation 997b2e202SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1097b2e202SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1197b2e202SAlex Deucher * Software is furnished to do so, subject to the following conditions: 1297b2e202SAlex Deucher * 1397b2e202SAlex Deucher * The above copyright notice and this permission notice shall be included in 1497b2e202SAlex Deucher * all copies or substantial portions of the Software. 1597b2e202SAlex Deucher * 1697b2e202SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1797b2e202SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1897b2e202SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1997b2e202SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2097b2e202SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2197b2e202SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2297b2e202SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2397b2e202SAlex Deucher * 2497b2e202SAlex Deucher * Authors: Dave Airlie 2597b2e202SAlex Deucher * Alex Deucher 2697b2e202SAlex Deucher * Jerome Glisse 2797b2e202SAlex Deucher */ 2897b2e202SAlex Deucher #ifndef __AMDGPU_H__ 2997b2e202SAlex Deucher #define __AMDGPU_H__ 3097b2e202SAlex Deucher 3197b2e202SAlex Deucher #include <linux/atomic.h> 3297b2e202SAlex Deucher #include <linux/wait.h> 3397b2e202SAlex Deucher #include <linux/list.h> 3497b2e202SAlex Deucher #include <linux/kref.h> 3597b2e202SAlex Deucher #include <linux/interval_tree.h> 3697b2e202SAlex Deucher #include <linux/hashtable.h> 3797b2e202SAlex Deucher #include <linux/fence.h> 3897b2e202SAlex Deucher 3997b2e202SAlex Deucher #include <ttm/ttm_bo_api.h> 4097b2e202SAlex Deucher #include <ttm/ttm_bo_driver.h> 4197b2e202SAlex Deucher #include <ttm/ttm_placement.h> 4297b2e202SAlex Deucher #include <ttm/ttm_module.h> 4397b2e202SAlex Deucher #include <ttm/ttm_execbuf_util.h> 4497b2e202SAlex Deucher 45d03846afSChunming Zhou #include <drm/drmP.h> 4697b2e202SAlex Deucher #include <drm/drm_gem.h> 477e5a547fSChunming Zhou #include <drm/amdgpu_drm.h> 4897b2e202SAlex Deucher 495fc3aeebSyanyang1 #include "amd_shared.h" 5097b2e202SAlex Deucher #include "amdgpu_mode.h" 5197b2e202SAlex Deucher #include "amdgpu_ih.h" 5297b2e202SAlex Deucher #include "amdgpu_irq.h" 5397b2e202SAlex Deucher #include "amdgpu_ucode.h" 5497b2e202SAlex Deucher #include "amdgpu_gds.h" 551f7371b2SAlex Deucher #include "amd_powerplay.h" 56a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h" 5797b2e202SAlex Deucher 58b80d8475SAlex Deucher #include "gpu_scheduler.h" 59b80d8475SAlex Deucher 6097b2e202SAlex Deucher /* 6197b2e202SAlex Deucher * Modules parameters. 6297b2e202SAlex Deucher */ 6397b2e202SAlex Deucher extern int amdgpu_modeset; 6497b2e202SAlex Deucher extern int amdgpu_vram_limit; 6597b2e202SAlex Deucher extern int amdgpu_gart_size; 6697b2e202SAlex Deucher extern int amdgpu_benchmarking; 6797b2e202SAlex Deucher extern int amdgpu_testing; 6897b2e202SAlex Deucher extern int amdgpu_audio; 6997b2e202SAlex Deucher extern int amdgpu_disp_priority; 7097b2e202SAlex Deucher extern int amdgpu_hw_i2c; 7197b2e202SAlex Deucher extern int amdgpu_pcie_gen2; 7297b2e202SAlex Deucher extern int amdgpu_msi; 7397b2e202SAlex Deucher extern int amdgpu_lockup_timeout; 7497b2e202SAlex Deucher extern int amdgpu_dpm; 7597b2e202SAlex Deucher extern int amdgpu_smc_load_fw; 7697b2e202SAlex Deucher extern int amdgpu_aspm; 7797b2e202SAlex Deucher extern int amdgpu_runtime_pm; 7897b2e202SAlex Deucher extern unsigned amdgpu_ip_block_mask; 7997b2e202SAlex Deucher extern int amdgpu_bapm; 8097b2e202SAlex Deucher extern int amdgpu_deep_color; 8197b2e202SAlex Deucher extern int amdgpu_vm_size; 8297b2e202SAlex Deucher extern int amdgpu_vm_block_size; 83d9c13156SChristian König extern int amdgpu_vm_fault_stop; 84b495bd3aSChristian König extern int amdgpu_vm_debug; 851333f723SJammy Zhou extern int amdgpu_sched_jobs; 864afcb303SJammy Zhou extern int amdgpu_sched_hw_submission; 871f7371b2SAlex Deucher extern int amdgpu_powerplay; 886bb6b297SHuang Rui extern int amdgpu_powercontainment; 89cd474ba0SAlex Deucher extern unsigned amdgpu_pcie_gen_cap; 90cd474ba0SAlex Deucher extern unsigned amdgpu_pcie_lane_cap; 91395d1fb9SNicolai Hähnle extern unsigned amdgpu_cg_mask; 92395d1fb9SNicolai Hähnle extern unsigned amdgpu_pg_mask; 936f8941a2SNicolai Hähnle extern char *amdgpu_disable_cu; 9497b2e202SAlex Deucher 954b559c90SChunming Zhou #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 9697b2e202SAlex Deucher #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 9797b2e202SAlex Deucher #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 9897b2e202SAlex Deucher /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 9997b2e202SAlex Deucher #define AMDGPU_IB_POOL_SIZE 16 10097b2e202SAlex Deucher #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 10197b2e202SAlex Deucher #define AMDGPUFB_CONN_LIMIT 4 10297b2e202SAlex Deucher #define AMDGPU_BIOS_NUM_SCRATCH 8 10397b2e202SAlex Deucher 10497b2e202SAlex Deucher /* max number of rings */ 10597b2e202SAlex Deucher #define AMDGPU_MAX_RINGS 16 10697b2e202SAlex Deucher #define AMDGPU_MAX_GFX_RINGS 1 10797b2e202SAlex Deucher #define AMDGPU_MAX_COMPUTE_RINGS 8 10897b2e202SAlex Deucher #define AMDGPU_MAX_VCE_RINGS 2 10997b2e202SAlex Deucher 11036f523a7SJammy Zhou /* max number of IP instances */ 11136f523a7SJammy Zhou #define AMDGPU_MAX_SDMA_INSTANCES 2 11236f523a7SJammy Zhou 11397b2e202SAlex Deucher /* hardcode that limit for now */ 11497b2e202SAlex Deucher #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 11597b2e202SAlex Deucher 11697b2e202SAlex Deucher /* hard reset data */ 11797b2e202SAlex Deucher #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 11897b2e202SAlex Deucher 11997b2e202SAlex Deucher /* reset flags */ 12097b2e202SAlex Deucher #define AMDGPU_RESET_GFX (1 << 0) 12197b2e202SAlex Deucher #define AMDGPU_RESET_COMPUTE (1 << 1) 12297b2e202SAlex Deucher #define AMDGPU_RESET_DMA (1 << 2) 12397b2e202SAlex Deucher #define AMDGPU_RESET_CP (1 << 3) 12497b2e202SAlex Deucher #define AMDGPU_RESET_GRBM (1 << 4) 12597b2e202SAlex Deucher #define AMDGPU_RESET_DMA1 (1 << 5) 12697b2e202SAlex Deucher #define AMDGPU_RESET_RLC (1 << 6) 12797b2e202SAlex Deucher #define AMDGPU_RESET_SEM (1 << 7) 12897b2e202SAlex Deucher #define AMDGPU_RESET_IH (1 << 8) 12997b2e202SAlex Deucher #define AMDGPU_RESET_VMC (1 << 9) 13097b2e202SAlex Deucher #define AMDGPU_RESET_MC (1 << 10) 13197b2e202SAlex Deucher #define AMDGPU_RESET_DISPLAY (1 << 11) 13297b2e202SAlex Deucher #define AMDGPU_RESET_UVD (1 << 12) 13397b2e202SAlex Deucher #define AMDGPU_RESET_VCE (1 << 13) 13497b2e202SAlex Deucher #define AMDGPU_RESET_VCE1 (1 << 14) 13597b2e202SAlex Deucher 13697b2e202SAlex Deucher /* GFX current status */ 13797b2e202SAlex Deucher #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 13897b2e202SAlex Deucher #define AMDGPU_GFX_SAFE_MODE 0x00000001L 13997b2e202SAlex Deucher #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 14097b2e202SAlex Deucher #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 14197b2e202SAlex Deucher #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 14297b2e202SAlex Deucher 14397b2e202SAlex Deucher /* max cursor sizes (in pixels) */ 14497b2e202SAlex Deucher #define CIK_CURSOR_WIDTH 128 14597b2e202SAlex Deucher #define CIK_CURSOR_HEIGHT 128 14697b2e202SAlex Deucher 14797b2e202SAlex Deucher struct amdgpu_device; 14897b2e202SAlex Deucher struct amdgpu_ib; 14997b2e202SAlex Deucher struct amdgpu_vm; 15097b2e202SAlex Deucher struct amdgpu_ring; 15197b2e202SAlex Deucher struct amdgpu_cs_parser; 152bb977d37SChunming Zhou struct amdgpu_job; 15397b2e202SAlex Deucher struct amdgpu_irq_src; 1540b492a4cSAlex Deucher struct amdgpu_fpriv; 15597b2e202SAlex Deucher 15697b2e202SAlex Deucher enum amdgpu_cp_irq { 15797b2e202SAlex Deucher AMDGPU_CP_IRQ_GFX_EOP = 0, 15897b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 15997b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 16097b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 16197b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 16297b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 16397b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 16497b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 16597b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 16697b2e202SAlex Deucher 16797b2e202SAlex Deucher AMDGPU_CP_IRQ_LAST 16897b2e202SAlex Deucher }; 16997b2e202SAlex Deucher 17097b2e202SAlex Deucher enum amdgpu_sdma_irq { 17197b2e202SAlex Deucher AMDGPU_SDMA_IRQ_TRAP0 = 0, 17297b2e202SAlex Deucher AMDGPU_SDMA_IRQ_TRAP1, 17397b2e202SAlex Deucher 17497b2e202SAlex Deucher AMDGPU_SDMA_IRQ_LAST 17597b2e202SAlex Deucher }; 17697b2e202SAlex Deucher 17797b2e202SAlex Deucher enum amdgpu_thermal_irq { 17897b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 17997b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 18097b2e202SAlex Deucher 18197b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LAST 18297b2e202SAlex Deucher }; 18397b2e202SAlex Deucher 18497b2e202SAlex Deucher int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 1855fc3aeebSyanyang1 enum amd_ip_block_type block_type, 1865fc3aeebSyanyang1 enum amd_clockgating_state state); 18797b2e202SAlex Deucher int amdgpu_set_powergating_state(struct amdgpu_device *adev, 1885fc3aeebSyanyang1 enum amd_ip_block_type block_type, 1895fc3aeebSyanyang1 enum amd_powergating_state state); 1905dbbb60bSAlex Deucher int amdgpu_wait_for_idle(struct amdgpu_device *adev, 1915dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 1925dbbb60bSAlex Deucher bool amdgpu_is_idle(struct amdgpu_device *adev, 1935dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 19497b2e202SAlex Deucher 19597b2e202SAlex Deucher struct amdgpu_ip_block_version { 1965fc3aeebSyanyang1 enum amd_ip_block_type type; 19797b2e202SAlex Deucher u32 major; 19897b2e202SAlex Deucher u32 minor; 19997b2e202SAlex Deucher u32 rev; 2005fc3aeebSyanyang1 const struct amd_ip_funcs *funcs; 20197b2e202SAlex Deucher }; 20297b2e202SAlex Deucher 20397b2e202SAlex Deucher int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 2045fc3aeebSyanyang1 enum amd_ip_block_type type, 20597b2e202SAlex Deucher u32 major, u32 minor); 20697b2e202SAlex Deucher 20797b2e202SAlex Deucher const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 20897b2e202SAlex Deucher struct amdgpu_device *adev, 2095fc3aeebSyanyang1 enum amd_ip_block_type type); 21097b2e202SAlex Deucher 21197b2e202SAlex Deucher /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 21297b2e202SAlex Deucher struct amdgpu_buffer_funcs { 21397b2e202SAlex Deucher /* maximum bytes in a single operation */ 21497b2e202SAlex Deucher uint32_t copy_max_bytes; 21597b2e202SAlex Deucher 21697b2e202SAlex Deucher /* number of dw to reserve per operation */ 21797b2e202SAlex Deucher unsigned copy_num_dw; 21897b2e202SAlex Deucher 21997b2e202SAlex Deucher /* used for buffer migration */ 220c7ae72c0SChunming Zhou void (*emit_copy_buffer)(struct amdgpu_ib *ib, 22197b2e202SAlex Deucher /* src addr in bytes */ 22297b2e202SAlex Deucher uint64_t src_offset, 22397b2e202SAlex Deucher /* dst addr in bytes */ 22497b2e202SAlex Deucher uint64_t dst_offset, 22597b2e202SAlex Deucher /* number of byte to transfer */ 22697b2e202SAlex Deucher uint32_t byte_count); 22797b2e202SAlex Deucher 22897b2e202SAlex Deucher /* maximum bytes in a single operation */ 22997b2e202SAlex Deucher uint32_t fill_max_bytes; 23097b2e202SAlex Deucher 23197b2e202SAlex Deucher /* number of dw to reserve per operation */ 23297b2e202SAlex Deucher unsigned fill_num_dw; 23397b2e202SAlex Deucher 23497b2e202SAlex Deucher /* used for buffer clearing */ 2356e7a3840SChunming Zhou void (*emit_fill_buffer)(struct amdgpu_ib *ib, 23697b2e202SAlex Deucher /* value to write to memory */ 23797b2e202SAlex Deucher uint32_t src_data, 23897b2e202SAlex Deucher /* dst addr in bytes */ 23997b2e202SAlex Deucher uint64_t dst_offset, 24097b2e202SAlex Deucher /* number of byte to fill */ 24197b2e202SAlex Deucher uint32_t byte_count); 24297b2e202SAlex Deucher }; 24397b2e202SAlex Deucher 24497b2e202SAlex Deucher /* provided by hw blocks that can write ptes, e.g., sdma */ 24597b2e202SAlex Deucher struct amdgpu_vm_pte_funcs { 24697b2e202SAlex Deucher /* copy pte entries from GART */ 24797b2e202SAlex Deucher void (*copy_pte)(struct amdgpu_ib *ib, 24897b2e202SAlex Deucher uint64_t pe, uint64_t src, 24997b2e202SAlex Deucher unsigned count); 25097b2e202SAlex Deucher /* write pte one entry at a time with addr mapping */ 25197b2e202SAlex Deucher void (*write_pte)(struct amdgpu_ib *ib, 252b07c9d2aSChristian König const dma_addr_t *pages_addr, uint64_t pe, 25397b2e202SAlex Deucher uint64_t addr, unsigned count, 25497b2e202SAlex Deucher uint32_t incr, uint32_t flags); 25597b2e202SAlex Deucher /* for linear pte/pde updates without addr mapping */ 25697b2e202SAlex Deucher void (*set_pte_pde)(struct amdgpu_ib *ib, 25797b2e202SAlex Deucher uint64_t pe, 25897b2e202SAlex Deucher uint64_t addr, unsigned count, 25997b2e202SAlex Deucher uint32_t incr, uint32_t flags); 26097b2e202SAlex Deucher }; 26197b2e202SAlex Deucher 26297b2e202SAlex Deucher /* provided by the gmc block */ 26397b2e202SAlex Deucher struct amdgpu_gart_funcs { 26497b2e202SAlex Deucher /* flush the vm tlb via mmio */ 26597b2e202SAlex Deucher void (*flush_gpu_tlb)(struct amdgpu_device *adev, 26697b2e202SAlex Deucher uint32_t vmid); 26797b2e202SAlex Deucher /* write pte/pde updates using the cpu */ 26897b2e202SAlex Deucher int (*set_pte_pde)(struct amdgpu_device *adev, 26997b2e202SAlex Deucher void *cpu_pt_addr, /* cpu addr of page table */ 27097b2e202SAlex Deucher uint32_t gpu_page_idx, /* pte/pde to update */ 27197b2e202SAlex Deucher uint64_t addr, /* addr to write into pte/pde */ 27297b2e202SAlex Deucher uint32_t flags); /* access flags */ 27397b2e202SAlex Deucher }; 27497b2e202SAlex Deucher 27597b2e202SAlex Deucher /* provided by the ih block */ 27697b2e202SAlex Deucher struct amdgpu_ih_funcs { 27797b2e202SAlex Deucher /* ring read/write ptr handling, called from interrupt context */ 27897b2e202SAlex Deucher u32 (*get_wptr)(struct amdgpu_device *adev); 27997b2e202SAlex Deucher void (*decode_iv)(struct amdgpu_device *adev, 28097b2e202SAlex Deucher struct amdgpu_iv_entry *entry); 28197b2e202SAlex Deucher void (*set_rptr)(struct amdgpu_device *adev); 28297b2e202SAlex Deucher }; 28397b2e202SAlex Deucher 28497b2e202SAlex Deucher /* provided by hw blocks that expose a ring buffer for commands */ 28597b2e202SAlex Deucher struct amdgpu_ring_funcs { 28697b2e202SAlex Deucher /* ring read/write ptr handling */ 28797b2e202SAlex Deucher u32 (*get_rptr)(struct amdgpu_ring *ring); 28897b2e202SAlex Deucher u32 (*get_wptr)(struct amdgpu_ring *ring); 28997b2e202SAlex Deucher void (*set_wptr)(struct amdgpu_ring *ring); 29097b2e202SAlex Deucher /* validating and patching of IBs */ 29197b2e202SAlex Deucher int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 29297b2e202SAlex Deucher /* command emit functions */ 29397b2e202SAlex Deucher void (*emit_ib)(struct amdgpu_ring *ring, 294d88bf583SChristian König struct amdgpu_ib *ib, 295d88bf583SChristian König unsigned vm_id, bool ctx_switch); 29697b2e202SAlex Deucher void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 297890ee23fSChunming Zhou uint64_t seq, unsigned flags); 298b8c7b39eSChristian König void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 29997b2e202SAlex Deucher void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 30097b2e202SAlex Deucher uint64_t pd_addr); 301d2edb07bSChristian König void (*emit_hdp_flush)(struct amdgpu_ring *ring); 30211afbde8SChunming Zhou void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); 30397b2e202SAlex Deucher void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 30497b2e202SAlex Deucher uint32_t gds_base, uint32_t gds_size, 30597b2e202SAlex Deucher uint32_t gws_base, uint32_t gws_size, 30697b2e202SAlex Deucher uint32_t oa_base, uint32_t oa_size); 30797b2e202SAlex Deucher /* testing functions */ 30897b2e202SAlex Deucher int (*test_ring)(struct amdgpu_ring *ring); 30997b2e202SAlex Deucher int (*test_ib)(struct amdgpu_ring *ring); 310edff0e28SJammy Zhou /* insert NOP packets */ 311edff0e28SJammy Zhou void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 3129e5d5309SChristian König /* pad the indirect buffer to the necessary number of dw */ 3139e5d5309SChristian König void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 31403ccf481SMonk Liu unsigned (*init_cond_exec)(struct amdgpu_ring *ring); 31503ccf481SMonk Liu void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); 31697b2e202SAlex Deucher }; 31797b2e202SAlex Deucher 31897b2e202SAlex Deucher /* 31997b2e202SAlex Deucher * BIOS. 32097b2e202SAlex Deucher */ 32197b2e202SAlex Deucher bool amdgpu_get_bios(struct amdgpu_device *adev); 32297b2e202SAlex Deucher bool amdgpu_read_bios(struct amdgpu_device *adev); 32397b2e202SAlex Deucher 32497b2e202SAlex Deucher /* 32597b2e202SAlex Deucher * Dummy page 32697b2e202SAlex Deucher */ 32797b2e202SAlex Deucher struct amdgpu_dummy_page { 32897b2e202SAlex Deucher struct page *page; 32997b2e202SAlex Deucher dma_addr_t addr; 33097b2e202SAlex Deucher }; 33197b2e202SAlex Deucher int amdgpu_dummy_page_init(struct amdgpu_device *adev); 33297b2e202SAlex Deucher void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 33397b2e202SAlex Deucher 33497b2e202SAlex Deucher 33597b2e202SAlex Deucher /* 33697b2e202SAlex Deucher * Clocks 33797b2e202SAlex Deucher */ 33897b2e202SAlex Deucher 33997b2e202SAlex Deucher #define AMDGPU_MAX_PPLL 3 34097b2e202SAlex Deucher 34197b2e202SAlex Deucher struct amdgpu_clock { 34297b2e202SAlex Deucher struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 34397b2e202SAlex Deucher struct amdgpu_pll spll; 34497b2e202SAlex Deucher struct amdgpu_pll mpll; 34597b2e202SAlex Deucher /* 10 Khz units */ 34697b2e202SAlex Deucher uint32_t default_mclk; 34797b2e202SAlex Deucher uint32_t default_sclk; 34897b2e202SAlex Deucher uint32_t default_dispclk; 34997b2e202SAlex Deucher uint32_t current_dispclk; 35097b2e202SAlex Deucher uint32_t dp_extclk; 35197b2e202SAlex Deucher uint32_t max_pixel_clock; 35297b2e202SAlex Deucher }; 35397b2e202SAlex Deucher 35497b2e202SAlex Deucher /* 35597b2e202SAlex Deucher * Fences. 35697b2e202SAlex Deucher */ 35797b2e202SAlex Deucher struct amdgpu_fence_driver { 35897b2e202SAlex Deucher uint64_t gpu_addr; 35997b2e202SAlex Deucher volatile uint32_t *cpu_addr; 36097b2e202SAlex Deucher /* sync_seq is protected by ring emission lock */ 361742c085fSChristian König uint32_t sync_seq; 362742c085fSChristian König atomic_t last_seq; 36397b2e202SAlex Deucher bool initialized; 36497b2e202SAlex Deucher struct amdgpu_irq_src *irq_src; 36597b2e202SAlex Deucher unsigned irq_type; 366c2776afeSChristian König struct timer_list fallback_timer; 367c89377d1SChristian König unsigned num_fences_mask; 3684a7d74f1SChristian König spinlock_t lock; 369c89377d1SChristian König struct fence **fences; 37097b2e202SAlex Deucher }; 37197b2e202SAlex Deucher 37297b2e202SAlex Deucher /* some special values for the owner field */ 37397b2e202SAlex Deucher #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 37497b2e202SAlex Deucher #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 37597b2e202SAlex Deucher 376890ee23fSChunming Zhou #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 377890ee23fSChunming Zhou #define AMDGPU_FENCE_FLAG_INT (1 << 1) 378890ee23fSChunming Zhou 37997b2e202SAlex Deucher int amdgpu_fence_driver_init(struct amdgpu_device *adev); 38097b2e202SAlex Deucher void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 38197b2e202SAlex Deucher void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 38297b2e202SAlex Deucher 383e6151a08SChristian König int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 384e6151a08SChristian König unsigned num_hw_submission); 38597b2e202SAlex Deucher int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 38697b2e202SAlex Deucher struct amdgpu_irq_src *irq_src, 38797b2e202SAlex Deucher unsigned irq_type); 3885ceb54c6SAlex Deucher void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 3895ceb54c6SAlex Deucher void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 390364beb2cSChristian König int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence); 39197b2e202SAlex Deucher void amdgpu_fence_process(struct amdgpu_ring *ring); 39297b2e202SAlex Deucher int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 39397b2e202SAlex Deucher unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 39497b2e202SAlex Deucher 39597b2e202SAlex Deucher /* 39697b2e202SAlex Deucher * TTM. 39797b2e202SAlex Deucher */ 39829b3259aSChristian König 39929b3259aSChristian König #define AMDGPU_TTM_LRU_SIZE 20 40029b3259aSChristian König 40129b3259aSChristian König struct amdgpu_mman_lru { 40229b3259aSChristian König struct list_head *lru[TTM_NUM_MEM_TYPES]; 40329b3259aSChristian König struct list_head *swap_lru; 40429b3259aSChristian König }; 40529b3259aSChristian König 40697b2e202SAlex Deucher struct amdgpu_mman { 40797b2e202SAlex Deucher struct ttm_bo_global_ref bo_global_ref; 40897b2e202SAlex Deucher struct drm_global_reference mem_global_ref; 40997b2e202SAlex Deucher struct ttm_bo_device bdev; 41097b2e202SAlex Deucher bool mem_global_referenced; 41197b2e202SAlex Deucher bool initialized; 41297b2e202SAlex Deucher 41397b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS) 41497b2e202SAlex Deucher struct dentry *vram; 41597b2e202SAlex Deucher struct dentry *gtt; 41697b2e202SAlex Deucher #endif 41797b2e202SAlex Deucher 41897b2e202SAlex Deucher /* buffer handling */ 41997b2e202SAlex Deucher const struct amdgpu_buffer_funcs *buffer_funcs; 42097b2e202SAlex Deucher struct amdgpu_ring *buffer_funcs_ring; 421703297c1SChristian König /* Scheduler entity for buffer moves */ 422703297c1SChristian König struct amd_sched_entity entity; 42329b3259aSChristian König 42429b3259aSChristian König /* custom LRU management */ 42529b3259aSChristian König struct amdgpu_mman_lru log2_size[AMDGPU_TTM_LRU_SIZE]; 42697b2e202SAlex Deucher }; 42797b2e202SAlex Deucher 42897b2e202SAlex Deucher int amdgpu_copy_buffer(struct amdgpu_ring *ring, 42997b2e202SAlex Deucher uint64_t src_offset, 43097b2e202SAlex Deucher uint64_t dst_offset, 43197b2e202SAlex Deucher uint32_t byte_count, 43297b2e202SAlex Deucher struct reservation_object *resv, 433c7ae72c0SChunming Zhou struct fence **fence); 43497b2e202SAlex Deucher int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 43597b2e202SAlex Deucher 43697b2e202SAlex Deucher struct amdgpu_bo_list_entry { 43797b2e202SAlex Deucher struct amdgpu_bo *robj; 43897b2e202SAlex Deucher struct ttm_validate_buffer tv; 43997b2e202SAlex Deucher struct amdgpu_bo_va *bo_va; 44097b2e202SAlex Deucher uint32_t priority; 4412f568dbdSChristian König struct page **user_pages; 4422f568dbdSChristian König int user_invalidated; 44397b2e202SAlex Deucher }; 44497b2e202SAlex Deucher 44597b2e202SAlex Deucher struct amdgpu_bo_va_mapping { 44697b2e202SAlex Deucher struct list_head list; 44797b2e202SAlex Deucher struct interval_tree_node it; 44897b2e202SAlex Deucher uint64_t offset; 44997b2e202SAlex Deucher uint32_t flags; 45097b2e202SAlex Deucher }; 45197b2e202SAlex Deucher 45297b2e202SAlex Deucher /* bo virtual addresses in a specific vm */ 45397b2e202SAlex Deucher struct amdgpu_bo_va { 45497b2e202SAlex Deucher /* protected by bo being reserved */ 45597b2e202SAlex Deucher struct list_head bo_list; 456bb1e38a4SChunming Zhou struct fence *last_pt_update; 45797b2e202SAlex Deucher unsigned ref_count; 45897b2e202SAlex Deucher 4597fc11959SChristian König /* protected by vm mutex and spinlock */ 46097b2e202SAlex Deucher struct list_head vm_status; 46197b2e202SAlex Deucher 4627fc11959SChristian König /* mappings for this bo_va */ 4637fc11959SChristian König struct list_head invalids; 4647fc11959SChristian König struct list_head valids; 4657fc11959SChristian König 46697b2e202SAlex Deucher /* constant after initialization */ 46797b2e202SAlex Deucher struct amdgpu_vm *vm; 46897b2e202SAlex Deucher struct amdgpu_bo *bo; 46997b2e202SAlex Deucher }; 47097b2e202SAlex Deucher 4717e5a547fSChunming Zhou #define AMDGPU_GEM_DOMAIN_MAX 0x3 4727e5a547fSChunming Zhou 47397b2e202SAlex Deucher struct amdgpu_bo { 47497b2e202SAlex Deucher /* Protected by gem.mutex */ 47597b2e202SAlex Deucher struct list_head list; 47697b2e202SAlex Deucher /* Protected by tbo.reserved */ 4771ea863fdSChristian König u32 prefered_domains; 4781ea863fdSChristian König u32 allowed_domains; 4797e5a547fSChunming Zhou struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 48097b2e202SAlex Deucher struct ttm_placement placement; 48197b2e202SAlex Deucher struct ttm_buffer_object tbo; 48297b2e202SAlex Deucher struct ttm_bo_kmap_obj kmap; 48397b2e202SAlex Deucher u64 flags; 48497b2e202SAlex Deucher unsigned pin_count; 48597b2e202SAlex Deucher void *kptr; 48697b2e202SAlex Deucher u64 tiling_flags; 48797b2e202SAlex Deucher u64 metadata_flags; 48897b2e202SAlex Deucher void *metadata; 48997b2e202SAlex Deucher u32 metadata_size; 49097b2e202SAlex Deucher /* list of all virtual address to which this bo 49197b2e202SAlex Deucher * is associated to 49297b2e202SAlex Deucher */ 49397b2e202SAlex Deucher struct list_head va; 49497b2e202SAlex Deucher /* Constant after initialization */ 49597b2e202SAlex Deucher struct amdgpu_device *adev; 49697b2e202SAlex Deucher struct drm_gem_object gem_base; 49782b9c55bSChristian König struct amdgpu_bo *parent; 49897b2e202SAlex Deucher 49997b2e202SAlex Deucher struct ttm_bo_kmap_obj dma_buf_vmap; 50097b2e202SAlex Deucher struct amdgpu_mn *mn; 50197b2e202SAlex Deucher struct list_head mn_list; 50297b2e202SAlex Deucher }; 50397b2e202SAlex Deucher #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 50497b2e202SAlex Deucher 50597b2e202SAlex Deucher void amdgpu_gem_object_free(struct drm_gem_object *obj); 50697b2e202SAlex Deucher int amdgpu_gem_object_open(struct drm_gem_object *obj, 50797b2e202SAlex Deucher struct drm_file *file_priv); 50897b2e202SAlex Deucher void amdgpu_gem_object_close(struct drm_gem_object *obj, 50997b2e202SAlex Deucher struct drm_file *file_priv); 51097b2e202SAlex Deucher unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 51197b2e202SAlex Deucher struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 5124d9c514dSChristian König struct drm_gem_object * 5134d9c514dSChristian König amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 51497b2e202SAlex Deucher struct dma_buf_attachment *attach, 51597b2e202SAlex Deucher struct sg_table *sg); 51697b2e202SAlex Deucher struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 51797b2e202SAlex Deucher struct drm_gem_object *gobj, 51897b2e202SAlex Deucher int flags); 51997b2e202SAlex Deucher int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 52097b2e202SAlex Deucher void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 52197b2e202SAlex Deucher struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 52297b2e202SAlex Deucher void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 52397b2e202SAlex Deucher void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 52497b2e202SAlex Deucher int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 52597b2e202SAlex Deucher 52697b2e202SAlex Deucher /* sub-allocation manager, it has to be protected by another lock. 52797b2e202SAlex Deucher * By conception this is an helper for other part of the driver 52897b2e202SAlex Deucher * like the indirect buffer or semaphore, which both have their 52997b2e202SAlex Deucher * locking. 53097b2e202SAlex Deucher * 53197b2e202SAlex Deucher * Principe is simple, we keep a list of sub allocation in offset 53297b2e202SAlex Deucher * order (first entry has offset == 0, last entry has the highest 53397b2e202SAlex Deucher * offset). 53497b2e202SAlex Deucher * 53597b2e202SAlex Deucher * When allocating new object we first check if there is room at 53697b2e202SAlex Deucher * the end total_size - (last_object_offset + last_object_size) >= 53797b2e202SAlex Deucher * alloc_size. If so we allocate new object there. 53897b2e202SAlex Deucher * 53997b2e202SAlex Deucher * When there is not enough room at the end, we start waiting for 54097b2e202SAlex Deucher * each sub object until we reach object_offset+object_size >= 54197b2e202SAlex Deucher * alloc_size, this object then become the sub object we return. 54297b2e202SAlex Deucher * 54397b2e202SAlex Deucher * Alignment can't be bigger than page size. 54497b2e202SAlex Deucher * 54597b2e202SAlex Deucher * Hole are not considered for allocation to keep things simple. 54697b2e202SAlex Deucher * Assumption is that there won't be hole (all object on same 54797b2e202SAlex Deucher * alignment). 54897b2e202SAlex Deucher */ 5496ba60b89SChristian König 5506ba60b89SChristian König #define AMDGPU_SA_NUM_FENCE_LISTS 32 5516ba60b89SChristian König 55297b2e202SAlex Deucher struct amdgpu_sa_manager { 55397b2e202SAlex Deucher wait_queue_head_t wq; 55497b2e202SAlex Deucher struct amdgpu_bo *bo; 55597b2e202SAlex Deucher struct list_head *hole; 5566ba60b89SChristian König struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 55797b2e202SAlex Deucher struct list_head olist; 55897b2e202SAlex Deucher unsigned size; 55997b2e202SAlex Deucher uint64_t gpu_addr; 56097b2e202SAlex Deucher void *cpu_ptr; 56197b2e202SAlex Deucher uint32_t domain; 56297b2e202SAlex Deucher uint32_t align; 56397b2e202SAlex Deucher }; 56497b2e202SAlex Deucher 56597b2e202SAlex Deucher /* sub-allocation buffer */ 56697b2e202SAlex Deucher struct amdgpu_sa_bo { 56797b2e202SAlex Deucher struct list_head olist; 56897b2e202SAlex Deucher struct list_head flist; 56997b2e202SAlex Deucher struct amdgpu_sa_manager *manager; 57097b2e202SAlex Deucher unsigned soffset; 57197b2e202SAlex Deucher unsigned eoffset; 5724ce9891eSChunming Zhou struct fence *fence; 57397b2e202SAlex Deucher }; 57497b2e202SAlex Deucher 57597b2e202SAlex Deucher /* 57697b2e202SAlex Deucher * GEM objects. 57797b2e202SAlex Deucher */ 578418aa0c2SChristian König void amdgpu_gem_force_release(struct amdgpu_device *adev); 57997b2e202SAlex Deucher int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 58097b2e202SAlex Deucher int alignment, u32 initial_domain, 58197b2e202SAlex Deucher u64 flags, bool kernel, 58297b2e202SAlex Deucher struct drm_gem_object **obj); 58397b2e202SAlex Deucher 58497b2e202SAlex Deucher int amdgpu_mode_dumb_create(struct drm_file *file_priv, 58597b2e202SAlex Deucher struct drm_device *dev, 58697b2e202SAlex Deucher struct drm_mode_create_dumb *args); 58797b2e202SAlex Deucher int amdgpu_mode_dumb_mmap(struct drm_file *filp, 58897b2e202SAlex Deucher struct drm_device *dev, 58997b2e202SAlex Deucher uint32_t handle, uint64_t *offset_p); 59097b2e202SAlex Deucher /* 59197b2e202SAlex Deucher * Synchronization 59297b2e202SAlex Deucher */ 59397b2e202SAlex Deucher struct amdgpu_sync { 594f91b3a69SChristian König DECLARE_HASHTABLE(fences, 4); 5953c62338cSChunming Zhou struct fence *last_vm_update; 59697b2e202SAlex Deucher }; 59797b2e202SAlex Deucher 59897b2e202SAlex Deucher void amdgpu_sync_create(struct amdgpu_sync *sync); 59991e1a520SChristian König int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 60091e1a520SChristian König struct fence *f); 60197b2e202SAlex Deucher int amdgpu_sync_resv(struct amdgpu_device *adev, 60297b2e202SAlex Deucher struct amdgpu_sync *sync, 60397b2e202SAlex Deucher struct reservation_object *resv, 60497b2e202SAlex Deucher void *owner); 6051fbb2e92SChristian König struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, 60635420238SChristian König struct amdgpu_ring *ring); 607e61235dbSChristian König struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 6088a8f0b48SChristian König void amdgpu_sync_free(struct amdgpu_sync *sync); 609257bf15aSChristian König int amdgpu_sync_init(void); 610257bf15aSChristian König void amdgpu_sync_fini(void); 611d573de2dSRex Zhu int amdgpu_fence_slab_init(void); 612d573de2dSRex Zhu void amdgpu_fence_slab_fini(void); 61397b2e202SAlex Deucher 61497b2e202SAlex Deucher /* 61597b2e202SAlex Deucher * GART structures, functions & helpers 61697b2e202SAlex Deucher */ 61797b2e202SAlex Deucher struct amdgpu_mc; 61897b2e202SAlex Deucher 61997b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_SIZE 4096 62097b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 62197b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_SHIFT 12 62297b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 62397b2e202SAlex Deucher 62497b2e202SAlex Deucher struct amdgpu_gart { 62597b2e202SAlex Deucher dma_addr_t table_addr; 62697b2e202SAlex Deucher struct amdgpu_bo *robj; 62797b2e202SAlex Deucher void *ptr; 62897b2e202SAlex Deucher unsigned num_gpu_pages; 62997b2e202SAlex Deucher unsigned num_cpu_pages; 63097b2e202SAlex Deucher unsigned table_size; 631a1d29476SChristian König #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 63297b2e202SAlex Deucher struct page **pages; 633a1d29476SChristian König #endif 63497b2e202SAlex Deucher bool ready; 63597b2e202SAlex Deucher const struct amdgpu_gart_funcs *gart_funcs; 63697b2e202SAlex Deucher }; 63797b2e202SAlex Deucher 63897b2e202SAlex Deucher int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 63997b2e202SAlex Deucher void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 64097b2e202SAlex Deucher int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 64197b2e202SAlex Deucher void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 64297b2e202SAlex Deucher int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 64397b2e202SAlex Deucher void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 64497b2e202SAlex Deucher int amdgpu_gart_init(struct amdgpu_device *adev); 64597b2e202SAlex Deucher void amdgpu_gart_fini(struct amdgpu_device *adev); 64697b2e202SAlex Deucher void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 64797b2e202SAlex Deucher int pages); 64897b2e202SAlex Deucher int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 64997b2e202SAlex Deucher int pages, struct page **pagelist, 65097b2e202SAlex Deucher dma_addr_t *dma_addr, uint32_t flags); 65197b2e202SAlex Deucher 65297b2e202SAlex Deucher /* 65397b2e202SAlex Deucher * GPU MC structures, functions & helpers 65497b2e202SAlex Deucher */ 65597b2e202SAlex Deucher struct amdgpu_mc { 65697b2e202SAlex Deucher resource_size_t aper_size; 65797b2e202SAlex Deucher resource_size_t aper_base; 65897b2e202SAlex Deucher resource_size_t agp_base; 65997b2e202SAlex Deucher /* for some chips with <= 32MB we need to lie 66097b2e202SAlex Deucher * about vram size near mc fb location */ 66197b2e202SAlex Deucher u64 mc_vram_size; 66297b2e202SAlex Deucher u64 visible_vram_size; 66397b2e202SAlex Deucher u64 gtt_size; 66497b2e202SAlex Deucher u64 gtt_start; 66597b2e202SAlex Deucher u64 gtt_end; 66697b2e202SAlex Deucher u64 vram_start; 66797b2e202SAlex Deucher u64 vram_end; 66897b2e202SAlex Deucher unsigned vram_width; 66997b2e202SAlex Deucher u64 real_vram_size; 67097b2e202SAlex Deucher int vram_mtrr; 67197b2e202SAlex Deucher u64 gtt_base_align; 67297b2e202SAlex Deucher u64 mc_mask; 67397b2e202SAlex Deucher const struct firmware *fw; /* MC firmware */ 67497b2e202SAlex Deucher uint32_t fw_version; 67597b2e202SAlex Deucher struct amdgpu_irq_src vm_fault; 67681c59f54SKen Wang uint32_t vram_type; 67797b2e202SAlex Deucher }; 67897b2e202SAlex Deucher 67997b2e202SAlex Deucher /* 68097b2e202SAlex Deucher * GPU doorbell structures, functions & helpers 68197b2e202SAlex Deucher */ 68297b2e202SAlex Deucher typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 68397b2e202SAlex Deucher { 68497b2e202SAlex Deucher AMDGPU_DOORBELL_KIQ = 0x000, 68597b2e202SAlex Deucher AMDGPU_DOORBELL_HIQ = 0x001, 68697b2e202SAlex Deucher AMDGPU_DOORBELL_DIQ = 0x002, 68797b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING0 = 0x010, 68897b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING1 = 0x011, 68997b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING2 = 0x012, 69097b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING3 = 0x013, 69197b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING4 = 0x014, 69297b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING5 = 0x015, 69397b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING6 = 0x016, 69497b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING7 = 0x017, 69597b2e202SAlex Deucher AMDGPU_DOORBELL_GFX_RING0 = 0x020, 69697b2e202SAlex Deucher AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 69797b2e202SAlex Deucher AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 69897b2e202SAlex Deucher AMDGPU_DOORBELL_IH = 0x1E8, 69997b2e202SAlex Deucher AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 70097b2e202SAlex Deucher AMDGPU_DOORBELL_INVALID = 0xFFFF 70197b2e202SAlex Deucher } AMDGPU_DOORBELL_ASSIGNMENT; 70297b2e202SAlex Deucher 70397b2e202SAlex Deucher struct amdgpu_doorbell { 70497b2e202SAlex Deucher /* doorbell mmio */ 70597b2e202SAlex Deucher resource_size_t base; 70697b2e202SAlex Deucher resource_size_t size; 70797b2e202SAlex Deucher u32 __iomem *ptr; 70897b2e202SAlex Deucher u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 70997b2e202SAlex Deucher }; 71097b2e202SAlex Deucher 71197b2e202SAlex Deucher void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 71297b2e202SAlex Deucher phys_addr_t *aperture_base, 71397b2e202SAlex Deucher size_t *aperture_size, 71497b2e202SAlex Deucher size_t *start_offset); 71597b2e202SAlex Deucher 71697b2e202SAlex Deucher /* 71797b2e202SAlex Deucher * IRQS. 71897b2e202SAlex Deucher */ 71997b2e202SAlex Deucher 72097b2e202SAlex Deucher struct amdgpu_flip_work { 72197b2e202SAlex Deucher struct work_struct flip_work; 72297b2e202SAlex Deucher struct work_struct unpin_work; 72397b2e202SAlex Deucher struct amdgpu_device *adev; 72497b2e202SAlex Deucher int crtc_id; 72597b2e202SAlex Deucher uint64_t base; 72697b2e202SAlex Deucher struct drm_pending_vblank_event *event; 72797b2e202SAlex Deucher struct amdgpu_bo *old_rbo; 7281ffd2652SChristian König struct fence *excl; 7291ffd2652SChristian König unsigned shared_count; 7301ffd2652SChristian König struct fence **shared; 731c3874b75SChristian König struct fence_cb cb; 732cb9e59d7SAlex Deucher bool async; 73397b2e202SAlex Deucher }; 73497b2e202SAlex Deucher 73597b2e202SAlex Deucher 73697b2e202SAlex Deucher /* 73797b2e202SAlex Deucher * CP & rings. 73897b2e202SAlex Deucher */ 73997b2e202SAlex Deucher 74097b2e202SAlex Deucher struct amdgpu_ib { 74197b2e202SAlex Deucher struct amdgpu_sa_bo *sa_bo; 74297b2e202SAlex Deucher uint32_t length_dw; 74397b2e202SAlex Deucher uint64_t gpu_addr; 74497b2e202SAlex Deucher uint32_t *ptr; 745de807f81SJammy Zhou uint32_t flags; 74697b2e202SAlex Deucher }; 74797b2e202SAlex Deucher 74897b2e202SAlex Deucher enum amdgpu_ring_type { 74997b2e202SAlex Deucher AMDGPU_RING_TYPE_GFX, 75097b2e202SAlex Deucher AMDGPU_RING_TYPE_COMPUTE, 75197b2e202SAlex Deucher AMDGPU_RING_TYPE_SDMA, 75297b2e202SAlex Deucher AMDGPU_RING_TYPE_UVD, 75397b2e202SAlex Deucher AMDGPU_RING_TYPE_VCE 75497b2e202SAlex Deucher }; 75597b2e202SAlex Deucher 75662250a91SNils Wallménius extern const struct amd_sched_backend_ops amdgpu_sched_ops; 757c1b69ed0SChunming Zhou 75850838c8cSChristian König int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 759c5637837SMonk Liu struct amdgpu_job **job, struct amdgpu_vm *vm); 760d71518b5SChristian König int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 761d71518b5SChristian König struct amdgpu_job **job); 762b6723c8dSMonk Liu 76350838c8cSChristian König void amdgpu_job_free(struct amdgpu_job *job); 764d71518b5SChristian König int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 7652bd9ccfaSChristian König struct amd_sched_entity *entity, void *owner, 7662bd9ccfaSChristian König struct fence **f); 7673c704e93SChunming Zhou 76897b2e202SAlex Deucher struct amdgpu_ring { 76997b2e202SAlex Deucher struct amdgpu_device *adev; 77097b2e202SAlex Deucher const struct amdgpu_ring_funcs *funcs; 77197b2e202SAlex Deucher struct amdgpu_fence_driver fence_drv; 7724f839a24SChristian König struct amd_gpu_scheduler sched; 77397b2e202SAlex Deucher 774176e1ab1SChunming Zhou spinlock_t fence_lock; 77597b2e202SAlex Deucher struct amdgpu_bo *ring_obj; 77697b2e202SAlex Deucher volatile uint32_t *ring; 77797b2e202SAlex Deucher unsigned rptr_offs; 77897b2e202SAlex Deucher u64 next_rptr_gpu_addr; 77997b2e202SAlex Deucher volatile u32 *next_rptr_cpu_addr; 78097b2e202SAlex Deucher unsigned wptr; 78197b2e202SAlex Deucher unsigned wptr_old; 78297b2e202SAlex Deucher unsigned ring_size; 783c7e6be23SChristian König unsigned max_dw; 78497b2e202SAlex Deucher int count_dw; 78597b2e202SAlex Deucher uint64_t gpu_addr; 78697b2e202SAlex Deucher uint32_t align_mask; 78797b2e202SAlex Deucher uint32_t ptr_mask; 78897b2e202SAlex Deucher bool ready; 78997b2e202SAlex Deucher u32 nop; 79097b2e202SAlex Deucher u32 idx; 79197b2e202SAlex Deucher u32 me; 79297b2e202SAlex Deucher u32 pipe; 79397b2e202SAlex Deucher u32 queue; 79497b2e202SAlex Deucher struct amdgpu_bo *mqd_obj; 79597b2e202SAlex Deucher u32 doorbell_index; 79697b2e202SAlex Deucher bool use_doorbell; 79797b2e202SAlex Deucher unsigned wptr_offs; 79897b2e202SAlex Deucher unsigned next_rptr_offs; 79997b2e202SAlex Deucher unsigned fence_offs; 800aa3b73f6SChristian König uint64_t current_ctx; 80197b2e202SAlex Deucher enum amdgpu_ring_type type; 80297b2e202SAlex Deucher char name[16]; 803128cff1aSMonk Liu unsigned cond_exe_offs; 804128cff1aSMonk Liu u64 cond_exe_gpu_addr; 805128cff1aSMonk Liu volatile u32 *cond_exe_cpu_addr; 806a909c6bdSMonk Liu #if defined(CONFIG_DEBUG_FS) 807a909c6bdSMonk Liu struct dentry *ent; 808a909c6bdSMonk Liu #endif 80997b2e202SAlex Deucher }; 81097b2e202SAlex Deucher 81197b2e202SAlex Deucher /* 81297b2e202SAlex Deucher * VM 81397b2e202SAlex Deucher */ 81497b2e202SAlex Deucher 81597b2e202SAlex Deucher /* maximum number of VMIDs */ 81697b2e202SAlex Deucher #define AMDGPU_NUM_VM 16 81797b2e202SAlex Deucher 81897b2e202SAlex Deucher /* number of entries in page table */ 81997b2e202SAlex Deucher #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 82097b2e202SAlex Deucher 82197b2e202SAlex Deucher /* PTBs (Page Table Blocks) need to be aligned to 32K */ 82297b2e202SAlex Deucher #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 82397b2e202SAlex Deucher #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 82497b2e202SAlex Deucher #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 82597b2e202SAlex Deucher 82697b2e202SAlex Deucher #define AMDGPU_PTE_VALID (1 << 0) 82797b2e202SAlex Deucher #define AMDGPU_PTE_SYSTEM (1 << 1) 82897b2e202SAlex Deucher #define AMDGPU_PTE_SNOOPED (1 << 2) 82997b2e202SAlex Deucher 83097b2e202SAlex Deucher /* VI only */ 83197b2e202SAlex Deucher #define AMDGPU_PTE_EXECUTABLE (1 << 4) 83297b2e202SAlex Deucher 83397b2e202SAlex Deucher #define AMDGPU_PTE_READABLE (1 << 5) 83497b2e202SAlex Deucher #define AMDGPU_PTE_WRITEABLE (1 << 6) 83597b2e202SAlex Deucher 83697b2e202SAlex Deucher /* PTE (Page Table Entry) fragment field for different page sizes */ 83797b2e202SAlex Deucher #define AMDGPU_PTE_FRAG_4KB (0 << 7) 83897b2e202SAlex Deucher #define AMDGPU_PTE_FRAG_64KB (4 << 7) 83997b2e202SAlex Deucher #define AMDGPU_LOG2_PAGES_PER_FRAG 4 84097b2e202SAlex Deucher 841d9c13156SChristian König /* How to programm VM fault handling */ 842d9c13156SChristian König #define AMDGPU_VM_FAULT_STOP_NEVER 0 843d9c13156SChristian König #define AMDGPU_VM_FAULT_STOP_FIRST 1 844d9c13156SChristian König #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 845d9c13156SChristian König 84697b2e202SAlex Deucher struct amdgpu_vm_pt { 847ee1782c3SChristian König struct amdgpu_bo_list_entry entry; 84897b2e202SAlex Deucher uint64_t addr; 84997b2e202SAlex Deucher }; 85097b2e202SAlex Deucher 85197b2e202SAlex Deucher struct amdgpu_vm { 85225cfc3c2SChristian König /* tree of virtual addresses mapped */ 85397b2e202SAlex Deucher struct rb_root va; 85497b2e202SAlex Deucher 8557fc11959SChristian König /* protecting invalidated */ 85697b2e202SAlex Deucher spinlock_t status_lock; 85797b2e202SAlex Deucher 85897b2e202SAlex Deucher /* BOs moved, but not yet updated in the PT */ 85997b2e202SAlex Deucher struct list_head invalidated; 86097b2e202SAlex Deucher 8617fc11959SChristian König /* BOs cleared in the PT because of a move */ 8627fc11959SChristian König struct list_head cleared; 8637fc11959SChristian König 8647fc11959SChristian König /* BO mappings freed, but not yet updated in the PT */ 86597b2e202SAlex Deucher struct list_head freed; 86697b2e202SAlex Deucher 86797b2e202SAlex Deucher /* contains the page directory */ 86897b2e202SAlex Deucher struct amdgpu_bo *page_directory; 86997b2e202SAlex Deucher unsigned max_pde_used; 87005906decSBas Nieuwenhuizen struct fence *page_directory_fence; 8715a712a87SChristian König uint64_t last_eviction_counter; 87297b2e202SAlex Deucher 87397b2e202SAlex Deucher /* array of page tables, one for each page directory entry */ 87497b2e202SAlex Deucher struct amdgpu_vm_pt *page_tables; 87597b2e202SAlex Deucher 87697b2e202SAlex Deucher /* for id and flush management per ring */ 877bcb1ba35SChristian König struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS]; 87825cfc3c2SChristian König 87981d75a30Sjimqu /* protecting freed */ 88081d75a30Sjimqu spinlock_t freed_lock; 8812bd9ccfaSChristian König 8822bd9ccfaSChristian König /* Scheduler entity for page table updates */ 8832bd9ccfaSChristian König struct amd_sched_entity entity; 884031e2983SChunming Zhou 885031e2983SChunming Zhou /* client id */ 886031e2983SChunming Zhou u64 client_id; 88797b2e202SAlex Deucher }; 88897b2e202SAlex Deucher 889bcb1ba35SChristian König struct amdgpu_vm_id { 890a9a78b32SChristian König struct list_head list; 891832a902fSChristian König struct fence *first; 892832a902fSChristian König struct amdgpu_sync active; 89341d9eb2cSChristian König struct fence *last_flush; 8940ea54b9bSChristian König atomic64_t owner; 895971fe9a9SChristian König 896bcb1ba35SChristian König uint64_t pd_gpu_addr; 897bcb1ba35SChristian König /* last flushed PD/PT update */ 898bcb1ba35SChristian König struct fence *flushed_updates; 899bcb1ba35SChristian König 9006adb0513SChunming Zhou uint32_t current_gpu_reset_count; 9016adb0513SChunming Zhou 902971fe9a9SChristian König uint32_t gds_base; 903971fe9a9SChristian König uint32_t gds_size; 904971fe9a9SChristian König uint32_t gws_base; 905971fe9a9SChristian König uint32_t gws_size; 906971fe9a9SChristian König uint32_t oa_base; 907971fe9a9SChristian König uint32_t oa_size; 908a9a78b32SChristian König }; 909a9a78b32SChristian König 910a9a78b32SChristian König struct amdgpu_vm_manager { 911a9a78b32SChristian König /* Handling of VMIDs */ 912a9a78b32SChristian König struct mutex lock; 913a9a78b32SChristian König unsigned num_ids; 914a9a78b32SChristian König struct list_head ids_lru; 915bcb1ba35SChristian König struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; 9161c16c0a7SChristian König 9171fbb2e92SChristian König /* Handling of VM fences */ 9181fbb2e92SChristian König u64 fence_context; 9191fbb2e92SChristian König unsigned seqno[AMDGPU_MAX_RINGS]; 9201fbb2e92SChristian König 92197b2e202SAlex Deucher uint32_t max_pfn; 92297b2e202SAlex Deucher /* vram base address for page table entry */ 92397b2e202SAlex Deucher u64 vram_base_offset; 92497b2e202SAlex Deucher /* is vm enabled? */ 92597b2e202SAlex Deucher bool enabled; 92697b2e202SAlex Deucher /* vm pte handling */ 92797b2e202SAlex Deucher const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 9282d55e45aSChristian König struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; 9292d55e45aSChristian König unsigned vm_pte_num_rings; 9302d55e45aSChristian König atomic_t vm_pte_next_ring; 931031e2983SChunming Zhou /* client id counter */ 932031e2983SChunming Zhou atomic64_t client_counter; 93397b2e202SAlex Deucher }; 93497b2e202SAlex Deucher 935a9a78b32SChristian König void amdgpu_vm_manager_init(struct amdgpu_device *adev); 936ea89f8c9SChristian König void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 9378b4fb00bSChristian König int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 9388b4fb00bSChristian König void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 93956467ebfSChristian König void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 9403c0eea6cSChristian König struct list_head *validated, 94156467ebfSChristian König struct amdgpu_bo_list_entry *entry); 9425a712a87SChristian König void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, 9435a712a87SChristian König struct list_head *duplicates); 944eceb8a15SChristian König void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, 945eceb8a15SChristian König struct amdgpu_vm *vm); 9468b4fb00bSChristian König int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 9474ff37a83SChristian König struct amdgpu_sync *sync, struct fence *fence, 9484ff37a83SChristian König unsigned *vm_id, uint64_t *vm_pd_addr); 94941d9eb2cSChristian König int amdgpu_vm_flush(struct amdgpu_ring *ring, 950cffadc83SChristian König unsigned vm_id, uint64_t pd_addr, 951cffadc83SChristian König uint32_t gds_base, uint32_t gds_size, 952cffadc83SChristian König uint32_t gws_base, uint32_t gws_size, 953cffadc83SChristian König uint32_t oa_base, uint32_t oa_size); 954971fe9a9SChristian König void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); 955b07c9d2aSChristian König uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 9568b4fb00bSChristian König int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 9578b4fb00bSChristian König struct amdgpu_vm *vm); 9588b4fb00bSChristian König int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 9598b4fb00bSChristian König struct amdgpu_vm *vm); 9608b4fb00bSChristian König int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, 9618b4fb00bSChristian König struct amdgpu_sync *sync); 9628b4fb00bSChristian König int amdgpu_vm_bo_update(struct amdgpu_device *adev, 9638b4fb00bSChristian König struct amdgpu_bo_va *bo_va, 9648b4fb00bSChristian König struct ttm_mem_reg *mem); 9658b4fb00bSChristian König void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 9668b4fb00bSChristian König struct amdgpu_bo *bo); 9678b4fb00bSChristian König struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 9688b4fb00bSChristian König struct amdgpu_bo *bo); 9698b4fb00bSChristian König struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 9708b4fb00bSChristian König struct amdgpu_vm *vm, 9718b4fb00bSChristian König struct amdgpu_bo *bo); 9728b4fb00bSChristian König int amdgpu_vm_bo_map(struct amdgpu_device *adev, 9738b4fb00bSChristian König struct amdgpu_bo_va *bo_va, 9748b4fb00bSChristian König uint64_t addr, uint64_t offset, 9758b4fb00bSChristian König uint64_t size, uint32_t flags); 9768b4fb00bSChristian König int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 9778b4fb00bSChristian König struct amdgpu_bo_va *bo_va, 9788b4fb00bSChristian König uint64_t addr); 9798b4fb00bSChristian König void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 9808b4fb00bSChristian König struct amdgpu_bo_va *bo_va); 9818b4fb00bSChristian König 98297b2e202SAlex Deucher /* 98397b2e202SAlex Deucher * context related structures 98497b2e202SAlex Deucher */ 98597b2e202SAlex Deucher 98621c16bf6SChristian König struct amdgpu_ctx_ring { 98721c16bf6SChristian König uint64_t sequence; 98837cd0ca2SChunming Zhou struct fence **fences; 98991404fb2SChristian König struct amd_sched_entity entity; 99021c16bf6SChristian König }; 99121c16bf6SChristian König 99297b2e202SAlex Deucher struct amdgpu_ctx { 99397b2e202SAlex Deucher struct kref refcount; 9949cb7e5a9SChunming Zhou struct amdgpu_device *adev; 995d94aed5aSMarek Olšák unsigned reset_counter; 99621c16bf6SChristian König spinlock_t ring_lock; 99737cd0ca2SChunming Zhou struct fence **fences; 99821c16bf6SChristian König struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 99997b2e202SAlex Deucher }; 100097b2e202SAlex Deucher 100197b2e202SAlex Deucher struct amdgpu_ctx_mgr { 100297b2e202SAlex Deucher struct amdgpu_device *adev; 10030147ee0fSMarek Olšák struct mutex lock; 10040b492a4cSAlex Deucher /* protected by lock */ 10050b492a4cSAlex Deucher struct idr ctx_handles; 100697b2e202SAlex Deucher }; 100797b2e202SAlex Deucher 10080b492a4cSAlex Deucher struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 10090b492a4cSAlex Deucher int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 10100b492a4cSAlex Deucher 101121c16bf6SChristian König uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 1012ce882e6dSChristian König struct fence *fence); 101321c16bf6SChristian König struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 101421c16bf6SChristian König struct amdgpu_ring *ring, uint64_t seq); 101521c16bf6SChristian König 10160b492a4cSAlex Deucher int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 10170b492a4cSAlex Deucher struct drm_file *filp); 10180b492a4cSAlex Deucher 1019efd4ccb5SChristian König void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1020efd4ccb5SChristian König void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 10210b492a4cSAlex Deucher 102297b2e202SAlex Deucher /* 102397b2e202SAlex Deucher * file private structure 102497b2e202SAlex Deucher */ 102597b2e202SAlex Deucher 102697b2e202SAlex Deucher struct amdgpu_fpriv { 102797b2e202SAlex Deucher struct amdgpu_vm vm; 102897b2e202SAlex Deucher struct mutex bo_list_lock; 102997b2e202SAlex Deucher struct idr bo_list_handles; 103097b2e202SAlex Deucher struct amdgpu_ctx_mgr ctx_mgr; 103197b2e202SAlex Deucher }; 103297b2e202SAlex Deucher 103397b2e202SAlex Deucher /* 103497b2e202SAlex Deucher * residency list 103597b2e202SAlex Deucher */ 103697b2e202SAlex Deucher 103797b2e202SAlex Deucher struct amdgpu_bo_list { 103897b2e202SAlex Deucher struct mutex lock; 103997b2e202SAlex Deucher struct amdgpu_bo *gds_obj; 104097b2e202SAlex Deucher struct amdgpu_bo *gws_obj; 104197b2e202SAlex Deucher struct amdgpu_bo *oa_obj; 1042211dff55SChristian König unsigned first_userptr; 104397b2e202SAlex Deucher unsigned num_entries; 104497b2e202SAlex Deucher struct amdgpu_bo_list_entry *array; 104597b2e202SAlex Deucher }; 104697b2e202SAlex Deucher 104797b2e202SAlex Deucher struct amdgpu_bo_list * 104897b2e202SAlex Deucher amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1049636ce25cSChristian König void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 1050636ce25cSChristian König struct list_head *validated); 105197b2e202SAlex Deucher void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 105297b2e202SAlex Deucher void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 105397b2e202SAlex Deucher 105497b2e202SAlex Deucher /* 105597b2e202SAlex Deucher * GFX stuff 105697b2e202SAlex Deucher */ 105797b2e202SAlex Deucher #include "clearstate_defs.h" 105897b2e202SAlex Deucher 105979e5412cSAlex Deucher struct amdgpu_rlc_funcs { 106079e5412cSAlex Deucher void (*enter_safe_mode)(struct amdgpu_device *adev); 106179e5412cSAlex Deucher void (*exit_safe_mode)(struct amdgpu_device *adev); 106279e5412cSAlex Deucher }; 106379e5412cSAlex Deucher 106497b2e202SAlex Deucher struct amdgpu_rlc { 106597b2e202SAlex Deucher /* for power gating */ 106697b2e202SAlex Deucher struct amdgpu_bo *save_restore_obj; 106797b2e202SAlex Deucher uint64_t save_restore_gpu_addr; 106897b2e202SAlex Deucher volatile uint32_t *sr_ptr; 106997b2e202SAlex Deucher const u32 *reg_list; 107097b2e202SAlex Deucher u32 reg_list_size; 107197b2e202SAlex Deucher /* for clear state */ 107297b2e202SAlex Deucher struct amdgpu_bo *clear_state_obj; 107397b2e202SAlex Deucher uint64_t clear_state_gpu_addr; 107497b2e202SAlex Deucher volatile uint32_t *cs_ptr; 107597b2e202SAlex Deucher const struct cs_section_def *cs_data; 107697b2e202SAlex Deucher u32 clear_state_size; 107797b2e202SAlex Deucher /* for cp tables */ 107897b2e202SAlex Deucher struct amdgpu_bo *cp_table_obj; 107997b2e202SAlex Deucher uint64_t cp_table_gpu_addr; 108097b2e202SAlex Deucher volatile uint32_t *cp_table_ptr; 108197b2e202SAlex Deucher u32 cp_table_size; 108279e5412cSAlex Deucher 108379e5412cSAlex Deucher /* safe mode for updating CG/PG state */ 108479e5412cSAlex Deucher bool in_safe_mode; 108579e5412cSAlex Deucher const struct amdgpu_rlc_funcs *funcs; 10862b6cd977SEric Huang 10872b6cd977SEric Huang /* for firmware data */ 10882b6cd977SEric Huang u32 save_and_restore_offset; 10892b6cd977SEric Huang u32 clear_state_descriptor_offset; 10902b6cd977SEric Huang u32 avail_scratch_ram_locations; 10912b6cd977SEric Huang u32 reg_restore_list_size; 10922b6cd977SEric Huang u32 reg_list_format_start; 10932b6cd977SEric Huang u32 reg_list_format_separate_start; 10942b6cd977SEric Huang u32 starting_offsets_start; 10952b6cd977SEric Huang u32 reg_list_format_size_bytes; 10962b6cd977SEric Huang u32 reg_list_size_bytes; 10972b6cd977SEric Huang 10982b6cd977SEric Huang u32 *register_list_format; 10992b6cd977SEric Huang u32 *register_restore; 110097b2e202SAlex Deucher }; 110197b2e202SAlex Deucher 110297b2e202SAlex Deucher struct amdgpu_mec { 110397b2e202SAlex Deucher struct amdgpu_bo *hpd_eop_obj; 110497b2e202SAlex Deucher u64 hpd_eop_gpu_addr; 110597b2e202SAlex Deucher u32 num_pipe; 110697b2e202SAlex Deucher u32 num_mec; 110797b2e202SAlex Deucher u32 num_queue; 110897b2e202SAlex Deucher }; 110997b2e202SAlex Deucher 111097b2e202SAlex Deucher /* 111197b2e202SAlex Deucher * GPU scratch registers structures, functions & helpers 111297b2e202SAlex Deucher */ 111397b2e202SAlex Deucher struct amdgpu_scratch { 111497b2e202SAlex Deucher unsigned num_reg; 111597b2e202SAlex Deucher uint32_t reg_base; 111697b2e202SAlex Deucher bool free[32]; 111797b2e202SAlex Deucher uint32_t reg[32]; 111897b2e202SAlex Deucher }; 111997b2e202SAlex Deucher 112097b2e202SAlex Deucher /* 112197b2e202SAlex Deucher * GFX configurations 112297b2e202SAlex Deucher */ 112397b2e202SAlex Deucher struct amdgpu_gca_config { 112497b2e202SAlex Deucher unsigned max_shader_engines; 112597b2e202SAlex Deucher unsigned max_tile_pipes; 112697b2e202SAlex Deucher unsigned max_cu_per_sh; 112797b2e202SAlex Deucher unsigned max_sh_per_se; 112897b2e202SAlex Deucher unsigned max_backends_per_se; 112997b2e202SAlex Deucher unsigned max_texture_channel_caches; 113097b2e202SAlex Deucher unsigned max_gprs; 113197b2e202SAlex Deucher unsigned max_gs_threads; 113297b2e202SAlex Deucher unsigned max_hw_contexts; 113397b2e202SAlex Deucher unsigned sc_prim_fifo_size_frontend; 113497b2e202SAlex Deucher unsigned sc_prim_fifo_size_backend; 113597b2e202SAlex Deucher unsigned sc_hiz_tile_fifo_size; 113697b2e202SAlex Deucher unsigned sc_earlyz_tile_fifo_size; 113797b2e202SAlex Deucher 113897b2e202SAlex Deucher unsigned num_tile_pipes; 113997b2e202SAlex Deucher unsigned backend_enable_mask; 114097b2e202SAlex Deucher unsigned mem_max_burst_length_bytes; 114197b2e202SAlex Deucher unsigned mem_row_size_in_kb; 114297b2e202SAlex Deucher unsigned shader_engine_tile_size; 114397b2e202SAlex Deucher unsigned num_gpus; 114497b2e202SAlex Deucher unsigned multi_gpu_tile_size; 114597b2e202SAlex Deucher unsigned mc_arb_ramcfg; 114697b2e202SAlex Deucher unsigned gb_addr_config; 11478f8e00c1SAlex Deucher unsigned num_rbs; 114897b2e202SAlex Deucher 114997b2e202SAlex Deucher uint32_t tile_mode_array[32]; 115097b2e202SAlex Deucher uint32_t macrotile_mode_array[16]; 115197b2e202SAlex Deucher }; 115297b2e202SAlex Deucher 11537dae69a2SAlex Deucher struct amdgpu_cu_info { 11547dae69a2SAlex Deucher uint32_t number; /* total active CU number */ 11557dae69a2SAlex Deucher uint32_t ao_cu_mask; 11567dae69a2SAlex Deucher uint32_t bitmap[4][4]; 11577dae69a2SAlex Deucher }; 11587dae69a2SAlex Deucher 1159b95e31fdSAlex Deucher struct amdgpu_gfx_funcs { 1160b95e31fdSAlex Deucher /* get the gpu clock counter */ 1161b95e31fdSAlex Deucher uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 11629559ef5bSTom St Denis void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 1163b95e31fdSAlex Deucher }; 1164b95e31fdSAlex Deucher 116597b2e202SAlex Deucher struct amdgpu_gfx { 116697b2e202SAlex Deucher struct mutex gpu_clock_mutex; 116797b2e202SAlex Deucher struct amdgpu_gca_config config; 116897b2e202SAlex Deucher struct amdgpu_rlc rlc; 116997b2e202SAlex Deucher struct amdgpu_mec mec; 117097b2e202SAlex Deucher struct amdgpu_scratch scratch; 117197b2e202SAlex Deucher const struct firmware *me_fw; /* ME firmware */ 117297b2e202SAlex Deucher uint32_t me_fw_version; 117397b2e202SAlex Deucher const struct firmware *pfp_fw; /* PFP firmware */ 117497b2e202SAlex Deucher uint32_t pfp_fw_version; 117597b2e202SAlex Deucher const struct firmware *ce_fw; /* CE firmware */ 117697b2e202SAlex Deucher uint32_t ce_fw_version; 117797b2e202SAlex Deucher const struct firmware *rlc_fw; /* RLC firmware */ 117897b2e202SAlex Deucher uint32_t rlc_fw_version; 117997b2e202SAlex Deucher const struct firmware *mec_fw; /* MEC firmware */ 118097b2e202SAlex Deucher uint32_t mec_fw_version; 118197b2e202SAlex Deucher const struct firmware *mec2_fw; /* MEC2 firmware */ 118297b2e202SAlex Deucher uint32_t mec2_fw_version; 118302558a00SKen Wang uint32_t me_feature_version; 118402558a00SKen Wang uint32_t ce_feature_version; 118502558a00SKen Wang uint32_t pfp_feature_version; 1186351643d7SJammy Zhou uint32_t rlc_feature_version; 1187351643d7SJammy Zhou uint32_t mec_feature_version; 1188351643d7SJammy Zhou uint32_t mec2_feature_version; 118997b2e202SAlex Deucher struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 119097b2e202SAlex Deucher unsigned num_gfx_rings; 119197b2e202SAlex Deucher struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 119297b2e202SAlex Deucher unsigned num_compute_rings; 119397b2e202SAlex Deucher struct amdgpu_irq_src eop_irq; 119497b2e202SAlex Deucher struct amdgpu_irq_src priv_reg_irq; 119597b2e202SAlex Deucher struct amdgpu_irq_src priv_inst_irq; 119697b2e202SAlex Deucher /* gfx status */ 119797b2e202SAlex Deucher uint32_t gfx_current_status; 1198a101a899SKen Wang /* ce ram size*/ 1199a101a899SKen Wang unsigned ce_ram_size; 12007dae69a2SAlex Deucher struct amdgpu_cu_info cu_info; 1201b95e31fdSAlex Deucher const struct amdgpu_gfx_funcs *funcs; 120297b2e202SAlex Deucher }; 120397b2e202SAlex Deucher 1204b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 120597b2e202SAlex Deucher unsigned size, struct amdgpu_ib *ib); 12064d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 12074d9c514dSChristian König struct fence *f); 1208b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 1209336d1f5eSChristian König struct amdgpu_ib *ib, struct fence *last_vm_update, 1210c5637837SMonk Liu struct amdgpu_job *job, struct fence **f); 121197b2e202SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev); 121297b2e202SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 121397b2e202SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 121497b2e202SAlex Deucher int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1215edff0e28SJammy Zhou void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 12169e5d5309SChristian König void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 121797b2e202SAlex Deucher void amdgpu_ring_commit(struct amdgpu_ring *ring); 121897b2e202SAlex Deucher void amdgpu_ring_undo(struct amdgpu_ring *ring); 121997b2e202SAlex Deucher unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 122097b2e202SAlex Deucher uint32_t **data); 122197b2e202SAlex Deucher int amdgpu_ring_restore(struct amdgpu_ring *ring, 122297b2e202SAlex Deucher unsigned size, uint32_t *data); 122397b2e202SAlex Deucher int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 122497b2e202SAlex Deucher unsigned ring_size, u32 nop, u32 align_mask, 122597b2e202SAlex Deucher struct amdgpu_irq_src *irq_src, unsigned irq_type, 122697b2e202SAlex Deucher enum amdgpu_ring_type ring_type); 122797b2e202SAlex Deucher void amdgpu_ring_fini(struct amdgpu_ring *ring); 122897b2e202SAlex Deucher 122997b2e202SAlex Deucher /* 123097b2e202SAlex Deucher * CS. 123197b2e202SAlex Deucher */ 123297b2e202SAlex Deucher struct amdgpu_cs_chunk { 123397b2e202SAlex Deucher uint32_t chunk_id; 123497b2e202SAlex Deucher uint32_t length_dw; 1235758ac17fSChristian König void *kdata; 123697b2e202SAlex Deucher }; 123797b2e202SAlex Deucher 123897b2e202SAlex Deucher struct amdgpu_cs_parser { 123997b2e202SAlex Deucher struct amdgpu_device *adev; 124097b2e202SAlex Deucher struct drm_file *filp; 12413cb485f3SChristian König struct amdgpu_ctx *ctx; 1242c3cca41eSChristian König 124397b2e202SAlex Deucher /* chunks */ 124497b2e202SAlex Deucher unsigned nchunks; 124597b2e202SAlex Deucher struct amdgpu_cs_chunk *chunks; 1246c3cca41eSChristian König 124750838c8cSChristian König /* scheduler job object */ 124850838c8cSChristian König struct amdgpu_job *job; 1249c3cca41eSChristian König 1250c3cca41eSChristian König /* buffer objects */ 1251c3cca41eSChristian König struct ww_acquire_ctx ticket; 1252c3cca41eSChristian König struct amdgpu_bo_list *bo_list; 125356467ebfSChristian König struct amdgpu_bo_list_entry vm_pd; 125497b2e202SAlex Deucher struct list_head validated; 1255984810fcSChristian König struct fence *fence; 1256f69f90a1SChristian König uint64_t bytes_moved_threshold; 1257f69f90a1SChristian König uint64_t bytes_moved; 125897b2e202SAlex Deucher 125997b2e202SAlex Deucher /* user fence */ 126091acbeb6SChristian König struct amdgpu_bo_list_entry uf_entry; 126197b2e202SAlex Deucher }; 126297b2e202SAlex Deucher 1263bb977d37SChunming Zhou struct amdgpu_job { 1264bb977d37SChunming Zhou struct amd_sched_job base; 1265bb977d37SChunming Zhou struct amdgpu_device *adev; 1266c5637837SMonk Liu struct amdgpu_vm *vm; 1267b07c60c0SChristian König struct amdgpu_ring *ring; 1268e86f9ceeSChristian König struct amdgpu_sync sync; 1269bb977d37SChunming Zhou struct amdgpu_ib *ibs; 127073cfa5f5SMonk Liu struct fence *fence; /* the hw fence */ 1271bb977d37SChunming Zhou uint32_t num_ibs; 1272e2840221SChristian König void *owner; 127392f25098SChristian König uint64_t ctx; 1274d88bf583SChristian König unsigned vm_id; 1275d88bf583SChristian König uint64_t vm_pd_addr; 1276d88bf583SChristian König uint32_t gds_base, gds_size; 1277d88bf583SChristian König uint32_t gws_base, gws_size; 1278d88bf583SChristian König uint32_t oa_base, oa_size; 1279758ac17fSChristian König 1280758ac17fSChristian König /* user fence handling */ 1281758ac17fSChristian König struct amdgpu_bo *uf_bo; 1282758ac17fSChristian König uint32_t uf_offset; 1283758ac17fSChristian König uint64_t uf_sequence; 1284758ac17fSChristian König 1285bb977d37SChunming Zhou }; 1286a6db8a33SJunwei Zhang #define to_amdgpu_job(sched_job) \ 1287a6db8a33SJunwei Zhang container_of((sched_job), struct amdgpu_job, base) 1288bb977d37SChunming Zhou 12897270f839SChristian König static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 12907270f839SChristian König uint32_t ib_idx, int idx) 129197b2e202SAlex Deucher { 129250838c8cSChristian König return p->job->ibs[ib_idx].ptr[idx]; 129397b2e202SAlex Deucher } 129497b2e202SAlex Deucher 12957270f839SChristian König static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 12967270f839SChristian König uint32_t ib_idx, int idx, 12977270f839SChristian König uint32_t value) 12987270f839SChristian König { 129950838c8cSChristian König p->job->ibs[ib_idx].ptr[idx] = value; 13007270f839SChristian König } 13017270f839SChristian König 130297b2e202SAlex Deucher /* 130397b2e202SAlex Deucher * Writeback 130497b2e202SAlex Deucher */ 130597b2e202SAlex Deucher #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 130697b2e202SAlex Deucher 130797b2e202SAlex Deucher struct amdgpu_wb { 130897b2e202SAlex Deucher struct amdgpu_bo *wb_obj; 130997b2e202SAlex Deucher volatile uint32_t *wb; 131097b2e202SAlex Deucher uint64_t gpu_addr; 131197b2e202SAlex Deucher u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 131297b2e202SAlex Deucher unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 131397b2e202SAlex Deucher }; 131497b2e202SAlex Deucher 131597b2e202SAlex Deucher int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 131697b2e202SAlex Deucher void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 131797b2e202SAlex Deucher 131897b2e202SAlex Deucher 131997b2e202SAlex Deucher 132097b2e202SAlex Deucher enum amdgpu_int_thermal_type { 132197b2e202SAlex Deucher THERMAL_TYPE_NONE, 132297b2e202SAlex Deucher THERMAL_TYPE_EXTERNAL, 132397b2e202SAlex Deucher THERMAL_TYPE_EXTERNAL_GPIO, 132497b2e202SAlex Deucher THERMAL_TYPE_RV6XX, 132597b2e202SAlex Deucher THERMAL_TYPE_RV770, 132697b2e202SAlex Deucher THERMAL_TYPE_ADT7473_WITH_INTERNAL, 132797b2e202SAlex Deucher THERMAL_TYPE_EVERGREEN, 132897b2e202SAlex Deucher THERMAL_TYPE_SUMO, 132997b2e202SAlex Deucher THERMAL_TYPE_NI, 133097b2e202SAlex Deucher THERMAL_TYPE_SI, 133197b2e202SAlex Deucher THERMAL_TYPE_EMC2103_WITH_INTERNAL, 133297b2e202SAlex Deucher THERMAL_TYPE_CI, 133397b2e202SAlex Deucher THERMAL_TYPE_KV, 133497b2e202SAlex Deucher }; 133597b2e202SAlex Deucher 133697b2e202SAlex Deucher enum amdgpu_dpm_auto_throttle_src { 133797b2e202SAlex Deucher AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 133897b2e202SAlex Deucher AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 133997b2e202SAlex Deucher }; 134097b2e202SAlex Deucher 134197b2e202SAlex Deucher enum amdgpu_dpm_event_src { 134297b2e202SAlex Deucher AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 134397b2e202SAlex Deucher AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 134497b2e202SAlex Deucher AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 134597b2e202SAlex Deucher AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 134697b2e202SAlex Deucher AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 134797b2e202SAlex Deucher }; 134897b2e202SAlex Deucher 134997b2e202SAlex Deucher #define AMDGPU_MAX_VCE_LEVELS 6 135097b2e202SAlex Deucher 135197b2e202SAlex Deucher enum amdgpu_vce_level { 135297b2e202SAlex Deucher AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 135397b2e202SAlex Deucher AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 135497b2e202SAlex Deucher AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 135597b2e202SAlex Deucher AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 135697b2e202SAlex Deucher AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 135797b2e202SAlex Deucher AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 135897b2e202SAlex Deucher }; 135997b2e202SAlex Deucher 136097b2e202SAlex Deucher struct amdgpu_ps { 136197b2e202SAlex Deucher u32 caps; /* vbios flags */ 136297b2e202SAlex Deucher u32 class; /* vbios flags */ 136397b2e202SAlex Deucher u32 class2; /* vbios flags */ 136497b2e202SAlex Deucher /* UVD clocks */ 136597b2e202SAlex Deucher u32 vclk; 136697b2e202SAlex Deucher u32 dclk; 136797b2e202SAlex Deucher /* VCE clocks */ 136897b2e202SAlex Deucher u32 evclk; 136997b2e202SAlex Deucher u32 ecclk; 137097b2e202SAlex Deucher bool vce_active; 137197b2e202SAlex Deucher enum amdgpu_vce_level vce_level; 137297b2e202SAlex Deucher /* asic priv */ 137397b2e202SAlex Deucher void *ps_priv; 137497b2e202SAlex Deucher }; 137597b2e202SAlex Deucher 137697b2e202SAlex Deucher struct amdgpu_dpm_thermal { 137797b2e202SAlex Deucher /* thermal interrupt work */ 137897b2e202SAlex Deucher struct work_struct work; 137997b2e202SAlex Deucher /* low temperature threshold */ 138097b2e202SAlex Deucher int min_temp; 138197b2e202SAlex Deucher /* high temperature threshold */ 138297b2e202SAlex Deucher int max_temp; 138397b2e202SAlex Deucher /* was last interrupt low to high or high to low */ 138497b2e202SAlex Deucher bool high_to_low; 138597b2e202SAlex Deucher /* interrupt source */ 138697b2e202SAlex Deucher struct amdgpu_irq_src irq; 138797b2e202SAlex Deucher }; 138897b2e202SAlex Deucher 138997b2e202SAlex Deucher enum amdgpu_clk_action 139097b2e202SAlex Deucher { 139197b2e202SAlex Deucher AMDGPU_SCLK_UP = 1, 139297b2e202SAlex Deucher AMDGPU_SCLK_DOWN 139397b2e202SAlex Deucher }; 139497b2e202SAlex Deucher 139597b2e202SAlex Deucher struct amdgpu_blacklist_clocks 139697b2e202SAlex Deucher { 139797b2e202SAlex Deucher u32 sclk; 139897b2e202SAlex Deucher u32 mclk; 139997b2e202SAlex Deucher enum amdgpu_clk_action action; 140097b2e202SAlex Deucher }; 140197b2e202SAlex Deucher 140297b2e202SAlex Deucher struct amdgpu_clock_and_voltage_limits { 140397b2e202SAlex Deucher u32 sclk; 140497b2e202SAlex Deucher u32 mclk; 140597b2e202SAlex Deucher u16 vddc; 140697b2e202SAlex Deucher u16 vddci; 140797b2e202SAlex Deucher }; 140897b2e202SAlex Deucher 140997b2e202SAlex Deucher struct amdgpu_clock_array { 141097b2e202SAlex Deucher u32 count; 141197b2e202SAlex Deucher u32 *values; 141297b2e202SAlex Deucher }; 141397b2e202SAlex Deucher 141497b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_entry { 141597b2e202SAlex Deucher u32 clk; 141697b2e202SAlex Deucher u16 v; 141797b2e202SAlex Deucher }; 141897b2e202SAlex Deucher 141997b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table { 142097b2e202SAlex Deucher u32 count; 142197b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_entry *entries; 142297b2e202SAlex Deucher }; 142397b2e202SAlex Deucher 142497b2e202SAlex Deucher union amdgpu_cac_leakage_entry { 142597b2e202SAlex Deucher struct { 142697b2e202SAlex Deucher u16 vddc; 142797b2e202SAlex Deucher u32 leakage; 142897b2e202SAlex Deucher }; 142997b2e202SAlex Deucher struct { 143097b2e202SAlex Deucher u16 vddc1; 143197b2e202SAlex Deucher u16 vddc2; 143297b2e202SAlex Deucher u16 vddc3; 143397b2e202SAlex Deucher }; 143497b2e202SAlex Deucher }; 143597b2e202SAlex Deucher 143697b2e202SAlex Deucher struct amdgpu_cac_leakage_table { 143797b2e202SAlex Deucher u32 count; 143897b2e202SAlex Deucher union amdgpu_cac_leakage_entry *entries; 143997b2e202SAlex Deucher }; 144097b2e202SAlex Deucher 144197b2e202SAlex Deucher struct amdgpu_phase_shedding_limits_entry { 144297b2e202SAlex Deucher u16 voltage; 144397b2e202SAlex Deucher u32 sclk; 144497b2e202SAlex Deucher u32 mclk; 144597b2e202SAlex Deucher }; 144697b2e202SAlex Deucher 144797b2e202SAlex Deucher struct amdgpu_phase_shedding_limits_table { 144897b2e202SAlex Deucher u32 count; 144997b2e202SAlex Deucher struct amdgpu_phase_shedding_limits_entry *entries; 145097b2e202SAlex Deucher }; 145197b2e202SAlex Deucher 145297b2e202SAlex Deucher struct amdgpu_uvd_clock_voltage_dependency_entry { 145397b2e202SAlex Deucher u32 vclk; 145497b2e202SAlex Deucher u32 dclk; 145597b2e202SAlex Deucher u16 v; 145697b2e202SAlex Deucher }; 145797b2e202SAlex Deucher 145897b2e202SAlex Deucher struct amdgpu_uvd_clock_voltage_dependency_table { 145997b2e202SAlex Deucher u8 count; 146097b2e202SAlex Deucher struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 146197b2e202SAlex Deucher }; 146297b2e202SAlex Deucher 146397b2e202SAlex Deucher struct amdgpu_vce_clock_voltage_dependency_entry { 146497b2e202SAlex Deucher u32 ecclk; 146597b2e202SAlex Deucher u32 evclk; 146697b2e202SAlex Deucher u16 v; 146797b2e202SAlex Deucher }; 146897b2e202SAlex Deucher 146997b2e202SAlex Deucher struct amdgpu_vce_clock_voltage_dependency_table { 147097b2e202SAlex Deucher u8 count; 147197b2e202SAlex Deucher struct amdgpu_vce_clock_voltage_dependency_entry *entries; 147297b2e202SAlex Deucher }; 147397b2e202SAlex Deucher 147497b2e202SAlex Deucher struct amdgpu_ppm_table { 147597b2e202SAlex Deucher u8 ppm_design; 147697b2e202SAlex Deucher u16 cpu_core_number; 147797b2e202SAlex Deucher u32 platform_tdp; 147897b2e202SAlex Deucher u32 small_ac_platform_tdp; 147997b2e202SAlex Deucher u32 platform_tdc; 148097b2e202SAlex Deucher u32 small_ac_platform_tdc; 148197b2e202SAlex Deucher u32 apu_tdp; 148297b2e202SAlex Deucher u32 dgpu_tdp; 148397b2e202SAlex Deucher u32 dgpu_ulv_power; 148497b2e202SAlex Deucher u32 tj_max; 148597b2e202SAlex Deucher }; 148697b2e202SAlex Deucher 148797b2e202SAlex Deucher struct amdgpu_cac_tdp_table { 148897b2e202SAlex Deucher u16 tdp; 148997b2e202SAlex Deucher u16 configurable_tdp; 149097b2e202SAlex Deucher u16 tdc; 149197b2e202SAlex Deucher u16 battery_power_limit; 149297b2e202SAlex Deucher u16 small_power_limit; 149397b2e202SAlex Deucher u16 low_cac_leakage; 149497b2e202SAlex Deucher u16 high_cac_leakage; 149597b2e202SAlex Deucher u16 maximum_power_delivery_limit; 149697b2e202SAlex Deucher }; 149797b2e202SAlex Deucher 149897b2e202SAlex Deucher struct amdgpu_dpm_dynamic_state { 149997b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 150097b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 150197b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 150297b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 150397b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 150497b2e202SAlex Deucher struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 150597b2e202SAlex Deucher struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 150697b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 150797b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 150897b2e202SAlex Deucher struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 150997b2e202SAlex Deucher struct amdgpu_clock_array valid_sclk_values; 151097b2e202SAlex Deucher struct amdgpu_clock_array valid_mclk_values; 151197b2e202SAlex Deucher struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 151297b2e202SAlex Deucher struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 151397b2e202SAlex Deucher u32 mclk_sclk_ratio; 151497b2e202SAlex Deucher u32 sclk_mclk_delta; 151597b2e202SAlex Deucher u16 vddc_vddci_delta; 151697b2e202SAlex Deucher u16 min_vddc_for_pcie_gen2; 151797b2e202SAlex Deucher struct amdgpu_cac_leakage_table cac_leakage_table; 151897b2e202SAlex Deucher struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 151997b2e202SAlex Deucher struct amdgpu_ppm_table *ppm_table; 152097b2e202SAlex Deucher struct amdgpu_cac_tdp_table *cac_tdp_table; 152197b2e202SAlex Deucher }; 152297b2e202SAlex Deucher 152397b2e202SAlex Deucher struct amdgpu_dpm_fan { 152497b2e202SAlex Deucher u16 t_min; 152597b2e202SAlex Deucher u16 t_med; 152697b2e202SAlex Deucher u16 t_high; 152797b2e202SAlex Deucher u16 pwm_min; 152897b2e202SAlex Deucher u16 pwm_med; 152997b2e202SAlex Deucher u16 pwm_high; 153097b2e202SAlex Deucher u8 t_hyst; 153197b2e202SAlex Deucher u32 cycle_delay; 153297b2e202SAlex Deucher u16 t_max; 153397b2e202SAlex Deucher u8 control_mode; 153497b2e202SAlex Deucher u16 default_max_fan_pwm; 153597b2e202SAlex Deucher u16 default_fan_output_sensitivity; 153697b2e202SAlex Deucher u16 fan_output_sensitivity; 153797b2e202SAlex Deucher bool ucode_fan_control; 153897b2e202SAlex Deucher }; 153997b2e202SAlex Deucher 154097b2e202SAlex Deucher enum amdgpu_pcie_gen { 154197b2e202SAlex Deucher AMDGPU_PCIE_GEN1 = 0, 154297b2e202SAlex Deucher AMDGPU_PCIE_GEN2 = 1, 154397b2e202SAlex Deucher AMDGPU_PCIE_GEN3 = 2, 154497b2e202SAlex Deucher AMDGPU_PCIE_GEN_INVALID = 0xffff 154597b2e202SAlex Deucher }; 154697b2e202SAlex Deucher 154797b2e202SAlex Deucher enum amdgpu_dpm_forced_level { 154897b2e202SAlex Deucher AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 154997b2e202SAlex Deucher AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 155097b2e202SAlex Deucher AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1551f3898ea1SEric Huang AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3, 155297b2e202SAlex Deucher }; 155397b2e202SAlex Deucher 155497b2e202SAlex Deucher struct amdgpu_vce_state { 155597b2e202SAlex Deucher /* vce clocks */ 155697b2e202SAlex Deucher u32 evclk; 155797b2e202SAlex Deucher u32 ecclk; 155897b2e202SAlex Deucher /* gpu clocks */ 155997b2e202SAlex Deucher u32 sclk; 156097b2e202SAlex Deucher u32 mclk; 156197b2e202SAlex Deucher u8 clk_idx; 156297b2e202SAlex Deucher u8 pstate; 156397b2e202SAlex Deucher }; 156497b2e202SAlex Deucher 156597b2e202SAlex Deucher struct amdgpu_dpm_funcs { 156697b2e202SAlex Deucher int (*get_temperature)(struct amdgpu_device *adev); 156797b2e202SAlex Deucher int (*pre_set_power_state)(struct amdgpu_device *adev); 156897b2e202SAlex Deucher int (*set_power_state)(struct amdgpu_device *adev); 156997b2e202SAlex Deucher void (*post_set_power_state)(struct amdgpu_device *adev); 157097b2e202SAlex Deucher void (*display_configuration_changed)(struct amdgpu_device *adev); 157197b2e202SAlex Deucher u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 157297b2e202SAlex Deucher u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 157397b2e202SAlex Deucher void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 157497b2e202SAlex Deucher void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 157597b2e202SAlex Deucher int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 157697b2e202SAlex Deucher bool (*vblank_too_short)(struct amdgpu_device *adev); 157797b2e202SAlex Deucher void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1578b7a07769SSonny Jiang void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 157997b2e202SAlex Deucher void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 158097b2e202SAlex Deucher void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 158197b2e202SAlex Deucher u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 158297b2e202SAlex Deucher int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 158397b2e202SAlex Deucher int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1584c85e299fSEric Huang int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask); 1585c85e299fSEric Huang int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf); 15868b2e574dSEric Huang int (*get_sclk_od)(struct amdgpu_device *adev); 15878b2e574dSEric Huang int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value); 1588f2bdc05fSEric Huang int (*get_mclk_od)(struct amdgpu_device *adev); 1589f2bdc05fSEric Huang int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value); 159097b2e202SAlex Deucher }; 159197b2e202SAlex Deucher 159297b2e202SAlex Deucher struct amdgpu_dpm { 159397b2e202SAlex Deucher struct amdgpu_ps *ps; 159497b2e202SAlex Deucher /* number of valid power states */ 159597b2e202SAlex Deucher int num_ps; 159697b2e202SAlex Deucher /* current power state that is active */ 159797b2e202SAlex Deucher struct amdgpu_ps *current_ps; 159897b2e202SAlex Deucher /* requested power state */ 159997b2e202SAlex Deucher struct amdgpu_ps *requested_ps; 160097b2e202SAlex Deucher /* boot up power state */ 160197b2e202SAlex Deucher struct amdgpu_ps *boot_ps; 160297b2e202SAlex Deucher /* default uvd power state */ 160397b2e202SAlex Deucher struct amdgpu_ps *uvd_ps; 160497b2e202SAlex Deucher /* vce requirements */ 160597b2e202SAlex Deucher struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 160697b2e202SAlex Deucher enum amdgpu_vce_level vce_level; 16073a2c788dSRex Zhu enum amd_pm_state_type state; 16083a2c788dSRex Zhu enum amd_pm_state_type user_state; 160997b2e202SAlex Deucher u32 platform_caps; 161097b2e202SAlex Deucher u32 voltage_response_time; 161197b2e202SAlex Deucher u32 backbias_response_time; 161297b2e202SAlex Deucher void *priv; 161397b2e202SAlex Deucher u32 new_active_crtcs; 161497b2e202SAlex Deucher int new_active_crtc_count; 161597b2e202SAlex Deucher u32 current_active_crtcs; 161697b2e202SAlex Deucher int current_active_crtc_count; 161797b2e202SAlex Deucher struct amdgpu_dpm_dynamic_state dyn_state; 161897b2e202SAlex Deucher struct amdgpu_dpm_fan fan; 161997b2e202SAlex Deucher u32 tdp_limit; 162097b2e202SAlex Deucher u32 near_tdp_limit; 162197b2e202SAlex Deucher u32 near_tdp_limit_adjusted; 162297b2e202SAlex Deucher u32 sq_ramping_threshold; 162397b2e202SAlex Deucher u32 cac_leakage; 162497b2e202SAlex Deucher u16 tdp_od_limit; 162597b2e202SAlex Deucher u32 tdp_adjustment; 162697b2e202SAlex Deucher u16 load_line_slope; 162797b2e202SAlex Deucher bool power_control; 162897b2e202SAlex Deucher bool ac_power; 162997b2e202SAlex Deucher /* special states active */ 163097b2e202SAlex Deucher bool thermal_active; 163197b2e202SAlex Deucher bool uvd_active; 163297b2e202SAlex Deucher bool vce_active; 163397b2e202SAlex Deucher /* thermal handling */ 163497b2e202SAlex Deucher struct amdgpu_dpm_thermal thermal; 163597b2e202SAlex Deucher /* forced levels */ 163697b2e202SAlex Deucher enum amdgpu_dpm_forced_level forced_level; 163797b2e202SAlex Deucher }; 163897b2e202SAlex Deucher 163997b2e202SAlex Deucher struct amdgpu_pm { 164097b2e202SAlex Deucher struct mutex mutex; 164197b2e202SAlex Deucher u32 current_sclk; 164297b2e202SAlex Deucher u32 current_mclk; 164397b2e202SAlex Deucher u32 default_sclk; 164497b2e202SAlex Deucher u32 default_mclk; 164597b2e202SAlex Deucher struct amdgpu_i2c_chan *i2c_bus; 164697b2e202SAlex Deucher /* internal thermal controller on rv6xx+ */ 164797b2e202SAlex Deucher enum amdgpu_int_thermal_type int_thermal_type; 164897b2e202SAlex Deucher struct device *int_hwmon_dev; 164997b2e202SAlex Deucher /* fan control parameters */ 165097b2e202SAlex Deucher bool no_fan; 165197b2e202SAlex Deucher u8 fan_pulses_per_revolution; 165297b2e202SAlex Deucher u8 fan_min_rpm; 165397b2e202SAlex Deucher u8 fan_max_rpm; 165497b2e202SAlex Deucher /* dpm */ 165597b2e202SAlex Deucher bool dpm_enabled; 1656c86f5ebfSAlex Deucher bool sysfs_initialized; 165797b2e202SAlex Deucher struct amdgpu_dpm dpm; 165897b2e202SAlex Deucher const struct firmware *fw; /* SMC firmware */ 165997b2e202SAlex Deucher uint32_t fw_version; 166097b2e202SAlex Deucher const struct amdgpu_dpm_funcs *funcs; 1661d0dd7f0cSAlex Deucher uint32_t pcie_gen_mask; 1662d0dd7f0cSAlex Deucher uint32_t pcie_mlw_mask; 16637fb72a1fSRex Zhu struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ 166497b2e202SAlex Deucher }; 166597b2e202SAlex Deucher 1666d0dd7f0cSAlex Deucher void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1667d0dd7f0cSAlex Deucher 166897b2e202SAlex Deucher /* 166997b2e202SAlex Deucher * UVD 167097b2e202SAlex Deucher */ 1671c0365541SArindam Nath #define AMDGPU_DEFAULT_UVD_HANDLES 10 1672c0365541SArindam Nath #define AMDGPU_MAX_UVD_HANDLES 40 1673c0365541SArindam Nath #define AMDGPU_UVD_STACK_SIZE (200*1024) 1674c0365541SArindam Nath #define AMDGPU_UVD_HEAP_SIZE (256*1024) 1675c0365541SArindam Nath #define AMDGPU_UVD_SESSION_SIZE (50*1024) 167697b2e202SAlex Deucher #define AMDGPU_UVD_FIRMWARE_OFFSET 256 167797b2e202SAlex Deucher 167897b2e202SAlex Deucher struct amdgpu_uvd { 167997b2e202SAlex Deucher struct amdgpu_bo *vcpu_bo; 168097b2e202SAlex Deucher void *cpu_addr; 168197b2e202SAlex Deucher uint64_t gpu_addr; 1682562e2689SSonny Jiang unsigned fw_version; 16833f99dd81SLeo Liu void *saved_bo; 1684c0365541SArindam Nath unsigned max_handles; 168597b2e202SAlex Deucher atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 168697b2e202SAlex Deucher struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 168797b2e202SAlex Deucher struct delayed_work idle_work; 168897b2e202SAlex Deucher const struct firmware *fw; /* UVD firmware */ 168997b2e202SAlex Deucher struct amdgpu_ring ring; 169097b2e202SAlex Deucher struct amdgpu_irq_src irq; 169197b2e202SAlex Deucher bool address_64_bit; 1692ead833ecSChristian König struct amd_sched_entity entity; 169397b2e202SAlex Deucher }; 169497b2e202SAlex Deucher 169597b2e202SAlex Deucher /* 169697b2e202SAlex Deucher * VCE 169797b2e202SAlex Deucher */ 169897b2e202SAlex Deucher #define AMDGPU_MAX_VCE_HANDLES 16 169997b2e202SAlex Deucher #define AMDGPU_VCE_FIRMWARE_OFFSET 256 170097b2e202SAlex Deucher 17016a585777SAlex Deucher #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 17026a585777SAlex Deucher #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 17036a585777SAlex Deucher 170497b2e202SAlex Deucher struct amdgpu_vce { 170597b2e202SAlex Deucher struct amdgpu_bo *vcpu_bo; 170697b2e202SAlex Deucher uint64_t gpu_addr; 170797b2e202SAlex Deucher unsigned fw_version; 170897b2e202SAlex Deucher unsigned fb_version; 170997b2e202SAlex Deucher atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 171097b2e202SAlex Deucher struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1711f1689ec1SChristian König uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 171297b2e202SAlex Deucher struct delayed_work idle_work; 171397b2e202SAlex Deucher const struct firmware *fw; /* VCE firmware */ 171497b2e202SAlex Deucher struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 171597b2e202SAlex Deucher struct amdgpu_irq_src irq; 17166a585777SAlex Deucher unsigned harvest_config; 1717c594989cSChristian König struct amd_sched_entity entity; 171897b2e202SAlex Deucher }; 171997b2e202SAlex Deucher 172097b2e202SAlex Deucher /* 172197b2e202SAlex Deucher * SDMA 172297b2e202SAlex Deucher */ 1723c113ea1cSAlex Deucher struct amdgpu_sdma_instance { 172497b2e202SAlex Deucher /* SDMA firmware */ 172597b2e202SAlex Deucher const struct firmware *fw; 172697b2e202SAlex Deucher uint32_t fw_version; 1727cfa2104fSJammy Zhou uint32_t feature_version; 172897b2e202SAlex Deucher 172997b2e202SAlex Deucher struct amdgpu_ring ring; 173018111de0SJammy Zhou bool burst_nop; 173197b2e202SAlex Deucher }; 173297b2e202SAlex Deucher 1733c113ea1cSAlex Deucher struct amdgpu_sdma { 1734c113ea1cSAlex Deucher struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1735c113ea1cSAlex Deucher struct amdgpu_irq_src trap_irq; 1736c113ea1cSAlex Deucher struct amdgpu_irq_src illegal_inst_irq; 1737c113ea1cSAlex Deucher int num_instances; 1738c113ea1cSAlex Deucher }; 1739c113ea1cSAlex Deucher 174097b2e202SAlex Deucher /* 174197b2e202SAlex Deucher * Firmware 174297b2e202SAlex Deucher */ 174397b2e202SAlex Deucher struct amdgpu_firmware { 174497b2e202SAlex Deucher struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 174597b2e202SAlex Deucher bool smu_load; 174697b2e202SAlex Deucher struct amdgpu_bo *fw_buf; 174797b2e202SAlex Deucher unsigned int fw_size; 174897b2e202SAlex Deucher }; 174997b2e202SAlex Deucher 175097b2e202SAlex Deucher /* 175197b2e202SAlex Deucher * Benchmarking 175297b2e202SAlex Deucher */ 175397b2e202SAlex Deucher void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 175497b2e202SAlex Deucher 175597b2e202SAlex Deucher 175697b2e202SAlex Deucher /* 175797b2e202SAlex Deucher * Testing 175897b2e202SAlex Deucher */ 175997b2e202SAlex Deucher void amdgpu_test_moves(struct amdgpu_device *adev); 176097b2e202SAlex Deucher void amdgpu_test_ring_sync(struct amdgpu_device *adev, 176197b2e202SAlex Deucher struct amdgpu_ring *cpA, 176297b2e202SAlex Deucher struct amdgpu_ring *cpB); 176397b2e202SAlex Deucher void amdgpu_test_syncing(struct amdgpu_device *adev); 176497b2e202SAlex Deucher 176597b2e202SAlex Deucher /* 176697b2e202SAlex Deucher * MMU Notifier 176797b2e202SAlex Deucher */ 176897b2e202SAlex Deucher #if defined(CONFIG_MMU_NOTIFIER) 176997b2e202SAlex Deucher int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 177097b2e202SAlex Deucher void amdgpu_mn_unregister(struct amdgpu_bo *bo); 177197b2e202SAlex Deucher #else 17721d1106b0SHarry Wentland static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 177397b2e202SAlex Deucher { 177497b2e202SAlex Deucher return -ENODEV; 177597b2e202SAlex Deucher } 17761d1106b0SHarry Wentland static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 177797b2e202SAlex Deucher #endif 177897b2e202SAlex Deucher 177997b2e202SAlex Deucher /* 178097b2e202SAlex Deucher * Debugfs 178197b2e202SAlex Deucher */ 178297b2e202SAlex Deucher struct amdgpu_debugfs { 178306ab6832SNils Wallménius const struct drm_info_list *files; 178497b2e202SAlex Deucher unsigned num_files; 178597b2e202SAlex Deucher }; 178697b2e202SAlex Deucher 178797b2e202SAlex Deucher int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 178806ab6832SNils Wallménius const struct drm_info_list *files, 178997b2e202SAlex Deucher unsigned nfiles); 179097b2e202SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 179197b2e202SAlex Deucher 179297b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS) 179397b2e202SAlex Deucher int amdgpu_debugfs_init(struct drm_minor *minor); 179497b2e202SAlex Deucher void amdgpu_debugfs_cleanup(struct drm_minor *minor); 179597b2e202SAlex Deucher #endif 179697b2e202SAlex Deucher 179750ab2533SHuang Rui int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); 179850ab2533SHuang Rui 179997b2e202SAlex Deucher /* 180097b2e202SAlex Deucher * amdgpu smumgr functions 180197b2e202SAlex Deucher */ 180297b2e202SAlex Deucher struct amdgpu_smumgr_funcs { 180397b2e202SAlex Deucher int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 180497b2e202SAlex Deucher int (*request_smu_load_fw)(struct amdgpu_device *adev); 180597b2e202SAlex Deucher int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 180697b2e202SAlex Deucher }; 180797b2e202SAlex Deucher 180897b2e202SAlex Deucher /* 180997b2e202SAlex Deucher * amdgpu smumgr 181097b2e202SAlex Deucher */ 181197b2e202SAlex Deucher struct amdgpu_smumgr { 181297b2e202SAlex Deucher struct amdgpu_bo *toc_buf; 181397b2e202SAlex Deucher struct amdgpu_bo *smu_buf; 181497b2e202SAlex Deucher /* asic priv smu data */ 181597b2e202SAlex Deucher void *priv; 181697b2e202SAlex Deucher spinlock_t smu_lock; 181797b2e202SAlex Deucher /* smumgr functions */ 181897b2e202SAlex Deucher const struct amdgpu_smumgr_funcs *smumgr_funcs; 181997b2e202SAlex Deucher /* ucode loading complete flag */ 182097b2e202SAlex Deucher uint32_t fw_flags; 182197b2e202SAlex Deucher }; 182297b2e202SAlex Deucher 182397b2e202SAlex Deucher /* 182497b2e202SAlex Deucher * ASIC specific register table accessible by UMD 182597b2e202SAlex Deucher */ 182697b2e202SAlex Deucher struct amdgpu_allowed_register_entry { 182797b2e202SAlex Deucher uint32_t reg_offset; 182897b2e202SAlex Deucher bool untouched; 182997b2e202SAlex Deucher bool grbm_indexed; 183097b2e202SAlex Deucher }; 183197b2e202SAlex Deucher 183297b2e202SAlex Deucher /* 183397b2e202SAlex Deucher * ASIC specific functions. 183497b2e202SAlex Deucher */ 183597b2e202SAlex Deucher struct amdgpu_asic_funcs { 183697b2e202SAlex Deucher bool (*read_disabled_bios)(struct amdgpu_device *adev); 18377946b878SAlex Deucher bool (*read_bios_from_rom)(struct amdgpu_device *adev, 18387946b878SAlex Deucher u8 *bios, u32 length_bytes); 183997b2e202SAlex Deucher int (*read_register)(struct amdgpu_device *adev, u32 se_num, 184097b2e202SAlex Deucher u32 sh_num, u32 reg_offset, u32 *value); 184197b2e202SAlex Deucher void (*set_vga_state)(struct amdgpu_device *adev, bool state); 184297b2e202SAlex Deucher int (*reset)(struct amdgpu_device *adev); 184397b2e202SAlex Deucher /* get the reference clock */ 184497b2e202SAlex Deucher u32 (*get_xclk)(struct amdgpu_device *adev); 184597b2e202SAlex Deucher /* MM block clocks */ 184697b2e202SAlex Deucher int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 184797b2e202SAlex Deucher int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1848048765adSAndres Rodriguez /* query virtual capabilities */ 1849048765adSAndres Rodriguez u32 (*get_virtual_caps)(struct amdgpu_device *adev); 185097b2e202SAlex Deucher }; 185197b2e202SAlex Deucher 185297b2e202SAlex Deucher /* 185397b2e202SAlex Deucher * IOCTL. 185497b2e202SAlex Deucher */ 185597b2e202SAlex Deucher int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 185697b2e202SAlex Deucher struct drm_file *filp); 185797b2e202SAlex Deucher int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 185897b2e202SAlex Deucher struct drm_file *filp); 185997b2e202SAlex Deucher 186097b2e202SAlex Deucher int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 186197b2e202SAlex Deucher struct drm_file *filp); 186297b2e202SAlex Deucher int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 186397b2e202SAlex Deucher struct drm_file *filp); 186497b2e202SAlex Deucher int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 186597b2e202SAlex Deucher struct drm_file *filp); 186697b2e202SAlex Deucher int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 186797b2e202SAlex Deucher struct drm_file *filp); 186897b2e202SAlex Deucher int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 186997b2e202SAlex Deucher struct drm_file *filp); 187097b2e202SAlex Deucher int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 187197b2e202SAlex Deucher struct drm_file *filp); 187297b2e202SAlex Deucher int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 187397b2e202SAlex Deucher int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 187497b2e202SAlex Deucher 187597b2e202SAlex Deucher int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 187697b2e202SAlex Deucher struct drm_file *filp); 187797b2e202SAlex Deucher 187897b2e202SAlex Deucher /* VRAM scratch page for HDP bug, default vram page */ 187997b2e202SAlex Deucher struct amdgpu_vram_scratch { 188097b2e202SAlex Deucher struct amdgpu_bo *robj; 188197b2e202SAlex Deucher volatile uint32_t *ptr; 188297b2e202SAlex Deucher u64 gpu_addr; 188397b2e202SAlex Deucher }; 188497b2e202SAlex Deucher 188597b2e202SAlex Deucher /* 188697b2e202SAlex Deucher * ACPI 188797b2e202SAlex Deucher */ 188897b2e202SAlex Deucher struct amdgpu_atif_notification_cfg { 188997b2e202SAlex Deucher bool enabled; 189097b2e202SAlex Deucher int command_code; 189197b2e202SAlex Deucher }; 189297b2e202SAlex Deucher 189397b2e202SAlex Deucher struct amdgpu_atif_notifications { 189497b2e202SAlex Deucher bool display_switch; 189597b2e202SAlex Deucher bool expansion_mode_change; 189697b2e202SAlex Deucher bool thermal_state; 189797b2e202SAlex Deucher bool forced_power_state; 189897b2e202SAlex Deucher bool system_power_state; 189997b2e202SAlex Deucher bool display_conf_change; 190097b2e202SAlex Deucher bool px_gfx_switch; 190197b2e202SAlex Deucher bool brightness_change; 190297b2e202SAlex Deucher bool dgpu_display_event; 190397b2e202SAlex Deucher }; 190497b2e202SAlex Deucher 190597b2e202SAlex Deucher struct amdgpu_atif_functions { 190697b2e202SAlex Deucher bool system_params; 190797b2e202SAlex Deucher bool sbios_requests; 190897b2e202SAlex Deucher bool select_active_disp; 190997b2e202SAlex Deucher bool lid_state; 191097b2e202SAlex Deucher bool get_tv_standard; 191197b2e202SAlex Deucher bool set_tv_standard; 191297b2e202SAlex Deucher bool get_panel_expansion_mode; 191397b2e202SAlex Deucher bool set_panel_expansion_mode; 191497b2e202SAlex Deucher bool temperature_change; 191597b2e202SAlex Deucher bool graphics_device_types; 191697b2e202SAlex Deucher }; 191797b2e202SAlex Deucher 191897b2e202SAlex Deucher struct amdgpu_atif { 191997b2e202SAlex Deucher struct amdgpu_atif_notifications notifications; 192097b2e202SAlex Deucher struct amdgpu_atif_functions functions; 192197b2e202SAlex Deucher struct amdgpu_atif_notification_cfg notification_cfg; 192297b2e202SAlex Deucher struct amdgpu_encoder *encoder_for_bl; 192397b2e202SAlex Deucher }; 192497b2e202SAlex Deucher 192597b2e202SAlex Deucher struct amdgpu_atcs_functions { 192697b2e202SAlex Deucher bool get_ext_state; 192797b2e202SAlex Deucher bool pcie_perf_req; 192897b2e202SAlex Deucher bool pcie_dev_rdy; 192997b2e202SAlex Deucher bool pcie_bus_width; 193097b2e202SAlex Deucher }; 193197b2e202SAlex Deucher 193297b2e202SAlex Deucher struct amdgpu_atcs { 193397b2e202SAlex Deucher struct amdgpu_atcs_functions functions; 193497b2e202SAlex Deucher }; 193597b2e202SAlex Deucher 193697b2e202SAlex Deucher /* 1937d03846afSChunming Zhou * CGS 1938d03846afSChunming Zhou */ 1939110e6f26SDave Airlie struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1940110e6f26SDave Airlie void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1941a8fe58ceSMaruthi Bayyavarapu 1942a8fe58ceSMaruthi Bayyavarapu 19437e471e6fSAlex Deucher /* GPU virtualization */ 1944048765adSAndres Rodriguez #define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0) 1945048765adSAndres Rodriguez #define AMDGPU_VIRT_CAPS_IS_VF (1 << 1) 19467e471e6fSAlex Deucher struct amdgpu_virtualization { 19477e471e6fSAlex Deucher bool supports_sr_iov; 1948048765adSAndres Rodriguez bool is_virtual; 1949048765adSAndres Rodriguez u32 caps; 19507e471e6fSAlex Deucher }; 19517e471e6fSAlex Deucher 1952a8fe58ceSMaruthi Bayyavarapu /* 195397b2e202SAlex Deucher * Core structure, functions and helpers. 195497b2e202SAlex Deucher */ 195597b2e202SAlex Deucher typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 195697b2e202SAlex Deucher typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 195797b2e202SAlex Deucher 195897b2e202SAlex Deucher typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 195997b2e202SAlex Deucher typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 196097b2e202SAlex Deucher 19618faf0e08SAlex Deucher struct amdgpu_ip_block_status { 19628faf0e08SAlex Deucher bool valid; 19638faf0e08SAlex Deucher bool sw; 19648faf0e08SAlex Deucher bool hw; 19658faf0e08SAlex Deucher }; 19668faf0e08SAlex Deucher 196797b2e202SAlex Deucher struct amdgpu_device { 196897b2e202SAlex Deucher struct device *dev; 196997b2e202SAlex Deucher struct drm_device *ddev; 197097b2e202SAlex Deucher struct pci_dev *pdev; 197197b2e202SAlex Deucher 1972a8fe58ceSMaruthi Bayyavarapu #ifdef CONFIG_DRM_AMD_ACP 1973a8fe58ceSMaruthi Bayyavarapu struct amdgpu_acp acp; 1974a8fe58ceSMaruthi Bayyavarapu #endif 1975a8fe58ceSMaruthi Bayyavarapu 197697b2e202SAlex Deucher /* ASIC */ 19772f7d10b3SJammy Zhou enum amd_asic_type asic_type; 197897b2e202SAlex Deucher uint32_t family; 197997b2e202SAlex Deucher uint32_t rev_id; 198097b2e202SAlex Deucher uint32_t external_rev_id; 198197b2e202SAlex Deucher unsigned long flags; 198297b2e202SAlex Deucher int usec_timeout; 198397b2e202SAlex Deucher const struct amdgpu_asic_funcs *asic_funcs; 198497b2e202SAlex Deucher bool shutdown; 198597b2e202SAlex Deucher bool need_dma32; 198697b2e202SAlex Deucher bool accel_working; 198797b2e202SAlex Deucher struct work_struct reset_work; 198897b2e202SAlex Deucher struct notifier_block acpi_nb; 198997b2e202SAlex Deucher struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 199097b2e202SAlex Deucher struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 199197b2e202SAlex Deucher unsigned debugfs_count; 199297b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS) 1993adcec288STom St Denis struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 199497b2e202SAlex Deucher #endif 199597b2e202SAlex Deucher struct amdgpu_atif atif; 199697b2e202SAlex Deucher struct amdgpu_atcs atcs; 199797b2e202SAlex Deucher struct mutex srbm_mutex; 199897b2e202SAlex Deucher /* GRBM index mutex. Protects concurrent access to GRBM index */ 199997b2e202SAlex Deucher struct mutex grbm_idx_mutex; 200097b2e202SAlex Deucher struct dev_pm_domain vga_pm_domain; 200197b2e202SAlex Deucher bool have_disp_power_ref; 200297b2e202SAlex Deucher 200397b2e202SAlex Deucher /* BIOS */ 200497b2e202SAlex Deucher uint8_t *bios; 200597b2e202SAlex Deucher bool is_atom_bios; 200697b2e202SAlex Deucher struct amdgpu_bo *stollen_vga_memory; 200797b2e202SAlex Deucher uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 200897b2e202SAlex Deucher 200997b2e202SAlex Deucher /* Register/doorbell mmio */ 201097b2e202SAlex Deucher resource_size_t rmmio_base; 201197b2e202SAlex Deucher resource_size_t rmmio_size; 201297b2e202SAlex Deucher void __iomem *rmmio; 201397b2e202SAlex Deucher /* protects concurrent MM_INDEX/DATA based register access */ 201497b2e202SAlex Deucher spinlock_t mmio_idx_lock; 201597b2e202SAlex Deucher /* protects concurrent SMC based register access */ 201697b2e202SAlex Deucher spinlock_t smc_idx_lock; 201797b2e202SAlex Deucher amdgpu_rreg_t smc_rreg; 201897b2e202SAlex Deucher amdgpu_wreg_t smc_wreg; 201997b2e202SAlex Deucher /* protects concurrent PCIE register access */ 202097b2e202SAlex Deucher spinlock_t pcie_idx_lock; 202197b2e202SAlex Deucher amdgpu_rreg_t pcie_rreg; 202297b2e202SAlex Deucher amdgpu_wreg_t pcie_wreg; 202397b2e202SAlex Deucher /* protects concurrent UVD register access */ 202497b2e202SAlex Deucher spinlock_t uvd_ctx_idx_lock; 202597b2e202SAlex Deucher amdgpu_rreg_t uvd_ctx_rreg; 202697b2e202SAlex Deucher amdgpu_wreg_t uvd_ctx_wreg; 202797b2e202SAlex Deucher /* protects concurrent DIDT register access */ 202897b2e202SAlex Deucher spinlock_t didt_idx_lock; 202997b2e202SAlex Deucher amdgpu_rreg_t didt_rreg; 203097b2e202SAlex Deucher amdgpu_wreg_t didt_wreg; 203197b2e202SAlex Deucher /* protects concurrent ENDPOINT (audio) register access */ 203297b2e202SAlex Deucher spinlock_t audio_endpt_idx_lock; 203397b2e202SAlex Deucher amdgpu_block_rreg_t audio_endpt_rreg; 203497b2e202SAlex Deucher amdgpu_block_wreg_t audio_endpt_wreg; 203597b2e202SAlex Deucher void __iomem *rio_mem; 203697b2e202SAlex Deucher resource_size_t rio_mem_size; 203797b2e202SAlex Deucher struct amdgpu_doorbell doorbell; 203897b2e202SAlex Deucher 203997b2e202SAlex Deucher /* clock/pll info */ 204097b2e202SAlex Deucher struct amdgpu_clock clock; 204197b2e202SAlex Deucher 204297b2e202SAlex Deucher /* MC */ 204397b2e202SAlex Deucher struct amdgpu_mc mc; 204497b2e202SAlex Deucher struct amdgpu_gart gart; 204597b2e202SAlex Deucher struct amdgpu_dummy_page dummy_page; 204697b2e202SAlex Deucher struct amdgpu_vm_manager vm_manager; 204797b2e202SAlex Deucher 204897b2e202SAlex Deucher /* memory management */ 204997b2e202SAlex Deucher struct amdgpu_mman mman; 205097b2e202SAlex Deucher struct amdgpu_vram_scratch vram_scratch; 205197b2e202SAlex Deucher struct amdgpu_wb wb; 205297b2e202SAlex Deucher atomic64_t vram_usage; 205397b2e202SAlex Deucher atomic64_t vram_vis_usage; 205497b2e202SAlex Deucher atomic64_t gtt_usage; 205597b2e202SAlex Deucher atomic64_t num_bytes_moved; 2056dbd5ed60SChristian König atomic64_t num_evictions; 2057d94aed5aSMarek Olšák atomic_t gpu_reset_counter; 205897b2e202SAlex Deucher 205997b2e202SAlex Deucher /* display */ 206097b2e202SAlex Deucher struct amdgpu_mode_info mode_info; 206197b2e202SAlex Deucher struct work_struct hotplug_work; 206297b2e202SAlex Deucher struct amdgpu_irq_src crtc_irq; 206397b2e202SAlex Deucher struct amdgpu_irq_src pageflip_irq; 206497b2e202SAlex Deucher struct amdgpu_irq_src hpd_irq; 206597b2e202SAlex Deucher 206697b2e202SAlex Deucher /* rings */ 206776bf0db5SChristian König u64 fence_context; 206897b2e202SAlex Deucher unsigned num_rings; 206997b2e202SAlex Deucher struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 207097b2e202SAlex Deucher bool ib_pool_ready; 207197b2e202SAlex Deucher struct amdgpu_sa_manager ring_tmp_bo; 207297b2e202SAlex Deucher 207397b2e202SAlex Deucher /* interrupts */ 207497b2e202SAlex Deucher struct amdgpu_irq irq; 207597b2e202SAlex Deucher 20761f7371b2SAlex Deucher /* powerplay */ 20771f7371b2SAlex Deucher struct amd_powerplay powerplay; 2078e61710c5SJammy Zhou bool pp_enabled; 2079f3898ea1SEric Huang bool pp_force_state_enabled; 20801f7371b2SAlex Deucher 208197b2e202SAlex Deucher /* dpm */ 208297b2e202SAlex Deucher struct amdgpu_pm pm; 208397b2e202SAlex Deucher u32 cg_flags; 208497b2e202SAlex Deucher u32 pg_flags; 208597b2e202SAlex Deucher 208697b2e202SAlex Deucher /* amdgpu smumgr */ 208797b2e202SAlex Deucher struct amdgpu_smumgr smu; 208897b2e202SAlex Deucher 208997b2e202SAlex Deucher /* gfx */ 209097b2e202SAlex Deucher struct amdgpu_gfx gfx; 209197b2e202SAlex Deucher 209297b2e202SAlex Deucher /* sdma */ 2093c113ea1cSAlex Deucher struct amdgpu_sdma sdma; 209497b2e202SAlex Deucher 209597b2e202SAlex Deucher /* uvd */ 209697b2e202SAlex Deucher struct amdgpu_uvd uvd; 209797b2e202SAlex Deucher 209897b2e202SAlex Deucher /* vce */ 209997b2e202SAlex Deucher struct amdgpu_vce vce; 210097b2e202SAlex Deucher 210197b2e202SAlex Deucher /* firmwares */ 210297b2e202SAlex Deucher struct amdgpu_firmware firmware; 210397b2e202SAlex Deucher 210497b2e202SAlex Deucher /* GDS */ 210597b2e202SAlex Deucher struct amdgpu_gds gds; 210697b2e202SAlex Deucher 210797b2e202SAlex Deucher const struct amdgpu_ip_block_version *ip_blocks; 210897b2e202SAlex Deucher int num_ip_blocks; 21098faf0e08SAlex Deucher struct amdgpu_ip_block_status *ip_block_status; 211097b2e202SAlex Deucher struct mutex mn_lock; 211197b2e202SAlex Deucher DECLARE_HASHTABLE(mn_hash, 7); 211297b2e202SAlex Deucher 211397b2e202SAlex Deucher /* tracking pinned memory */ 211497b2e202SAlex Deucher u64 vram_pin_size; 2115e131b914SChunming Zhou u64 invisible_pin_size; 211697b2e202SAlex Deucher u64 gart_pin_size; 2117130e0371SOded Gabbay 2118130e0371SOded Gabbay /* amdkfd interface */ 2119130e0371SOded Gabbay struct kfd_dev *kfd; 212023ca0e4eSChunming Zhou 21217e471e6fSAlex Deucher struct amdgpu_virtualization virtualization; 212297b2e202SAlex Deucher }; 212397b2e202SAlex Deucher 212497b2e202SAlex Deucher bool amdgpu_device_is_px(struct drm_device *dev); 212597b2e202SAlex Deucher int amdgpu_device_init(struct amdgpu_device *adev, 212697b2e202SAlex Deucher struct drm_device *ddev, 212797b2e202SAlex Deucher struct pci_dev *pdev, 212897b2e202SAlex Deucher uint32_t flags); 212997b2e202SAlex Deucher void amdgpu_device_fini(struct amdgpu_device *adev); 213097b2e202SAlex Deucher int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 213197b2e202SAlex Deucher 213297b2e202SAlex Deucher uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 213397b2e202SAlex Deucher bool always_indirect); 213497b2e202SAlex Deucher void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 213597b2e202SAlex Deucher bool always_indirect); 213697b2e202SAlex Deucher u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 213797b2e202SAlex Deucher void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 213897b2e202SAlex Deucher 213997b2e202SAlex Deucher u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 214097b2e202SAlex Deucher void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 214197b2e202SAlex Deucher 214297b2e202SAlex Deucher /* 214397b2e202SAlex Deucher * Registers read & write functions. 214497b2e202SAlex Deucher */ 214597b2e202SAlex Deucher #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 214697b2e202SAlex Deucher #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 214797b2e202SAlex Deucher #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 214897b2e202SAlex Deucher #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 214997b2e202SAlex Deucher #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 215097b2e202SAlex Deucher #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 215197b2e202SAlex Deucher #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 215297b2e202SAlex Deucher #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 215397b2e202SAlex Deucher #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 215497b2e202SAlex Deucher #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 215597b2e202SAlex Deucher #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 215697b2e202SAlex Deucher #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 215797b2e202SAlex Deucher #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 215897b2e202SAlex Deucher #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 215997b2e202SAlex Deucher #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 216097b2e202SAlex Deucher #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 216197b2e202SAlex Deucher #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 216297b2e202SAlex Deucher #define WREG32_P(reg, val, mask) \ 216397b2e202SAlex Deucher do { \ 216497b2e202SAlex Deucher uint32_t tmp_ = RREG32(reg); \ 216597b2e202SAlex Deucher tmp_ &= (mask); \ 216697b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 216797b2e202SAlex Deucher WREG32(reg, tmp_); \ 216897b2e202SAlex Deucher } while (0) 216997b2e202SAlex Deucher #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 217097b2e202SAlex Deucher #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 217197b2e202SAlex Deucher #define WREG32_PLL_P(reg, val, mask) \ 217297b2e202SAlex Deucher do { \ 217397b2e202SAlex Deucher uint32_t tmp_ = RREG32_PLL(reg); \ 217497b2e202SAlex Deucher tmp_ &= (mask); \ 217597b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 217697b2e202SAlex Deucher WREG32_PLL(reg, tmp_); \ 217797b2e202SAlex Deucher } while (0) 217897b2e202SAlex Deucher #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 217997b2e202SAlex Deucher #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 218097b2e202SAlex Deucher #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 218197b2e202SAlex Deucher 218297b2e202SAlex Deucher #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 218397b2e202SAlex Deucher #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 218497b2e202SAlex Deucher 218597b2e202SAlex Deucher #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 218697b2e202SAlex Deucher #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 218797b2e202SAlex Deucher 218897b2e202SAlex Deucher #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 218997b2e202SAlex Deucher (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 219097b2e202SAlex Deucher (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 219197b2e202SAlex Deucher 219297b2e202SAlex Deucher #define REG_GET_FIELD(value, reg, field) \ 219397b2e202SAlex Deucher (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 219497b2e202SAlex Deucher 219597b2e202SAlex Deucher /* 219697b2e202SAlex Deucher * BIOS helpers. 219797b2e202SAlex Deucher */ 219897b2e202SAlex Deucher #define RBIOS8(i) (adev->bios[i]) 219997b2e202SAlex Deucher #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 220097b2e202SAlex Deucher #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 220197b2e202SAlex Deucher 220297b2e202SAlex Deucher /* 220397b2e202SAlex Deucher * RING helpers. 220497b2e202SAlex Deucher */ 220597b2e202SAlex Deucher static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 220697b2e202SAlex Deucher { 220797b2e202SAlex Deucher if (ring->count_dw <= 0) 220886c2b790SJammy Zhou DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 220997b2e202SAlex Deucher ring->ring[ring->wptr++] = v; 221097b2e202SAlex Deucher ring->wptr &= ring->ptr_mask; 221197b2e202SAlex Deucher ring->count_dw--; 221297b2e202SAlex Deucher } 221397b2e202SAlex Deucher 2214c113ea1cSAlex Deucher static inline struct amdgpu_sdma_instance * 2215c113ea1cSAlex Deucher amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 22164b2f7e2cSJammy Zhou { 22174b2f7e2cSJammy Zhou struct amdgpu_device *adev = ring->adev; 22184b2f7e2cSJammy Zhou int i; 22194b2f7e2cSJammy Zhou 2220c113ea1cSAlex Deucher for (i = 0; i < adev->sdma.num_instances; i++) 2221c113ea1cSAlex Deucher if (&adev->sdma.instance[i].ring == ring) 22224b2f7e2cSJammy Zhou break; 22234b2f7e2cSJammy Zhou 22244b2f7e2cSJammy Zhou if (i < AMDGPU_MAX_SDMA_INSTANCES) 2225c113ea1cSAlex Deucher return &adev->sdma.instance[i]; 22264b2f7e2cSJammy Zhou else 22274b2f7e2cSJammy Zhou return NULL; 22284b2f7e2cSJammy Zhou } 22294b2f7e2cSJammy Zhou 223097b2e202SAlex Deucher /* 223197b2e202SAlex Deucher * ASICs macro. 223297b2e202SAlex Deucher */ 223397b2e202SAlex Deucher #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 223497b2e202SAlex Deucher #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 223597b2e202SAlex Deucher #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 223697b2e202SAlex Deucher #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 223797b2e202SAlex Deucher #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2238048765adSAndres Rodriguez #define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev))) 223997b2e202SAlex Deucher #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 22407946b878SAlex Deucher #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 224197b2e202SAlex Deucher #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 224297b2e202SAlex Deucher #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 224397b2e202SAlex Deucher #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 224497b2e202SAlex Deucher #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2245b07c9d2aSChristian König #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags))) 224697b2e202SAlex Deucher #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 224797b2e202SAlex Deucher #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 224897b2e202SAlex Deucher #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 224997b2e202SAlex Deucher #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 225097b2e202SAlex Deucher #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 225197b2e202SAlex Deucher #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 225297b2e202SAlex Deucher #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2253d88bf583SChristian König #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 2254b8c7b39eSChristian König #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 225597b2e202SAlex Deucher #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2256890ee23fSChunming Zhou #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 225797b2e202SAlex Deucher #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2258d2edb07bSChristian König #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 225911afbde8SChunming Zhou #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 22609e5d5309SChristian König #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 226103ccf481SMonk Liu #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 226203ccf481SMonk Liu #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 226397b2e202SAlex Deucher #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 226497b2e202SAlex Deucher #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 226597b2e202SAlex Deucher #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 226697b2e202SAlex Deucher #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 226797b2e202SAlex Deucher #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 226897b2e202SAlex Deucher #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 226997b2e202SAlex Deucher #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 227097b2e202SAlex Deucher #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 227197b2e202SAlex Deucher #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 227297b2e202SAlex Deucher #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 227397b2e202SAlex Deucher #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 227497b2e202SAlex Deucher #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 227597b2e202SAlex Deucher #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2276cb9e59d7SAlex Deucher #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 227797b2e202SAlex Deucher #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 227897b2e202SAlex Deucher #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 227997b2e202SAlex Deucher #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 228097b2e202SAlex Deucher #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 228197b2e202SAlex Deucher #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2282c7ae72c0SChunming Zhou #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 22836e7a3840SChunming Zhou #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 228497b2e202SAlex Deucher #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 228597b2e202SAlex Deucher #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 228697b2e202SAlex Deucher #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 228797b2e202SAlex Deucher #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 228897b2e202SAlex Deucher #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 228997b2e202SAlex Deucher #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 229097b2e202SAlex Deucher #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2291b95e31fdSAlex Deucher #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 22929559ef5bSTom St Denis #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 22933af76f23SRex Zhu 22943af76f23SRex Zhu #define amdgpu_dpm_get_temperature(adev) \ 22954b5ece24SEric Huang ((adev)->pp_enabled ? \ 22963af76f23SRex Zhu (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ 22974b5ece24SEric Huang (adev)->pm.funcs->get_temperature((adev))) 22983af76f23SRex Zhu 22993af76f23SRex Zhu #define amdgpu_dpm_set_fan_control_mode(adev, m) \ 23004b5ece24SEric Huang ((adev)->pp_enabled ? \ 23013af76f23SRex Zhu (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ 23024b5ece24SEric Huang (adev)->pm.funcs->set_fan_control_mode((adev), (m))) 23033af76f23SRex Zhu 23043af76f23SRex Zhu #define amdgpu_dpm_get_fan_control_mode(adev) \ 23054b5ece24SEric Huang ((adev)->pp_enabled ? \ 23063af76f23SRex Zhu (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ 23074b5ece24SEric Huang (adev)->pm.funcs->get_fan_control_mode((adev))) 23083af76f23SRex Zhu 23093af76f23SRex Zhu #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ 23104b5ece24SEric Huang ((adev)->pp_enabled ? \ 23113af76f23SRex Zhu (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 23124b5ece24SEric Huang (adev)->pm.funcs->set_fan_speed_percent((adev), (s))) 23133af76f23SRex Zhu 23143af76f23SRex Zhu #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ 23154b5ece24SEric Huang ((adev)->pp_enabled ? \ 23163af76f23SRex Zhu (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 23174b5ece24SEric Huang (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) 231897b2e202SAlex Deucher 23191b5708ffSRex Zhu #define amdgpu_dpm_get_sclk(adev, l) \ 23204b5ece24SEric Huang ((adev)->pp_enabled ? \ 23211b5708ffSRex Zhu (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ 23224b5ece24SEric Huang (adev)->pm.funcs->get_sclk((adev), (l))) 23231b5708ffSRex Zhu 23241b5708ffSRex Zhu #define amdgpu_dpm_get_mclk(adev, l) \ 23254b5ece24SEric Huang ((adev)->pp_enabled ? \ 23261b5708ffSRex Zhu (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ 23274b5ece24SEric Huang (adev)->pm.funcs->get_mclk((adev), (l))) 23281b5708ffSRex Zhu 23291b5708ffSRex Zhu 23301b5708ffSRex Zhu #define amdgpu_dpm_force_performance_level(adev, l) \ 23314b5ece24SEric Huang ((adev)->pp_enabled ? \ 23321b5708ffSRex Zhu (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ 23334b5ece24SEric Huang (adev)->pm.funcs->force_performance_level((adev), (l))) 23341b5708ffSRex Zhu 23351b5708ffSRex Zhu #define amdgpu_dpm_powergate_uvd(adev, g) \ 23364b5ece24SEric Huang ((adev)->pp_enabled ? \ 23371b5708ffSRex Zhu (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ 23384b5ece24SEric Huang (adev)->pm.funcs->powergate_uvd((adev), (g))) 23391b5708ffSRex Zhu 23401b5708ffSRex Zhu #define amdgpu_dpm_powergate_vce(adev, g) \ 23414b5ece24SEric Huang ((adev)->pp_enabled ? \ 23421b5708ffSRex Zhu (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ 23434b5ece24SEric Huang (adev)->pm.funcs->powergate_vce((adev), (g))) 23441b5708ffSRex Zhu 23451b5708ffSRex Zhu #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \ 23464b5ece24SEric Huang ((adev)->pp_enabled ? \ 23471b5708ffSRex Zhu (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \ 23484b5ece24SEric Huang (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))) 23491b5708ffSRex Zhu 23501b5708ffSRex Zhu #define amdgpu_dpm_get_current_power_state(adev) \ 23511b5708ffSRex Zhu (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) 23521b5708ffSRex Zhu 23531b5708ffSRex Zhu #define amdgpu_dpm_get_performance_level(adev) \ 23541b5708ffSRex Zhu (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) 23551b5708ffSRex Zhu 2356f3898ea1SEric Huang #define amdgpu_dpm_get_pp_num_states(adev, data) \ 2357f3898ea1SEric Huang (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data) 2358f3898ea1SEric Huang 2359f3898ea1SEric Huang #define amdgpu_dpm_get_pp_table(adev, table) \ 2360f3898ea1SEric Huang (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table) 2361f3898ea1SEric Huang 2362f3898ea1SEric Huang #define amdgpu_dpm_set_pp_table(adev, buf, size) \ 2363f3898ea1SEric Huang (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size) 2364f3898ea1SEric Huang 2365f3898ea1SEric Huang #define amdgpu_dpm_print_clock_levels(adev, type, buf) \ 2366f3898ea1SEric Huang (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf) 2367f3898ea1SEric Huang 2368f3898ea1SEric Huang #define amdgpu_dpm_force_clock_level(adev, type, level) \ 2369f3898ea1SEric Huang (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level) 2370f3898ea1SEric Huang 2371428bafa8SEric Huang #define amdgpu_dpm_get_sclk_od(adev) \ 2372428bafa8SEric Huang (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle) 2373428bafa8SEric Huang 2374428bafa8SEric Huang #define amdgpu_dpm_set_sclk_od(adev, value) \ 2375428bafa8SEric Huang (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value) 2376428bafa8SEric Huang 2377f2bdc05fSEric Huang #define amdgpu_dpm_get_mclk_od(adev) \ 2378f2bdc05fSEric Huang ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle)) 2379f2bdc05fSEric Huang 2380f2bdc05fSEric Huang #define amdgpu_dpm_set_mclk_od(adev, value) \ 2381f2bdc05fSEric Huang ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value)) 2382f2bdc05fSEric Huang 23831b5708ffSRex Zhu #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ 23841b5708ffSRex Zhu (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) 238597b2e202SAlex Deucher 238697b2e202SAlex Deucher #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 238797b2e202SAlex Deucher 238897b2e202SAlex Deucher /* Common functions */ 238997b2e202SAlex Deucher int amdgpu_gpu_reset(struct amdgpu_device *adev); 239097b2e202SAlex Deucher void amdgpu_pci_config_reset(struct amdgpu_device *adev); 239197b2e202SAlex Deucher bool amdgpu_card_posted(struct amdgpu_device *adev); 239297b2e202SAlex Deucher void amdgpu_update_display_priority(struct amdgpu_device *adev); 2393d5fc5e82SChunming Zhou 239497b2e202SAlex Deucher int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 239597b2e202SAlex Deucher int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 239697b2e202SAlex Deucher u32 ip_instance, u32 ring, 239797b2e202SAlex Deucher struct amdgpu_ring **out_ring); 239897b2e202SAlex Deucher void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 239997b2e202SAlex Deucher bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 24002f568dbdSChristian König int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 240197b2e202SAlex Deucher int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 240297b2e202SAlex Deucher uint32_t flags); 240397b2e202SAlex Deucher bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2404cc325d19SChristian König struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 2405d7006964SChristian König bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 2406d7006964SChristian König unsigned long end); 24072f568dbdSChristian König bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 24082f568dbdSChristian König int *last_invalidated); 240997b2e202SAlex Deucher bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 241097b2e202SAlex Deucher uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 241197b2e202SAlex Deucher struct ttm_mem_reg *mem); 241297b2e202SAlex Deucher void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 241397b2e202SAlex Deucher void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 241497b2e202SAlex Deucher void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 241597b2e202SAlex Deucher void amdgpu_program_register_sequence(struct amdgpu_device *adev, 241697b2e202SAlex Deucher const u32 *registers, 241797b2e202SAlex Deucher const u32 array_size); 241897b2e202SAlex Deucher 241997b2e202SAlex Deucher bool amdgpu_device_is_px(struct drm_device *dev); 242097b2e202SAlex Deucher /* atpx handler */ 242197b2e202SAlex Deucher #if defined(CONFIG_VGA_SWITCHEROO) 242297b2e202SAlex Deucher void amdgpu_register_atpx_handler(void); 242397b2e202SAlex Deucher void amdgpu_unregister_atpx_handler(void); 2424a78fe133SAlex Deucher bool amdgpu_has_atpx_dgpu_power_cntl(void); 24252f5af82eSAlex Deucher bool amdgpu_is_atpx_hybrid(void); 242697b2e202SAlex Deucher #else 242797b2e202SAlex Deucher static inline void amdgpu_register_atpx_handler(void) {} 242897b2e202SAlex Deucher static inline void amdgpu_unregister_atpx_handler(void) {} 2429a78fe133SAlex Deucher static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 24302f5af82eSAlex Deucher static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 243197b2e202SAlex Deucher #endif 243297b2e202SAlex Deucher 243397b2e202SAlex Deucher /* 243497b2e202SAlex Deucher * KMS 243597b2e202SAlex Deucher */ 243697b2e202SAlex Deucher extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2437f498d9edSNils Wallménius extern const int amdgpu_max_kms_ioctl; 243897b2e202SAlex Deucher 243997b2e202SAlex Deucher int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 244097b2e202SAlex Deucher int amdgpu_driver_unload_kms(struct drm_device *dev); 244197b2e202SAlex Deucher void amdgpu_driver_lastclose_kms(struct drm_device *dev); 244297b2e202SAlex Deucher int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 244397b2e202SAlex Deucher void amdgpu_driver_postclose_kms(struct drm_device *dev, 244497b2e202SAlex Deucher struct drm_file *file_priv); 244597b2e202SAlex Deucher void amdgpu_driver_preclose_kms(struct drm_device *dev, 244697b2e202SAlex Deucher struct drm_file *file_priv); 244797b2e202SAlex Deucher int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 244897b2e202SAlex Deucher int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 244988e72717SThierry Reding u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 245088e72717SThierry Reding int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 245188e72717SThierry Reding void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 245288e72717SThierry Reding int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 245397b2e202SAlex Deucher int *max_error, 245497b2e202SAlex Deucher struct timeval *vblank_time, 245597b2e202SAlex Deucher unsigned flags); 245697b2e202SAlex Deucher long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 245797b2e202SAlex Deucher unsigned long arg); 245897b2e202SAlex Deucher 245997b2e202SAlex Deucher /* 246097b2e202SAlex Deucher * functions used by amdgpu_encoder.c 246197b2e202SAlex Deucher */ 246297b2e202SAlex Deucher struct amdgpu_afmt_acr { 246397b2e202SAlex Deucher u32 clock; 246497b2e202SAlex Deucher 246597b2e202SAlex Deucher int n_32khz; 246697b2e202SAlex Deucher int cts_32khz; 246797b2e202SAlex Deucher 246897b2e202SAlex Deucher int n_44_1khz; 246997b2e202SAlex Deucher int cts_44_1khz; 247097b2e202SAlex Deucher 247197b2e202SAlex Deucher int n_48khz; 247297b2e202SAlex Deucher int cts_48khz; 247397b2e202SAlex Deucher 247497b2e202SAlex Deucher }; 247597b2e202SAlex Deucher 247697b2e202SAlex Deucher struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 247797b2e202SAlex Deucher 247897b2e202SAlex Deucher /* amdgpu_acpi.c */ 247997b2e202SAlex Deucher #if defined(CONFIG_ACPI) 248097b2e202SAlex Deucher int amdgpu_acpi_init(struct amdgpu_device *adev); 248197b2e202SAlex Deucher void amdgpu_acpi_fini(struct amdgpu_device *adev); 248297b2e202SAlex Deucher bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 248397b2e202SAlex Deucher int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 248497b2e202SAlex Deucher u8 perf_req, bool advertise); 248597b2e202SAlex Deucher int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 248697b2e202SAlex Deucher #else 248797b2e202SAlex Deucher static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 248897b2e202SAlex Deucher static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 248997b2e202SAlex Deucher #endif 249097b2e202SAlex Deucher 249197b2e202SAlex Deucher struct amdgpu_bo_va_mapping * 249297b2e202SAlex Deucher amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 249397b2e202SAlex Deucher uint64_t addr, struct amdgpu_bo **bo); 249497b2e202SAlex Deucher 249597b2e202SAlex Deucher #include "amdgpu_object.h" 249697b2e202SAlex Deucher #endif 2497