197b2e202SAlex Deucher /* 297b2e202SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 397b2e202SAlex Deucher * Copyright 2008 Red Hat Inc. 497b2e202SAlex Deucher * Copyright 2009 Jerome Glisse. 597b2e202SAlex Deucher * 697b2e202SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 797b2e202SAlex Deucher * copy of this software and associated documentation files (the "Software"), 897b2e202SAlex Deucher * to deal in the Software without restriction, including without limitation 997b2e202SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1097b2e202SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1197b2e202SAlex Deucher * Software is furnished to do so, subject to the following conditions: 1297b2e202SAlex Deucher * 1397b2e202SAlex Deucher * The above copyright notice and this permission notice shall be included in 1497b2e202SAlex Deucher * all copies or substantial portions of the Software. 1597b2e202SAlex Deucher * 1697b2e202SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1797b2e202SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1897b2e202SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1997b2e202SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2097b2e202SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2197b2e202SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2297b2e202SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2397b2e202SAlex Deucher * 2497b2e202SAlex Deucher * Authors: Dave Airlie 2597b2e202SAlex Deucher * Alex Deucher 2697b2e202SAlex Deucher * Jerome Glisse 2797b2e202SAlex Deucher */ 2897b2e202SAlex Deucher #ifndef __AMDGPU_H__ 2997b2e202SAlex Deucher #define __AMDGPU_H__ 3097b2e202SAlex Deucher 31d57229b1SAurabindo Pillai #ifdef pr_fmt 32d57229b1SAurabindo Pillai #undef pr_fmt 33d57229b1SAurabindo Pillai #endif 34d57229b1SAurabindo Pillai 35d57229b1SAurabindo Pillai #define pr_fmt(fmt) "amdgpu: " fmt 36d57229b1SAurabindo Pillai 37539489fcSAurabindo Pillai #ifdef dev_fmt 38539489fcSAurabindo Pillai #undef dev_fmt 39539489fcSAurabindo Pillai #endif 40539489fcSAurabindo Pillai 41539489fcSAurabindo Pillai #define dev_fmt(fmt) "amdgpu: " fmt 42539489fcSAurabindo Pillai 438290268fSChristian König #include "amdgpu_ctx.h" 448290268fSChristian König 4597b2e202SAlex Deucher #include <linux/atomic.h> 4697b2e202SAlex Deucher #include <linux/wait.h> 4797b2e202SAlex Deucher #include <linux/list.h> 4897b2e202SAlex Deucher #include <linux/kref.h> 49a9f87f64SChristian König #include <linux/rbtree.h> 5097b2e202SAlex Deucher #include <linux/hashtable.h> 51f54d1867SChris Wilson #include <linux/dma-fence.h> 52c9a6b82fSAndrey Grodzovsky #include <linux/pci.h> 53c9a6b82fSAndrey Grodzovsky #include <linux/aer.h> 5497b2e202SAlex Deucher 55248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_bo_api.h> 56248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_bo_driver.h> 57248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_placement.h> 58248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_execbuf_util.h> 5997b2e202SAlex Deucher 607e5a547fSChunming Zhou #include <drm/amdgpu_drm.h> 61f867723bSSam Ravnborg #include <drm/drm_gem.h> 62f867723bSSam Ravnborg #include <drm/drm_ioctl.h> 6397b2e202SAlex Deucher 6478c16834SAndres Rodriguez #include <kgd_kfd_interface.h> 65c79563a3SRex Zhu #include "dm_pp_interface.h" 66c79563a3SRex Zhu #include "kgd_pp_interface.h" 6778c16834SAndres Rodriguez 685fc3aeebSyanyang1 #include "amd_shared.h" 6997b2e202SAlex Deucher #include "amdgpu_mode.h" 7097b2e202SAlex Deucher #include "amdgpu_ih.h" 7197b2e202SAlex Deucher #include "amdgpu_irq.h" 7297b2e202SAlex Deucher #include "amdgpu_ucode.h" 73c632d799SFlora Cui #include "amdgpu_ttm.h" 740e5ca0d1SHuang Rui #include "amdgpu_psp.h" 7597b2e202SAlex Deucher #include "amdgpu_gds.h" 7656113504SChristian König #include "amdgpu_sync.h" 7778023016SChristian König #include "amdgpu_ring.h" 78073440d2SChristian König #include "amdgpu_vm.h" 79cf097881SAlex Deucher #include "amdgpu_dpm.h" 80a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h" 814df654d2SLeo Liu #include "amdgpu_uvd.h" 825e568178SLeo Liu #include "amdgpu_vce.h" 8395aa13f6SLeo Liu #include "amdgpu_vcn.h" 8488a1c40aSLeo Liu #include "amdgpu_jpeg.h" 859a189996SChristian König #include "amdgpu_mn.h" 86770d13b1SChristian König #include "amdgpu_gmc.h" 87448fe192SHuang Rui #include "amdgpu_gfx.h" 88bb7743bcSHuang Rui #include "amdgpu_sdma.h" 891b491330SLikun Gao #include "amdgpu_lsdma.h" 90bebc0762SHawking Zhang #include "amdgpu_nbio.h" 91455d40c9SLikun Gao #include "amdgpu_hdp.h" 924562236bSHarry Wentland #include "amdgpu_dm.h" 93ceeb50edSMonk Liu #include "amdgpu_virt.h" 947946340fSRex Zhu #include "amdgpu_csa.h" 952bc956efSJack Xiao #include "amdgpu_mes_ctx.h" 963490bdb5SChristian König #include "amdgpu_gart.h" 9775758255SAlex Deucher #include "amdgpu_debugfs.h" 98050d9d43SChristian König #include "amdgpu_job.h" 994a8c21a1SChristian König #include "amdgpu_bo_list.h" 1002cddc50eSHuang Rui #include "amdgpu_gem.h" 101cde577bdSOak Zeng #include "amdgpu_doorbell.h" 102611736d8SFelix Kuehling #include "amdgpu_amdkfd.h" 103f39f5bb1SXiaojie Yuan #include "amdgpu_discovery.h" 104a538bbe7SJack Xiao #include "amdgpu_mes.h" 1059e585a52SHawking Zhang #include "amdgpu_umc.h" 1063d093da0STao Zhou #include "amdgpu_mmhub.h" 1078ffff9b4SOak Zeng #include "amdgpu_gfxhub.h" 108bdf84a80SJoseph Greathouse #include "amdgpu_df.h" 109293f2563SHawking Zhang #include "amdgpu_smuio.h" 11087444254SRoy Sun #include "amdgpu_fdinfo.h" 1113907c492SJohn Clements #include "amdgpu_mca.h" 1127cab2124Syipechai #include "amdgpu_ras.h" 113c79563a3SRex Zhu 11462d73fbcSEvan Quan #define MAX_GPU_INSTANCE 16 11562d73fbcSEvan Quan 11662d73fbcSEvan Quan struct amdgpu_gpu_instance 11762d73fbcSEvan Quan { 11862d73fbcSEvan Quan struct amdgpu_device *adev; 11962d73fbcSEvan Quan int mgpu_fan_enabled; 12062d73fbcSEvan Quan }; 12162d73fbcSEvan Quan 12262d73fbcSEvan Quan struct amdgpu_mgpu_info 12362d73fbcSEvan Quan { 12462d73fbcSEvan Quan struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 12562d73fbcSEvan Quan struct mutex mutex; 12662d73fbcSEvan Quan uint32_t num_gpu; 12762d73fbcSEvan Quan uint32_t num_dgpu; 12862d73fbcSEvan Quan uint32_t num_apu; 129e3c1b071Sshaoyunl 130e3c1b071Sshaoyunl /* delayed reset_func for XGMI configuration if necessary */ 131e3c1b071Sshaoyunl struct delayed_work delayed_reset_work; 132e3c1b071Sshaoyunl bool pending_reset; 13362d73fbcSEvan Quan }; 13462d73fbcSEvan Quan 1353fa8f89dSSathishkumar S enum amdgpu_ss { 1363fa8f89dSSathishkumar S AMDGPU_SS_DRV_LOAD, 1373fa8f89dSSathishkumar S AMDGPU_SS_DEV_D0, 1383fa8f89dSSathishkumar S AMDGPU_SS_DEV_D3, 1393fa8f89dSSathishkumar S AMDGPU_SS_DRV_UNLOAD 1403fa8f89dSSathishkumar S }; 1413fa8f89dSSathishkumar S 14288f8575bSDennis Li struct amdgpu_watchdog_timer 14388f8575bSDennis Li { 14488f8575bSDennis Li bool timeout_fatal_disable; 14588f8575bSDennis Li uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 146b80d8475SAlex Deucher }; 14797b2e202SAlex Deucher 148f440ff44SWambui Karuga #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 14971f98027SAlex Deucher 15097b2e202SAlex Deucher /* 15197b2e202SAlex Deucher * Modules parameters. 15297b2e202SAlex Deucher */ 15397b2e202SAlex Deucher extern int amdgpu_modeset; 15497b2e202SAlex Deucher extern int amdgpu_vram_limit; 155218b5dcdSJohn Brooks extern int amdgpu_vis_vram_limit; 15683e74db6SAlex Deucher extern int amdgpu_gart_size; 15736d38372SChristian König extern int amdgpu_gtt_size; 15895844d20SMarek Olšák extern int amdgpu_moverate; 15997b2e202SAlex Deucher extern int amdgpu_audio; 16097b2e202SAlex Deucher extern int amdgpu_disp_priority; 16197b2e202SAlex Deucher extern int amdgpu_hw_i2c; 16297b2e202SAlex Deucher extern int amdgpu_pcie_gen2; 16397b2e202SAlex Deucher extern int amdgpu_msi; 164f440ff44SWambui Karuga extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 16597b2e202SAlex Deucher extern int amdgpu_dpm; 166e635ee07SHuang Rui extern int amdgpu_fw_load_type; 16797b2e202SAlex Deucher extern int amdgpu_aspm; 16897b2e202SAlex Deucher extern int amdgpu_runtime_pm; 1690b693f0bSRex Zhu extern uint amdgpu_ip_block_mask; 17097b2e202SAlex Deucher extern int amdgpu_bapm; 17197b2e202SAlex Deucher extern int amdgpu_deep_color; 17297b2e202SAlex Deucher extern int amdgpu_vm_size; 17397b2e202SAlex Deucher extern int amdgpu_vm_block_size; 174d07f14beSRoger He extern int amdgpu_vm_fragment_size; 175d9c13156SChristian König extern int amdgpu_vm_fault_stop; 176b495bd3aSChristian König extern int amdgpu_vm_debug; 1779a4b7d4cSHarish Kasiviswanathan extern int amdgpu_vm_update_mode; 1787e0ff20cSWambui Karuga extern int amdgpu_exp_hw_support; 1794562236bSHarry Wentland extern int amdgpu_dc; 1801333f723SJammy Zhou extern int amdgpu_sched_jobs; 1814afcb303SJammy Zhou extern int amdgpu_sched_hw_submission; 1820b693f0bSRex Zhu extern uint amdgpu_pcie_gen_cap; 1830b693f0bSRex Zhu extern uint amdgpu_pcie_lane_cap; 18425faeddcSEvan Quan extern u64 amdgpu_cg_mask; 1850b693f0bSRex Zhu extern uint amdgpu_pg_mask; 1860b693f0bSRex Zhu extern uint amdgpu_sdma_phase_quantum; 1876f8941a2SNicolai Hähnle extern char *amdgpu_disable_cu; 1889accf2fdSEmily Deng extern char *amdgpu_virtual_display; 1890b693f0bSRex Zhu extern uint amdgpu_pp_feature_mask; 190367039bfSTianci.Yin extern uint amdgpu_force_long_training; 19165781c78SMonk Liu extern int amdgpu_job_hang_limit; 192e8835e0eSHawking Zhang extern int amdgpu_lbpw; 1934a75aefeSAndres Rodriguez extern int amdgpu_compute_multipipe; 194dcebf026SAndrey Grodzovsky extern int amdgpu_gpu_recovery; 195bfca0289SShaoyun Liu extern int amdgpu_emu_mode; 1967951e376SRex Zhu extern uint amdgpu_smu_memory_pool_size; 1978738a82bSLijo Lazar extern int amdgpu_smu_pptable_id; 1987875a226SAlex Deucher extern uint amdgpu_dc_feature_mask; 1998a791dabSHarry Wentland extern uint amdgpu_dc_debug_mask; 200792a0cddSLeo Li extern uint amdgpu_dc_visual_confirm; 201ad4de27fSNicholas Kazlauskas extern uint amdgpu_dm_abm_level; 2027a46f05eSTakashi Iwai extern int amdgpu_backlight; 20362d73fbcSEvan Quan extern struct amdgpu_mgpu_info mgpu_info; 2041218252fSxinhui pan extern int amdgpu_ras_enable; 2051218252fSxinhui pan extern uint amdgpu_ras_mask; 206acc0204cSGuchun Chen extern int amdgpu_bad_page_threshold; 20768daadf3SKent Russell extern bool amdgpu_ignore_bad_page_threshold; 20888f8575bSDennis Li extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 20951bcce46SHawking Zhang extern int amdgpu_async_gfx_ring; 210b239c017SJack Xiao extern int amdgpu_mcbp; 211a190d1c7SXiaojie Yuan extern int amdgpu_discovery; 21238487284SJack Xiao extern int amdgpu_mes; 213928fe236SJack Xiao extern int amdgpu_mes_kiq; 21475ee6487SFelix Kuehling extern int amdgpu_noretry; 2154e66d7d2SYong Zhao extern int amdgpu_force_asic_type; 21630d95a37SSathishkumar S extern int amdgpu_smartshift_bias; 217158a05a0SAlex Sierra extern int amdgpu_use_xgmi_p2p; 2188c9f69bcSShirish S #ifdef CONFIG_HSA_AMD 219aa978594SHuang Rui extern int sched_policy; 220b2057956SFelix Kuehling extern bool debug_evictions; 221b80f050fSPhilip Yang extern bool no_system_mem_limit; 222a35ad98bSShirish S #else 22302f40f82SLee Jones static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 22402f40f82SLee Jones static const bool __maybe_unused debug_evictions; /* = false */ 22502f40f82SLee Jones static const bool __maybe_unused no_system_mem_limit; 2268c9f69bcSShirish S #endif 22708a2fd23SRamesh Errabolu #ifdef CONFIG_HSA_AMD_P2P 22808a2fd23SRamesh Errabolu extern bool pcie_p2p; 22908a2fd23SRamesh Errabolu #endif 23097b2e202SAlex Deucher 231d7ccb38dSHuang Rui extern int amdgpu_tmz; 232273da6ffSWenhui Sheng extern int amdgpu_reset_method; 233d7ccb38dSHuang Rui 2346dd13096SFelix Kuehling #ifdef CONFIG_DRM_AMDGPU_SI 2356dd13096SFelix Kuehling extern int amdgpu_si_support; 2366dd13096SFelix Kuehling #endif 2377df28986SFelix Kuehling #ifdef CONFIG_DRM_AMDGPU_CIK 2387df28986SFelix Kuehling extern int amdgpu_cik_support; 2397df28986SFelix Kuehling #endif 240a300de40SMonk Liu extern int amdgpu_num_kcq; 24197b2e202SAlex Deucher 24211eb648dSRuijing Dong #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 24311eb648dSRuijing Dong extern int amdgpu_vcnfw_log; 24411eb648dSRuijing Dong 24508d1bdd4SRex Zhu #define AMDGPU_VM_MAX_NUM_CTX 4096 2466c8d74caSSamuel Li #define AMDGPU_SG_THRESHOLD (256*1024*1024) 24755ed8cafSChunming Zhou #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 2484b559c90SChunming Zhou #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 24997b2e202SAlex Deucher #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 2508c5e13ecSAndrey Grodzovsky #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 25197b2e202SAlex Deucher #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 25297b2e202SAlex Deucher #define AMDGPUFB_CONN_LIMIT 4 253a5bde2f9SAlex Deucher #define AMDGPU_BIOS_NUM_SCRATCH 16 25497b2e202SAlex Deucher 25581b54fb7SAlex Deucher #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 25681b54fb7SAlex Deucher 25797b2e202SAlex Deucher /* hard reset data */ 25897b2e202SAlex Deucher #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 25997b2e202SAlex Deucher 26097b2e202SAlex Deucher /* reset flags */ 26197b2e202SAlex Deucher #define AMDGPU_RESET_GFX (1 << 0) 26297b2e202SAlex Deucher #define AMDGPU_RESET_COMPUTE (1 << 1) 26397b2e202SAlex Deucher #define AMDGPU_RESET_DMA (1 << 2) 26497b2e202SAlex Deucher #define AMDGPU_RESET_CP (1 << 3) 26597b2e202SAlex Deucher #define AMDGPU_RESET_GRBM (1 << 4) 26697b2e202SAlex Deucher #define AMDGPU_RESET_DMA1 (1 << 5) 26797b2e202SAlex Deucher #define AMDGPU_RESET_RLC (1 << 6) 26897b2e202SAlex Deucher #define AMDGPU_RESET_SEM (1 << 7) 26997b2e202SAlex Deucher #define AMDGPU_RESET_IH (1 << 8) 27097b2e202SAlex Deucher #define AMDGPU_RESET_VMC (1 << 9) 27197b2e202SAlex Deucher #define AMDGPU_RESET_MC (1 << 10) 27297b2e202SAlex Deucher #define AMDGPU_RESET_DISPLAY (1 << 11) 27397b2e202SAlex Deucher #define AMDGPU_RESET_UVD (1 << 12) 27497b2e202SAlex Deucher #define AMDGPU_RESET_VCE (1 << 13) 27597b2e202SAlex Deucher #define AMDGPU_RESET_VCE1 (1 << 14) 27697b2e202SAlex Deucher 2775bd8d53fSVictor Zhao #define AMDGPU_RESET_LEVEL_SOFT_RECOVERY (1 << 0) 2785bd8d53fSVictor Zhao #define AMDGPU_RESET_LEVEL_MODE2 (1 << 1) 2795bd8d53fSVictor Zhao 28097b2e202SAlex Deucher /* max cursor sizes (in pixels) */ 28197b2e202SAlex Deucher #define CIK_CURSOR_WIDTH 128 28297b2e202SAlex Deucher #define CIK_CURSOR_HEIGHT 128 28397b2e202SAlex Deucher 284faf26f2bSpengfuyuan /* smart shift bias level limits */ 28530d95a37SSathishkumar S #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 28630d95a37SSathishkumar S #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 28730d95a37SSathishkumar S 28897b2e202SAlex Deucher struct amdgpu_device; 28997b2e202SAlex Deucher struct amdgpu_irq_src; 2900b492a4cSAlex Deucher struct amdgpu_fpriv; 2919cca0b8eSChristian König struct amdgpu_bo_va_mapping; 292992af942SJonathan Kim struct kfd_vm_fault_info; 293d95e8e97SDennis Li struct amdgpu_hive_info; 29404442bf7SLijo Lazar struct amdgpu_reset_context; 295e071dce3SLijo Lazar struct amdgpu_reset_control; 29697b2e202SAlex Deucher 29797b2e202SAlex Deucher enum amdgpu_cp_irq { 29853b2fe41SHawking Zhang AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 29953b2fe41SHawking Zhang AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 30097b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 30197b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 30297b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 30397b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 30497b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 30597b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 30697b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 30797b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 30897b2e202SAlex Deucher 30997b2e202SAlex Deucher AMDGPU_CP_IRQ_LAST 31097b2e202SAlex Deucher }; 31197b2e202SAlex Deucher 31297b2e202SAlex Deucher enum amdgpu_thermal_irq { 31397b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 31497b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 31597b2e202SAlex Deucher 31697b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LAST 31797b2e202SAlex Deucher }; 31897b2e202SAlex Deucher 3194e638ae9SXiangliang Yu enum amdgpu_kiq_irq { 3204e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 3214e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_LAST 3224e638ae9SXiangliang Yu }; 323373008bfSDusica Milinkovic #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 3243890d111SEmily Deng #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 3253890d111SEmily Deng #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 326006cc1a2SJiawei Gu #define MAX_KIQ_REG_TRY 1000 3273890d111SEmily Deng 32843fa561fSRex Zhu int amdgpu_device_ip_set_clockgating_state(void *dev, 3295fc3aeebSyanyang1 enum amd_ip_block_type block_type, 3305fc3aeebSyanyang1 enum amd_clockgating_state state); 33143fa561fSRex Zhu int amdgpu_device_ip_set_powergating_state(void *dev, 3325fc3aeebSyanyang1 enum amd_ip_block_type block_type, 3335fc3aeebSyanyang1 enum amd_powergating_state state); 3342990a1fcSAlex Deucher void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 33525faeddcSEvan Quan u64 *flags); 3362990a1fcSAlex Deucher int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 3375dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 3382990a1fcSAlex Deucher bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 3395dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 34097b2e202SAlex Deucher 341a1255107SAlex Deucher #define AMDGPU_MAX_IP_NUM 16 342a1255107SAlex Deucher 343a1255107SAlex Deucher struct amdgpu_ip_block_status { 344a1255107SAlex Deucher bool valid; 345a1255107SAlex Deucher bool sw; 346a1255107SAlex Deucher bool hw; 347a1255107SAlex Deucher bool late_initialized; 348a1255107SAlex Deucher bool hang; 349a1255107SAlex Deucher }; 350a1255107SAlex Deucher 35197b2e202SAlex Deucher struct amdgpu_ip_block_version { 352a1255107SAlex Deucher const enum amd_ip_block_type type; 353a1255107SAlex Deucher const u32 major; 354a1255107SAlex Deucher const u32 minor; 355a1255107SAlex Deucher const u32 rev; 3565fc3aeebSyanyang1 const struct amd_ip_funcs *funcs; 35797b2e202SAlex Deucher }; 35897b2e202SAlex Deucher 359efe4f000STianci.Yin #define HW_REV(_Major, _Minor, _Rev) \ 360efe4f000STianci.Yin ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 361efe4f000STianci.Yin 362a1255107SAlex Deucher struct amdgpu_ip_block { 363a1255107SAlex Deucher struct amdgpu_ip_block_status status; 364a1255107SAlex Deucher const struct amdgpu_ip_block_version *version; 365a1255107SAlex Deucher }; 366a1255107SAlex Deucher 3672990a1fcSAlex Deucher int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 3685fc3aeebSyanyang1 enum amd_ip_block_type type, 36997b2e202SAlex Deucher u32 major, u32 minor); 37097b2e202SAlex Deucher 3712990a1fcSAlex Deucher struct amdgpu_ip_block * 3722990a1fcSAlex Deucher amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 3735fc3aeebSyanyang1 enum amd_ip_block_type type); 37497b2e202SAlex Deucher 3752990a1fcSAlex Deucher int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 376a1255107SAlex Deucher const struct amdgpu_ip_block_version *ip_block_version); 377a1255107SAlex Deucher 37897b2e202SAlex Deucher /* 37997b2e202SAlex Deucher * BIOS. 38097b2e202SAlex Deucher */ 38197b2e202SAlex Deucher bool amdgpu_get_bios(struct amdgpu_device *adev); 38297b2e202SAlex Deucher bool amdgpu_read_bios(struct amdgpu_device *adev); 38304022982SHawking Zhang bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 38404022982SHawking Zhang u8 *bios, u32 length_bytes); 38597b2e202SAlex Deucher /* 38697b2e202SAlex Deucher * Clocks 38797b2e202SAlex Deucher */ 38897b2e202SAlex Deucher 38997b2e202SAlex Deucher #define AMDGPU_MAX_PPLL 3 39097b2e202SAlex Deucher 39197b2e202SAlex Deucher struct amdgpu_clock { 39297b2e202SAlex Deucher struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 39397b2e202SAlex Deucher struct amdgpu_pll spll; 39497b2e202SAlex Deucher struct amdgpu_pll mpll; 39597b2e202SAlex Deucher /* 10 Khz units */ 39697b2e202SAlex Deucher uint32_t default_mclk; 39797b2e202SAlex Deucher uint32_t default_sclk; 39897b2e202SAlex Deucher uint32_t default_dispclk; 39997b2e202SAlex Deucher uint32_t current_dispclk; 40097b2e202SAlex Deucher uint32_t dp_extclk; 40197b2e202SAlex Deucher uint32_t max_pixel_clock; 40297b2e202SAlex Deucher }; 40397b2e202SAlex Deucher 40497b2e202SAlex Deucher /* sub-allocation manager, it has to be protected by another lock. 40597b2e202SAlex Deucher * By conception this is an helper for other part of the driver 40697b2e202SAlex Deucher * like the indirect buffer or semaphore, which both have their 40797b2e202SAlex Deucher * locking. 40897b2e202SAlex Deucher * 40997b2e202SAlex Deucher * Principe is simple, we keep a list of sub allocation in offset 41097b2e202SAlex Deucher * order (first entry has offset == 0, last entry has the highest 41197b2e202SAlex Deucher * offset). 41297b2e202SAlex Deucher * 41397b2e202SAlex Deucher * When allocating new object we first check if there is room at 41497b2e202SAlex Deucher * the end total_size - (last_object_offset + last_object_size) >= 41597b2e202SAlex Deucher * alloc_size. If so we allocate new object there. 41697b2e202SAlex Deucher * 41797b2e202SAlex Deucher * When there is not enough room at the end, we start waiting for 41897b2e202SAlex Deucher * each sub object until we reach object_offset+object_size >= 41997b2e202SAlex Deucher * alloc_size, this object then become the sub object we return. 42097b2e202SAlex Deucher * 42197b2e202SAlex Deucher * Alignment can't be bigger than page size. 42297b2e202SAlex Deucher * 42397b2e202SAlex Deucher * Hole are not considered for allocation to keep things simple. 42497b2e202SAlex Deucher * Assumption is that there won't be hole (all object on same 42597b2e202SAlex Deucher * alignment). 42697b2e202SAlex Deucher */ 4276ba60b89SChristian König 4286ba60b89SChristian König #define AMDGPU_SA_NUM_FENCE_LISTS 32 4296ba60b89SChristian König 43097b2e202SAlex Deucher struct amdgpu_sa_manager { 43197b2e202SAlex Deucher wait_queue_head_t wq; 43297b2e202SAlex Deucher struct amdgpu_bo *bo; 43397b2e202SAlex Deucher struct list_head *hole; 4346ba60b89SChristian König struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 43597b2e202SAlex Deucher struct list_head olist; 43697b2e202SAlex Deucher unsigned size; 43797b2e202SAlex Deucher uint64_t gpu_addr; 43897b2e202SAlex Deucher void *cpu_ptr; 43997b2e202SAlex Deucher uint32_t domain; 44097b2e202SAlex Deucher uint32_t align; 44197b2e202SAlex Deucher }; 44297b2e202SAlex Deucher 44397b2e202SAlex Deucher /* sub-allocation buffer */ 44497b2e202SAlex Deucher struct amdgpu_sa_bo { 44597b2e202SAlex Deucher struct list_head olist; 44697b2e202SAlex Deucher struct list_head flist; 44797b2e202SAlex Deucher struct amdgpu_sa_manager *manager; 44897b2e202SAlex Deucher unsigned soffset; 44997b2e202SAlex Deucher unsigned eoffset; 450f54d1867SChris Wilson struct dma_fence *fence; 45197b2e202SAlex Deucher }; 45297b2e202SAlex Deucher 453d573de2dSRex Zhu int amdgpu_fence_slab_init(void); 454d573de2dSRex Zhu void amdgpu_fence_slab_fini(void); 45597b2e202SAlex Deucher 45697b2e202SAlex Deucher /* 45797b2e202SAlex Deucher * IRQS. 45897b2e202SAlex Deucher */ 45997b2e202SAlex Deucher 46097b2e202SAlex Deucher struct amdgpu_flip_work { 461325cbba1SMichel Dänzer struct delayed_work flip_work; 46297b2e202SAlex Deucher struct work_struct unpin_work; 46397b2e202SAlex Deucher struct amdgpu_device *adev; 46497b2e202SAlex Deucher int crtc_id; 465325cbba1SMichel Dänzer u32 target_vblank; 46697b2e202SAlex Deucher uint64_t base; 46797b2e202SAlex Deucher struct drm_pending_vblank_event *event; 468765e7fbfSChristian König struct amdgpu_bo *old_abo; 4691ffd2652SChristian König unsigned shared_count; 470f54d1867SChris Wilson struct dma_fence **shared; 471f54d1867SChris Wilson struct dma_fence_cb cb; 472cb9e59d7SAlex Deucher bool async; 47397b2e202SAlex Deucher }; 47497b2e202SAlex Deucher 47597b2e202SAlex Deucher 47697b2e202SAlex Deucher /* 47797b2e202SAlex Deucher * file private structure 47897b2e202SAlex Deucher */ 47997b2e202SAlex Deucher 48097b2e202SAlex Deucher struct amdgpu_fpriv { 48197b2e202SAlex Deucher struct amdgpu_vm vm; 482b85891bdSJunwei Zhang struct amdgpu_bo_va *prt_va; 4830f4b3c68SChristian König struct amdgpu_bo_va *csa_va; 48497b2e202SAlex Deucher struct mutex bo_list_lock; 48597b2e202SAlex Deucher struct idr bo_list_handles; 48697b2e202SAlex Deucher struct amdgpu_ctx_mgr ctx_mgr; 48797b2e202SAlex Deucher }; 48897b2e202SAlex Deucher 489021830d2SBas Nieuwenhuizen int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 490021830d2SBas Nieuwenhuizen 49197b2e202SAlex Deucher /* 49297b2e202SAlex Deucher * Writeback 49397b2e202SAlex Deucher */ 49454208194SYintian Tao #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 49597b2e202SAlex Deucher 49697b2e202SAlex Deucher struct amdgpu_wb { 49797b2e202SAlex Deucher struct amdgpu_bo *wb_obj; 49897b2e202SAlex Deucher volatile uint32_t *wb; 49997b2e202SAlex Deucher uint64_t gpu_addr; 50097b2e202SAlex Deucher u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 50197b2e202SAlex Deucher unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 50297b2e202SAlex Deucher }; 50397b2e202SAlex Deucher 504131b4b36SAlex Deucher int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 505131b4b36SAlex Deucher void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 50697b2e202SAlex Deucher 50797b2e202SAlex Deucher /* 50897b2e202SAlex Deucher * Benchmarking 50997b2e202SAlex Deucher */ 510e460f244SAlex Deucher int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 51197b2e202SAlex Deucher 51297b2e202SAlex Deucher /* 51397b2e202SAlex Deucher * ASIC specific register table accessible by UMD 51497b2e202SAlex Deucher */ 51597b2e202SAlex Deucher struct amdgpu_allowed_register_entry { 51697b2e202SAlex Deucher uint32_t reg_offset; 51797b2e202SAlex Deucher bool grbm_indexed; 51897b2e202SAlex Deucher }; 51997b2e202SAlex Deucher 5200cf3c64fSAlex Deucher enum amd_reset_method { 521e071dce3SLijo Lazar AMD_RESET_METHOD_NONE = -1, 5220cf3c64fSAlex Deucher AMD_RESET_METHOD_LEGACY = 0, 5230cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE0, 5240cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE1, 5250cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE2, 526af484df8SAlex Deucher AMD_RESET_METHOD_BACO, 527af484df8SAlex Deucher AMD_RESET_METHOD_PCI, 5280cf3c64fSAlex Deucher }; 5290cf3c64fSAlex Deucher 5309269bf18SAlex Deucher struct amdgpu_video_codec_info { 5319269bf18SAlex Deucher u32 codec_type; 5329269bf18SAlex Deucher u32 max_width; 5339269bf18SAlex Deucher u32 max_height; 5349269bf18SAlex Deucher u32 max_pixels_per_frame; 5359269bf18SAlex Deucher u32 max_level; 5369269bf18SAlex Deucher }; 5379269bf18SAlex Deucher 5389075096bSVeerabadhran Gopalakrishnan #define codec_info_build(type, width, height, level) \ 5399075096bSVeerabadhran Gopalakrishnan .codec_type = type,\ 5409075096bSVeerabadhran Gopalakrishnan .max_width = width,\ 5419075096bSVeerabadhran Gopalakrishnan .max_height = height,\ 5429075096bSVeerabadhran Gopalakrishnan .max_pixels_per_frame = height * width,\ 5439075096bSVeerabadhran Gopalakrishnan .max_level = level, 5449075096bSVeerabadhran Gopalakrishnan 5459269bf18SAlex Deucher struct amdgpu_video_codecs { 5469269bf18SAlex Deucher const u32 codec_count; 5479269bf18SAlex Deucher const struct amdgpu_video_codec_info *codec_array; 5489269bf18SAlex Deucher }; 5499269bf18SAlex Deucher 55097b2e202SAlex Deucher /* 55197b2e202SAlex Deucher * ASIC specific functions. 55297b2e202SAlex Deucher */ 55397b2e202SAlex Deucher struct amdgpu_asic_funcs { 55497b2e202SAlex Deucher bool (*read_disabled_bios)(struct amdgpu_device *adev); 5557946b878SAlex Deucher bool (*read_bios_from_rom)(struct amdgpu_device *adev, 5567946b878SAlex Deucher u8 *bios, u32 length_bytes); 55797b2e202SAlex Deucher int (*read_register)(struct amdgpu_device *adev, u32 se_num, 55897b2e202SAlex Deucher u32 sh_num, u32 reg_offset, u32 *value); 55997b2e202SAlex Deucher void (*set_vga_state)(struct amdgpu_device *adev, bool state); 56097b2e202SAlex Deucher int (*reset)(struct amdgpu_device *adev); 5610cf3c64fSAlex Deucher enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 56297b2e202SAlex Deucher /* get the reference clock */ 56397b2e202SAlex Deucher u32 (*get_xclk)(struct amdgpu_device *adev); 56497b2e202SAlex Deucher /* MM block clocks */ 56597b2e202SAlex Deucher int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 56697b2e202SAlex Deucher int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 567841686dfSMaruthi Bayyavarapu /* static power management */ 568841686dfSMaruthi Bayyavarapu int (*get_pcie_lanes)(struct amdgpu_device *adev); 569841686dfSMaruthi Bayyavarapu void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 570bbf282d8SAlex Deucher /* get config memsize register */ 571bbf282d8SAlex Deucher u32 (*get_config_memsize)(struct amdgpu_device *adev); 5722df1b8b6SAlex Deucher /* flush hdp write queue */ 57369882565SChristian König void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 5742df1b8b6SAlex Deucher /* invalidate hdp read cache */ 57569882565SChristian König void (*invalidate_hdp)(struct amdgpu_device *adev, 57669882565SChristian König struct amdgpu_ring *ring); 57769070690SAlex Deucher /* check if the asic needs a full reset of if soft reset will work */ 57869070690SAlex Deucher bool (*need_full_reset)(struct amdgpu_device *adev); 5795253163aSOak Zeng /* initialize doorbell layout for specific asic*/ 5805253163aSOak Zeng void (*init_doorbell_index)(struct amdgpu_device *adev); 581b45e18acSKent Russell /* PCIe bandwidth usage */ 582b45e18acSKent Russell void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 583b45e18acSKent Russell uint64_t *count1); 58444401889SAlex Deucher /* do we need to reset the asic at init time (e.g., kexec) */ 58544401889SAlex Deucher bool (*need_reset_on_init)(struct amdgpu_device *adev); 586dcea6e65SKent Russell /* PCIe replay counter */ 587dcea6e65SKent Russell uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 58869d5436dSAlex Deucher /* device supports BACO */ 58969d5436dSAlex Deucher bool (*supports_baco)(struct amdgpu_device *adev); 5909737a923SAlex Deucher /* pre asic_init quirks */ 5919737a923SAlex Deucher void (*pre_asic_init)(struct amdgpu_device *adev); 592f2b75bc2SEvan Quan /* enter/exit umd stable pstate */ 593f2b75bc2SEvan Quan int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 5949269bf18SAlex Deucher /* query video codecs */ 5959269bf18SAlex Deucher int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 5969269bf18SAlex Deucher const struct amdgpu_video_codecs **codecs); 59797b2e202SAlex Deucher }; 59897b2e202SAlex Deucher 59997b2e202SAlex Deucher /* 60097b2e202SAlex Deucher * IOCTL. 60197b2e202SAlex Deucher */ 60297b2e202SAlex Deucher int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 60397b2e202SAlex Deucher struct drm_file *filp); 60497b2e202SAlex Deucher 60597b2e202SAlex Deucher int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 6067ca24cf2SMarek Olšák int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 6077ca24cf2SMarek Olšák struct drm_file *filp); 60897b2e202SAlex Deucher int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 609eef18a82SJunwei Zhang int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 610eef18a82SJunwei Zhang struct drm_file *filp); 61197b2e202SAlex Deucher 61297b2e202SAlex Deucher /* VRAM scratch page for HDP bug, default vram page */ 61397b2e202SAlex Deucher struct amdgpu_vram_scratch { 61497b2e202SAlex Deucher struct amdgpu_bo *robj; 61597b2e202SAlex Deucher volatile uint32_t *ptr; 61697b2e202SAlex Deucher u64 gpu_addr; 61797b2e202SAlex Deucher }; 61897b2e202SAlex Deucher 61997b2e202SAlex Deucher /* 620d03846afSChunming Zhou * CGS 621d03846afSChunming Zhou */ 622110e6f26SDave Airlie struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 623110e6f26SDave Airlie void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 624a8fe58ceSMaruthi Bayyavarapu 625a8fe58ceSMaruthi Bayyavarapu /* 62697b2e202SAlex Deucher * Core structure, functions and helpers. 62797b2e202SAlex Deucher */ 62897b2e202SAlex Deucher typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 62997b2e202SAlex Deucher typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 63097b2e202SAlex Deucher 6314fa1c6a6STao Zhou typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 6324fa1c6a6STao Zhou typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 6334fa1c6a6STao Zhou 63497b2e202SAlex Deucher typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 63597b2e202SAlex Deucher typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 63697b2e202SAlex Deucher 63788807dc8SOak Zeng struct amdgpu_mmio_remap { 63888807dc8SOak Zeng u32 reg_offset; 63988807dc8SOak Zeng resource_size_t bus_addr; 64088807dc8SOak Zeng }; 64188807dc8SOak Zeng 6424522824cSShaoyun Liu /* Define the HW IP blocks will be used in driver , add more if necessary */ 6434522824cSShaoyun Liu enum amd_hw_ip_block_type { 6444522824cSShaoyun Liu GC_HWIP = 1, 6454522824cSShaoyun Liu HDP_HWIP, 6464522824cSShaoyun Liu SDMA0_HWIP, 6474522824cSShaoyun Liu SDMA1_HWIP, 648fa5d2e6fSLe Ma SDMA2_HWIP, 649fa5d2e6fSLe Ma SDMA3_HWIP, 650fa5d2e6fSLe Ma SDMA4_HWIP, 651fa5d2e6fSLe Ma SDMA5_HWIP, 652fa5d2e6fSLe Ma SDMA6_HWIP, 653fa5d2e6fSLe Ma SDMA7_HWIP, 6541b491330SLikun Gao LSDMA_HWIP, 6554522824cSShaoyun Liu MMHUB_HWIP, 6564522824cSShaoyun Liu ATHUB_HWIP, 6574522824cSShaoyun Liu NBIO_HWIP, 6584522824cSShaoyun Liu MP0_HWIP, 659e6636ae1SEvan Quan MP1_HWIP, 6604522824cSShaoyun Liu UVD_HWIP, 6614522824cSShaoyun Liu VCN_HWIP = UVD_HWIP, 66288a1c40aSLeo Liu JPEG_HWIP = VCN_HWIP, 6635eceb201SAlex Deucher VCN1_HWIP, 6644522824cSShaoyun Liu VCE_HWIP, 6654522824cSShaoyun Liu DF_HWIP, 6664522824cSShaoyun Liu DCE_HWIP, 6674522824cSShaoyun Liu OSSSYS_HWIP, 6684522824cSShaoyun Liu SMUIO_HWIP, 6694522824cSShaoyun Liu PWR_HWIP, 6704522824cSShaoyun Liu NBIF_HWIP, 671e6636ae1SEvan Quan THM_HWIP, 67273b19174SRex Zhu CLK_HWIP, 6736501a771SHawking Zhang UMC_HWIP, 6746501a771SHawking Zhang RSMU_HWIP, 6751534db55SAlex Deucher XGMI_HWIP, 6765f931489SAlex Deucher DCI_HWIP, 67762f8f5c3SEvan Quan PCIE_HWIP, 6784522824cSShaoyun Liu MAX_HWIP 6794522824cSShaoyun Liu }; 6804522824cSShaoyun Liu 681*7a94c860SHawking Zhang #define HWIP_MAX_INSTANCE 28 6824522824cSShaoyun Liu 6835f52e9a7SAlex Deucher #define HW_ID_MAX 300 6845f52e9a7SAlex Deucher #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 6851d5eee7dSLikun Gao #define IP_VERSION_MAJ(ver) ((ver) >> 16) 6861d5eee7dSLikun Gao #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF) 6871d5eee7dSLikun Gao #define IP_VERSION_REV(ver) ((ver) & 0xFF) 6885f52e9a7SAlex Deucher 68911dc9364SRex Zhu struct amd_powerplay { 69011dc9364SRex Zhu void *pp_handle; 69111dc9364SRex Zhu const struct amd_pm_funcs *pp_funcs; 69211dc9364SRex Zhu }; 69311dc9364SRex Zhu 694a6c40b17SLuben Tuikov struct ip_discovery_top; 695a6c40b17SLuben Tuikov 69673275181SEvan Quan /* polaris10 kickers */ 69773275181SEvan Quan #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 69873275181SEvan Quan ((rid == 0xE3) || \ 69973275181SEvan Quan (rid == 0xE4) || \ 70073275181SEvan Quan (rid == 0xE5) || \ 70173275181SEvan Quan (rid == 0xE7) || \ 70273275181SEvan Quan (rid == 0xEF))) || \ 70373275181SEvan Quan ((did == 0x6FDF) && \ 70473275181SEvan Quan ((rid == 0xE7) || \ 70573275181SEvan Quan (rid == 0xEF) || \ 70673275181SEvan Quan (rid == 0xFF)))) 70773275181SEvan Quan 70873275181SEvan Quan #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 70973275181SEvan Quan ((rid == 0xE1) || \ 71073275181SEvan Quan (rid == 0xF7))) 71173275181SEvan Quan 71273275181SEvan Quan /* polaris11 kickers */ 71373275181SEvan Quan #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 71473275181SEvan Quan ((rid == 0xE0) || \ 71573275181SEvan Quan (rid == 0xE5))) || \ 71673275181SEvan Quan ((did == 0x67FF) && \ 71773275181SEvan Quan ((rid == 0xCF) || \ 71873275181SEvan Quan (rid == 0xEF) || \ 71973275181SEvan Quan (rid == 0xFF)))) 72073275181SEvan Quan 72173275181SEvan Quan #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 72273275181SEvan Quan ((rid == 0xE2))) 72373275181SEvan Quan 72473275181SEvan Quan /* polaris12 kickers */ 72573275181SEvan Quan #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 72673275181SEvan Quan ((rid == 0xC0) || \ 72773275181SEvan Quan (rid == 0xC1) || \ 72873275181SEvan Quan (rid == 0xC3) || \ 72973275181SEvan Quan (rid == 0xC7))) || \ 73073275181SEvan Quan ((did == 0x6981) && \ 73173275181SEvan Quan ((rid == 0x00) || \ 73273275181SEvan Quan (rid == 0x01) || \ 73373275181SEvan Quan (rid == 0x10)))) 73473275181SEvan Quan 7355405a526SJack Xiao struct amdgpu_mqd_prop { 7365405a526SJack Xiao uint64_t mqd_gpu_addr; 7375405a526SJack Xiao uint64_t hqd_base_gpu_addr; 7385405a526SJack Xiao uint64_t rptr_gpu_addr; 7395405a526SJack Xiao uint64_t wptr_gpu_addr; 7405405a526SJack Xiao uint32_t queue_size; 7415405a526SJack Xiao bool use_doorbell; 7425405a526SJack Xiao uint32_t doorbell_index; 7435405a526SJack Xiao uint64_t eop_gpu_addr; 7445405a526SJack Xiao uint32_t hqd_pipe_priority; 7455405a526SJack Xiao uint32_t hqd_queue_priority; 7465405a526SJack Xiao bool hqd_active; 7475405a526SJack Xiao }; 7485405a526SJack Xiao 7495405a526SJack Xiao struct amdgpu_mqd { 7505405a526SJack Xiao unsigned mqd_size; 7515405a526SJack Xiao int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 7525405a526SJack Xiao struct amdgpu_mqd_prop *p); 7535405a526SJack Xiao }; 7545405a526SJack Xiao 7550c49e0b8SChunming Zhou #define AMDGPU_RESET_MAGIC_NUM 64 756e4cf4bf5SJonathan Kim #define AMDGPU_MAX_DF_PERFMONS 4 7576c92fe5fSKent Russell #define AMDGPU_PRODUCT_NAME_LEN 64 758cfbb6b00SAndrey Grodzovsky struct amdgpu_reset_domain; 759a4c63cafSAndrey Grodzovsky 76097b2e202SAlex Deucher struct amdgpu_device { 76197b2e202SAlex Deucher struct device *dev; 76297b2e202SAlex Deucher struct pci_dev *pdev; 7638aba21b7SLuben Tuikov struct drm_device ddev; 76497b2e202SAlex Deucher 765a8fe58ceSMaruthi Bayyavarapu #ifdef CONFIG_DRM_AMD_ACP 766a8fe58ceSMaruthi Bayyavarapu struct amdgpu_acp acp; 767a8fe58ceSMaruthi Bayyavarapu #endif 768d95e8e97SDennis Li struct amdgpu_hive_info *hive; 76997b2e202SAlex Deucher /* ASIC */ 7702f7d10b3SJammy Zhou enum amd_asic_type asic_type; 77197b2e202SAlex Deucher uint32_t family; 77297b2e202SAlex Deucher uint32_t rev_id; 77397b2e202SAlex Deucher uint32_t external_rev_id; 77497b2e202SAlex Deucher unsigned long flags; 77554f78a76SAlex Deucher unsigned long apu_flags; 77697b2e202SAlex Deucher int usec_timeout; 77797b2e202SAlex Deucher const struct amdgpu_asic_funcs *asic_funcs; 77897b2e202SAlex Deucher bool shutdown; 779fd5fd480SChunming Zhou bool need_swiotlb; 78097b2e202SAlex Deucher bool accel_working; 78197b2e202SAlex Deucher struct notifier_block acpi_nb; 78297b2e202SAlex Deucher struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 78398d28ac2SNirmoy Das struct debugfs_blob_wrapper debugfs_vbios_blob; 78481d1bf01SAlex Deucher struct debugfs_blob_wrapper debugfs_discovery_blob; 78597b2e202SAlex Deucher struct mutex srbm_mutex; 78697b2e202SAlex Deucher /* GRBM index mutex. Protects concurrent access to GRBM index */ 78797b2e202SAlex Deucher struct mutex grbm_idx_mutex; 78897b2e202SAlex Deucher struct dev_pm_domain vga_pm_domain; 78997b2e202SAlex Deucher bool have_disp_power_ref; 790bae17d2aSJack Xiao bool have_atomics_support; 79197b2e202SAlex Deucher 79297b2e202SAlex Deucher /* BIOS */ 7930cdd5005SAlex Deucher bool is_atom_fw; 79497b2e202SAlex Deucher uint8_t *bios; 795a9f5db9cSEvan Quan uint32_t bios_size; 796a5bde2f9SAlex Deucher uint32_t bios_scratch_reg_offset; 79797b2e202SAlex Deucher uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 79897b2e202SAlex Deucher 79997b2e202SAlex Deucher /* Register/doorbell mmio */ 80097b2e202SAlex Deucher resource_size_t rmmio_base; 80197b2e202SAlex Deucher resource_size_t rmmio_size; 80297b2e202SAlex Deucher void __iomem *rmmio; 80397b2e202SAlex Deucher /* protects concurrent MM_INDEX/DATA based register access */ 80497b2e202SAlex Deucher spinlock_t mmio_idx_lock; 80588807dc8SOak Zeng struct amdgpu_mmio_remap rmmio_remap; 80697b2e202SAlex Deucher /* protects concurrent SMC based register access */ 80797b2e202SAlex Deucher spinlock_t smc_idx_lock; 80897b2e202SAlex Deucher amdgpu_rreg_t smc_rreg; 80997b2e202SAlex Deucher amdgpu_wreg_t smc_wreg; 81097b2e202SAlex Deucher /* protects concurrent PCIE register access */ 81197b2e202SAlex Deucher spinlock_t pcie_idx_lock; 81297b2e202SAlex Deucher amdgpu_rreg_t pcie_rreg; 81397b2e202SAlex Deucher amdgpu_wreg_t pcie_wreg; 81436b9a952SHuang Rui amdgpu_rreg_t pciep_rreg; 81536b9a952SHuang Rui amdgpu_wreg_t pciep_wreg; 8164fa1c6a6STao Zhou amdgpu_rreg64_t pcie_rreg64; 8174fa1c6a6STao Zhou amdgpu_wreg64_t pcie_wreg64; 81897b2e202SAlex Deucher /* protects concurrent UVD register access */ 81997b2e202SAlex Deucher spinlock_t uvd_ctx_idx_lock; 82097b2e202SAlex Deucher amdgpu_rreg_t uvd_ctx_rreg; 82197b2e202SAlex Deucher amdgpu_wreg_t uvd_ctx_wreg; 82297b2e202SAlex Deucher /* protects concurrent DIDT register access */ 82397b2e202SAlex Deucher spinlock_t didt_idx_lock; 82497b2e202SAlex Deucher amdgpu_rreg_t didt_rreg; 82597b2e202SAlex Deucher amdgpu_wreg_t didt_wreg; 826ccdbb20aSRex Zhu /* protects concurrent gc_cac register access */ 827ccdbb20aSRex Zhu spinlock_t gc_cac_idx_lock; 828ccdbb20aSRex Zhu amdgpu_rreg_t gc_cac_rreg; 829ccdbb20aSRex Zhu amdgpu_wreg_t gc_cac_wreg; 83016abb5d2SEvan Quan /* protects concurrent se_cac register access */ 83116abb5d2SEvan Quan spinlock_t se_cac_idx_lock; 83216abb5d2SEvan Quan amdgpu_rreg_t se_cac_rreg; 83316abb5d2SEvan Quan amdgpu_wreg_t se_cac_wreg; 83497b2e202SAlex Deucher /* protects concurrent ENDPOINT (audio) register access */ 83597b2e202SAlex Deucher spinlock_t audio_endpt_idx_lock; 83697b2e202SAlex Deucher amdgpu_block_rreg_t audio_endpt_rreg; 83797b2e202SAlex Deucher amdgpu_block_wreg_t audio_endpt_wreg; 83897b2e202SAlex Deucher struct amdgpu_doorbell doorbell; 83997b2e202SAlex Deucher 84097b2e202SAlex Deucher /* clock/pll info */ 84197b2e202SAlex Deucher struct amdgpu_clock clock; 84297b2e202SAlex Deucher 84397b2e202SAlex Deucher /* MC */ 844770d13b1SChristian König struct amdgpu_gmc gmc; 84597b2e202SAlex Deucher struct amdgpu_gart gart; 84692e71b06SChristian König dma_addr_t dummy_page_addr; 84797b2e202SAlex Deucher struct amdgpu_vm_manager vm_manager; 848e60f8db5SAlex Xie struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 8491daa2bfaSLe Ma unsigned num_vmhubs; 85097b2e202SAlex Deucher 85197b2e202SAlex Deucher /* memory management */ 85297b2e202SAlex Deucher struct amdgpu_mman mman; 85397b2e202SAlex Deucher struct amdgpu_vram_scratch vram_scratch; 85497b2e202SAlex Deucher struct amdgpu_wb wb; 85597b2e202SAlex Deucher atomic64_t num_bytes_moved; 856dbd5ed60SChristian König atomic64_t num_evictions; 85768e2c5ffSMarek Olšák atomic64_t num_vram_cpu_page_faults; 858d94aed5aSMarek Olšák atomic_t gpu_reset_counter; 859f1892138SChunming Zhou atomic_t vram_lost_counter; 86097b2e202SAlex Deucher 86195844d20SMarek Olšák /* data for buffer migration throttling */ 86295844d20SMarek Olšák struct { 86395844d20SMarek Olšák spinlock_t lock; 86495844d20SMarek Olšák s64 last_update_us; 86595844d20SMarek Olšák s64 accum_us; /* accumulated microseconds */ 86600f06b24SJohn Brooks s64 accum_us_vis; /* for visible VRAM */ 86795844d20SMarek Olšák u32 log2_max_MBps; 86895844d20SMarek Olšák } mm_stats; 86995844d20SMarek Olšák 87097b2e202SAlex Deucher /* display */ 8719accf2fdSEmily Deng bool enable_virtual_display; 87284ec374bSRyan Taylor struct amdgpu_vkms_output *amdgpu_vkms_output; 87397b2e202SAlex Deucher struct amdgpu_mode_info mode_info; 8744562236bSHarry Wentland /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 87597b2e202SAlex Deucher struct work_struct hotplug_work; 87697b2e202SAlex Deucher struct amdgpu_irq_src crtc_irq; 87711f1a553SWayne Lin struct amdgpu_irq_src vline0_irq; 878d2574c33SMario Kleiner struct amdgpu_irq_src vupdate_irq; 87997b2e202SAlex Deucher struct amdgpu_irq_src pageflip_irq; 88097b2e202SAlex Deucher struct amdgpu_irq_src hpd_irq; 881c79fe9b4SLeo (Hanghong) Ma struct amdgpu_irq_src dmub_trace_irq; 882f066af88SJude Shih struct amdgpu_irq_src dmub_outbox_irq; 88397b2e202SAlex Deucher 88497b2e202SAlex Deucher /* rings */ 88576bf0db5SChristian König u64 fence_context; 88697b2e202SAlex Deucher unsigned num_rings; 88797b2e202SAlex Deucher struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 88868ce8b24SChristian König struct dma_fence __rcu *gang_submit; 88997b2e202SAlex Deucher bool ib_pool_ready; 8909ecefb19SChristian König struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 8911c6d567bSNirmoy Das struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 89297b2e202SAlex Deucher 89397b2e202SAlex Deucher /* interrupts */ 89497b2e202SAlex Deucher struct amdgpu_irq irq; 89597b2e202SAlex Deucher 8961f7371b2SAlex Deucher /* powerplay */ 8971f7371b2SAlex Deucher struct amd_powerplay powerplay; 89897b2e202SAlex Deucher struct amdgpu_pm pm; 89925faeddcSEvan Quan u64 cg_flags; 90097b2e202SAlex Deucher u32 pg_flags; 90197b2e202SAlex Deucher 902bebc0762SHawking Zhang /* nbio */ 903bebc0762SHawking Zhang struct amdgpu_nbio nbio; 904bebc0762SHawking Zhang 905b291a387SHawking Zhang /* hdp */ 906b291a387SHawking Zhang struct amdgpu_hdp hdp; 907b291a387SHawking Zhang 908293f2563SHawking Zhang /* smuio */ 909293f2563SHawking Zhang struct amdgpu_smuio smuio; 910293f2563SHawking Zhang 911d3a5a121STao Zhou /* mmhub */ 912d3a5a121STao Zhou struct amdgpu_mmhub mmhub; 913d3a5a121STao Zhou 9148ffff9b4SOak Zeng /* gfxhub */ 9158ffff9b4SOak Zeng struct amdgpu_gfxhub gfxhub; 9168ffff9b4SOak Zeng 91797b2e202SAlex Deucher /* gfx */ 91897b2e202SAlex Deucher struct amdgpu_gfx gfx; 91997b2e202SAlex Deucher 92097b2e202SAlex Deucher /* sdma */ 921c113ea1cSAlex Deucher struct amdgpu_sdma sdma; 92297b2e202SAlex Deucher 9231b491330SLikun Gao /* lsdma */ 9241b491330SLikun Gao struct amdgpu_lsdma lsdma; 9251b491330SLikun Gao 92697b2e202SAlex Deucher /* uvd */ 92797b2e202SAlex Deucher struct amdgpu_uvd uvd; 92897b2e202SAlex Deucher 92997b2e202SAlex Deucher /* vce */ 93097b2e202SAlex Deucher struct amdgpu_vce vce; 93195d0906fSLeo Liu 93295d0906fSLeo Liu /* vcn */ 93395d0906fSLeo Liu struct amdgpu_vcn vcn; 93497b2e202SAlex Deucher 93588a1c40aSLeo Liu /* jpeg */ 93688a1c40aSLeo Liu struct amdgpu_jpeg jpeg; 93788a1c40aSLeo Liu 93897b2e202SAlex Deucher /* firmwares */ 93997b2e202SAlex Deucher struct amdgpu_firmware firmware; 94097b2e202SAlex Deucher 9410e5ca0d1SHuang Rui /* PSP */ 9420e5ca0d1SHuang Rui struct psp_context psp; 9430e5ca0d1SHuang Rui 94497b2e202SAlex Deucher /* GDS */ 94597b2e202SAlex Deucher struct amdgpu_gds gds; 94697b2e202SAlex Deucher 947611736d8SFelix Kuehling /* KFD */ 948611736d8SFelix Kuehling struct amdgpu_kfd_dev kfd; 949611736d8SFelix Kuehling 950045c0216STao Zhou /* UMC */ 951045c0216STao Zhou struct amdgpu_umc umc; 952045c0216STao Zhou 9534562236bSHarry Wentland /* display related functionality */ 9544562236bSHarry Wentland struct amdgpu_display_manager dm; 9554562236bSHarry Wentland 956a538bbe7SJack Xiao /* mes */ 957a538bbe7SJack Xiao bool enable_mes; 958928fe236SJack Xiao bool enable_mes_kiq; 959a538bbe7SJack Xiao struct amdgpu_mes mes; 9605405a526SJack Xiao struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 961a538bbe7SJack Xiao 962bdf84a80SJoseph Greathouse /* df */ 963bdf84a80SJoseph Greathouse struct amdgpu_df df; 964bdf84a80SJoseph Greathouse 9653907c492SJohn Clements /* MCA */ 9663907c492SJohn Clements struct amdgpu_mca mca; 9673907c492SJohn Clements 968a1255107SAlex Deucher struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 96983a0b863SLikun GAO uint32_t harvest_ip_mask; 97097b2e202SAlex Deucher int num_ip_blocks; 97197b2e202SAlex Deucher struct mutex mn_lock; 97297b2e202SAlex Deucher DECLARE_HASHTABLE(mn_hash, 7); 97397b2e202SAlex Deucher 97497b2e202SAlex Deucher /* tracking pinned memory */ 975a5ccfe5cSMichel Dänzer atomic64_t vram_pin_size; 976a5ccfe5cSMichel Dänzer atomic64_t visible_pin_size; 977a5ccfe5cSMichel Dänzer atomic64_t gart_pin_size; 978130e0371SOded Gabbay 9794522824cSShaoyun Liu /* soc15 register offset based on ip, instance and segment */ 9804522824cSShaoyun Liu uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 9814522824cSShaoyun Liu 9822dc80b00SShirish S /* delayed work_func for deferring clockgating during resume */ 983beff74bcSAlex Deucher struct delayed_work delayed_init_work; 9842dc80b00SShirish S 9855a5099cbSXiangliang Yu struct amdgpu_virt virt; 9860c4e7fa5SChunming Zhou 9870c4e7fa5SChunming Zhou /* link all shadow bo */ 9880c4e7fa5SChunming Zhou struct list_head shadow_list; 9890c4e7fa5SChunming Zhou struct mutex shadow_list_lock; 9905c1354bdSChunming Zhou 991c836fec5SJim Qu /* record hw reset is performed */ 992c836fec5SJim Qu bool has_hw_reset; 9930c49e0b8SChunming Zhou u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 994c836fec5SJim Qu 99544779b43SRex Zhu /* s3/s4 mask */ 99644779b43SRex Zhu bool in_suspend; 99762498733SAlex Deucher bool in_s3; 99862498733SAlex Deucher bool in_s4; 99962498733SAlex Deucher bool in_s0ix; 1000b092b196SPrike Liang 1001a3a09142SAlex Deucher enum pp_mp1_state mp1_state; 1002409c5191SOak Zeng struct amdgpu_doorbell_index doorbell_index; 1003d4535e2cSAndrey Grodzovsky 100462914a99SJason Gunthorpe struct mutex notifier_lock; 100562914a99SJason Gunthorpe 100626bc5340SAndrey Grodzovsky int asic_reset_res; 1007d4535e2cSAndrey Grodzovsky struct work_struct xgmi_reset_work; 1008655ce9cbSshaoyunl struct list_head reset_list; 10099b638f97Sshaoyunl 1010912dfc84SEvan Quan long gfx_timeout; 1011912dfc84SEvan Quan long sdma_timeout; 1012912dfc84SEvan Quan long video_timeout; 1013912dfc84SEvan Quan long compute_timeout; 1014fb2dbfd2SKent Russell 1015fb2dbfd2SKent Russell uint64_t unique_id; 1016e4cf4bf5SJonathan Kim uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 10175c5b2ba0SEvan Quan 10186ae6c7d4SAlex Deucher /* enable runtime pm on the device */ 1019f0f7ddfcSAlex Deucher bool in_runpm; 1020b10c1c5bSAlex Deucher bool has_pr3; 10217c868b59SYintian Tao 10227c868b59SYintian Tao bool pm_sysfs_en; 10237c868b59SYintian Tao bool ucode_sysfs_en; 10248424f2ccSLikun Gao bool psp_sysfs_en; 1025bd607166SKent Russell 1026bd607166SKent Russell /* Chip product information */ 10271f83db6bSRoy Sun char product_number[20]; 10286c92fe5fSKent Russell char product_name[AMDGPU_PRODUCT_NAME_LEN]; 10298df1a28fSDan Carpenter char serial[20]; 1030728e7e0cSJiange Zhao 1031b265bdbdSEvan Quan atomic_t throttling_logging_enabled; 1032b265bdbdSEvan Quan struct ratelimit_state throttling_logging_rs; 10338ab0d6f0SLuben Tuikov uint32_t ras_hw_enabled; 10348ab0d6f0SLuben Tuikov uint32_t ras_enabled; 1035c1dd4aa6SAndrey Grodzovsky 10367afefb81SAndrey Grodzovsky bool no_hw_access; 1037c1dd4aa6SAndrey Grodzovsky struct pci_saved_state *pci_state; 1038e17e27f9SGuchun Chen pci_channel_state_t pci_channel_state; 103904442bf7SLijo Lazar 1040e071dce3SLijo Lazar struct amdgpu_reset_control *reset_cntl; 1041fe9c5c9aSLijo Lazar uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 10424a74c38cSPhilip Yang 10434a74c38cSPhilip Yang bool ram_is_direct_mapped; 10446492e1b0Syipechai 10456492e1b0Syipechai struct list_head ras_list; 1046a6c40b17SLuben Tuikov 1047a6c40b17SLuben Tuikov struct ip_discovery_top *ip_top; 104854f43c17SDave Airlie 1049cfbb6b00SAndrey Grodzovsky struct amdgpu_reset_domain *reset_domain; 105038a15ad9SDave Airlie 1051f113cc32SAlex Deucher struct mutex benchmark_mutex; 10525ce5a584SSomalapuram Amaranath 10535ce5a584SSomalapuram Amaranath /* reset dump register */ 10545ce5a584SSomalapuram Amaranath uint32_t *reset_dump_reg_list; 1055651d7ee6SSomalapuram Amaranath uint32_t *reset_dump_reg_value; 10565ce5a584SSomalapuram Amaranath int num_regs; 10573d8785f6SSomalapuram Amaranath #ifdef CONFIG_DEV_COREDUMP 10583d8785f6SSomalapuram Amaranath struct amdgpu_task_info reset_task_info; 10593d8785f6SSomalapuram Amaranath bool reset_vram_lost; 10603d8785f6SSomalapuram Amaranath struct timespec64 reset_time; 10613d8785f6SSomalapuram Amaranath #endif 10627f318f4eSLikun Gao 10637f318f4eSLikun Gao bool scpm_enabled; 10647f318f4eSLikun Gao uint32_t scpm_status; 10652f83658fSAndrey Grodzovsky 10662f83658fSAndrey Grodzovsky struct work_struct reset_work; 10675bd8d53fSVictor Zhao 10685bd8d53fSVictor Zhao uint32_t amdgpu_reset_level_mask; 1069194eb174SVictor Zhao bool job_hang; 107097b2e202SAlex Deucher }; 107197b2e202SAlex Deucher 10721348969aSLuben Tuikov static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 10731348969aSLuben Tuikov { 10748aba21b7SLuben Tuikov return container_of(ddev, struct amdgpu_device, ddev); 10751348969aSLuben Tuikov } 10761348969aSLuben Tuikov 10774a580877SLuben Tuikov static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 10784a580877SLuben Tuikov { 10798aba21b7SLuben Tuikov return &adev->ddev; 10804a580877SLuben Tuikov } 10814a580877SLuben Tuikov 10828af8a109SChristian König static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1083a7d64de6SChristian König { 1084a7d64de6SChristian König return container_of(bdev, struct amdgpu_device, mman.bdev); 1085a7d64de6SChristian König } 1086a7d64de6SChristian König 108797b2e202SAlex Deucher int amdgpu_device_init(struct amdgpu_device *adev, 108897b2e202SAlex Deucher uint32_t flags); 108972c8c97bSAndrey Grodzovsky void amdgpu_device_fini_hw(struct amdgpu_device *adev); 109072c8c97bSAndrey Grodzovsky void amdgpu_device_fini_sw(struct amdgpu_device *adev); 109172c8c97bSAndrey Grodzovsky 109297b2e202SAlex Deucher int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 109397b2e202SAlex Deucher 1094048af66bSKevin Wang void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1095048af66bSKevin Wang void *buf, size_t size, bool write); 1096048af66bSKevin Wang size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1097048af66bSKevin Wang void *buf, size_t size, bool write); 1098048af66bSKevin Wang 1099e35e2b11STianci.Yin void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1100048af66bSKevin Wang void *buf, size_t size, bool write); 1101f7ee1874SHawking Zhang uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1102f7ee1874SHawking Zhang uint32_t reg, uint32_t acc_flags); 1103f7ee1874SHawking Zhang void amdgpu_device_wreg(struct amdgpu_device *adev, 1104f7ee1874SHawking Zhang uint32_t reg, uint32_t v, 110515d72fd7SMonk Liu uint32_t acc_flags); 1106f7ee1874SHawking Zhang void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1107f7ee1874SHawking Zhang uint32_t reg, uint32_t v); 1108421a2a30SMonk Liu void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1109421a2a30SMonk Liu uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1110421a2a30SMonk Liu 11111bba3683SHawking Zhang u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 11121bba3683SHawking Zhang u32 pcie_index, u32 pcie_data, 11131bba3683SHawking Zhang u32 reg_addr); 11141bba3683SHawking Zhang u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 11151bba3683SHawking Zhang u32 pcie_index, u32 pcie_data, 11161bba3683SHawking Zhang u32 reg_addr); 11171bba3683SHawking Zhang void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 11181bba3683SHawking Zhang u32 pcie_index, u32 pcie_data, 11191bba3683SHawking Zhang u32 reg_addr, u32 reg_data); 11201bba3683SHawking Zhang void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 11211bba3683SHawking Zhang u32 pcie_index, u32 pcie_data, 11221bba3683SHawking Zhang u32 reg_addr, u64 reg_data); 11231bba3683SHawking Zhang 11244562236bSHarry Wentland bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 11254562236bSHarry Wentland bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 11264562236bSHarry Wentland 1127e3c1b071Sshaoyunl int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 112804442bf7SLijo Lazar struct amdgpu_reset_context *reset_context); 1129e3c1b071Sshaoyunl 113004442bf7SLijo Lazar int amdgpu_do_asic_reset(struct list_head *device_list_handle, 113104442bf7SLijo Lazar struct amdgpu_reset_context *reset_context); 1132e3c1b071Sshaoyunl 11339475a943SShaoyun Liu int emu_soc_asic_init(struct amdgpu_device *adev); 11349475a943SShaoyun Liu 113597b2e202SAlex Deucher /* 113697b2e202SAlex Deucher * Registers read & write functions. 113797b2e202SAlex Deucher */ 113815d72fd7SMonk Liu #define AMDGPU_REGS_NO_KIQ (1<<1) 1139a5504e9aSPeng Ju Zhou #define AMDGPU_REGS_RLC (1<<2) 114015d72fd7SMonk Liu 1141f7ee1874SHawking Zhang #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1142f7ee1874SHawking Zhang #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 114315d72fd7SMonk Liu 1144f384ff95SHawking Zhang #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1145f384ff95SHawking Zhang #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1146c68dbcd8Schen gong 1147421a2a30SMonk Liu #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1148421a2a30SMonk Liu #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1149421a2a30SMonk Liu 1150f7ee1874SHawking Zhang #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1151f7ee1874SHawking Zhang #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1152f7ee1874SHawking Zhang #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 115397b2e202SAlex Deucher #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 115497b2e202SAlex Deucher #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 115597b2e202SAlex Deucher #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 115697b2e202SAlex Deucher #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 115736b9a952SHuang Rui #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 115836b9a952SHuang Rui #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 11594fa1c6a6STao Zhou #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 11604fa1c6a6STao Zhou #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 116197b2e202SAlex Deucher #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 116297b2e202SAlex Deucher #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 116397b2e202SAlex Deucher #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 116497b2e202SAlex Deucher #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 116597b2e202SAlex Deucher #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 116697b2e202SAlex Deucher #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1167ccdbb20aSRex Zhu #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1168ccdbb20aSRex Zhu #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 116916abb5d2SEvan Quan #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 117016abb5d2SEvan Quan #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 117197b2e202SAlex Deucher #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 117297b2e202SAlex Deucher #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 117397b2e202SAlex Deucher #define WREG32_P(reg, val, mask) \ 117497b2e202SAlex Deucher do { \ 117597b2e202SAlex Deucher uint32_t tmp_ = RREG32(reg); \ 117697b2e202SAlex Deucher tmp_ &= (mask); \ 117797b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 117897b2e202SAlex Deucher WREG32(reg, tmp_); \ 117997b2e202SAlex Deucher } while (0) 118097b2e202SAlex Deucher #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 118197b2e202SAlex Deucher #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 118297b2e202SAlex Deucher #define WREG32_PLL_P(reg, val, mask) \ 118397b2e202SAlex Deucher do { \ 118497b2e202SAlex Deucher uint32_t tmp_ = RREG32_PLL(reg); \ 118597b2e202SAlex Deucher tmp_ &= (mask); \ 118697b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 118797b2e202SAlex Deucher WREG32_PLL(reg, tmp_); \ 118897b2e202SAlex Deucher } while (0) 1189fb40bcebSAlex Jivin 1190fb40bcebSAlex Jivin #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1191fb40bcebSAlex Jivin do { \ 1192fb40bcebSAlex Jivin u32 tmp = RREG32_SMC(_Reg); \ 1193fb40bcebSAlex Jivin tmp &= (_Mask); \ 1194fb40bcebSAlex Jivin tmp |= ((_Val) & ~(_Mask)); \ 1195fb40bcebSAlex Jivin WREG32_SMC(_Reg, tmp); \ 1196fb40bcebSAlex Jivin } while (0) 1197fb40bcebSAlex Jivin 1198f7ee1874SHawking Zhang #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 119997b2e202SAlex Deucher 120097b2e202SAlex Deucher #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 120197b2e202SAlex Deucher #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 120297b2e202SAlex Deucher 120397b2e202SAlex Deucher #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 120497b2e202SAlex Deucher (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 120597b2e202SAlex Deucher (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 120697b2e202SAlex Deucher 120797b2e202SAlex Deucher #define REG_GET_FIELD(value, reg, field) \ 120897b2e202SAlex Deucher (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 120997b2e202SAlex Deucher 121061cb8cefSTom St Denis #define WREG32_FIELD(reg, field, val) \ 121161cb8cefSTom St Denis WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 121261cb8cefSTom St Denis 1213ccaf3574STom St Denis #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1214ccaf3574STom St Denis WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1215ccaf3574STom St Denis 121697b2e202SAlex Deucher /* 121797b2e202SAlex Deucher * BIOS helpers. 121897b2e202SAlex Deucher */ 121997b2e202SAlex Deucher #define RBIOS8(i) (adev->bios[i]) 122097b2e202SAlex Deucher #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 122197b2e202SAlex Deucher #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 122297b2e202SAlex Deucher 122397b2e202SAlex Deucher /* 122497b2e202SAlex Deucher * ASICs macro. 122597b2e202SAlex Deucher */ 122697b2e202SAlex Deucher #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 122797b2e202SAlex Deucher #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 12280cf3c64fSAlex Deucher #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 122997b2e202SAlex Deucher #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 123097b2e202SAlex Deucher #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 123197b2e202SAlex Deucher #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1232841686dfSMaruthi Bayyavarapu #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1233841686dfSMaruthi Bayyavarapu #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1234841686dfSMaruthi Bayyavarapu #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 123597b2e202SAlex Deucher #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 12367946b878SAlex Deucher #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 123797b2e202SAlex Deucher #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1238bbf282d8SAlex Deucher #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1239455d40c9SLikun Gao #define amdgpu_asic_flush_hdp(adev, r) \ 1240455d40c9SLikun Gao ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1241455d40c9SLikun Gao #define amdgpu_asic_invalidate_hdp(adev, r) \ 1242563fcfbfSLikun Gao ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1243563fcfbfSLikun Gao ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0)) 124469070690SAlex Deucher #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 12455253163aSOak Zeng #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1246b45e18acSKent Russell #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 124744401889SAlex Deucher #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1248dcea6e65SKent Russell #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 124969d5436dSAlex Deucher #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 12509737a923SAlex Deucher #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1251f2b75bc2SEvan Quan #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1252f2b75bc2SEvan Quan ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 12539269bf18SAlex Deucher #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 125469d5436dSAlex Deucher 1255e3526257SMonk Liu #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 125697b2e202SAlex Deucher 12570d8318e1SEvan Quan #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 12580d8318e1SEvan Quan 125997b2e202SAlex Deucher /* Common functions */ 12609a1cddd6Sjqdeng bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 126112938fadSChristian König bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 12625f152b5eSAlex Deucher int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1263f1549c09SLikun Gao struct amdgpu_job *job, 1264f1549c09SLikun Gao struct amdgpu_reset_context *reset_context); 12658111c387SAlex Deucher void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1266af484df8SAlex Deucher int amdgpu_device_pci_reset(struct amdgpu_device *adev); 126739c640c0SAlex Deucher bool amdgpu_device_need_post(struct amdgpu_device *adev); 12680ab5d711SMario Limonciello bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1269d5fc5e82SChunming Zhou 127000f06b24SJohn Brooks void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 127100f06b24SJohn Brooks u64 num_vis_bytes); 1272d6895ad3SChristian König int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 12739c3f2b54SAlex Deucher void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 127497b2e202SAlex Deucher const u32 *registers, 127597b2e202SAlex Deucher const u32 array_size); 127697b2e202SAlex Deucher 12775c03e584SFeifei Xu int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1278b98c6299SAlex Deucher bool amdgpu_device_supports_atpx(struct drm_device *dev); 1279b98c6299SAlex Deucher bool amdgpu_device_supports_px(struct drm_device *dev); 128031af062aSAlex Deucher bool amdgpu_device_supports_boco(struct drm_device *dev); 12813fa8f89dSSathishkumar S bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1282a69cba42SAlex Deucher bool amdgpu_device_supports_baco(struct drm_device *dev); 1283992af942SJonathan Kim bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1284992af942SJonathan Kim struct amdgpu_device *peer_adev); 1285361dbd01SAlex Deucher int amdgpu_device_baco_enter(struct drm_device *dev); 1286361dbd01SAlex Deucher int amdgpu_device_baco_exit(struct drm_device *dev); 1287992af942SJonathan Kim 1288810085ddSEric Huang void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1289810085ddSEric Huang struct amdgpu_ring *ring); 1290810085ddSEric Huang void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1291810085ddSEric Huang struct amdgpu_ring *ring); 1292810085ddSEric Huang 129334f3a4a9SLang Yu void amdgpu_device_halt(struct amdgpu_device *adev); 129486700a40SXiaojian Du u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 129586700a40SXiaojian Du u32 reg); 129686700a40SXiaojian Du void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 129786700a40SXiaojian Du u32 reg, u32 v); 129868ce8b24SChristian König struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 129968ce8b24SChristian König struct dma_fence *gang); 130034f3a4a9SLang Yu 130197b2e202SAlex Deucher /* atpx handler */ 130297b2e202SAlex Deucher #if defined(CONFIG_VGA_SWITCHEROO) 130397b2e202SAlex Deucher void amdgpu_register_atpx_handler(void); 130497b2e202SAlex Deucher void amdgpu_unregister_atpx_handler(void); 1305a78fe133SAlex Deucher bool amdgpu_has_atpx_dgpu_power_cntl(void); 13062f5af82eSAlex Deucher bool amdgpu_is_atpx_hybrid(void); 1307efc83cf4SAlex Deucher bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1308714f88e0SAlex Xie bool amdgpu_has_atpx(void); 130997b2e202SAlex Deucher #else 131097b2e202SAlex Deucher static inline void amdgpu_register_atpx_handler(void) {} 131197b2e202SAlex Deucher static inline void amdgpu_unregister_atpx_handler(void) {} 1312a78fe133SAlex Deucher static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 13132f5af82eSAlex Deucher static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1314efc83cf4SAlex Deucher static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1315714f88e0SAlex Xie static inline bool amdgpu_has_atpx(void) { return false; } 131697b2e202SAlex Deucher #endif 131797b2e202SAlex Deucher 131824aeefcdSLyude Paul #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 131924aeefcdSLyude Paul void *amdgpu_atpx_get_dhandle(void); 132024aeefcdSLyude Paul #else 132124aeefcdSLyude Paul static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 132224aeefcdSLyude Paul #endif 132324aeefcdSLyude Paul 132497b2e202SAlex Deucher /* 132597b2e202SAlex Deucher * KMS 132697b2e202SAlex Deucher */ 132797b2e202SAlex Deucher extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1328f498d9edSNils Wallménius extern const int amdgpu_max_kms_ioctl; 132997b2e202SAlex Deucher 13308aba21b7SLuben Tuikov int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 133111b3c20bSGabriel Krisman Bertazi void amdgpu_driver_unload_kms(struct drm_device *dev); 133297b2e202SAlex Deucher void amdgpu_driver_lastclose_kms(struct drm_device *dev); 133397b2e202SAlex Deucher int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 133497b2e202SAlex Deucher void amdgpu_driver_postclose_kms(struct drm_device *dev, 133597b2e202SAlex Deucher struct drm_file *file_priv); 133672c8c97bSAndrey Grodzovsky void amdgpu_driver_release_kms(struct drm_device *dev); 133772c8c97bSAndrey Grodzovsky 1338cdd61df6SAlex Deucher int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1339de185019SAlex Deucher int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1340de185019SAlex Deucher int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1341e3eff4b5SThomas Zimmermann u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1342e3eff4b5SThomas Zimmermann int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1343e3eff4b5SThomas Zimmermann void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1344b1246bd4SLuben Tuikov int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1345b1246bd4SLuben Tuikov struct drm_file *filp); 134697b2e202SAlex Deucher 134797b2e202SAlex Deucher /* 134897b2e202SAlex Deucher * functions used by amdgpu_encoder.c 134997b2e202SAlex Deucher */ 135097b2e202SAlex Deucher struct amdgpu_afmt_acr { 135197b2e202SAlex Deucher u32 clock; 135297b2e202SAlex Deucher 135397b2e202SAlex Deucher int n_32khz; 135497b2e202SAlex Deucher int cts_32khz; 135597b2e202SAlex Deucher 135697b2e202SAlex Deucher int n_44_1khz; 135797b2e202SAlex Deucher int cts_44_1khz; 135897b2e202SAlex Deucher 135997b2e202SAlex Deucher int n_48khz; 136097b2e202SAlex Deucher int cts_48khz; 136197b2e202SAlex Deucher 136297b2e202SAlex Deucher }; 136397b2e202SAlex Deucher 136497b2e202SAlex Deucher struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 136597b2e202SAlex Deucher 136697b2e202SAlex Deucher /* amdgpu_acpi.c */ 13673fa8f89dSSathishkumar S 13683fa8f89dSSathishkumar S /* ATCS Device/Driver State */ 13693fa8f89dSSathishkumar S #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 13703fa8f89dSSathishkumar S #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 13713fa8f89dSSathishkumar S #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 13723fa8f89dSSathishkumar S #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 13733fa8f89dSSathishkumar S 137497b2e202SAlex Deucher #if defined(CONFIG_ACPI) 137597b2e202SAlex Deucher int amdgpu_acpi_init(struct amdgpu_device *adev); 137697b2e202SAlex Deucher void amdgpu_acpi_fini(struct amdgpu_device *adev); 137797b2e202SAlex Deucher bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 137816eb48c6SSathishkumar S bool amdgpu_acpi_is_power_shift_control_supported(void); 137997b2e202SAlex Deucher int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 138097b2e202SAlex Deucher u8 perf_req, bool advertise); 138116eb48c6SSathishkumar S int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 138216eb48c6SSathishkumar S u8 dev_state, bool drv_state); 13833fa8f89dSSathishkumar S int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 138497b2e202SAlex Deucher int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1385206bbafeSDavid Francis 1386f9b7f370SAlex Deucher void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1387f9b7f370SAlex Deucher void amdgpu_acpi_detect(void); 138897b2e202SAlex Deucher #else 138997b2e202SAlex Deucher static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 139097b2e202SAlex Deucher static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1391f9b7f370SAlex Deucher static inline void amdgpu_acpi_detect(void) { } 139216eb48c6SSathishkumar S static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 139316eb48c6SSathishkumar S static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 139416eb48c6SSathishkumar S u8 dev_state, bool drv_state) { return 0; } 13953fa8f89dSSathishkumar S static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 13963fa8f89dSSathishkumar S enum amdgpu_ss ss_state) { return 0; } 139797b2e202SAlex Deucher #endif 139897b2e202SAlex Deucher 1399f588a1bbSMario Limonciello #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 140018b66aceSMario Limonciello bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 14010223e516SMario Limonciello bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1402f588a1bbSMario Limonciello bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1403f588a1bbSMario Limonciello #else 1404f588a1bbSMario Limonciello static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 14050223e516SMario Limonciello static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 140618b66aceSMario Limonciello static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1407f588a1bbSMario Limonciello #endif 1408f588a1bbSMario Limonciello 14094562236bSHarry Wentland #if defined(CONFIG_DRM_AMD_DC) 14104562236bSHarry Wentland int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 14114562236bSHarry Wentland #else 14124562236bSHarry Wentland static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 14134562236bSHarry Wentland #endif 14144562236bSHarry Wentland 1415fdafb359SEvan Quan 1416fdafb359SEvan Quan void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1417fdafb359SEvan Quan void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1418fdafb359SEvan Quan 1419c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1420c9a6b82fSAndrey Grodzovsky pci_channel_state_t state); 1421c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1422c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1423c9a6b82fSAndrey Grodzovsky void amdgpu_pci_resume(struct pci_dev *pdev); 1424c9a6b82fSAndrey Grodzovsky 1425c1dd4aa6SAndrey Grodzovsky bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1426c1dd4aa6SAndrey Grodzovsky bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1427c1dd4aa6SAndrey Grodzovsky 142856b53c0bSDennis Li bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 142956b53c0bSDennis Li 14305d89bb2dSLijo Lazar int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 14315d89bb2dSLijo Lazar enum amd_clockgating_state state); 14325d89bb2dSLijo Lazar int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 14335d89bb2dSLijo Lazar enum amd_powergating_state state); 14345d89bb2dSLijo Lazar 1435400ef298SJonathan Kim static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1436400ef298SJonathan Kim { 1437400ef298SJonathan Kim return amdgpu_gpu_recovery != 0 && 1438400ef298SJonathan Kim adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1439400ef298SJonathan Kim adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1440400ef298SJonathan Kim adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1441400ef298SJonathan Kim adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1442400ef298SJonathan Kim } 1443400ef298SJonathan Kim 144497b2e202SAlex Deucher #include "amdgpu_object.h" 1445e4cf4bf5SJonathan Kim 1446c6252390SLuben Tuikov static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1447c6252390SLuben Tuikov { 1448c6252390SLuben Tuikov return adev->gmc.tmz_enabled; 1449c6252390SLuben Tuikov } 1450e4cf4bf5SJonathan Kim 145189a7a870SAndrey Grodzovsky int amdgpu_in_reset(struct amdgpu_device *adev); 145289a7a870SAndrey Grodzovsky 1453c6252390SLuben Tuikov #endif 1454