197b2e202SAlex Deucher /* 297b2e202SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 397b2e202SAlex Deucher * Copyright 2008 Red Hat Inc. 497b2e202SAlex Deucher * Copyright 2009 Jerome Glisse. 597b2e202SAlex Deucher * 697b2e202SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 797b2e202SAlex Deucher * copy of this software and associated documentation files (the "Software"), 897b2e202SAlex Deucher * to deal in the Software without restriction, including without limitation 997b2e202SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1097b2e202SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1197b2e202SAlex Deucher * Software is furnished to do so, subject to the following conditions: 1297b2e202SAlex Deucher * 1397b2e202SAlex Deucher * The above copyright notice and this permission notice shall be included in 1497b2e202SAlex Deucher * all copies or substantial portions of the Software. 1597b2e202SAlex Deucher * 1697b2e202SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1797b2e202SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1897b2e202SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1997b2e202SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2097b2e202SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2197b2e202SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2297b2e202SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2397b2e202SAlex Deucher * 2497b2e202SAlex Deucher * Authors: Dave Airlie 2597b2e202SAlex Deucher * Alex Deucher 2697b2e202SAlex Deucher * Jerome Glisse 2797b2e202SAlex Deucher */ 2897b2e202SAlex Deucher #ifndef __AMDGPU_H__ 2997b2e202SAlex Deucher #define __AMDGPU_H__ 3097b2e202SAlex Deucher 3197b2e202SAlex Deucher #include <linux/atomic.h> 3297b2e202SAlex Deucher #include <linux/wait.h> 3397b2e202SAlex Deucher #include <linux/list.h> 3497b2e202SAlex Deucher #include <linux/kref.h> 35a9f87f64SChristian König #include <linux/rbtree.h> 3697b2e202SAlex Deucher #include <linux/hashtable.h> 37f54d1867SChris Wilson #include <linux/dma-fence.h> 3897b2e202SAlex Deucher 3997b2e202SAlex Deucher #include <ttm/ttm_bo_api.h> 4097b2e202SAlex Deucher #include <ttm/ttm_bo_driver.h> 4197b2e202SAlex Deucher #include <ttm/ttm_placement.h> 4297b2e202SAlex Deucher #include <ttm/ttm_module.h> 4397b2e202SAlex Deucher #include <ttm/ttm_execbuf_util.h> 4497b2e202SAlex Deucher 45d03846afSChunming Zhou #include <drm/drmP.h> 4697b2e202SAlex Deucher #include <drm/drm_gem.h> 477e5a547fSChunming Zhou #include <drm/amdgpu_drm.h> 4897b2e202SAlex Deucher 4978c16834SAndres Rodriguez #include <kgd_kfd_interface.h> 5078c16834SAndres Rodriguez 515fc3aeebSyanyang1 #include "amd_shared.h" 5297b2e202SAlex Deucher #include "amdgpu_mode.h" 5397b2e202SAlex Deucher #include "amdgpu_ih.h" 5497b2e202SAlex Deucher #include "amdgpu_irq.h" 5597b2e202SAlex Deucher #include "amdgpu_ucode.h" 56c632d799SFlora Cui #include "amdgpu_ttm.h" 570e5ca0d1SHuang Rui #include "amdgpu_psp.h" 5897b2e202SAlex Deucher #include "amdgpu_gds.h" 5956113504SChristian König #include "amdgpu_sync.h" 6078023016SChristian König #include "amdgpu_ring.h" 61073440d2SChristian König #include "amdgpu_vm.h" 621f7371b2SAlex Deucher #include "amd_powerplay.h" 63cf097881SAlex Deucher #include "amdgpu_dpm.h" 64a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h" 654df654d2SLeo Liu #include "amdgpu_uvd.h" 665e568178SLeo Liu #include "amdgpu_vce.h" 6795aa13f6SLeo Liu #include "amdgpu_vcn.h" 6897b2e202SAlex Deucher 69b80d8475SAlex Deucher #include "gpu_scheduler.h" 70ceeb50edSMonk Liu #include "amdgpu_virt.h" 71b80d8475SAlex Deucher 7297b2e202SAlex Deucher /* 7397b2e202SAlex Deucher * Modules parameters. 7497b2e202SAlex Deucher */ 7597b2e202SAlex Deucher extern int amdgpu_modeset; 7697b2e202SAlex Deucher extern int amdgpu_vram_limit; 7797b2e202SAlex Deucher extern int amdgpu_gart_size; 7895844d20SMarek Olšák extern int amdgpu_moverate; 7997b2e202SAlex Deucher extern int amdgpu_benchmarking; 8097b2e202SAlex Deucher extern int amdgpu_testing; 8197b2e202SAlex Deucher extern int amdgpu_audio; 8297b2e202SAlex Deucher extern int amdgpu_disp_priority; 8397b2e202SAlex Deucher extern int amdgpu_hw_i2c; 8497b2e202SAlex Deucher extern int amdgpu_pcie_gen2; 8597b2e202SAlex Deucher extern int amdgpu_msi; 8697b2e202SAlex Deucher extern int amdgpu_lockup_timeout; 8797b2e202SAlex Deucher extern int amdgpu_dpm; 88e635ee07SHuang Rui extern int amdgpu_fw_load_type; 8997b2e202SAlex Deucher extern int amdgpu_aspm; 9097b2e202SAlex Deucher extern int amdgpu_runtime_pm; 9197b2e202SAlex Deucher extern unsigned amdgpu_ip_block_mask; 9297b2e202SAlex Deucher extern int amdgpu_bapm; 9397b2e202SAlex Deucher extern int amdgpu_deep_color; 9497b2e202SAlex Deucher extern int amdgpu_vm_size; 9597b2e202SAlex Deucher extern int amdgpu_vm_block_size; 96d9c13156SChristian König extern int amdgpu_vm_fault_stop; 97b495bd3aSChristian König extern int amdgpu_vm_debug; 981333f723SJammy Zhou extern int amdgpu_sched_jobs; 994afcb303SJammy Zhou extern int amdgpu_sched_hw_submission; 1003ca67300SRex Zhu extern int amdgpu_no_evict; 1013ca67300SRex Zhu extern int amdgpu_direct_gma_size; 102cd474ba0SAlex Deucher extern unsigned amdgpu_pcie_gen_cap; 103cd474ba0SAlex Deucher extern unsigned amdgpu_pcie_lane_cap; 104395d1fb9SNicolai Hähnle extern unsigned amdgpu_cg_mask; 105395d1fb9SNicolai Hähnle extern unsigned amdgpu_pg_mask; 1066f8941a2SNicolai Hähnle extern char *amdgpu_disable_cu; 1079accf2fdSEmily Deng extern char *amdgpu_virtual_display; 1085141e9d2SRex Zhu extern unsigned amdgpu_pp_feature_mask; 1096a7f76e7SChristian König extern int amdgpu_vram_page_split; 110bce23e00SAlex Deucher extern int amdgpu_ngg; 111bce23e00SAlex Deucher extern int amdgpu_prim_buf_per_se; 112bce23e00SAlex Deucher extern int amdgpu_pos_buf_per_se; 113bce23e00SAlex Deucher extern int amdgpu_cntl_sb_buf_per_se; 114bce23e00SAlex Deucher extern int amdgpu_param_buf_per_se; 11565781c78SMonk Liu extern int amdgpu_job_hang_limit; 116e8835e0eSHawking Zhang extern int amdgpu_lbpw; 11797b2e202SAlex Deucher 11855ed8cafSChunming Zhou #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 1194b559c90SChunming Zhou #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 12097b2e202SAlex Deucher #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 12197b2e202SAlex Deucher #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 12297b2e202SAlex Deucher /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 12397b2e202SAlex Deucher #define AMDGPU_IB_POOL_SIZE 16 12497b2e202SAlex Deucher #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 12597b2e202SAlex Deucher #define AMDGPUFB_CONN_LIMIT 4 126a5bde2f9SAlex Deucher #define AMDGPU_BIOS_NUM_SCRATCH 16 12797b2e202SAlex Deucher 12836f523a7SJammy Zhou /* max number of IP instances */ 12936f523a7SJammy Zhou #define AMDGPU_MAX_SDMA_INSTANCES 2 13036f523a7SJammy Zhou 13197b2e202SAlex Deucher /* hard reset data */ 13297b2e202SAlex Deucher #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 13397b2e202SAlex Deucher 13497b2e202SAlex Deucher /* reset flags */ 13597b2e202SAlex Deucher #define AMDGPU_RESET_GFX (1 << 0) 13697b2e202SAlex Deucher #define AMDGPU_RESET_COMPUTE (1 << 1) 13797b2e202SAlex Deucher #define AMDGPU_RESET_DMA (1 << 2) 13897b2e202SAlex Deucher #define AMDGPU_RESET_CP (1 << 3) 13997b2e202SAlex Deucher #define AMDGPU_RESET_GRBM (1 << 4) 14097b2e202SAlex Deucher #define AMDGPU_RESET_DMA1 (1 << 5) 14197b2e202SAlex Deucher #define AMDGPU_RESET_RLC (1 << 6) 14297b2e202SAlex Deucher #define AMDGPU_RESET_SEM (1 << 7) 14397b2e202SAlex Deucher #define AMDGPU_RESET_IH (1 << 8) 14497b2e202SAlex Deucher #define AMDGPU_RESET_VMC (1 << 9) 14597b2e202SAlex Deucher #define AMDGPU_RESET_MC (1 << 10) 14697b2e202SAlex Deucher #define AMDGPU_RESET_DISPLAY (1 << 11) 14797b2e202SAlex Deucher #define AMDGPU_RESET_UVD (1 << 12) 14897b2e202SAlex Deucher #define AMDGPU_RESET_VCE (1 << 13) 14997b2e202SAlex Deucher #define AMDGPU_RESET_VCE1 (1 << 14) 15097b2e202SAlex Deucher 15197b2e202SAlex Deucher /* GFX current status */ 15297b2e202SAlex Deucher #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 15397b2e202SAlex Deucher #define AMDGPU_GFX_SAFE_MODE 0x00000001L 15497b2e202SAlex Deucher #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 15597b2e202SAlex Deucher #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 15697b2e202SAlex Deucher #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 15797b2e202SAlex Deucher 15897b2e202SAlex Deucher /* max cursor sizes (in pixels) */ 15997b2e202SAlex Deucher #define CIK_CURSOR_WIDTH 128 16097b2e202SAlex Deucher #define CIK_CURSOR_HEIGHT 128 16197b2e202SAlex Deucher 16297b2e202SAlex Deucher struct amdgpu_device; 16397b2e202SAlex Deucher struct amdgpu_ib; 16497b2e202SAlex Deucher struct amdgpu_cs_parser; 165bb977d37SChunming Zhou struct amdgpu_job; 16697b2e202SAlex Deucher struct amdgpu_irq_src; 1670b492a4cSAlex Deucher struct amdgpu_fpriv; 16897b2e202SAlex Deucher 16997b2e202SAlex Deucher enum amdgpu_cp_irq { 17097b2e202SAlex Deucher AMDGPU_CP_IRQ_GFX_EOP = 0, 17197b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 17297b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 17397b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 17497b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 17597b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 17697b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 17797b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 17897b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 17997b2e202SAlex Deucher 18097b2e202SAlex Deucher AMDGPU_CP_IRQ_LAST 18197b2e202SAlex Deucher }; 18297b2e202SAlex Deucher 18397b2e202SAlex Deucher enum amdgpu_sdma_irq { 18497b2e202SAlex Deucher AMDGPU_SDMA_IRQ_TRAP0 = 0, 18597b2e202SAlex Deucher AMDGPU_SDMA_IRQ_TRAP1, 18697b2e202SAlex Deucher 18797b2e202SAlex Deucher AMDGPU_SDMA_IRQ_LAST 18897b2e202SAlex Deucher }; 18997b2e202SAlex Deucher 19097b2e202SAlex Deucher enum amdgpu_thermal_irq { 19197b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 19297b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 19397b2e202SAlex Deucher 19497b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LAST 19597b2e202SAlex Deucher }; 19697b2e202SAlex Deucher 1974e638ae9SXiangliang Yu enum amdgpu_kiq_irq { 1984e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 1994e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_LAST 2004e638ae9SXiangliang Yu }; 2014e638ae9SXiangliang Yu 20297b2e202SAlex Deucher int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 2035fc3aeebSyanyang1 enum amd_ip_block_type block_type, 2045fc3aeebSyanyang1 enum amd_clockgating_state state); 20597b2e202SAlex Deucher int amdgpu_set_powergating_state(struct amdgpu_device *adev, 2065fc3aeebSyanyang1 enum amd_ip_block_type block_type, 2075fc3aeebSyanyang1 enum amd_powergating_state state); 2086cb2d4e4SHuang Rui void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); 2095dbbb60bSAlex Deucher int amdgpu_wait_for_idle(struct amdgpu_device *adev, 2105dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 2115dbbb60bSAlex Deucher bool amdgpu_is_idle(struct amdgpu_device *adev, 2125dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 21397b2e202SAlex Deucher 214a1255107SAlex Deucher #define AMDGPU_MAX_IP_NUM 16 215a1255107SAlex Deucher 216a1255107SAlex Deucher struct amdgpu_ip_block_status { 217a1255107SAlex Deucher bool valid; 218a1255107SAlex Deucher bool sw; 219a1255107SAlex Deucher bool hw; 220a1255107SAlex Deucher bool late_initialized; 221a1255107SAlex Deucher bool hang; 222a1255107SAlex Deucher }; 223a1255107SAlex Deucher 22497b2e202SAlex Deucher struct amdgpu_ip_block_version { 225a1255107SAlex Deucher const enum amd_ip_block_type type; 226a1255107SAlex Deucher const u32 major; 227a1255107SAlex Deucher const u32 minor; 228a1255107SAlex Deucher const u32 rev; 2295fc3aeebSyanyang1 const struct amd_ip_funcs *funcs; 23097b2e202SAlex Deucher }; 23197b2e202SAlex Deucher 232a1255107SAlex Deucher struct amdgpu_ip_block { 233a1255107SAlex Deucher struct amdgpu_ip_block_status status; 234a1255107SAlex Deucher const struct amdgpu_ip_block_version *version; 235a1255107SAlex Deucher }; 236a1255107SAlex Deucher 23797b2e202SAlex Deucher int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 2385fc3aeebSyanyang1 enum amd_ip_block_type type, 23997b2e202SAlex Deucher u32 major, u32 minor); 24097b2e202SAlex Deucher 241a1255107SAlex Deucher struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 2425fc3aeebSyanyang1 enum amd_ip_block_type type); 24397b2e202SAlex Deucher 244a1255107SAlex Deucher int amdgpu_ip_block_add(struct amdgpu_device *adev, 245a1255107SAlex Deucher const struct amdgpu_ip_block_version *ip_block_version); 246a1255107SAlex Deucher 24797b2e202SAlex Deucher /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 24897b2e202SAlex Deucher struct amdgpu_buffer_funcs { 24997b2e202SAlex Deucher /* maximum bytes in a single operation */ 25097b2e202SAlex Deucher uint32_t copy_max_bytes; 25197b2e202SAlex Deucher 25297b2e202SAlex Deucher /* number of dw to reserve per operation */ 25397b2e202SAlex Deucher unsigned copy_num_dw; 25497b2e202SAlex Deucher 25597b2e202SAlex Deucher /* used for buffer migration */ 256c7ae72c0SChunming Zhou void (*emit_copy_buffer)(struct amdgpu_ib *ib, 25797b2e202SAlex Deucher /* src addr in bytes */ 25897b2e202SAlex Deucher uint64_t src_offset, 25997b2e202SAlex Deucher /* dst addr in bytes */ 26097b2e202SAlex Deucher uint64_t dst_offset, 26197b2e202SAlex Deucher /* number of byte to transfer */ 26297b2e202SAlex Deucher uint32_t byte_count); 26397b2e202SAlex Deucher 26497b2e202SAlex Deucher /* maximum bytes in a single operation */ 26597b2e202SAlex Deucher uint32_t fill_max_bytes; 26697b2e202SAlex Deucher 26797b2e202SAlex Deucher /* number of dw to reserve per operation */ 26897b2e202SAlex Deucher unsigned fill_num_dw; 26997b2e202SAlex Deucher 27097b2e202SAlex Deucher /* used for buffer clearing */ 2716e7a3840SChunming Zhou void (*emit_fill_buffer)(struct amdgpu_ib *ib, 27297b2e202SAlex Deucher /* value to write to memory */ 27397b2e202SAlex Deucher uint32_t src_data, 27497b2e202SAlex Deucher /* dst addr in bytes */ 27597b2e202SAlex Deucher uint64_t dst_offset, 27697b2e202SAlex Deucher /* number of byte to fill */ 27797b2e202SAlex Deucher uint32_t byte_count); 27897b2e202SAlex Deucher }; 27997b2e202SAlex Deucher 28097b2e202SAlex Deucher /* provided by hw blocks that can write ptes, e.g., sdma */ 28197b2e202SAlex Deucher struct amdgpu_vm_pte_funcs { 28297b2e202SAlex Deucher /* copy pte entries from GART */ 28397b2e202SAlex Deucher void (*copy_pte)(struct amdgpu_ib *ib, 28497b2e202SAlex Deucher uint64_t pe, uint64_t src, 28597b2e202SAlex Deucher unsigned count); 28697b2e202SAlex Deucher /* write pte one entry at a time with addr mapping */ 287de9ea7bdSChristian König void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 288de9ea7bdSChristian König uint64_t value, unsigned count, 289de9ea7bdSChristian König uint32_t incr); 29097b2e202SAlex Deucher /* for linear pte/pde updates without addr mapping */ 29197b2e202SAlex Deucher void (*set_pte_pde)(struct amdgpu_ib *ib, 29297b2e202SAlex Deucher uint64_t pe, 29397b2e202SAlex Deucher uint64_t addr, unsigned count, 2946b777607SChunming Zhou uint32_t incr, uint64_t flags); 29597b2e202SAlex Deucher }; 29697b2e202SAlex Deucher 29797b2e202SAlex Deucher /* provided by the gmc block */ 29897b2e202SAlex Deucher struct amdgpu_gart_funcs { 29997b2e202SAlex Deucher /* flush the vm tlb via mmio */ 30097b2e202SAlex Deucher void (*flush_gpu_tlb)(struct amdgpu_device *adev, 30197b2e202SAlex Deucher uint32_t vmid); 30297b2e202SAlex Deucher /* write pte/pde updates using the cpu */ 30397b2e202SAlex Deucher int (*set_pte_pde)(struct amdgpu_device *adev, 30497b2e202SAlex Deucher void *cpu_pt_addr, /* cpu addr of page table */ 30597b2e202SAlex Deucher uint32_t gpu_page_idx, /* pte/pde to update */ 30697b2e202SAlex Deucher uint64_t addr, /* addr to write into pte/pde */ 3076b777607SChunming Zhou uint64_t flags); /* access flags */ 308284710faSChristian König /* enable/disable PRT support */ 309284710faSChristian König void (*set_prt)(struct amdgpu_device *adev, bool enable); 3105463545bSAlex Xie /* set pte flags based per asic */ 3115463545bSAlex Xie uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, 3125463545bSAlex Xie uint32_t flags); 313b1166325SChristian König /* get the pde for a given mc addr */ 314b1166325SChristian König u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr); 31503f89febSChristian König uint32_t (*get_invalidate_req)(unsigned int vm_id); 316e60f8db5SAlex Xie }; 317e60f8db5SAlex Xie 31897b2e202SAlex Deucher /* provided by the ih block */ 31997b2e202SAlex Deucher struct amdgpu_ih_funcs { 32097b2e202SAlex Deucher /* ring read/write ptr handling, called from interrupt context */ 32197b2e202SAlex Deucher u32 (*get_wptr)(struct amdgpu_device *adev); 32297b2e202SAlex Deucher void (*decode_iv)(struct amdgpu_device *adev, 32397b2e202SAlex Deucher struct amdgpu_iv_entry *entry); 32497b2e202SAlex Deucher void (*set_rptr)(struct amdgpu_device *adev); 32597b2e202SAlex Deucher }; 32697b2e202SAlex Deucher 32797b2e202SAlex Deucher /* 32897b2e202SAlex Deucher * BIOS. 32997b2e202SAlex Deucher */ 33097b2e202SAlex Deucher bool amdgpu_get_bios(struct amdgpu_device *adev); 33197b2e202SAlex Deucher bool amdgpu_read_bios(struct amdgpu_device *adev); 33297b2e202SAlex Deucher 33397b2e202SAlex Deucher /* 33497b2e202SAlex Deucher * Dummy page 33597b2e202SAlex Deucher */ 33697b2e202SAlex Deucher struct amdgpu_dummy_page { 33797b2e202SAlex Deucher struct page *page; 33897b2e202SAlex Deucher dma_addr_t addr; 33997b2e202SAlex Deucher }; 34097b2e202SAlex Deucher int amdgpu_dummy_page_init(struct amdgpu_device *adev); 34197b2e202SAlex Deucher void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 34297b2e202SAlex Deucher 34397b2e202SAlex Deucher 34497b2e202SAlex Deucher /* 34597b2e202SAlex Deucher * Clocks 34697b2e202SAlex Deucher */ 34797b2e202SAlex Deucher 34897b2e202SAlex Deucher #define AMDGPU_MAX_PPLL 3 34997b2e202SAlex Deucher 35097b2e202SAlex Deucher struct amdgpu_clock { 35197b2e202SAlex Deucher struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 35297b2e202SAlex Deucher struct amdgpu_pll spll; 35397b2e202SAlex Deucher struct amdgpu_pll mpll; 35497b2e202SAlex Deucher /* 10 Khz units */ 35597b2e202SAlex Deucher uint32_t default_mclk; 35697b2e202SAlex Deucher uint32_t default_sclk; 35797b2e202SAlex Deucher uint32_t default_dispclk; 35897b2e202SAlex Deucher uint32_t current_dispclk; 35997b2e202SAlex Deucher uint32_t dp_extclk; 36097b2e202SAlex Deucher uint32_t max_pixel_clock; 36197b2e202SAlex Deucher }; 36297b2e202SAlex Deucher 36397b2e202SAlex Deucher /* 364c632d799SFlora Cui * BO. 36597b2e202SAlex Deucher */ 36697b2e202SAlex Deucher struct amdgpu_bo_list_entry { 36797b2e202SAlex Deucher struct amdgpu_bo *robj; 36897b2e202SAlex Deucher struct ttm_validate_buffer tv; 36997b2e202SAlex Deucher struct amdgpu_bo_va *bo_va; 37097b2e202SAlex Deucher uint32_t priority; 3712f568dbdSChristian König struct page **user_pages; 3722f568dbdSChristian König int user_invalidated; 37397b2e202SAlex Deucher }; 37497b2e202SAlex Deucher 37597b2e202SAlex Deucher struct amdgpu_bo_va_mapping { 37697b2e202SAlex Deucher struct list_head list; 377a9f87f64SChristian König struct rb_node rb; 378a9f87f64SChristian König uint64_t start; 379a9f87f64SChristian König uint64_t last; 380a9f87f64SChristian König uint64_t __subtree_last; 38197b2e202SAlex Deucher uint64_t offset; 382268c3001SChristian König uint64_t flags; 38397b2e202SAlex Deucher }; 38497b2e202SAlex Deucher 38597b2e202SAlex Deucher /* bo virtual addresses in a specific vm */ 38697b2e202SAlex Deucher struct amdgpu_bo_va { 38797b2e202SAlex Deucher /* protected by bo being reserved */ 38897b2e202SAlex Deucher struct list_head bo_list; 389f54d1867SChris Wilson struct dma_fence *last_pt_update; 39097b2e202SAlex Deucher unsigned ref_count; 39197b2e202SAlex Deucher 3927fc11959SChristian König /* protected by vm mutex and spinlock */ 39397b2e202SAlex Deucher struct list_head vm_status; 39497b2e202SAlex Deucher 3957fc11959SChristian König /* mappings for this bo_va */ 3967fc11959SChristian König struct list_head invalids; 3977fc11959SChristian König struct list_head valids; 3987fc11959SChristian König 39997b2e202SAlex Deucher /* constant after initialization */ 40097b2e202SAlex Deucher struct amdgpu_vm *vm; 40197b2e202SAlex Deucher struct amdgpu_bo *bo; 40297b2e202SAlex Deucher }; 40397b2e202SAlex Deucher 4047e5a547fSChunming Zhou #define AMDGPU_GEM_DOMAIN_MAX 0x3 4057e5a547fSChunming Zhou 40697b2e202SAlex Deucher struct amdgpu_bo { 40797b2e202SAlex Deucher /* Protected by tbo.reserved */ 4081ea863fdSChristian König u32 prefered_domains; 4091ea863fdSChristian König u32 allowed_domains; 4107e5a547fSChunming Zhou struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 41197b2e202SAlex Deucher struct ttm_placement placement; 41297b2e202SAlex Deucher struct ttm_buffer_object tbo; 41397b2e202SAlex Deucher struct ttm_bo_kmap_obj kmap; 41497b2e202SAlex Deucher u64 flags; 41597b2e202SAlex Deucher unsigned pin_count; 41697b2e202SAlex Deucher void *kptr; 41797b2e202SAlex Deucher u64 tiling_flags; 41897b2e202SAlex Deucher u64 metadata_flags; 41997b2e202SAlex Deucher void *metadata; 42097b2e202SAlex Deucher u32 metadata_size; 4218e94a46cSMario Kleiner unsigned prime_shared_count; 42297b2e202SAlex Deucher /* list of all virtual address to which this bo 42397b2e202SAlex Deucher * is associated to 42497b2e202SAlex Deucher */ 42597b2e202SAlex Deucher struct list_head va; 42697b2e202SAlex Deucher /* Constant after initialization */ 42797b2e202SAlex Deucher struct drm_gem_object gem_base; 42882b9c55bSChristian König struct amdgpu_bo *parent; 429e7893c4bSChunming Zhou struct amdgpu_bo *shadow; 43097b2e202SAlex Deucher 43197b2e202SAlex Deucher struct ttm_bo_kmap_obj dma_buf_vmap; 43297b2e202SAlex Deucher struct amdgpu_mn *mn; 43397b2e202SAlex Deucher struct list_head mn_list; 4340c4e7fa5SChunming Zhou struct list_head shadow_list; 43597b2e202SAlex Deucher }; 43697b2e202SAlex Deucher #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 43797b2e202SAlex Deucher 43897b2e202SAlex Deucher void amdgpu_gem_object_free(struct drm_gem_object *obj); 43997b2e202SAlex Deucher int amdgpu_gem_object_open(struct drm_gem_object *obj, 44097b2e202SAlex Deucher struct drm_file *file_priv); 44197b2e202SAlex Deucher void amdgpu_gem_object_close(struct drm_gem_object *obj, 44297b2e202SAlex Deucher struct drm_file *file_priv); 44397b2e202SAlex Deucher unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 44497b2e202SAlex Deucher struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 4454d9c514dSChristian König struct drm_gem_object * 4464d9c514dSChristian König amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 44797b2e202SAlex Deucher struct dma_buf_attachment *attach, 44897b2e202SAlex Deucher struct sg_table *sg); 44997b2e202SAlex Deucher struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 45097b2e202SAlex Deucher struct drm_gem_object *gobj, 45197b2e202SAlex Deucher int flags); 45297b2e202SAlex Deucher int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 45397b2e202SAlex Deucher void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 45497b2e202SAlex Deucher struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 45597b2e202SAlex Deucher void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 45697b2e202SAlex Deucher void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 45797b2e202SAlex Deucher int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 45897b2e202SAlex Deucher 45997b2e202SAlex Deucher /* sub-allocation manager, it has to be protected by another lock. 46097b2e202SAlex Deucher * By conception this is an helper for other part of the driver 46197b2e202SAlex Deucher * like the indirect buffer or semaphore, which both have their 46297b2e202SAlex Deucher * locking. 46397b2e202SAlex Deucher * 46497b2e202SAlex Deucher * Principe is simple, we keep a list of sub allocation in offset 46597b2e202SAlex Deucher * order (first entry has offset == 0, last entry has the highest 46697b2e202SAlex Deucher * offset). 46797b2e202SAlex Deucher * 46897b2e202SAlex Deucher * When allocating new object we first check if there is room at 46997b2e202SAlex Deucher * the end total_size - (last_object_offset + last_object_size) >= 47097b2e202SAlex Deucher * alloc_size. If so we allocate new object there. 47197b2e202SAlex Deucher * 47297b2e202SAlex Deucher * When there is not enough room at the end, we start waiting for 47397b2e202SAlex Deucher * each sub object until we reach object_offset+object_size >= 47497b2e202SAlex Deucher * alloc_size, this object then become the sub object we return. 47597b2e202SAlex Deucher * 47697b2e202SAlex Deucher * Alignment can't be bigger than page size. 47797b2e202SAlex Deucher * 47897b2e202SAlex Deucher * Hole are not considered for allocation to keep things simple. 47997b2e202SAlex Deucher * Assumption is that there won't be hole (all object on same 48097b2e202SAlex Deucher * alignment). 48197b2e202SAlex Deucher */ 4826ba60b89SChristian König 4836ba60b89SChristian König #define AMDGPU_SA_NUM_FENCE_LISTS 32 4846ba60b89SChristian König 48597b2e202SAlex Deucher struct amdgpu_sa_manager { 48697b2e202SAlex Deucher wait_queue_head_t wq; 48797b2e202SAlex Deucher struct amdgpu_bo *bo; 48897b2e202SAlex Deucher struct list_head *hole; 4896ba60b89SChristian König struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 49097b2e202SAlex Deucher struct list_head olist; 49197b2e202SAlex Deucher unsigned size; 49297b2e202SAlex Deucher uint64_t gpu_addr; 49397b2e202SAlex Deucher void *cpu_ptr; 49497b2e202SAlex Deucher uint32_t domain; 49597b2e202SAlex Deucher uint32_t align; 49697b2e202SAlex Deucher }; 49797b2e202SAlex Deucher 49897b2e202SAlex Deucher /* sub-allocation buffer */ 49997b2e202SAlex Deucher struct amdgpu_sa_bo { 50097b2e202SAlex Deucher struct list_head olist; 50197b2e202SAlex Deucher struct list_head flist; 50297b2e202SAlex Deucher struct amdgpu_sa_manager *manager; 50397b2e202SAlex Deucher unsigned soffset; 50497b2e202SAlex Deucher unsigned eoffset; 505f54d1867SChris Wilson struct dma_fence *fence; 50697b2e202SAlex Deucher }; 50797b2e202SAlex Deucher 50897b2e202SAlex Deucher /* 50997b2e202SAlex Deucher * GEM objects. 51097b2e202SAlex Deucher */ 511418aa0c2SChristian König void amdgpu_gem_force_release(struct amdgpu_device *adev); 51297b2e202SAlex Deucher int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 51397b2e202SAlex Deucher int alignment, u32 initial_domain, 51497b2e202SAlex Deucher u64 flags, bool kernel, 51597b2e202SAlex Deucher struct drm_gem_object **obj); 51697b2e202SAlex Deucher 51797b2e202SAlex Deucher int amdgpu_mode_dumb_create(struct drm_file *file_priv, 51897b2e202SAlex Deucher struct drm_device *dev, 51997b2e202SAlex Deucher struct drm_mode_create_dumb *args); 52097b2e202SAlex Deucher int amdgpu_mode_dumb_mmap(struct drm_file *filp, 52197b2e202SAlex Deucher struct drm_device *dev, 52297b2e202SAlex Deucher uint32_t handle, uint64_t *offset_p); 523d573de2dSRex Zhu int amdgpu_fence_slab_init(void); 524d573de2dSRex Zhu void amdgpu_fence_slab_fini(void); 52597b2e202SAlex Deucher 52697b2e202SAlex Deucher /* 52797b2e202SAlex Deucher * GART structures, functions & helpers 52897b2e202SAlex Deucher */ 52997b2e202SAlex Deucher struct amdgpu_mc; 53097b2e202SAlex Deucher 53197b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_SIZE 4096 53297b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 53397b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_SHIFT 12 53497b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 53597b2e202SAlex Deucher 53697b2e202SAlex Deucher struct amdgpu_gart { 53797b2e202SAlex Deucher dma_addr_t table_addr; 53897b2e202SAlex Deucher struct amdgpu_bo *robj; 53997b2e202SAlex Deucher void *ptr; 54097b2e202SAlex Deucher unsigned num_gpu_pages; 54197b2e202SAlex Deucher unsigned num_cpu_pages; 54297b2e202SAlex Deucher unsigned table_size; 543a1d29476SChristian König #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 54497b2e202SAlex Deucher struct page **pages; 545a1d29476SChristian König #endif 54697b2e202SAlex Deucher bool ready; 5474b98e0c4SAlex Xie 5484b98e0c4SAlex Xie /* Asic default pte flags */ 5494b98e0c4SAlex Xie uint64_t gart_pte_flags; 5504b98e0c4SAlex Xie 55197b2e202SAlex Deucher const struct amdgpu_gart_funcs *gart_funcs; 55297b2e202SAlex Deucher }; 55397b2e202SAlex Deucher 55497b2e202SAlex Deucher int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 55597b2e202SAlex Deucher void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 55697b2e202SAlex Deucher int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 55797b2e202SAlex Deucher void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 55897b2e202SAlex Deucher int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 55997b2e202SAlex Deucher void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 56097b2e202SAlex Deucher int amdgpu_gart_init(struct amdgpu_device *adev); 56197b2e202SAlex Deucher void amdgpu_gart_fini(struct amdgpu_device *adev); 562738f64ccSRoger.He int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 56397b2e202SAlex Deucher int pages); 564cab0b8d5SFelix Kuehling int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 56597b2e202SAlex Deucher int pages, struct page **pagelist, 5666b777607SChunming Zhou dma_addr_t *dma_addr, uint64_t flags); 5672c0d7318SChunming Zhou int amdgpu_ttm_recover_gart(struct amdgpu_device *adev); 56897b2e202SAlex Deucher 56997b2e202SAlex Deucher /* 570e60f8db5SAlex Xie * VMHUB structures, functions & helpers 571e60f8db5SAlex Xie */ 572e60f8db5SAlex Xie struct amdgpu_vmhub { 573e60f8db5SAlex Xie uint32_t ctx0_ptb_addr_lo32; 574e60f8db5SAlex Xie uint32_t ctx0_ptb_addr_hi32; 575e60f8db5SAlex Xie uint32_t vm_inv_eng0_req; 576e60f8db5SAlex Xie uint32_t vm_inv_eng0_ack; 577e60f8db5SAlex Xie uint32_t vm_context0_cntl; 578e60f8db5SAlex Xie uint32_t vm_l2_pro_fault_status; 579e60f8db5SAlex Xie uint32_t vm_l2_pro_fault_cntl; 580e60f8db5SAlex Xie }; 581e60f8db5SAlex Xie 582e60f8db5SAlex Xie /* 58397b2e202SAlex Deucher * GPU MC structures, functions & helpers 58497b2e202SAlex Deucher */ 58597b2e202SAlex Deucher struct amdgpu_mc { 58697b2e202SAlex Deucher resource_size_t aper_size; 58797b2e202SAlex Deucher resource_size_t aper_base; 58897b2e202SAlex Deucher resource_size_t agp_base; 58997b2e202SAlex Deucher /* for some chips with <= 32MB we need to lie 59097b2e202SAlex Deucher * about vram size near mc fb location */ 59197b2e202SAlex Deucher u64 mc_vram_size; 59297b2e202SAlex Deucher u64 visible_vram_size; 59397b2e202SAlex Deucher u64 gtt_size; 59497b2e202SAlex Deucher u64 gtt_start; 59597b2e202SAlex Deucher u64 gtt_end; 59697b2e202SAlex Deucher u64 vram_start; 59797b2e202SAlex Deucher u64 vram_end; 59897b2e202SAlex Deucher unsigned vram_width; 59997b2e202SAlex Deucher u64 real_vram_size; 60097b2e202SAlex Deucher int vram_mtrr; 60197b2e202SAlex Deucher u64 gtt_base_align; 60297b2e202SAlex Deucher u64 mc_mask; 60397b2e202SAlex Deucher const struct firmware *fw; /* MC firmware */ 60497b2e202SAlex Deucher uint32_t fw_version; 60597b2e202SAlex Deucher struct amdgpu_irq_src vm_fault; 60681c59f54SKen Wang uint32_t vram_type; 60750b0197aSChunming Zhou uint32_t srbm_soft_reset; 60850b0197aSChunming Zhou struct amdgpu_mode_mc_save save; 609f7c35abeSChristian König bool prt_warning; 6108fe73328SJunwei Zhang /* apertures */ 6118fe73328SJunwei Zhang u64 shared_aperture_start; 6128fe73328SJunwei Zhang u64 shared_aperture_end; 6138fe73328SJunwei Zhang u64 private_aperture_start; 6148fe73328SJunwei Zhang u64 private_aperture_end; 615e60f8db5SAlex Xie /* protects concurrent invalidation */ 616e60f8db5SAlex Xie spinlock_t invalidate_lock; 61797b2e202SAlex Deucher }; 61897b2e202SAlex Deucher 61997b2e202SAlex Deucher /* 62097b2e202SAlex Deucher * GPU doorbell structures, functions & helpers 62197b2e202SAlex Deucher */ 62297b2e202SAlex Deucher typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 62397b2e202SAlex Deucher { 62497b2e202SAlex Deucher AMDGPU_DOORBELL_KIQ = 0x000, 62597b2e202SAlex Deucher AMDGPU_DOORBELL_HIQ = 0x001, 62697b2e202SAlex Deucher AMDGPU_DOORBELL_DIQ = 0x002, 62797b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING0 = 0x010, 62897b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING1 = 0x011, 62997b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING2 = 0x012, 63097b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING3 = 0x013, 63197b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING4 = 0x014, 63297b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING5 = 0x015, 63397b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING6 = 0x016, 63497b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING7 = 0x017, 63597b2e202SAlex Deucher AMDGPU_DOORBELL_GFX_RING0 = 0x020, 63697b2e202SAlex Deucher AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 63797b2e202SAlex Deucher AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 63897b2e202SAlex Deucher AMDGPU_DOORBELL_IH = 0x1E8, 63997b2e202SAlex Deucher AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 64097b2e202SAlex Deucher AMDGPU_DOORBELL_INVALID = 0xFFFF 64197b2e202SAlex Deucher } AMDGPU_DOORBELL_ASSIGNMENT; 64297b2e202SAlex Deucher 64397b2e202SAlex Deucher struct amdgpu_doorbell { 64497b2e202SAlex Deucher /* doorbell mmio */ 64597b2e202SAlex Deucher resource_size_t base; 64697b2e202SAlex Deucher resource_size_t size; 64797b2e202SAlex Deucher u32 __iomem *ptr; 64897b2e202SAlex Deucher u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 64997b2e202SAlex Deucher }; 65097b2e202SAlex Deucher 65139807b93SKen Wang /* 65239807b93SKen Wang * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 65339807b93SKen Wang */ 65439807b93SKen Wang typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 65539807b93SKen Wang { 65639807b93SKen Wang /* 65739807b93SKen Wang * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 65839807b93SKen Wang * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 65939807b93SKen Wang * Compute related doorbells are allocated from 0x00 to 0x8a 66039807b93SKen Wang */ 66139807b93SKen Wang 66239807b93SKen Wang 66339807b93SKen Wang /* kernel scheduling */ 66439807b93SKen Wang AMDGPU_DOORBELL64_KIQ = 0x00, 66539807b93SKen Wang 66639807b93SKen Wang /* HSA interface queue and debug queue */ 66739807b93SKen Wang AMDGPU_DOORBELL64_HIQ = 0x01, 66839807b93SKen Wang AMDGPU_DOORBELL64_DIQ = 0x02, 66939807b93SKen Wang 67039807b93SKen Wang /* Compute engines */ 67139807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 67239807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 67339807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 67439807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 67539807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 67639807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 67739807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 67839807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 67939807b93SKen Wang 68039807b93SKen Wang /* User queue doorbell range (128 doorbells) */ 68139807b93SKen Wang AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 68239807b93SKen Wang AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 68339807b93SKen Wang 68439807b93SKen Wang /* Graphics engine */ 68539807b93SKen Wang AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 68639807b93SKen Wang 68739807b93SKen Wang /* 68839807b93SKen Wang * Other graphics doorbells can be allocated here: from 0x8c to 0xef 68939807b93SKen Wang * Graphics voltage island aperture 1 69039807b93SKen Wang * default non-graphics QWORD index is 0xF0 - 0xFF inclusive 69139807b93SKen Wang */ 69239807b93SKen Wang 69339807b93SKen Wang /* sDMA engines */ 69439807b93SKen Wang AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 69539807b93SKen Wang AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 69639807b93SKen Wang AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 69739807b93SKen Wang AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 69839807b93SKen Wang 69939807b93SKen Wang /* Interrupt handler */ 70039807b93SKen Wang AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 70139807b93SKen Wang AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 70239807b93SKen Wang AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 70339807b93SKen Wang 704e6b3ecb4SMonk Liu /* VCN engine use 32 bits doorbell */ 705e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 706e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 707e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 708e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 709e6b3ecb4SMonk Liu 710e6b3ecb4SMonk Liu /* overlap the doorbell assignment with VCN as they are mutually exclusive 711e6b3ecb4SMonk Liu * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 712e6b3ecb4SMonk Liu */ 713e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_RING0_1 = 0xF8, 714e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_RING2_3 = 0xF9, 715e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_RING4_5 = 0xFA, 716e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_RING6_7 = 0xFB, 717e6b3ecb4SMonk Liu 718e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC, 719e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD, 720e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE, 721e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF, 72239807b93SKen Wang 72339807b93SKen Wang AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 72439807b93SKen Wang AMDGPU_DOORBELL64_INVALID = 0xFFFF 72539807b93SKen Wang } AMDGPU_DOORBELL64_ASSIGNMENT; 72639807b93SKen Wang 72739807b93SKen Wang 72897b2e202SAlex Deucher void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 72997b2e202SAlex Deucher phys_addr_t *aperture_base, 73097b2e202SAlex Deucher size_t *aperture_size, 73197b2e202SAlex Deucher size_t *start_offset); 73297b2e202SAlex Deucher 73397b2e202SAlex Deucher /* 73497b2e202SAlex Deucher * IRQS. 73597b2e202SAlex Deucher */ 73697b2e202SAlex Deucher 73797b2e202SAlex Deucher struct amdgpu_flip_work { 738325cbba1SMichel Dänzer struct delayed_work flip_work; 73997b2e202SAlex Deucher struct work_struct unpin_work; 74097b2e202SAlex Deucher struct amdgpu_device *adev; 74197b2e202SAlex Deucher int crtc_id; 742325cbba1SMichel Dänzer u32 target_vblank; 74397b2e202SAlex Deucher uint64_t base; 74497b2e202SAlex Deucher struct drm_pending_vblank_event *event; 745765e7fbfSChristian König struct amdgpu_bo *old_abo; 746f54d1867SChris Wilson struct dma_fence *excl; 7471ffd2652SChristian König unsigned shared_count; 748f54d1867SChris Wilson struct dma_fence **shared; 749f54d1867SChris Wilson struct dma_fence_cb cb; 750cb9e59d7SAlex Deucher bool async; 75197b2e202SAlex Deucher }; 75297b2e202SAlex Deucher 75397b2e202SAlex Deucher 75497b2e202SAlex Deucher /* 75597b2e202SAlex Deucher * CP & rings. 75697b2e202SAlex Deucher */ 75797b2e202SAlex Deucher 75897b2e202SAlex Deucher struct amdgpu_ib { 75997b2e202SAlex Deucher struct amdgpu_sa_bo *sa_bo; 76097b2e202SAlex Deucher uint32_t length_dw; 76197b2e202SAlex Deucher uint64_t gpu_addr; 76297b2e202SAlex Deucher uint32_t *ptr; 763de807f81SJammy Zhou uint32_t flags; 76497b2e202SAlex Deucher }; 76597b2e202SAlex Deucher 76662250a91SNils Wallménius extern const struct amd_sched_backend_ops amdgpu_sched_ops; 767c1b69ed0SChunming Zhou 76850838c8cSChristian König int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 769c5637837SMonk Liu struct amdgpu_job **job, struct amdgpu_vm *vm); 770d71518b5SChristian König int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 771d71518b5SChristian König struct amdgpu_job **job); 772b6723c8dSMonk Liu 773a5fb4ec2SChristian König void amdgpu_job_free_resources(struct amdgpu_job *job); 77450838c8cSChristian König void amdgpu_job_free(struct amdgpu_job *job); 775d71518b5SChristian König int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 7762bd9ccfaSChristian König struct amd_sched_entity *entity, void *owner, 777f54d1867SChris Wilson struct dma_fence **f); 7788b4fb00bSChristian König 77997b2e202SAlex Deucher /* 78097b2e202SAlex Deucher * context related structures 78197b2e202SAlex Deucher */ 78297b2e202SAlex Deucher 78321c16bf6SChristian König struct amdgpu_ctx_ring { 78421c16bf6SChristian König uint64_t sequence; 785f54d1867SChris Wilson struct dma_fence **fences; 78691404fb2SChristian König struct amd_sched_entity entity; 78721c16bf6SChristian König }; 78821c16bf6SChristian König 78997b2e202SAlex Deucher struct amdgpu_ctx { 79097b2e202SAlex Deucher struct kref refcount; 7919cb7e5a9SChunming Zhou struct amdgpu_device *adev; 792d94aed5aSMarek Olšák unsigned reset_counter; 79321c16bf6SChristian König spinlock_t ring_lock; 794f54d1867SChris Wilson struct dma_fence **fences; 79521c16bf6SChristian König struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 796753ad49cSMonk Liu bool preamble_presented; 79797b2e202SAlex Deucher }; 79897b2e202SAlex Deucher 79997b2e202SAlex Deucher struct amdgpu_ctx_mgr { 80097b2e202SAlex Deucher struct amdgpu_device *adev; 8010147ee0fSMarek Olšák struct mutex lock; 8020b492a4cSAlex Deucher /* protected by lock */ 8030b492a4cSAlex Deucher struct idr ctx_handles; 80497b2e202SAlex Deucher }; 80597b2e202SAlex Deucher 8060b492a4cSAlex Deucher struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 8070b492a4cSAlex Deucher int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 8080b492a4cSAlex Deucher 80921c16bf6SChristian König uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 810f54d1867SChris Wilson struct dma_fence *fence); 811f54d1867SChris Wilson struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 81221c16bf6SChristian König struct amdgpu_ring *ring, uint64_t seq); 81321c16bf6SChristian König 8140b492a4cSAlex Deucher int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 8150b492a4cSAlex Deucher struct drm_file *filp); 8160b492a4cSAlex Deucher 817efd4ccb5SChristian König void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 818efd4ccb5SChristian König void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 8190b492a4cSAlex Deucher 82097b2e202SAlex Deucher /* 82197b2e202SAlex Deucher * file private structure 82297b2e202SAlex Deucher */ 82397b2e202SAlex Deucher 82497b2e202SAlex Deucher struct amdgpu_fpriv { 82597b2e202SAlex Deucher struct amdgpu_vm vm; 826b85891bdSJunwei Zhang struct amdgpu_bo_va *prt_va; 82797b2e202SAlex Deucher struct mutex bo_list_lock; 82897b2e202SAlex Deucher struct idr bo_list_handles; 82997b2e202SAlex Deucher struct amdgpu_ctx_mgr ctx_mgr; 830f1892138SChunming Zhou u32 vram_lost_counter; 83197b2e202SAlex Deucher }; 83297b2e202SAlex Deucher 83397b2e202SAlex Deucher /* 83497b2e202SAlex Deucher * residency list 83597b2e202SAlex Deucher */ 83697b2e202SAlex Deucher 83797b2e202SAlex Deucher struct amdgpu_bo_list { 83897b2e202SAlex Deucher struct mutex lock; 83997b2e202SAlex Deucher struct amdgpu_bo *gds_obj; 84097b2e202SAlex Deucher struct amdgpu_bo *gws_obj; 84197b2e202SAlex Deucher struct amdgpu_bo *oa_obj; 842211dff55SChristian König unsigned first_userptr; 84397b2e202SAlex Deucher unsigned num_entries; 84497b2e202SAlex Deucher struct amdgpu_bo_list_entry *array; 84597b2e202SAlex Deucher }; 84697b2e202SAlex Deucher 84797b2e202SAlex Deucher struct amdgpu_bo_list * 84897b2e202SAlex Deucher amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 849636ce25cSChristian König void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 850636ce25cSChristian König struct list_head *validated); 85197b2e202SAlex Deucher void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 85297b2e202SAlex Deucher void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 85397b2e202SAlex Deucher 85497b2e202SAlex Deucher /* 85597b2e202SAlex Deucher * GFX stuff 85697b2e202SAlex Deucher */ 85797b2e202SAlex Deucher #include "clearstate_defs.h" 85897b2e202SAlex Deucher 85979e5412cSAlex Deucher struct amdgpu_rlc_funcs { 86079e5412cSAlex Deucher void (*enter_safe_mode)(struct amdgpu_device *adev); 86179e5412cSAlex Deucher void (*exit_safe_mode)(struct amdgpu_device *adev); 86279e5412cSAlex Deucher }; 86379e5412cSAlex Deucher 86497b2e202SAlex Deucher struct amdgpu_rlc { 86597b2e202SAlex Deucher /* for power gating */ 86697b2e202SAlex Deucher struct amdgpu_bo *save_restore_obj; 86797b2e202SAlex Deucher uint64_t save_restore_gpu_addr; 86897b2e202SAlex Deucher volatile uint32_t *sr_ptr; 86997b2e202SAlex Deucher const u32 *reg_list; 87097b2e202SAlex Deucher u32 reg_list_size; 87197b2e202SAlex Deucher /* for clear state */ 87297b2e202SAlex Deucher struct amdgpu_bo *clear_state_obj; 87397b2e202SAlex Deucher uint64_t clear_state_gpu_addr; 87497b2e202SAlex Deucher volatile uint32_t *cs_ptr; 87597b2e202SAlex Deucher const struct cs_section_def *cs_data; 87697b2e202SAlex Deucher u32 clear_state_size; 87797b2e202SAlex Deucher /* for cp tables */ 87897b2e202SAlex Deucher struct amdgpu_bo *cp_table_obj; 87997b2e202SAlex Deucher uint64_t cp_table_gpu_addr; 88097b2e202SAlex Deucher volatile uint32_t *cp_table_ptr; 88197b2e202SAlex Deucher u32 cp_table_size; 88279e5412cSAlex Deucher 88379e5412cSAlex Deucher /* safe mode for updating CG/PG state */ 88479e5412cSAlex Deucher bool in_safe_mode; 88579e5412cSAlex Deucher const struct amdgpu_rlc_funcs *funcs; 8862b6cd977SEric Huang 8872b6cd977SEric Huang /* for firmware data */ 8882b6cd977SEric Huang u32 save_and_restore_offset; 8892b6cd977SEric Huang u32 clear_state_descriptor_offset; 8902b6cd977SEric Huang u32 avail_scratch_ram_locations; 8912b6cd977SEric Huang u32 reg_restore_list_size; 8922b6cd977SEric Huang u32 reg_list_format_start; 8932b6cd977SEric Huang u32 reg_list_format_separate_start; 8942b6cd977SEric Huang u32 starting_offsets_start; 8952b6cd977SEric Huang u32 reg_list_format_size_bytes; 8962b6cd977SEric Huang u32 reg_list_size_bytes; 8972b6cd977SEric Huang 8982b6cd977SEric Huang u32 *register_list_format; 8992b6cd977SEric Huang u32 *register_restore; 90097b2e202SAlex Deucher }; 90197b2e202SAlex Deucher 90278c16834SAndres Rodriguez #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 90378c16834SAndres Rodriguez 90497b2e202SAlex Deucher struct amdgpu_mec { 90597b2e202SAlex Deucher struct amdgpu_bo *hpd_eop_obj; 90697b2e202SAlex Deucher u64 hpd_eop_gpu_addr; 907b1023571SKen Wang struct amdgpu_bo *mec_fw_obj; 908b1023571SKen Wang u64 mec_fw_gpu_addr; 90997b2e202SAlex Deucher u32 num_mec; 91042794b27SAndres Rodriguez u32 num_pipe_per_mec; 91142794b27SAndres Rodriguez u32 num_queue_per_pipe; 91259a82d7dSXiangliang Yu void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 91378c16834SAndres Rodriguez 91478c16834SAndres Rodriguez /* These are the resources for which amdgpu takes ownership */ 91578c16834SAndres Rodriguez DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 91697b2e202SAlex Deucher }; 91797b2e202SAlex Deucher 9184e638ae9SXiangliang Yu struct amdgpu_kiq { 9194e638ae9SXiangliang Yu u64 eop_gpu_addr; 9204e638ae9SXiangliang Yu struct amdgpu_bo *eop_obj; 921cdf6adb2SShaoyun Liu struct mutex ring_mutex; 9224e638ae9SXiangliang Yu struct amdgpu_ring ring; 9234e638ae9SXiangliang Yu struct amdgpu_irq_src irq; 9244e638ae9SXiangliang Yu }; 9254e638ae9SXiangliang Yu 92697b2e202SAlex Deucher /* 92797b2e202SAlex Deucher * GPU scratch registers structures, functions & helpers 92897b2e202SAlex Deucher */ 92997b2e202SAlex Deucher struct amdgpu_scratch { 93097b2e202SAlex Deucher unsigned num_reg; 93197b2e202SAlex Deucher uint32_t reg_base; 93250261151SNils Wallménius uint32_t free_mask; 93397b2e202SAlex Deucher }; 93497b2e202SAlex Deucher 93597b2e202SAlex Deucher /* 93697b2e202SAlex Deucher * GFX configurations 93797b2e202SAlex Deucher */ 938e3fa7630SAlex Deucher #define AMDGPU_GFX_MAX_SE 4 939e3fa7630SAlex Deucher #define AMDGPU_GFX_MAX_SH_PER_SE 2 940e3fa7630SAlex Deucher 941e3fa7630SAlex Deucher struct amdgpu_rb_config { 942e3fa7630SAlex Deucher uint32_t rb_backend_disable; 943e3fa7630SAlex Deucher uint32_t user_rb_backend_disable; 944e3fa7630SAlex Deucher uint32_t raster_config; 945e3fa7630SAlex Deucher uint32_t raster_config_1; 946e3fa7630SAlex Deucher }; 947e3fa7630SAlex Deucher 948d0e95758SAndrey Grodzovsky struct gb_addr_config { 949d0e95758SAndrey Grodzovsky uint16_t pipe_interleave_size; 950d0e95758SAndrey Grodzovsky uint8_t num_pipes; 951d0e95758SAndrey Grodzovsky uint8_t max_compress_frags; 952d0e95758SAndrey Grodzovsky uint8_t num_banks; 953d0e95758SAndrey Grodzovsky uint8_t num_se; 954d0e95758SAndrey Grodzovsky uint8_t num_rb_per_se; 955d0e95758SAndrey Grodzovsky }; 956d0e95758SAndrey Grodzovsky 957ea323f88SJunwei Zhang struct amdgpu_gfx_config { 95897b2e202SAlex Deucher unsigned max_shader_engines; 95997b2e202SAlex Deucher unsigned max_tile_pipes; 96097b2e202SAlex Deucher unsigned max_cu_per_sh; 96197b2e202SAlex Deucher unsigned max_sh_per_se; 96297b2e202SAlex Deucher unsigned max_backends_per_se; 96397b2e202SAlex Deucher unsigned max_texture_channel_caches; 96497b2e202SAlex Deucher unsigned max_gprs; 96597b2e202SAlex Deucher unsigned max_gs_threads; 96697b2e202SAlex Deucher unsigned max_hw_contexts; 96797b2e202SAlex Deucher unsigned sc_prim_fifo_size_frontend; 96897b2e202SAlex Deucher unsigned sc_prim_fifo_size_backend; 96997b2e202SAlex Deucher unsigned sc_hiz_tile_fifo_size; 97097b2e202SAlex Deucher unsigned sc_earlyz_tile_fifo_size; 97197b2e202SAlex Deucher 97297b2e202SAlex Deucher unsigned num_tile_pipes; 97397b2e202SAlex Deucher unsigned backend_enable_mask; 97497b2e202SAlex Deucher unsigned mem_max_burst_length_bytes; 97597b2e202SAlex Deucher unsigned mem_row_size_in_kb; 97697b2e202SAlex Deucher unsigned shader_engine_tile_size; 97797b2e202SAlex Deucher unsigned num_gpus; 97897b2e202SAlex Deucher unsigned multi_gpu_tile_size; 97997b2e202SAlex Deucher unsigned mc_arb_ramcfg; 98097b2e202SAlex Deucher unsigned gb_addr_config; 9818f8e00c1SAlex Deucher unsigned num_rbs; 982408bfe7cSJunwei Zhang unsigned gs_vgt_table_depth; 983408bfe7cSJunwei Zhang unsigned gs_prim_buffer_depth; 98497b2e202SAlex Deucher 98597b2e202SAlex Deucher uint32_t tile_mode_array[32]; 98697b2e202SAlex Deucher uint32_t macrotile_mode_array[16]; 987e3fa7630SAlex Deucher 988d0e95758SAndrey Grodzovsky struct gb_addr_config gb_addr_config_fields; 989e3fa7630SAlex Deucher struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 990df6e2c4aSJunwei Zhang 991df6e2c4aSJunwei Zhang /* gfx configure feature */ 992df6e2c4aSJunwei Zhang uint32_t double_offchip_lds_buf; 99397b2e202SAlex Deucher }; 99497b2e202SAlex Deucher 9957dae69a2SAlex Deucher struct amdgpu_cu_info { 9967dae69a2SAlex Deucher uint32_t number; /* total active CU number */ 9977dae69a2SAlex Deucher uint32_t ao_cu_mask; 998408bfe7cSJunwei Zhang uint32_t wave_front_size; 9997dae69a2SAlex Deucher uint32_t bitmap[4][4]; 10007dae69a2SAlex Deucher }; 10017dae69a2SAlex Deucher 1002b95e31fdSAlex Deucher struct amdgpu_gfx_funcs { 1003b95e31fdSAlex Deucher /* get the gpu clock counter */ 1004b95e31fdSAlex Deucher uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 10059559ef5bSTom St Denis void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 1006472259f0STom St Denis void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); 1007c5a60ce8STom St Denis void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); 1008c5a60ce8STom St Denis void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); 1009b95e31fdSAlex Deucher }; 1010b95e31fdSAlex Deucher 1011bce23e00SAlex Deucher struct amdgpu_ngg_buf { 1012bce23e00SAlex Deucher struct amdgpu_bo *bo; 1013bce23e00SAlex Deucher uint64_t gpu_addr; 1014bce23e00SAlex Deucher uint32_t size; 1015bce23e00SAlex Deucher uint32_t bo_size; 1016bce23e00SAlex Deucher }; 1017bce23e00SAlex Deucher 1018bce23e00SAlex Deucher enum { 1019af8baf15SGuenter Roeck NGG_PRIM = 0, 1020af8baf15SGuenter Roeck NGG_POS, 1021af8baf15SGuenter Roeck NGG_CNTL, 1022af8baf15SGuenter Roeck NGG_PARAM, 1023bce23e00SAlex Deucher NGG_BUF_MAX 1024bce23e00SAlex Deucher }; 1025bce23e00SAlex Deucher 1026bce23e00SAlex Deucher struct amdgpu_ngg { 1027bce23e00SAlex Deucher struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; 1028bce23e00SAlex Deucher uint32_t gds_reserve_addr; 1029bce23e00SAlex Deucher uint32_t gds_reserve_size; 1030bce23e00SAlex Deucher bool init; 1031bce23e00SAlex Deucher }; 1032bce23e00SAlex Deucher 103397b2e202SAlex Deucher struct amdgpu_gfx { 103497b2e202SAlex Deucher struct mutex gpu_clock_mutex; 1035ea323f88SJunwei Zhang struct amdgpu_gfx_config config; 103697b2e202SAlex Deucher struct amdgpu_rlc rlc; 103797b2e202SAlex Deucher struct amdgpu_mec mec; 10384e638ae9SXiangliang Yu struct amdgpu_kiq kiq; 103997b2e202SAlex Deucher struct amdgpu_scratch scratch; 104097b2e202SAlex Deucher const struct firmware *me_fw; /* ME firmware */ 104197b2e202SAlex Deucher uint32_t me_fw_version; 104297b2e202SAlex Deucher const struct firmware *pfp_fw; /* PFP firmware */ 104397b2e202SAlex Deucher uint32_t pfp_fw_version; 104497b2e202SAlex Deucher const struct firmware *ce_fw; /* CE firmware */ 104597b2e202SAlex Deucher uint32_t ce_fw_version; 104697b2e202SAlex Deucher const struct firmware *rlc_fw; /* RLC firmware */ 104797b2e202SAlex Deucher uint32_t rlc_fw_version; 104897b2e202SAlex Deucher const struct firmware *mec_fw; /* MEC firmware */ 104997b2e202SAlex Deucher uint32_t mec_fw_version; 105097b2e202SAlex Deucher const struct firmware *mec2_fw; /* MEC2 firmware */ 105197b2e202SAlex Deucher uint32_t mec2_fw_version; 105202558a00SKen Wang uint32_t me_feature_version; 105302558a00SKen Wang uint32_t ce_feature_version; 105402558a00SKen Wang uint32_t pfp_feature_version; 1055351643d7SJammy Zhou uint32_t rlc_feature_version; 1056351643d7SJammy Zhou uint32_t mec_feature_version; 1057351643d7SJammy Zhou uint32_t mec2_feature_version; 105897b2e202SAlex Deucher struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 105997b2e202SAlex Deucher unsigned num_gfx_rings; 106097b2e202SAlex Deucher struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 106197b2e202SAlex Deucher unsigned num_compute_rings; 106297b2e202SAlex Deucher struct amdgpu_irq_src eop_irq; 106397b2e202SAlex Deucher struct amdgpu_irq_src priv_reg_irq; 106497b2e202SAlex Deucher struct amdgpu_irq_src priv_inst_irq; 106597b2e202SAlex Deucher /* gfx status */ 106697b2e202SAlex Deucher uint32_t gfx_current_status; 1067a101a899SKen Wang /* ce ram size*/ 1068a101a899SKen Wang unsigned ce_ram_size; 10697dae69a2SAlex Deucher struct amdgpu_cu_info cu_info; 1070b95e31fdSAlex Deucher const struct amdgpu_gfx_funcs *funcs; 10713d7c6384SChunming Zhou 10723d7c6384SChunming Zhou /* reset mask */ 10733d7c6384SChunming Zhou uint32_t grbm_soft_reset; 10743d7c6384SChunming Zhou uint32_t srbm_soft_reset; 1075223049cdSMonk Liu bool in_reset; 1076b4e40676SDavid Panariti /* s3/s4 mask */ 1077b4e40676SDavid Panariti bool in_suspend; 1078bce23e00SAlex Deucher /* NGG */ 1079bce23e00SAlex Deucher struct amdgpu_ngg ngg; 108097b2e202SAlex Deucher }; 108197b2e202SAlex Deucher 1082b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 108397b2e202SAlex Deucher unsigned size, struct amdgpu_ib *ib); 10844d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 1085f54d1867SChris Wilson struct dma_fence *f); 1086b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 108750ddc75eSJunwei Zhang struct amdgpu_ib *ibs, struct amdgpu_job *job, 108850ddc75eSJunwei Zhang struct dma_fence **f); 108997b2e202SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev); 109097b2e202SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 109197b2e202SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 109297b2e202SAlex Deucher 109397b2e202SAlex Deucher /* 109497b2e202SAlex Deucher * CS. 109597b2e202SAlex Deucher */ 109697b2e202SAlex Deucher struct amdgpu_cs_chunk { 109797b2e202SAlex Deucher uint32_t chunk_id; 109897b2e202SAlex Deucher uint32_t length_dw; 1099758ac17fSChristian König void *kdata; 110097b2e202SAlex Deucher }; 110197b2e202SAlex Deucher 110297b2e202SAlex Deucher struct amdgpu_cs_parser { 110397b2e202SAlex Deucher struct amdgpu_device *adev; 110497b2e202SAlex Deucher struct drm_file *filp; 11053cb485f3SChristian König struct amdgpu_ctx *ctx; 1106c3cca41eSChristian König 110797b2e202SAlex Deucher /* chunks */ 110897b2e202SAlex Deucher unsigned nchunks; 110997b2e202SAlex Deucher struct amdgpu_cs_chunk *chunks; 1110c3cca41eSChristian König 111150838c8cSChristian König /* scheduler job object */ 111250838c8cSChristian König struct amdgpu_job *job; 1113c3cca41eSChristian König 1114c3cca41eSChristian König /* buffer objects */ 1115c3cca41eSChristian König struct ww_acquire_ctx ticket; 1116c3cca41eSChristian König struct amdgpu_bo_list *bo_list; 111756467ebfSChristian König struct amdgpu_bo_list_entry vm_pd; 111897b2e202SAlex Deucher struct list_head validated; 1119f54d1867SChris Wilson struct dma_fence *fence; 1120f69f90a1SChristian König uint64_t bytes_moved_threshold; 1121f69f90a1SChristian König uint64_t bytes_moved; 1122662bfa61SChristian König struct amdgpu_bo_list_entry *evictable; 112397b2e202SAlex Deucher 112497b2e202SAlex Deucher /* user fence */ 112591acbeb6SChristian König struct amdgpu_bo_list_entry uf_entry; 112697b2e202SAlex Deucher }; 112797b2e202SAlex Deucher 1128753ad49cSMonk Liu #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ 1129753ad49cSMonk Liu #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ 1130753ad49cSMonk Liu #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ 1131753ad49cSMonk Liu 1132bb977d37SChunming Zhou struct amdgpu_job { 1133bb977d37SChunming Zhou struct amd_sched_job base; 1134bb977d37SChunming Zhou struct amdgpu_device *adev; 1135c5637837SMonk Liu struct amdgpu_vm *vm; 1136b07c60c0SChristian König struct amdgpu_ring *ring; 1137e86f9ceeSChristian König struct amdgpu_sync sync; 1138a340c7bcSChunming Zhou struct amdgpu_sync dep_sync; 1139df83d1ebSChunming Zhou struct amdgpu_sync sched_sync; 1140bb977d37SChunming Zhou struct amdgpu_ib *ibs; 1141f54d1867SChris Wilson struct dma_fence *fence; /* the hw fence */ 1142753ad49cSMonk Liu uint32_t preamble_status; 1143bb977d37SChunming Zhou uint32_t num_ibs; 1144e2840221SChristian König void *owner; 11453aecd24cSMonk Liu uint64_t fence_ctx; /* the fence_context this job uses */ 1146fd53be30SChunming Zhou bool vm_needs_flush; 1147d88bf583SChristian König unsigned vm_id; 1148d88bf583SChristian König uint64_t vm_pd_addr; 1149d88bf583SChristian König uint32_t gds_base, gds_size; 1150d88bf583SChristian König uint32_t gws_base, gws_size; 1151d88bf583SChristian König uint32_t oa_base, oa_size; 1152758ac17fSChristian König 1153758ac17fSChristian König /* user fence handling */ 1154b5f5acbcSChristian König uint64_t uf_addr; 1155758ac17fSChristian König uint64_t uf_sequence; 1156758ac17fSChristian König 1157bb977d37SChunming Zhou }; 1158a6db8a33SJunwei Zhang #define to_amdgpu_job(sched_job) \ 1159a6db8a33SJunwei Zhang container_of((sched_job), struct amdgpu_job, base) 1160bb977d37SChunming Zhou 11617270f839SChristian König static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 11627270f839SChristian König uint32_t ib_idx, int idx) 116397b2e202SAlex Deucher { 116450838c8cSChristian König return p->job->ibs[ib_idx].ptr[idx]; 116597b2e202SAlex Deucher } 116697b2e202SAlex Deucher 11677270f839SChristian König static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 11687270f839SChristian König uint32_t ib_idx, int idx, 11697270f839SChristian König uint32_t value) 11707270f839SChristian König { 117150838c8cSChristian König p->job->ibs[ib_idx].ptr[idx] = value; 11727270f839SChristian König } 11737270f839SChristian König 117497b2e202SAlex Deucher /* 117597b2e202SAlex Deucher * Writeback 117697b2e202SAlex Deucher */ 117797b2e202SAlex Deucher #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 117897b2e202SAlex Deucher 117997b2e202SAlex Deucher struct amdgpu_wb { 118097b2e202SAlex Deucher struct amdgpu_bo *wb_obj; 118197b2e202SAlex Deucher volatile uint32_t *wb; 118297b2e202SAlex Deucher uint64_t gpu_addr; 118397b2e202SAlex Deucher u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 118497b2e202SAlex Deucher unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 118597b2e202SAlex Deucher }; 118697b2e202SAlex Deucher 118797b2e202SAlex Deucher int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 118897b2e202SAlex Deucher void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 11897014285aSKen Wang int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb); 11907014285aSKen Wang void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb); 119197b2e202SAlex Deucher 1192d0dd7f0cSAlex Deucher void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1193d0dd7f0cSAlex Deucher 119497b2e202SAlex Deucher /* 119597b2e202SAlex Deucher * SDMA 119697b2e202SAlex Deucher */ 1197c113ea1cSAlex Deucher struct amdgpu_sdma_instance { 119897b2e202SAlex Deucher /* SDMA firmware */ 119997b2e202SAlex Deucher const struct firmware *fw; 120097b2e202SAlex Deucher uint32_t fw_version; 1201cfa2104fSJammy Zhou uint32_t feature_version; 120297b2e202SAlex Deucher 120397b2e202SAlex Deucher struct amdgpu_ring ring; 120418111de0SJammy Zhou bool burst_nop; 120597b2e202SAlex Deucher }; 120697b2e202SAlex Deucher 1207c113ea1cSAlex Deucher struct amdgpu_sdma { 1208c113ea1cSAlex Deucher struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 120930d1574fSKen Wang #ifdef CONFIG_DRM_AMDGPU_SI 121030d1574fSKen Wang //SI DMA has a difference trap irq number for the second engine 121130d1574fSKen Wang struct amdgpu_irq_src trap_irq_1; 121230d1574fSKen Wang #endif 1213c113ea1cSAlex Deucher struct amdgpu_irq_src trap_irq; 1214c113ea1cSAlex Deucher struct amdgpu_irq_src illegal_inst_irq; 1215c113ea1cSAlex Deucher int num_instances; 1216e702a680SChunming Zhou uint32_t srbm_soft_reset; 1217c113ea1cSAlex Deucher }; 1218c113ea1cSAlex Deucher 121997b2e202SAlex Deucher /* 122097b2e202SAlex Deucher * Firmware 122197b2e202SAlex Deucher */ 1222e635ee07SHuang Rui enum amdgpu_firmware_load_type { 1223e635ee07SHuang Rui AMDGPU_FW_LOAD_DIRECT = 0, 1224e635ee07SHuang Rui AMDGPU_FW_LOAD_SMU, 1225e635ee07SHuang Rui AMDGPU_FW_LOAD_PSP, 1226e635ee07SHuang Rui }; 1227e635ee07SHuang Rui 122897b2e202SAlex Deucher struct amdgpu_firmware { 122997b2e202SAlex Deucher struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1230e635ee07SHuang Rui enum amdgpu_firmware_load_type load_type; 123197b2e202SAlex Deucher struct amdgpu_bo *fw_buf; 123297b2e202SAlex Deucher unsigned int fw_size; 12332445b227SHuang Rui unsigned int max_ucodes; 12340e5ca0d1SHuang Rui /* firmwares are loaded by psp instead of smu from vega10 */ 12350e5ca0d1SHuang Rui const struct amdgpu_psp_funcs *funcs; 12360e5ca0d1SHuang Rui struct amdgpu_bo *rbuf; 12370e5ca0d1SHuang Rui struct mutex mutex; 123897b2e202SAlex Deucher }; 123997b2e202SAlex Deucher 124097b2e202SAlex Deucher /* 124197b2e202SAlex Deucher * Benchmarking 124297b2e202SAlex Deucher */ 124397b2e202SAlex Deucher void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 124497b2e202SAlex Deucher 124597b2e202SAlex Deucher 124697b2e202SAlex Deucher /* 124797b2e202SAlex Deucher * Testing 124897b2e202SAlex Deucher */ 124997b2e202SAlex Deucher void amdgpu_test_moves(struct amdgpu_device *adev); 125097b2e202SAlex Deucher 125197b2e202SAlex Deucher /* 125297b2e202SAlex Deucher * MMU Notifier 125397b2e202SAlex Deucher */ 125497b2e202SAlex Deucher #if defined(CONFIG_MMU_NOTIFIER) 125597b2e202SAlex Deucher int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 125697b2e202SAlex Deucher void amdgpu_mn_unregister(struct amdgpu_bo *bo); 125797b2e202SAlex Deucher #else 12581d1106b0SHarry Wentland static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 125997b2e202SAlex Deucher { 126097b2e202SAlex Deucher return -ENODEV; 126197b2e202SAlex Deucher } 12621d1106b0SHarry Wentland static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 126397b2e202SAlex Deucher #endif 126497b2e202SAlex Deucher 126597b2e202SAlex Deucher /* 126697b2e202SAlex Deucher * Debugfs 126797b2e202SAlex Deucher */ 126897b2e202SAlex Deucher struct amdgpu_debugfs { 126906ab6832SNils Wallménius const struct drm_info_list *files; 127097b2e202SAlex Deucher unsigned num_files; 127197b2e202SAlex Deucher }; 127297b2e202SAlex Deucher 127397b2e202SAlex Deucher int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 127406ab6832SNils Wallménius const struct drm_info_list *files, 127597b2e202SAlex Deucher unsigned nfiles); 127697b2e202SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 127797b2e202SAlex Deucher 127897b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS) 127997b2e202SAlex Deucher int amdgpu_debugfs_init(struct drm_minor *minor); 128097b2e202SAlex Deucher #endif 128197b2e202SAlex Deucher 128250ab2533SHuang Rui int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); 128350ab2533SHuang Rui 128497b2e202SAlex Deucher /* 128597b2e202SAlex Deucher * amdgpu smumgr functions 128697b2e202SAlex Deucher */ 128797b2e202SAlex Deucher struct amdgpu_smumgr_funcs { 128897b2e202SAlex Deucher int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 128997b2e202SAlex Deucher int (*request_smu_load_fw)(struct amdgpu_device *adev); 129097b2e202SAlex Deucher int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 129197b2e202SAlex Deucher }; 129297b2e202SAlex Deucher 129397b2e202SAlex Deucher /* 129497b2e202SAlex Deucher * amdgpu smumgr 129597b2e202SAlex Deucher */ 129697b2e202SAlex Deucher struct amdgpu_smumgr { 129797b2e202SAlex Deucher struct amdgpu_bo *toc_buf; 129897b2e202SAlex Deucher struct amdgpu_bo *smu_buf; 129997b2e202SAlex Deucher /* asic priv smu data */ 130097b2e202SAlex Deucher void *priv; 130197b2e202SAlex Deucher spinlock_t smu_lock; 130297b2e202SAlex Deucher /* smumgr functions */ 130397b2e202SAlex Deucher const struct amdgpu_smumgr_funcs *smumgr_funcs; 130497b2e202SAlex Deucher /* ucode loading complete flag */ 130597b2e202SAlex Deucher uint32_t fw_flags; 130697b2e202SAlex Deucher }; 130797b2e202SAlex Deucher 130897b2e202SAlex Deucher /* 130997b2e202SAlex Deucher * ASIC specific register table accessible by UMD 131097b2e202SAlex Deucher */ 131197b2e202SAlex Deucher struct amdgpu_allowed_register_entry { 131297b2e202SAlex Deucher uint32_t reg_offset; 131397b2e202SAlex Deucher bool grbm_indexed; 131497b2e202SAlex Deucher }; 131597b2e202SAlex Deucher 131697b2e202SAlex Deucher /* 131797b2e202SAlex Deucher * ASIC specific functions. 131897b2e202SAlex Deucher */ 131997b2e202SAlex Deucher struct amdgpu_asic_funcs { 132097b2e202SAlex Deucher bool (*read_disabled_bios)(struct amdgpu_device *adev); 13217946b878SAlex Deucher bool (*read_bios_from_rom)(struct amdgpu_device *adev, 13227946b878SAlex Deucher u8 *bios, u32 length_bytes); 132397b2e202SAlex Deucher int (*read_register)(struct amdgpu_device *adev, u32 se_num, 132497b2e202SAlex Deucher u32 sh_num, u32 reg_offset, u32 *value); 132597b2e202SAlex Deucher void (*set_vga_state)(struct amdgpu_device *adev, bool state); 132697b2e202SAlex Deucher int (*reset)(struct amdgpu_device *adev); 132797b2e202SAlex Deucher /* get the reference clock */ 132897b2e202SAlex Deucher u32 (*get_xclk)(struct amdgpu_device *adev); 132997b2e202SAlex Deucher /* MM block clocks */ 133097b2e202SAlex Deucher int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 133197b2e202SAlex Deucher int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1332841686dfSMaruthi Bayyavarapu /* static power management */ 1333841686dfSMaruthi Bayyavarapu int (*get_pcie_lanes)(struct amdgpu_device *adev); 1334841686dfSMaruthi Bayyavarapu void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 1335bbf282d8SAlex Deucher /* get config memsize register */ 1336bbf282d8SAlex Deucher u32 (*get_config_memsize)(struct amdgpu_device *adev); 133797b2e202SAlex Deucher }; 133897b2e202SAlex Deucher 133997b2e202SAlex Deucher /* 134097b2e202SAlex Deucher * IOCTL. 134197b2e202SAlex Deucher */ 134297b2e202SAlex Deucher int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 134397b2e202SAlex Deucher struct drm_file *filp); 134497b2e202SAlex Deucher int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 134597b2e202SAlex Deucher struct drm_file *filp); 134697b2e202SAlex Deucher 134797b2e202SAlex Deucher int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 134897b2e202SAlex Deucher struct drm_file *filp); 134997b2e202SAlex Deucher int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 135097b2e202SAlex Deucher struct drm_file *filp); 135197b2e202SAlex Deucher int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 135297b2e202SAlex Deucher struct drm_file *filp); 135397b2e202SAlex Deucher int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 135497b2e202SAlex Deucher struct drm_file *filp); 135597b2e202SAlex Deucher int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 135697b2e202SAlex Deucher struct drm_file *filp); 135797b2e202SAlex Deucher int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 135897b2e202SAlex Deucher struct drm_file *filp); 135997b2e202SAlex Deucher int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 136097b2e202SAlex Deucher int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1361eef18a82SJunwei Zhang int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 1362eef18a82SJunwei Zhang struct drm_file *filp); 136397b2e202SAlex Deucher 136497b2e202SAlex Deucher int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 136597b2e202SAlex Deucher struct drm_file *filp); 136697b2e202SAlex Deucher 136797b2e202SAlex Deucher /* VRAM scratch page for HDP bug, default vram page */ 136897b2e202SAlex Deucher struct amdgpu_vram_scratch { 136997b2e202SAlex Deucher struct amdgpu_bo *robj; 137097b2e202SAlex Deucher volatile uint32_t *ptr; 137197b2e202SAlex Deucher u64 gpu_addr; 137297b2e202SAlex Deucher }; 137397b2e202SAlex Deucher 137497b2e202SAlex Deucher /* 137597b2e202SAlex Deucher * ACPI 137697b2e202SAlex Deucher */ 137797b2e202SAlex Deucher struct amdgpu_atif_notification_cfg { 137897b2e202SAlex Deucher bool enabled; 137997b2e202SAlex Deucher int command_code; 138097b2e202SAlex Deucher }; 138197b2e202SAlex Deucher 138297b2e202SAlex Deucher struct amdgpu_atif_notifications { 138397b2e202SAlex Deucher bool display_switch; 138497b2e202SAlex Deucher bool expansion_mode_change; 138597b2e202SAlex Deucher bool thermal_state; 138697b2e202SAlex Deucher bool forced_power_state; 138797b2e202SAlex Deucher bool system_power_state; 138897b2e202SAlex Deucher bool display_conf_change; 138997b2e202SAlex Deucher bool px_gfx_switch; 139097b2e202SAlex Deucher bool brightness_change; 139197b2e202SAlex Deucher bool dgpu_display_event; 139297b2e202SAlex Deucher }; 139397b2e202SAlex Deucher 139497b2e202SAlex Deucher struct amdgpu_atif_functions { 139597b2e202SAlex Deucher bool system_params; 139697b2e202SAlex Deucher bool sbios_requests; 139797b2e202SAlex Deucher bool select_active_disp; 139897b2e202SAlex Deucher bool lid_state; 139997b2e202SAlex Deucher bool get_tv_standard; 140097b2e202SAlex Deucher bool set_tv_standard; 140197b2e202SAlex Deucher bool get_panel_expansion_mode; 140297b2e202SAlex Deucher bool set_panel_expansion_mode; 140397b2e202SAlex Deucher bool temperature_change; 140497b2e202SAlex Deucher bool graphics_device_types; 140597b2e202SAlex Deucher }; 140697b2e202SAlex Deucher 140797b2e202SAlex Deucher struct amdgpu_atif { 140897b2e202SAlex Deucher struct amdgpu_atif_notifications notifications; 140997b2e202SAlex Deucher struct amdgpu_atif_functions functions; 141097b2e202SAlex Deucher struct amdgpu_atif_notification_cfg notification_cfg; 141197b2e202SAlex Deucher struct amdgpu_encoder *encoder_for_bl; 141297b2e202SAlex Deucher }; 141397b2e202SAlex Deucher 141497b2e202SAlex Deucher struct amdgpu_atcs_functions { 141597b2e202SAlex Deucher bool get_ext_state; 141697b2e202SAlex Deucher bool pcie_perf_req; 141797b2e202SAlex Deucher bool pcie_dev_rdy; 141897b2e202SAlex Deucher bool pcie_bus_width; 141997b2e202SAlex Deucher }; 142097b2e202SAlex Deucher 142197b2e202SAlex Deucher struct amdgpu_atcs { 142297b2e202SAlex Deucher struct amdgpu_atcs_functions functions; 142397b2e202SAlex Deucher }; 142497b2e202SAlex Deucher 142597b2e202SAlex Deucher /* 1426d03846afSChunming Zhou * CGS 1427d03846afSChunming Zhou */ 1428110e6f26SDave Airlie struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1429110e6f26SDave Airlie void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1430a8fe58ceSMaruthi Bayyavarapu 1431a8fe58ceSMaruthi Bayyavarapu /* 143297b2e202SAlex Deucher * Core structure, functions and helpers. 143397b2e202SAlex Deucher */ 143497b2e202SAlex Deucher typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 143597b2e202SAlex Deucher typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 143697b2e202SAlex Deucher 143797b2e202SAlex Deucher typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 143897b2e202SAlex Deucher typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 143997b2e202SAlex Deucher 14400c49e0b8SChunming Zhou #define AMDGPU_RESET_MAGIC_NUM 64 144197b2e202SAlex Deucher struct amdgpu_device { 144297b2e202SAlex Deucher struct device *dev; 144397b2e202SAlex Deucher struct drm_device *ddev; 144497b2e202SAlex Deucher struct pci_dev *pdev; 144597b2e202SAlex Deucher 1446a8fe58ceSMaruthi Bayyavarapu #ifdef CONFIG_DRM_AMD_ACP 1447a8fe58ceSMaruthi Bayyavarapu struct amdgpu_acp acp; 1448a8fe58ceSMaruthi Bayyavarapu #endif 1449a8fe58ceSMaruthi Bayyavarapu 145097b2e202SAlex Deucher /* ASIC */ 14512f7d10b3SJammy Zhou enum amd_asic_type asic_type; 145297b2e202SAlex Deucher uint32_t family; 145397b2e202SAlex Deucher uint32_t rev_id; 145497b2e202SAlex Deucher uint32_t external_rev_id; 145597b2e202SAlex Deucher unsigned long flags; 145697b2e202SAlex Deucher int usec_timeout; 145797b2e202SAlex Deucher const struct amdgpu_asic_funcs *asic_funcs; 145897b2e202SAlex Deucher bool shutdown; 145997b2e202SAlex Deucher bool need_dma32; 146097b2e202SAlex Deucher bool accel_working; 146197b2e202SAlex Deucher struct work_struct reset_work; 146297b2e202SAlex Deucher struct notifier_block acpi_nb; 146397b2e202SAlex Deucher struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 146497b2e202SAlex Deucher struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 146597b2e202SAlex Deucher unsigned debugfs_count; 146697b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS) 1467adcec288STom St Denis struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 146897b2e202SAlex Deucher #endif 146997b2e202SAlex Deucher struct amdgpu_atif atif; 147097b2e202SAlex Deucher struct amdgpu_atcs atcs; 147197b2e202SAlex Deucher struct mutex srbm_mutex; 147297b2e202SAlex Deucher /* GRBM index mutex. Protects concurrent access to GRBM index */ 147397b2e202SAlex Deucher struct mutex grbm_idx_mutex; 147497b2e202SAlex Deucher struct dev_pm_domain vga_pm_domain; 147597b2e202SAlex Deucher bool have_disp_power_ref; 147697b2e202SAlex Deucher 147797b2e202SAlex Deucher /* BIOS */ 14780cdd5005SAlex Deucher bool is_atom_fw; 147997b2e202SAlex Deucher uint8_t *bios; 1480a9f5db9cSEvan Quan uint32_t bios_size; 148197b2e202SAlex Deucher struct amdgpu_bo *stollen_vga_memory; 1482a5bde2f9SAlex Deucher uint32_t bios_scratch_reg_offset; 148397b2e202SAlex Deucher uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 148497b2e202SAlex Deucher 148597b2e202SAlex Deucher /* Register/doorbell mmio */ 148697b2e202SAlex Deucher resource_size_t rmmio_base; 148797b2e202SAlex Deucher resource_size_t rmmio_size; 148897b2e202SAlex Deucher void __iomem *rmmio; 148997b2e202SAlex Deucher /* protects concurrent MM_INDEX/DATA based register access */ 149097b2e202SAlex Deucher spinlock_t mmio_idx_lock; 149197b2e202SAlex Deucher /* protects concurrent SMC based register access */ 149297b2e202SAlex Deucher spinlock_t smc_idx_lock; 149397b2e202SAlex Deucher amdgpu_rreg_t smc_rreg; 149497b2e202SAlex Deucher amdgpu_wreg_t smc_wreg; 149597b2e202SAlex Deucher /* protects concurrent PCIE register access */ 149697b2e202SAlex Deucher spinlock_t pcie_idx_lock; 149797b2e202SAlex Deucher amdgpu_rreg_t pcie_rreg; 149897b2e202SAlex Deucher amdgpu_wreg_t pcie_wreg; 149936b9a952SHuang Rui amdgpu_rreg_t pciep_rreg; 150036b9a952SHuang Rui amdgpu_wreg_t pciep_wreg; 150197b2e202SAlex Deucher /* protects concurrent UVD register access */ 150297b2e202SAlex Deucher spinlock_t uvd_ctx_idx_lock; 150397b2e202SAlex Deucher amdgpu_rreg_t uvd_ctx_rreg; 150497b2e202SAlex Deucher amdgpu_wreg_t uvd_ctx_wreg; 150597b2e202SAlex Deucher /* protects concurrent DIDT register access */ 150697b2e202SAlex Deucher spinlock_t didt_idx_lock; 150797b2e202SAlex Deucher amdgpu_rreg_t didt_rreg; 150897b2e202SAlex Deucher amdgpu_wreg_t didt_wreg; 1509ccdbb20aSRex Zhu /* protects concurrent gc_cac register access */ 1510ccdbb20aSRex Zhu spinlock_t gc_cac_idx_lock; 1511ccdbb20aSRex Zhu amdgpu_rreg_t gc_cac_rreg; 1512ccdbb20aSRex Zhu amdgpu_wreg_t gc_cac_wreg; 151397b2e202SAlex Deucher /* protects concurrent ENDPOINT (audio) register access */ 151497b2e202SAlex Deucher spinlock_t audio_endpt_idx_lock; 151597b2e202SAlex Deucher amdgpu_block_rreg_t audio_endpt_rreg; 151697b2e202SAlex Deucher amdgpu_block_wreg_t audio_endpt_wreg; 151797b2e202SAlex Deucher void __iomem *rio_mem; 151897b2e202SAlex Deucher resource_size_t rio_mem_size; 151997b2e202SAlex Deucher struct amdgpu_doorbell doorbell; 152097b2e202SAlex Deucher 152197b2e202SAlex Deucher /* clock/pll info */ 152297b2e202SAlex Deucher struct amdgpu_clock clock; 152397b2e202SAlex Deucher 152497b2e202SAlex Deucher /* MC */ 152597b2e202SAlex Deucher struct amdgpu_mc mc; 152697b2e202SAlex Deucher struct amdgpu_gart gart; 152797b2e202SAlex Deucher struct amdgpu_dummy_page dummy_page; 152897b2e202SAlex Deucher struct amdgpu_vm_manager vm_manager; 1529e60f8db5SAlex Xie struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 153097b2e202SAlex Deucher 153197b2e202SAlex Deucher /* memory management */ 153297b2e202SAlex Deucher struct amdgpu_mman mman; 153397b2e202SAlex Deucher struct amdgpu_vram_scratch vram_scratch; 153497b2e202SAlex Deucher struct amdgpu_wb wb; 153597b2e202SAlex Deucher atomic64_t vram_usage; 153697b2e202SAlex Deucher atomic64_t vram_vis_usage; 153797b2e202SAlex Deucher atomic64_t gtt_usage; 153897b2e202SAlex Deucher atomic64_t num_bytes_moved; 1539dbd5ed60SChristian König atomic64_t num_evictions; 154068e2c5ffSMarek Olšák atomic64_t num_vram_cpu_page_faults; 1541d94aed5aSMarek Olšák atomic_t gpu_reset_counter; 1542f1892138SChunming Zhou atomic_t vram_lost_counter; 154397b2e202SAlex Deucher 154495844d20SMarek Olšák /* data for buffer migration throttling */ 154595844d20SMarek Olšák struct { 154695844d20SMarek Olšák spinlock_t lock; 154795844d20SMarek Olšák s64 last_update_us; 154895844d20SMarek Olšák s64 accum_us; /* accumulated microseconds */ 154995844d20SMarek Olšák u32 log2_max_MBps; 155095844d20SMarek Olšák } mm_stats; 155195844d20SMarek Olšák 155297b2e202SAlex Deucher /* display */ 15539accf2fdSEmily Deng bool enable_virtual_display; 155497b2e202SAlex Deucher struct amdgpu_mode_info mode_info; 155597b2e202SAlex Deucher struct work_struct hotplug_work; 155697b2e202SAlex Deucher struct amdgpu_irq_src crtc_irq; 155797b2e202SAlex Deucher struct amdgpu_irq_src pageflip_irq; 155897b2e202SAlex Deucher struct amdgpu_irq_src hpd_irq; 155997b2e202SAlex Deucher 156097b2e202SAlex Deucher /* rings */ 156176bf0db5SChristian König u64 fence_context; 156297b2e202SAlex Deucher unsigned num_rings; 156397b2e202SAlex Deucher struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 156497b2e202SAlex Deucher bool ib_pool_ready; 156597b2e202SAlex Deucher struct amdgpu_sa_manager ring_tmp_bo; 156697b2e202SAlex Deucher 156797b2e202SAlex Deucher /* interrupts */ 156897b2e202SAlex Deucher struct amdgpu_irq irq; 156997b2e202SAlex Deucher 15701f7371b2SAlex Deucher /* powerplay */ 15711f7371b2SAlex Deucher struct amd_powerplay powerplay; 1572e61710c5SJammy Zhou bool pp_enabled; 1573f3898ea1SEric Huang bool pp_force_state_enabled; 15741f7371b2SAlex Deucher 157597b2e202SAlex Deucher /* dpm */ 157697b2e202SAlex Deucher struct amdgpu_pm pm; 157797b2e202SAlex Deucher u32 cg_flags; 157897b2e202SAlex Deucher u32 pg_flags; 157997b2e202SAlex Deucher 158097b2e202SAlex Deucher /* amdgpu smumgr */ 158197b2e202SAlex Deucher struct amdgpu_smumgr smu; 158297b2e202SAlex Deucher 158397b2e202SAlex Deucher /* gfx */ 158497b2e202SAlex Deucher struct amdgpu_gfx gfx; 158597b2e202SAlex Deucher 158697b2e202SAlex Deucher /* sdma */ 1587c113ea1cSAlex Deucher struct amdgpu_sdma sdma; 158897b2e202SAlex Deucher 158995d0906fSLeo Liu union { 159095d0906fSLeo Liu struct { 159197b2e202SAlex Deucher /* uvd */ 159297b2e202SAlex Deucher struct amdgpu_uvd uvd; 159397b2e202SAlex Deucher 159497b2e202SAlex Deucher /* vce */ 159597b2e202SAlex Deucher struct amdgpu_vce vce; 159695d0906fSLeo Liu }; 159795d0906fSLeo Liu 159895d0906fSLeo Liu /* vcn */ 159995d0906fSLeo Liu struct amdgpu_vcn vcn; 160095d0906fSLeo Liu }; 160197b2e202SAlex Deucher 160297b2e202SAlex Deucher /* firmwares */ 160397b2e202SAlex Deucher struct amdgpu_firmware firmware; 160497b2e202SAlex Deucher 16050e5ca0d1SHuang Rui /* PSP */ 16060e5ca0d1SHuang Rui struct psp_context psp; 16070e5ca0d1SHuang Rui 160897b2e202SAlex Deucher /* GDS */ 160997b2e202SAlex Deucher struct amdgpu_gds gds; 161097b2e202SAlex Deucher 1611a1255107SAlex Deucher struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 161297b2e202SAlex Deucher int num_ip_blocks; 161397b2e202SAlex Deucher struct mutex mn_lock; 161497b2e202SAlex Deucher DECLARE_HASHTABLE(mn_hash, 7); 161597b2e202SAlex Deucher 161697b2e202SAlex Deucher /* tracking pinned memory */ 161797b2e202SAlex Deucher u64 vram_pin_size; 1618e131b914SChunming Zhou u64 invisible_pin_size; 161997b2e202SAlex Deucher u64 gart_pin_size; 1620130e0371SOded Gabbay 1621130e0371SOded Gabbay /* amdkfd interface */ 1622130e0371SOded Gabbay struct kfd_dev *kfd; 162323ca0e4eSChunming Zhou 16242dc80b00SShirish S /* delayed work_func for deferring clockgating during resume */ 16252dc80b00SShirish S struct delayed_work late_init_work; 16262dc80b00SShirish S 16275a5099cbSXiangliang Yu struct amdgpu_virt virt; 16280c4e7fa5SChunming Zhou 16290c4e7fa5SChunming Zhou /* link all shadow bo */ 16300c4e7fa5SChunming Zhou struct list_head shadow_list; 16310c4e7fa5SChunming Zhou struct mutex shadow_list_lock; 16325c1354bdSChunming Zhou /* link all gtt */ 16335c1354bdSChunming Zhou spinlock_t gtt_list_lock; 16345c1354bdSChunming Zhou struct list_head gtt_list; 16355c1354bdSChunming Zhou 1636c836fec5SJim Qu /* record hw reset is performed */ 1637c836fec5SJim Qu bool has_hw_reset; 16380c49e0b8SChunming Zhou u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1639c836fec5SJim Qu 164097b2e202SAlex Deucher }; 164197b2e202SAlex Deucher 1642a7d64de6SChristian König static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1643a7d64de6SChristian König { 1644a7d64de6SChristian König return container_of(bdev, struct amdgpu_device, mman.bdev); 1645a7d64de6SChristian König } 1646a7d64de6SChristian König 164797b2e202SAlex Deucher bool amdgpu_device_is_px(struct drm_device *dev); 164897b2e202SAlex Deucher int amdgpu_device_init(struct amdgpu_device *adev, 164997b2e202SAlex Deucher struct drm_device *ddev, 165097b2e202SAlex Deucher struct pci_dev *pdev, 165197b2e202SAlex Deucher uint32_t flags); 165297b2e202SAlex Deucher void amdgpu_device_fini(struct amdgpu_device *adev); 165397b2e202SAlex Deucher int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 165497b2e202SAlex Deucher 165597b2e202SAlex Deucher uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 165615d72fd7SMonk Liu uint32_t acc_flags); 165797b2e202SAlex Deucher void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 165815d72fd7SMonk Liu uint32_t acc_flags); 165997b2e202SAlex Deucher u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 166097b2e202SAlex Deucher void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 166197b2e202SAlex Deucher 166297b2e202SAlex Deucher u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 166397b2e202SAlex Deucher void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1664832be404SKen Wang u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 1665832be404SKen Wang void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 166697b2e202SAlex Deucher 166797b2e202SAlex Deucher /* 166897b2e202SAlex Deucher * Registers read & write functions. 166997b2e202SAlex Deucher */ 167015d72fd7SMonk Liu 167115d72fd7SMonk Liu #define AMDGPU_REGS_IDX (1<<0) 167215d72fd7SMonk Liu #define AMDGPU_REGS_NO_KIQ (1<<1) 167315d72fd7SMonk Liu 167415d72fd7SMonk Liu #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 167515d72fd7SMonk Liu #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 167615d72fd7SMonk Liu 167715d72fd7SMonk Liu #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 167815d72fd7SMonk Liu #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 167915d72fd7SMonk Liu #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 168015d72fd7SMonk Liu #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 168115d72fd7SMonk Liu #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 168297b2e202SAlex Deucher #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 168397b2e202SAlex Deucher #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 168497b2e202SAlex Deucher #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 168597b2e202SAlex Deucher #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 168636b9a952SHuang Rui #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 168736b9a952SHuang Rui #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 168897b2e202SAlex Deucher #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 168997b2e202SAlex Deucher #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 169097b2e202SAlex Deucher #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 169197b2e202SAlex Deucher #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 169297b2e202SAlex Deucher #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 169397b2e202SAlex Deucher #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1694ccdbb20aSRex Zhu #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1695ccdbb20aSRex Zhu #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 169697b2e202SAlex Deucher #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 169797b2e202SAlex Deucher #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 169897b2e202SAlex Deucher #define WREG32_P(reg, val, mask) \ 169997b2e202SAlex Deucher do { \ 170097b2e202SAlex Deucher uint32_t tmp_ = RREG32(reg); \ 170197b2e202SAlex Deucher tmp_ &= (mask); \ 170297b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 170397b2e202SAlex Deucher WREG32(reg, tmp_); \ 170497b2e202SAlex Deucher } while (0) 170597b2e202SAlex Deucher #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 170697b2e202SAlex Deucher #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 170797b2e202SAlex Deucher #define WREG32_PLL_P(reg, val, mask) \ 170897b2e202SAlex Deucher do { \ 170997b2e202SAlex Deucher uint32_t tmp_ = RREG32_PLL(reg); \ 171097b2e202SAlex Deucher tmp_ &= (mask); \ 171197b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 171297b2e202SAlex Deucher WREG32_PLL(reg, tmp_); \ 171397b2e202SAlex Deucher } while (0) 171497b2e202SAlex Deucher #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 171597b2e202SAlex Deucher #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 171697b2e202SAlex Deucher #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 171797b2e202SAlex Deucher 171897b2e202SAlex Deucher #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 171997b2e202SAlex Deucher #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1720832be404SKen Wang #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 1721832be404SKen Wang #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 172297b2e202SAlex Deucher 172397b2e202SAlex Deucher #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 172497b2e202SAlex Deucher #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 172597b2e202SAlex Deucher 172697b2e202SAlex Deucher #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 172797b2e202SAlex Deucher (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 172897b2e202SAlex Deucher (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 172997b2e202SAlex Deucher 173097b2e202SAlex Deucher #define REG_GET_FIELD(value, reg, field) \ 173197b2e202SAlex Deucher (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 173297b2e202SAlex Deucher 173361cb8cefSTom St Denis #define WREG32_FIELD(reg, field, val) \ 173461cb8cefSTom St Denis WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 173561cb8cefSTom St Denis 1736ccaf3574STom St Denis #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1737ccaf3574STom St Denis WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1738ccaf3574STom St Denis 173997b2e202SAlex Deucher /* 174097b2e202SAlex Deucher * BIOS helpers. 174197b2e202SAlex Deucher */ 174297b2e202SAlex Deucher #define RBIOS8(i) (adev->bios[i]) 174397b2e202SAlex Deucher #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 174497b2e202SAlex Deucher #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 174597b2e202SAlex Deucher 174697b2e202SAlex Deucher /* 174797b2e202SAlex Deucher * RING helpers. 174897b2e202SAlex Deucher */ 174997b2e202SAlex Deucher static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 175097b2e202SAlex Deucher { 175197b2e202SAlex Deucher if (ring->count_dw <= 0) 175286c2b790SJammy Zhou DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 1753536fbf94SKen Wang ring->ring[ring->wptr++ & ring->buf_mask] = v; 175497b2e202SAlex Deucher ring->wptr &= ring->ptr_mask; 175597b2e202SAlex Deucher ring->count_dw--; 175697b2e202SAlex Deucher } 175797b2e202SAlex Deucher 17580a8e1473SMonk Liu static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw) 17590a8e1473SMonk Liu { 17600a8e1473SMonk Liu unsigned occupied, chunk1, chunk2; 17610a8e1473SMonk Liu void *dst; 17620a8e1473SMonk Liu 17635b9c58f9SNikola Pajkovsky if (unlikely(ring->count_dw < count_dw)) { 17640a8e1473SMonk Liu DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 17655b9c58f9SNikola Pajkovsky return; 17665b9c58f9SNikola Pajkovsky } 17675b9c58f9SNikola Pajkovsky 17685846e355SMonk Liu occupied = ring->wptr & ring->buf_mask; 17690a8e1473SMonk Liu dst = (void *)&ring->ring[occupied]; 17705846e355SMonk Liu chunk1 = ring->buf_mask + 1 - occupied; 17710a8e1473SMonk Liu chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; 17720a8e1473SMonk Liu chunk2 = count_dw - chunk1; 17730a8e1473SMonk Liu chunk1 <<= 2; 17740a8e1473SMonk Liu chunk2 <<= 2; 17750a8e1473SMonk Liu 17760a8e1473SMonk Liu if (chunk1) 17770a8e1473SMonk Liu memcpy(dst, src, chunk1); 17780a8e1473SMonk Liu 17790a8e1473SMonk Liu if (chunk2) { 17800a8e1473SMonk Liu src += chunk1; 17810a8e1473SMonk Liu dst = (void *)ring->ring; 17820a8e1473SMonk Liu memcpy(dst, src, chunk2); 17830a8e1473SMonk Liu } 17840a8e1473SMonk Liu 17850a8e1473SMonk Liu ring->wptr += count_dw; 17860a8e1473SMonk Liu ring->wptr &= ring->ptr_mask; 17870a8e1473SMonk Liu ring->count_dw -= count_dw; 17880a8e1473SMonk Liu } 17890a8e1473SMonk Liu 1790c113ea1cSAlex Deucher static inline struct amdgpu_sdma_instance * 1791c113ea1cSAlex Deucher amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 17924b2f7e2cSJammy Zhou { 17934b2f7e2cSJammy Zhou struct amdgpu_device *adev = ring->adev; 17944b2f7e2cSJammy Zhou int i; 17954b2f7e2cSJammy Zhou 1796c113ea1cSAlex Deucher for (i = 0; i < adev->sdma.num_instances; i++) 1797c113ea1cSAlex Deucher if (&adev->sdma.instance[i].ring == ring) 17984b2f7e2cSJammy Zhou break; 17994b2f7e2cSJammy Zhou 18004b2f7e2cSJammy Zhou if (i < AMDGPU_MAX_SDMA_INSTANCES) 1801c113ea1cSAlex Deucher return &adev->sdma.instance[i]; 18024b2f7e2cSJammy Zhou else 18034b2f7e2cSJammy Zhou return NULL; 18044b2f7e2cSJammy Zhou } 18054b2f7e2cSJammy Zhou 180697b2e202SAlex Deucher /* 180797b2e202SAlex Deucher * ASICs macro. 180897b2e202SAlex Deucher */ 180997b2e202SAlex Deucher #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 181097b2e202SAlex Deucher #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 181197b2e202SAlex Deucher #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 181297b2e202SAlex Deucher #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 181397b2e202SAlex Deucher #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1814841686dfSMaruthi Bayyavarapu #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1815841686dfSMaruthi Bayyavarapu #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1816841686dfSMaruthi Bayyavarapu #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 181797b2e202SAlex Deucher #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 18187946b878SAlex Deucher #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 181997b2e202SAlex Deucher #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1820bbf282d8SAlex Deucher #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 182197b2e202SAlex Deucher #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 182297b2e202SAlex Deucher #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 1823b1166325SChristian König #define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr)) 182497b2e202SAlex Deucher #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 1825de9ea7bdSChristian König #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 182697b2e202SAlex Deucher #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 18275463545bSAlex Xie #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags)) 182897b2e202SAlex Deucher #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 182997b2e202SAlex Deucher #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 1830bbec97aaSChristian König #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 183197b2e202SAlex Deucher #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 183297b2e202SAlex Deucher #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 183397b2e202SAlex Deucher #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 1834d88bf583SChristian König #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 1835b8c7b39eSChristian König #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 183697b2e202SAlex Deucher #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 1837890ee23fSChunming Zhou #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 183897b2e202SAlex Deucher #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 1839d2edb07bSChristian König #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 184011afbde8SChunming Zhou #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 1841c2167a65SMonk Liu #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 1842753ad49cSMonk Liu #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 1843b6091c12SXiangliang Yu #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) 1844b6091c12SXiangliang Yu #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 18453b4d68e9SMonk Liu #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b)) 18469e5d5309SChristian König #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 184703ccf481SMonk Liu #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 184803ccf481SMonk Liu #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 184997b2e202SAlex Deucher #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 185097b2e202SAlex Deucher #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 185197b2e202SAlex Deucher #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 185297b2e202SAlex Deucher #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 185397b2e202SAlex Deucher #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 185497b2e202SAlex Deucher #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 185597b2e202SAlex Deucher #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 185697b2e202SAlex Deucher #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 185797b2e202SAlex Deucher #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 185897b2e202SAlex Deucher #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 185997b2e202SAlex Deucher #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 186097b2e202SAlex Deucher #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 1861cb9e59d7SAlex Deucher #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 186297b2e202SAlex Deucher #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 186397b2e202SAlex Deucher #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 186497b2e202SAlex Deucher #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 186597b2e202SAlex Deucher #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 186697b2e202SAlex Deucher #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 1867c7ae72c0SChunming Zhou #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 18686e7a3840SChunming Zhou #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 1869b95e31fdSAlex Deucher #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 18709559ef5bSTom St Denis #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 187197b2e202SAlex Deucher #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 18720e5ca0d1SHuang Rui #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) 187397b2e202SAlex Deucher 187497b2e202SAlex Deucher /* Common functions */ 187597b2e202SAlex Deucher int amdgpu_gpu_reset(struct amdgpu_device *adev); 18763ad81f16SChunming Zhou bool amdgpu_need_backup(struct amdgpu_device *adev); 187797b2e202SAlex Deucher void amdgpu_pci_config_reset(struct amdgpu_device *adev); 1878c836fec5SJim Qu bool amdgpu_need_post(struct amdgpu_device *adev); 187997b2e202SAlex Deucher void amdgpu_update_display_priority(struct amdgpu_device *adev); 1880d5fc5e82SChunming Zhou 188197b2e202SAlex Deucher int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 188297b2e202SAlex Deucher int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 188397b2e202SAlex Deucher u32 ip_instance, u32 ring, 188497b2e202SAlex Deucher struct amdgpu_ring **out_ring); 1885fad06127SSamuel Pitoiset void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes); 1886765e7fbfSChristian König void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 188797b2e202SAlex Deucher bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 18882f568dbdSChristian König int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 188997b2e202SAlex Deucher int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 189097b2e202SAlex Deucher uint32_t flags); 189197b2e202SAlex Deucher bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 1892cc325d19SChristian König struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 1893d7006964SChristian König bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1894d7006964SChristian König unsigned long end); 18952f568dbdSChristian König bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 18962f568dbdSChristian König int *last_invalidated); 189797b2e202SAlex Deucher bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 18986b777607SChunming Zhou uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 189997b2e202SAlex Deucher struct ttm_mem_reg *mem); 190097b2e202SAlex Deucher void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 190197b2e202SAlex Deucher void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 190297b2e202SAlex Deucher void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 19039f31a0b0SBaoyou Xie int amdgpu_ttm_init(struct amdgpu_device *adev); 19049f31a0b0SBaoyou Xie void amdgpu_ttm_fini(struct amdgpu_device *adev); 190597b2e202SAlex Deucher void amdgpu_program_register_sequence(struct amdgpu_device *adev, 190697b2e202SAlex Deucher const u32 *registers, 190797b2e202SAlex Deucher const u32 array_size); 190897b2e202SAlex Deucher 190997b2e202SAlex Deucher bool amdgpu_device_is_px(struct drm_device *dev); 191097b2e202SAlex Deucher /* atpx handler */ 191197b2e202SAlex Deucher #if defined(CONFIG_VGA_SWITCHEROO) 191297b2e202SAlex Deucher void amdgpu_register_atpx_handler(void); 191397b2e202SAlex Deucher void amdgpu_unregister_atpx_handler(void); 1914a78fe133SAlex Deucher bool amdgpu_has_atpx_dgpu_power_cntl(void); 19152f5af82eSAlex Deucher bool amdgpu_is_atpx_hybrid(void); 1916efc83cf4SAlex Deucher bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1917714f88e0SAlex Xie bool amdgpu_has_atpx(void); 191897b2e202SAlex Deucher #else 191997b2e202SAlex Deucher static inline void amdgpu_register_atpx_handler(void) {} 192097b2e202SAlex Deucher static inline void amdgpu_unregister_atpx_handler(void) {} 1921a78fe133SAlex Deucher static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 19222f5af82eSAlex Deucher static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1923efc83cf4SAlex Deucher static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1924714f88e0SAlex Xie static inline bool amdgpu_has_atpx(void) { return false; } 192597b2e202SAlex Deucher #endif 192697b2e202SAlex Deucher 192797b2e202SAlex Deucher /* 192897b2e202SAlex Deucher * KMS 192997b2e202SAlex Deucher */ 193097b2e202SAlex Deucher extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1931f498d9edSNils Wallménius extern const int amdgpu_max_kms_ioctl; 193297b2e202SAlex Deucher 1933f1892138SChunming Zhou bool amdgpu_kms_vram_lost(struct amdgpu_device *adev, 1934f1892138SChunming Zhou struct amdgpu_fpriv *fpriv); 193597b2e202SAlex Deucher int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 193611b3c20bSGabriel Krisman Bertazi void amdgpu_driver_unload_kms(struct drm_device *dev); 193797b2e202SAlex Deucher void amdgpu_driver_lastclose_kms(struct drm_device *dev); 193897b2e202SAlex Deucher int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 193997b2e202SAlex Deucher void amdgpu_driver_postclose_kms(struct drm_device *dev, 194097b2e202SAlex Deucher struct drm_file *file_priv); 1941faefba95SAlex Deucher int amdgpu_suspend(struct amdgpu_device *adev); 1942810ddc3aSAlex Deucher int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1943810ddc3aSAlex Deucher int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 194488e72717SThierry Reding u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 194588e72717SThierry Reding int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 194688e72717SThierry Reding void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 194797b2e202SAlex Deucher long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 194897b2e202SAlex Deucher unsigned long arg); 194997b2e202SAlex Deucher 195097b2e202SAlex Deucher /* 195197b2e202SAlex Deucher * functions used by amdgpu_encoder.c 195297b2e202SAlex Deucher */ 195397b2e202SAlex Deucher struct amdgpu_afmt_acr { 195497b2e202SAlex Deucher u32 clock; 195597b2e202SAlex Deucher 195697b2e202SAlex Deucher int n_32khz; 195797b2e202SAlex Deucher int cts_32khz; 195897b2e202SAlex Deucher 195997b2e202SAlex Deucher int n_44_1khz; 196097b2e202SAlex Deucher int cts_44_1khz; 196197b2e202SAlex Deucher 196297b2e202SAlex Deucher int n_48khz; 196397b2e202SAlex Deucher int cts_48khz; 196497b2e202SAlex Deucher 196597b2e202SAlex Deucher }; 196697b2e202SAlex Deucher 196797b2e202SAlex Deucher struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 196897b2e202SAlex Deucher 196997b2e202SAlex Deucher /* amdgpu_acpi.c */ 197097b2e202SAlex Deucher #if defined(CONFIG_ACPI) 197197b2e202SAlex Deucher int amdgpu_acpi_init(struct amdgpu_device *adev); 197297b2e202SAlex Deucher void amdgpu_acpi_fini(struct amdgpu_device *adev); 197397b2e202SAlex Deucher bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 197497b2e202SAlex Deucher int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 197597b2e202SAlex Deucher u8 perf_req, bool advertise); 197697b2e202SAlex Deucher int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 197797b2e202SAlex Deucher #else 197897b2e202SAlex Deucher static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 197997b2e202SAlex Deucher static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 198097b2e202SAlex Deucher #endif 198197b2e202SAlex Deucher 198297b2e202SAlex Deucher struct amdgpu_bo_va_mapping * 198397b2e202SAlex Deucher amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 198497b2e202SAlex Deucher uint64_t addr, struct amdgpu_bo **bo); 1985c855e250SChristian König int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser); 198697b2e202SAlex Deucher 198797b2e202SAlex Deucher #include "amdgpu_object.h" 198897b2e202SAlex Deucher #endif 1989