197b2e202SAlex Deucher /* 297b2e202SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 397b2e202SAlex Deucher * Copyright 2008 Red Hat Inc. 497b2e202SAlex Deucher * Copyright 2009 Jerome Glisse. 597b2e202SAlex Deucher * 697b2e202SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 797b2e202SAlex Deucher * copy of this software and associated documentation files (the "Software"), 897b2e202SAlex Deucher * to deal in the Software without restriction, including without limitation 997b2e202SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1097b2e202SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1197b2e202SAlex Deucher * Software is furnished to do so, subject to the following conditions: 1297b2e202SAlex Deucher * 1397b2e202SAlex Deucher * The above copyright notice and this permission notice shall be included in 1497b2e202SAlex Deucher * all copies or substantial portions of the Software. 1597b2e202SAlex Deucher * 1697b2e202SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1797b2e202SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1897b2e202SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1997b2e202SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2097b2e202SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2197b2e202SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2297b2e202SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2397b2e202SAlex Deucher * 2497b2e202SAlex Deucher * Authors: Dave Airlie 2597b2e202SAlex Deucher * Alex Deucher 2697b2e202SAlex Deucher * Jerome Glisse 2797b2e202SAlex Deucher */ 2897b2e202SAlex Deucher #ifndef __AMDGPU_H__ 2997b2e202SAlex Deucher #define __AMDGPU_H__ 3097b2e202SAlex Deucher 31d57229b1SAurabindo Pillai #ifdef pr_fmt 32d57229b1SAurabindo Pillai #undef pr_fmt 33d57229b1SAurabindo Pillai #endif 34d57229b1SAurabindo Pillai 35d57229b1SAurabindo Pillai #define pr_fmt(fmt) "amdgpu: " fmt 36d57229b1SAurabindo Pillai 37539489fcSAurabindo Pillai #ifdef dev_fmt 38539489fcSAurabindo Pillai #undef dev_fmt 39539489fcSAurabindo Pillai #endif 40539489fcSAurabindo Pillai 41539489fcSAurabindo Pillai #define dev_fmt(fmt) "amdgpu: " fmt 42539489fcSAurabindo Pillai 438290268fSChristian König #include "amdgpu_ctx.h" 448290268fSChristian König 4597b2e202SAlex Deucher #include <linux/atomic.h> 4697b2e202SAlex Deucher #include <linux/wait.h> 4797b2e202SAlex Deucher #include <linux/list.h> 4897b2e202SAlex Deucher #include <linux/kref.h> 49a9f87f64SChristian König #include <linux/rbtree.h> 5097b2e202SAlex Deucher #include <linux/hashtable.h> 51f54d1867SChris Wilson #include <linux/dma-fence.h> 52c9a6b82fSAndrey Grodzovsky #include <linux/pci.h> 53c9a6b82fSAndrey Grodzovsky #include <linux/aer.h> 5497b2e202SAlex Deucher 55248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_bo_api.h> 56248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_bo_driver.h> 57248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_placement.h> 58248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_execbuf_util.h> 5997b2e202SAlex Deucher 607e5a547fSChunming Zhou #include <drm/amdgpu_drm.h> 61f867723bSSam Ravnborg #include <drm/drm_gem.h> 62f867723bSSam Ravnborg #include <drm/drm_ioctl.h> 631b1f42d8SLucas Stach #include <drm/gpu_scheduler.h> 6497b2e202SAlex Deucher 6578c16834SAndres Rodriguez #include <kgd_kfd_interface.h> 66c79563a3SRex Zhu #include "dm_pp_interface.h" 67c79563a3SRex Zhu #include "kgd_pp_interface.h" 6878c16834SAndres Rodriguez 695fc3aeebSyanyang1 #include "amd_shared.h" 7097b2e202SAlex Deucher #include "amdgpu_mode.h" 7197b2e202SAlex Deucher #include "amdgpu_ih.h" 7297b2e202SAlex Deucher #include "amdgpu_irq.h" 7397b2e202SAlex Deucher #include "amdgpu_ucode.h" 74c632d799SFlora Cui #include "amdgpu_ttm.h" 750e5ca0d1SHuang Rui #include "amdgpu_psp.h" 7697b2e202SAlex Deucher #include "amdgpu_gds.h" 7756113504SChristian König #include "amdgpu_sync.h" 7878023016SChristian König #include "amdgpu_ring.h" 79073440d2SChristian König #include "amdgpu_vm.h" 80cf097881SAlex Deucher #include "amdgpu_dpm.h" 81a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h" 824df654d2SLeo Liu #include "amdgpu_uvd.h" 835e568178SLeo Liu #include "amdgpu_vce.h" 8495aa13f6SLeo Liu #include "amdgpu_vcn.h" 8588a1c40aSLeo Liu #include "amdgpu_jpeg.h" 869a189996SChristian König #include "amdgpu_mn.h" 87770d13b1SChristian König #include "amdgpu_gmc.h" 88448fe192SHuang Rui #include "amdgpu_gfx.h" 89bb7743bcSHuang Rui #include "amdgpu_sdma.h" 90bebc0762SHawking Zhang #include "amdgpu_nbio.h" 91455d40c9SLikun Gao #include "amdgpu_hdp.h" 924562236bSHarry Wentland #include "amdgpu_dm.h" 93ceeb50edSMonk Liu #include "amdgpu_virt.h" 947946340fSRex Zhu #include "amdgpu_csa.h" 953490bdb5SChristian König #include "amdgpu_gart.h" 9675758255SAlex Deucher #include "amdgpu_debugfs.h" 97050d9d43SChristian König #include "amdgpu_job.h" 984a8c21a1SChristian König #include "amdgpu_bo_list.h" 992cddc50eSHuang Rui #include "amdgpu_gem.h" 100cde577bdSOak Zeng #include "amdgpu_doorbell.h" 101611736d8SFelix Kuehling #include "amdgpu_amdkfd.h" 102137d63abSHuang Rui #include "amdgpu_smu.h" 103f39f5bb1SXiaojie Yuan #include "amdgpu_discovery.h" 104a538bbe7SJack Xiao #include "amdgpu_mes.h" 1059e585a52SHawking Zhang #include "amdgpu_umc.h" 1063d093da0STao Zhou #include "amdgpu_mmhub.h" 1078ffff9b4SOak Zeng #include "amdgpu_gfxhub.h" 108bdf84a80SJoseph Greathouse #include "amdgpu_df.h" 109293f2563SHawking Zhang #include "amdgpu_smuio.h" 110b291a387SHawking Zhang #include "amdgpu_hdp.h" 111c79563a3SRex Zhu 11262d73fbcSEvan Quan #define MAX_GPU_INSTANCE 16 11362d73fbcSEvan Quan 11462d73fbcSEvan Quan struct amdgpu_gpu_instance 11562d73fbcSEvan Quan { 11662d73fbcSEvan Quan struct amdgpu_device *adev; 11762d73fbcSEvan Quan int mgpu_fan_enabled; 11862d73fbcSEvan Quan }; 11962d73fbcSEvan Quan 12062d73fbcSEvan Quan struct amdgpu_mgpu_info 12162d73fbcSEvan Quan { 12262d73fbcSEvan Quan struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 12362d73fbcSEvan Quan struct mutex mutex; 12462d73fbcSEvan Quan uint32_t num_gpu; 12562d73fbcSEvan Quan uint32_t num_dgpu; 12662d73fbcSEvan Quan uint32_t num_apu; 12762d73fbcSEvan Quan }; 12862d73fbcSEvan Quan 12988f8575bSDennis Li struct amdgpu_watchdog_timer 13088f8575bSDennis Li { 13188f8575bSDennis Li bool timeout_fatal_disable; 13288f8575bSDennis Li uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 13388f8575bSDennis Li }; 13488f8575bSDennis Li 135f440ff44SWambui Karuga #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 13671f98027SAlex Deucher 13797b2e202SAlex Deucher /* 13897b2e202SAlex Deucher * Modules parameters. 13997b2e202SAlex Deucher */ 14097b2e202SAlex Deucher extern int amdgpu_modeset; 14197b2e202SAlex Deucher extern int amdgpu_vram_limit; 142218b5dcdSJohn Brooks extern int amdgpu_vis_vram_limit; 14383e74db6SAlex Deucher extern int amdgpu_gart_size; 14436d38372SChristian König extern int amdgpu_gtt_size; 14595844d20SMarek Olšák extern int amdgpu_moverate; 14697b2e202SAlex Deucher extern int amdgpu_benchmarking; 14797b2e202SAlex Deucher extern int amdgpu_testing; 14897b2e202SAlex Deucher extern int amdgpu_audio; 14997b2e202SAlex Deucher extern int amdgpu_disp_priority; 15097b2e202SAlex Deucher extern int amdgpu_hw_i2c; 15197b2e202SAlex Deucher extern int amdgpu_pcie_gen2; 15297b2e202SAlex Deucher extern int amdgpu_msi; 153f440ff44SWambui Karuga extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 15497b2e202SAlex Deucher extern int amdgpu_dpm; 155e635ee07SHuang Rui extern int amdgpu_fw_load_type; 15697b2e202SAlex Deucher extern int amdgpu_aspm; 15797b2e202SAlex Deucher extern int amdgpu_runtime_pm; 1580b693f0bSRex Zhu extern uint amdgpu_ip_block_mask; 15997b2e202SAlex Deucher extern int amdgpu_bapm; 16097b2e202SAlex Deucher extern int amdgpu_deep_color; 16197b2e202SAlex Deucher extern int amdgpu_vm_size; 16297b2e202SAlex Deucher extern int amdgpu_vm_block_size; 163d07f14beSRoger He extern int amdgpu_vm_fragment_size; 164d9c13156SChristian König extern int amdgpu_vm_fault_stop; 165b495bd3aSChristian König extern int amdgpu_vm_debug; 1669a4b7d4cSHarish Kasiviswanathan extern int amdgpu_vm_update_mode; 1677e0ff20cSWambui Karuga extern int amdgpu_exp_hw_support; 1684562236bSHarry Wentland extern int amdgpu_dc; 1691333f723SJammy Zhou extern int amdgpu_sched_jobs; 1704afcb303SJammy Zhou extern int amdgpu_sched_hw_submission; 1710b693f0bSRex Zhu extern uint amdgpu_pcie_gen_cap; 1720b693f0bSRex Zhu extern uint amdgpu_pcie_lane_cap; 1730b693f0bSRex Zhu extern uint amdgpu_cg_mask; 1740b693f0bSRex Zhu extern uint amdgpu_pg_mask; 1750b693f0bSRex Zhu extern uint amdgpu_sdma_phase_quantum; 1766f8941a2SNicolai Hähnle extern char *amdgpu_disable_cu; 1779accf2fdSEmily Deng extern char *amdgpu_virtual_display; 1780b693f0bSRex Zhu extern uint amdgpu_pp_feature_mask; 179367039bfSTianci.Yin extern uint amdgpu_force_long_training; 18065781c78SMonk Liu extern int amdgpu_job_hang_limit; 181e8835e0eSHawking Zhang extern int amdgpu_lbpw; 1824a75aefeSAndres Rodriguez extern int amdgpu_compute_multipipe; 183dcebf026SAndrey Grodzovsky extern int amdgpu_gpu_recovery; 184bfca0289SShaoyun Liu extern int amdgpu_emu_mode; 1857951e376SRex Zhu extern uint amdgpu_smu_memory_pool_size; 1868738a82bSLijo Lazar extern int amdgpu_smu_pptable_id; 1877875a226SAlex Deucher extern uint amdgpu_dc_feature_mask; 1888a791dabSHarry Wentland extern uint amdgpu_dc_debug_mask; 189ad4de27fSNicholas Kazlauskas extern uint amdgpu_dm_abm_level; 1907c209847STakashi Iwai extern int amdgpu_backlight; 19162d73fbcSEvan Quan extern struct amdgpu_mgpu_info mgpu_info; 1921218252fSxinhui pan extern int amdgpu_ras_enable; 1931218252fSxinhui pan extern uint amdgpu_ras_mask; 194acc0204cSGuchun Chen extern int amdgpu_bad_page_threshold; 19588f8575bSDennis Li extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 19651bcce46SHawking Zhang extern int amdgpu_async_gfx_ring; 197b239c017SJack Xiao extern int amdgpu_mcbp; 198a190d1c7SXiaojie Yuan extern int amdgpu_discovery; 19938487284SJack Xiao extern int amdgpu_mes; 20075ee6487SFelix Kuehling extern int amdgpu_noretry; 2014e66d7d2SYong Zhao extern int amdgpu_force_asic_type; 2028c9f69bcSShirish S #ifdef CONFIG_HSA_AMD 203aa978594SHuang Rui extern int sched_policy; 204b2057956SFelix Kuehling extern bool debug_evictions; 205b80f050fSPhilip Yang extern bool no_system_mem_limit; 206a35ad98bSShirish S #else 20702f40f82SLee Jones static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 20802f40f82SLee Jones static const bool __maybe_unused debug_evictions; /* = false */ 20902f40f82SLee Jones static const bool __maybe_unused no_system_mem_limit; 2108c9f69bcSShirish S #endif 21197b2e202SAlex Deucher 212d7ccb38dSHuang Rui extern int amdgpu_tmz; 213273da6ffSWenhui Sheng extern int amdgpu_reset_method; 214d7ccb38dSHuang Rui 2156dd13096SFelix Kuehling #ifdef CONFIG_DRM_AMDGPU_SI 2166dd13096SFelix Kuehling extern int amdgpu_si_support; 2176dd13096SFelix Kuehling #endif 2187df28986SFelix Kuehling #ifdef CONFIG_DRM_AMDGPU_CIK 2197df28986SFelix Kuehling extern int amdgpu_cik_support; 2207df28986SFelix Kuehling #endif 221a300de40SMonk Liu extern int amdgpu_num_kcq; 22297b2e202SAlex Deucher 22308d1bdd4SRex Zhu #define AMDGPU_VM_MAX_NUM_CTX 4096 2246c8d74caSSamuel Li #define AMDGPU_SG_THRESHOLD (256*1024*1024) 22555ed8cafSChunming Zhou #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 2264b559c90SChunming Zhou #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 22797b2e202SAlex Deucher #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 2288c5e13ecSAndrey Grodzovsky #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 22997b2e202SAlex Deucher #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 23097b2e202SAlex Deucher #define AMDGPUFB_CONN_LIMIT 4 231a5bde2f9SAlex Deucher #define AMDGPU_BIOS_NUM_SCRATCH 16 23297b2e202SAlex Deucher 23381b54fb7SAlex Deucher #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 23481b54fb7SAlex Deucher 23597b2e202SAlex Deucher /* hard reset data */ 23697b2e202SAlex Deucher #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 23797b2e202SAlex Deucher 23897b2e202SAlex Deucher /* reset flags */ 23997b2e202SAlex Deucher #define AMDGPU_RESET_GFX (1 << 0) 24097b2e202SAlex Deucher #define AMDGPU_RESET_COMPUTE (1 << 1) 24197b2e202SAlex Deucher #define AMDGPU_RESET_DMA (1 << 2) 24297b2e202SAlex Deucher #define AMDGPU_RESET_CP (1 << 3) 24397b2e202SAlex Deucher #define AMDGPU_RESET_GRBM (1 << 4) 24497b2e202SAlex Deucher #define AMDGPU_RESET_DMA1 (1 << 5) 24597b2e202SAlex Deucher #define AMDGPU_RESET_RLC (1 << 6) 24697b2e202SAlex Deucher #define AMDGPU_RESET_SEM (1 << 7) 24797b2e202SAlex Deucher #define AMDGPU_RESET_IH (1 << 8) 24897b2e202SAlex Deucher #define AMDGPU_RESET_VMC (1 << 9) 24997b2e202SAlex Deucher #define AMDGPU_RESET_MC (1 << 10) 25097b2e202SAlex Deucher #define AMDGPU_RESET_DISPLAY (1 << 11) 25197b2e202SAlex Deucher #define AMDGPU_RESET_UVD (1 << 12) 25297b2e202SAlex Deucher #define AMDGPU_RESET_VCE (1 << 13) 25397b2e202SAlex Deucher #define AMDGPU_RESET_VCE1 (1 << 14) 25497b2e202SAlex Deucher 25597b2e202SAlex Deucher /* max cursor sizes (in pixels) */ 25697b2e202SAlex Deucher #define CIK_CURSOR_WIDTH 128 25797b2e202SAlex Deucher #define CIK_CURSOR_HEIGHT 128 25897b2e202SAlex Deucher 25997b2e202SAlex Deucher struct amdgpu_device; 26097b2e202SAlex Deucher struct amdgpu_ib; 26197b2e202SAlex Deucher struct amdgpu_cs_parser; 262bb977d37SChunming Zhou struct amdgpu_job; 26397b2e202SAlex Deucher struct amdgpu_irq_src; 2640b492a4cSAlex Deucher struct amdgpu_fpriv; 2659cca0b8eSChristian König struct amdgpu_bo_va_mapping; 266102c16a0SLyude Paul struct amdgpu_atif; 267992af942SJonathan Kim struct kfd_vm_fault_info; 268d95e8e97SDennis Li struct amdgpu_hive_info; 26997b2e202SAlex Deucher 27097b2e202SAlex Deucher enum amdgpu_cp_irq { 27153b2fe41SHawking Zhang AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 27253b2fe41SHawking Zhang AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 27397b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 27497b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 27597b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 27697b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 27797b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 27897b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 27997b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 28097b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 28197b2e202SAlex Deucher 28297b2e202SAlex Deucher AMDGPU_CP_IRQ_LAST 28397b2e202SAlex Deucher }; 28497b2e202SAlex Deucher 28597b2e202SAlex Deucher enum amdgpu_thermal_irq { 28697b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 28797b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 28897b2e202SAlex Deucher 28997b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LAST 29097b2e202SAlex Deucher }; 29197b2e202SAlex Deucher 2924e638ae9SXiangliang Yu enum amdgpu_kiq_irq { 2934e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 2944e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_LAST 2954e638ae9SXiangliang Yu }; 2964e638ae9SXiangliang Yu 2973890d111SEmily Deng #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 2983890d111SEmily Deng #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 299006cc1a2SJiawei Gu #define MAX_KIQ_REG_TRY 1000 3003890d111SEmily Deng 30143fa561fSRex Zhu int amdgpu_device_ip_set_clockgating_state(void *dev, 3025fc3aeebSyanyang1 enum amd_ip_block_type block_type, 3035fc3aeebSyanyang1 enum amd_clockgating_state state); 30443fa561fSRex Zhu int amdgpu_device_ip_set_powergating_state(void *dev, 3055fc3aeebSyanyang1 enum amd_ip_block_type block_type, 3065fc3aeebSyanyang1 enum amd_powergating_state state); 3072990a1fcSAlex Deucher void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 3082990a1fcSAlex Deucher u32 *flags); 3092990a1fcSAlex Deucher int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 3105dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 3112990a1fcSAlex Deucher bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 3125dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 31397b2e202SAlex Deucher 314a1255107SAlex Deucher #define AMDGPU_MAX_IP_NUM 16 315a1255107SAlex Deucher 316a1255107SAlex Deucher struct amdgpu_ip_block_status { 317a1255107SAlex Deucher bool valid; 318a1255107SAlex Deucher bool sw; 319a1255107SAlex Deucher bool hw; 320a1255107SAlex Deucher bool late_initialized; 321a1255107SAlex Deucher bool hang; 322a1255107SAlex Deucher }; 323a1255107SAlex Deucher 32497b2e202SAlex Deucher struct amdgpu_ip_block_version { 325a1255107SAlex Deucher const enum amd_ip_block_type type; 326a1255107SAlex Deucher const u32 major; 327a1255107SAlex Deucher const u32 minor; 328a1255107SAlex Deucher const u32 rev; 3295fc3aeebSyanyang1 const struct amd_ip_funcs *funcs; 33097b2e202SAlex Deucher }; 33197b2e202SAlex Deucher 332efe4f000STianci.Yin #define HW_REV(_Major, _Minor, _Rev) \ 333efe4f000STianci.Yin ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 334efe4f000STianci.Yin 335a1255107SAlex Deucher struct amdgpu_ip_block { 336a1255107SAlex Deucher struct amdgpu_ip_block_status status; 337a1255107SAlex Deucher const struct amdgpu_ip_block_version *version; 338a1255107SAlex Deucher }; 339a1255107SAlex Deucher 3402990a1fcSAlex Deucher int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 3415fc3aeebSyanyang1 enum amd_ip_block_type type, 34297b2e202SAlex Deucher u32 major, u32 minor); 34397b2e202SAlex Deucher 3442990a1fcSAlex Deucher struct amdgpu_ip_block * 3452990a1fcSAlex Deucher amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 3465fc3aeebSyanyang1 enum amd_ip_block_type type); 34797b2e202SAlex Deucher 3482990a1fcSAlex Deucher int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 349a1255107SAlex Deucher const struct amdgpu_ip_block_version *ip_block_version); 350a1255107SAlex Deucher 35197b2e202SAlex Deucher /* 35297b2e202SAlex Deucher * BIOS. 35397b2e202SAlex Deucher */ 35497b2e202SAlex Deucher bool amdgpu_get_bios(struct amdgpu_device *adev); 35597b2e202SAlex Deucher bool amdgpu_read_bios(struct amdgpu_device *adev); 35697b2e202SAlex Deucher 35797b2e202SAlex Deucher /* 35897b2e202SAlex Deucher * Clocks 35997b2e202SAlex Deucher */ 36097b2e202SAlex Deucher 36197b2e202SAlex Deucher #define AMDGPU_MAX_PPLL 3 36297b2e202SAlex Deucher 36397b2e202SAlex Deucher struct amdgpu_clock { 36497b2e202SAlex Deucher struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 36597b2e202SAlex Deucher struct amdgpu_pll spll; 36697b2e202SAlex Deucher struct amdgpu_pll mpll; 36797b2e202SAlex Deucher /* 10 Khz units */ 36897b2e202SAlex Deucher uint32_t default_mclk; 36997b2e202SAlex Deucher uint32_t default_sclk; 37097b2e202SAlex Deucher uint32_t default_dispclk; 37197b2e202SAlex Deucher uint32_t current_dispclk; 37297b2e202SAlex Deucher uint32_t dp_extclk; 37397b2e202SAlex Deucher uint32_t max_pixel_clock; 37497b2e202SAlex Deucher }; 37597b2e202SAlex Deucher 37697b2e202SAlex Deucher /* sub-allocation manager, it has to be protected by another lock. 37797b2e202SAlex Deucher * By conception this is an helper for other part of the driver 37897b2e202SAlex Deucher * like the indirect buffer or semaphore, which both have their 37997b2e202SAlex Deucher * locking. 38097b2e202SAlex Deucher * 38197b2e202SAlex Deucher * Principe is simple, we keep a list of sub allocation in offset 38297b2e202SAlex Deucher * order (first entry has offset == 0, last entry has the highest 38397b2e202SAlex Deucher * offset). 38497b2e202SAlex Deucher * 38597b2e202SAlex Deucher * When allocating new object we first check if there is room at 38697b2e202SAlex Deucher * the end total_size - (last_object_offset + last_object_size) >= 38797b2e202SAlex Deucher * alloc_size. If so we allocate new object there. 38897b2e202SAlex Deucher * 38997b2e202SAlex Deucher * When there is not enough room at the end, we start waiting for 39097b2e202SAlex Deucher * each sub object until we reach object_offset+object_size >= 39197b2e202SAlex Deucher * alloc_size, this object then become the sub object we return. 39297b2e202SAlex Deucher * 39397b2e202SAlex Deucher * Alignment can't be bigger than page size. 39497b2e202SAlex Deucher * 39597b2e202SAlex Deucher * Hole are not considered for allocation to keep things simple. 39697b2e202SAlex Deucher * Assumption is that there won't be hole (all object on same 39797b2e202SAlex Deucher * alignment). 39897b2e202SAlex Deucher */ 3996ba60b89SChristian König 4006ba60b89SChristian König #define AMDGPU_SA_NUM_FENCE_LISTS 32 4016ba60b89SChristian König 40297b2e202SAlex Deucher struct amdgpu_sa_manager { 40397b2e202SAlex Deucher wait_queue_head_t wq; 40497b2e202SAlex Deucher struct amdgpu_bo *bo; 40597b2e202SAlex Deucher struct list_head *hole; 4066ba60b89SChristian König struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 40797b2e202SAlex Deucher struct list_head olist; 40897b2e202SAlex Deucher unsigned size; 40997b2e202SAlex Deucher uint64_t gpu_addr; 41097b2e202SAlex Deucher void *cpu_ptr; 41197b2e202SAlex Deucher uint32_t domain; 41297b2e202SAlex Deucher uint32_t align; 41397b2e202SAlex Deucher }; 41497b2e202SAlex Deucher 41597b2e202SAlex Deucher /* sub-allocation buffer */ 41697b2e202SAlex Deucher struct amdgpu_sa_bo { 41797b2e202SAlex Deucher struct list_head olist; 41897b2e202SAlex Deucher struct list_head flist; 41997b2e202SAlex Deucher struct amdgpu_sa_manager *manager; 42097b2e202SAlex Deucher unsigned soffset; 42197b2e202SAlex Deucher unsigned eoffset; 422f54d1867SChris Wilson struct dma_fence *fence; 42397b2e202SAlex Deucher }; 42497b2e202SAlex Deucher 425d573de2dSRex Zhu int amdgpu_fence_slab_init(void); 426d573de2dSRex Zhu void amdgpu_fence_slab_fini(void); 42797b2e202SAlex Deucher 42897b2e202SAlex Deucher /* 42997b2e202SAlex Deucher * IRQS. 43097b2e202SAlex Deucher */ 43197b2e202SAlex Deucher 43297b2e202SAlex Deucher struct amdgpu_flip_work { 433325cbba1SMichel Dänzer struct delayed_work flip_work; 43497b2e202SAlex Deucher struct work_struct unpin_work; 43597b2e202SAlex Deucher struct amdgpu_device *adev; 43697b2e202SAlex Deucher int crtc_id; 437325cbba1SMichel Dänzer u32 target_vblank; 43897b2e202SAlex Deucher uint64_t base; 43997b2e202SAlex Deucher struct drm_pending_vblank_event *event; 440765e7fbfSChristian König struct amdgpu_bo *old_abo; 441f54d1867SChris Wilson struct dma_fence *excl; 4421ffd2652SChristian König unsigned shared_count; 443f54d1867SChris Wilson struct dma_fence **shared; 444f54d1867SChris Wilson struct dma_fence_cb cb; 445cb9e59d7SAlex Deucher bool async; 44697b2e202SAlex Deucher }; 44797b2e202SAlex Deucher 44897b2e202SAlex Deucher 44997b2e202SAlex Deucher /* 45097b2e202SAlex Deucher * CP & rings. 45197b2e202SAlex Deucher */ 45297b2e202SAlex Deucher 45397b2e202SAlex Deucher struct amdgpu_ib { 45497b2e202SAlex Deucher struct amdgpu_sa_bo *sa_bo; 45597b2e202SAlex Deucher uint32_t length_dw; 45697b2e202SAlex Deucher uint64_t gpu_addr; 45797b2e202SAlex Deucher uint32_t *ptr; 458de807f81SJammy Zhou uint32_t flags; 45997b2e202SAlex Deucher }; 46097b2e202SAlex Deucher 4611b1f42d8SLucas Stach extern const struct drm_sched_backend_ops amdgpu_sched_ops; 462c1b69ed0SChunming Zhou 46397b2e202SAlex Deucher /* 46497b2e202SAlex Deucher * file private structure 46597b2e202SAlex Deucher */ 46697b2e202SAlex Deucher 46797b2e202SAlex Deucher struct amdgpu_fpriv { 46897b2e202SAlex Deucher struct amdgpu_vm vm; 469b85891bdSJunwei Zhang struct amdgpu_bo_va *prt_va; 4700f4b3c68SChristian König struct amdgpu_bo_va *csa_va; 47197b2e202SAlex Deucher struct mutex bo_list_lock; 47297b2e202SAlex Deucher struct idr bo_list_handles; 47397b2e202SAlex Deucher struct amdgpu_ctx_mgr ctx_mgr; 47497b2e202SAlex Deucher }; 47597b2e202SAlex Deucher 476021830d2SBas Nieuwenhuizen int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 477021830d2SBas Nieuwenhuizen 478b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 479c8e42d57Sxinhui pan unsigned size, 480c8e42d57Sxinhui pan enum amdgpu_ib_pool_type pool, 481c8e42d57Sxinhui pan struct amdgpu_ib *ib); 4824d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 483f54d1867SChris Wilson struct dma_fence *f); 484b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 48550ddc75eSJunwei Zhang struct amdgpu_ib *ibs, struct amdgpu_job *job, 48650ddc75eSJunwei Zhang struct dma_fence **f); 48797b2e202SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev); 48897b2e202SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 48997b2e202SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 49097b2e202SAlex Deucher 49197b2e202SAlex Deucher /* 49297b2e202SAlex Deucher * CS. 49397b2e202SAlex Deucher */ 49497b2e202SAlex Deucher struct amdgpu_cs_chunk { 49597b2e202SAlex Deucher uint32_t chunk_id; 49697b2e202SAlex Deucher uint32_t length_dw; 497758ac17fSChristian König void *kdata; 49897b2e202SAlex Deucher }; 49997b2e202SAlex Deucher 5002624dd15SChunming Zhou struct amdgpu_cs_post_dep { 5012624dd15SChunming Zhou struct drm_syncobj *syncobj; 5022624dd15SChunming Zhou struct dma_fence_chain *chain; 5032624dd15SChunming Zhou u64 point; 5042624dd15SChunming Zhou }; 5052624dd15SChunming Zhou 50697b2e202SAlex Deucher struct amdgpu_cs_parser { 50797b2e202SAlex Deucher struct amdgpu_device *adev; 50897b2e202SAlex Deucher struct drm_file *filp; 5093cb485f3SChristian König struct amdgpu_ctx *ctx; 510c3cca41eSChristian König 51197b2e202SAlex Deucher /* chunks */ 51297b2e202SAlex Deucher unsigned nchunks; 51397b2e202SAlex Deucher struct amdgpu_cs_chunk *chunks; 514c3cca41eSChristian König 51550838c8cSChristian König /* scheduler job object */ 51650838c8cSChristian König struct amdgpu_job *job; 5170d346a14SChristian König struct drm_sched_entity *entity; 518c3cca41eSChristian König 519c3cca41eSChristian König /* buffer objects */ 520c3cca41eSChristian König struct ww_acquire_ctx ticket; 521c3cca41eSChristian König struct amdgpu_bo_list *bo_list; 5223fe89771SChristian König struct amdgpu_mn *mn; 52356467ebfSChristian König struct amdgpu_bo_list_entry vm_pd; 52497b2e202SAlex Deucher struct list_head validated; 525f54d1867SChris Wilson struct dma_fence *fence; 526f69f90a1SChristian König uint64_t bytes_moved_threshold; 52700f06b24SJohn Brooks uint64_t bytes_moved_vis_threshold; 528f69f90a1SChristian König uint64_t bytes_moved; 52900f06b24SJohn Brooks uint64_t bytes_moved_vis; 53097b2e202SAlex Deucher 53197b2e202SAlex Deucher /* user fence */ 53291acbeb6SChristian König struct amdgpu_bo_list_entry uf_entry; 533660e8558SDave Airlie 5342624dd15SChunming Zhou unsigned num_post_deps; 5352624dd15SChunming Zhou struct amdgpu_cs_post_dep *post_deps; 53697b2e202SAlex Deucher }; 53797b2e202SAlex Deucher 5387270f839SChristian König static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 5397270f839SChristian König uint32_t ib_idx, int idx) 54097b2e202SAlex Deucher { 54150838c8cSChristian König return p->job->ibs[ib_idx].ptr[idx]; 54297b2e202SAlex Deucher } 54397b2e202SAlex Deucher 5447270f839SChristian König static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 5457270f839SChristian König uint32_t ib_idx, int idx, 5467270f839SChristian König uint32_t value) 5477270f839SChristian König { 54850838c8cSChristian König p->job->ibs[ib_idx].ptr[idx] = value; 5497270f839SChristian König } 5507270f839SChristian König 55197b2e202SAlex Deucher /* 55297b2e202SAlex Deucher * Writeback 55397b2e202SAlex Deucher */ 55454208194SYintian Tao #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 55597b2e202SAlex Deucher 55697b2e202SAlex Deucher struct amdgpu_wb { 55797b2e202SAlex Deucher struct amdgpu_bo *wb_obj; 55897b2e202SAlex Deucher volatile uint32_t *wb; 55997b2e202SAlex Deucher uint64_t gpu_addr; 56097b2e202SAlex Deucher u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 56197b2e202SAlex Deucher unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 56297b2e202SAlex Deucher }; 56397b2e202SAlex Deucher 564131b4b36SAlex Deucher int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 565131b4b36SAlex Deucher void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 56697b2e202SAlex Deucher 56797b2e202SAlex Deucher /* 56897b2e202SAlex Deucher * Benchmarking 56997b2e202SAlex Deucher */ 57097b2e202SAlex Deucher void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 57197b2e202SAlex Deucher 57297b2e202SAlex Deucher 57397b2e202SAlex Deucher /* 57497b2e202SAlex Deucher * Testing 57597b2e202SAlex Deucher */ 57697b2e202SAlex Deucher void amdgpu_test_moves(struct amdgpu_device *adev); 57797b2e202SAlex Deucher 57897b2e202SAlex Deucher /* 57997b2e202SAlex Deucher * ASIC specific register table accessible by UMD 58097b2e202SAlex Deucher */ 58197b2e202SAlex Deucher struct amdgpu_allowed_register_entry { 58297b2e202SAlex Deucher uint32_t reg_offset; 58397b2e202SAlex Deucher bool grbm_indexed; 58497b2e202SAlex Deucher }; 58597b2e202SAlex Deucher 5860cf3c64fSAlex Deucher enum amd_reset_method { 5870cf3c64fSAlex Deucher AMD_RESET_METHOD_LEGACY = 0, 5880cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE0, 5890cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE1, 5900cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE2, 591af484df8SAlex Deucher AMD_RESET_METHOD_BACO, 592af484df8SAlex Deucher AMD_RESET_METHOD_PCI, 5930cf3c64fSAlex Deucher }; 5940cf3c64fSAlex Deucher 5959269bf18SAlex Deucher struct amdgpu_video_codec_info { 5969269bf18SAlex Deucher u32 codec_type; 5979269bf18SAlex Deucher u32 max_width; 5989269bf18SAlex Deucher u32 max_height; 5999269bf18SAlex Deucher u32 max_pixels_per_frame; 6009269bf18SAlex Deucher u32 max_level; 6019269bf18SAlex Deucher }; 6029269bf18SAlex Deucher 6039269bf18SAlex Deucher struct amdgpu_video_codecs { 6049269bf18SAlex Deucher const u32 codec_count; 6059269bf18SAlex Deucher const struct amdgpu_video_codec_info *codec_array; 6069269bf18SAlex Deucher }; 6079269bf18SAlex Deucher 60897b2e202SAlex Deucher /* 60997b2e202SAlex Deucher * ASIC specific functions. 61097b2e202SAlex Deucher */ 61197b2e202SAlex Deucher struct amdgpu_asic_funcs { 61297b2e202SAlex Deucher bool (*read_disabled_bios)(struct amdgpu_device *adev); 6137946b878SAlex Deucher bool (*read_bios_from_rom)(struct amdgpu_device *adev, 6147946b878SAlex Deucher u8 *bios, u32 length_bytes); 61597b2e202SAlex Deucher int (*read_register)(struct amdgpu_device *adev, u32 se_num, 61697b2e202SAlex Deucher u32 sh_num, u32 reg_offset, u32 *value); 61797b2e202SAlex Deucher void (*set_vga_state)(struct amdgpu_device *adev, bool state); 61897b2e202SAlex Deucher int (*reset)(struct amdgpu_device *adev); 6190cf3c64fSAlex Deucher enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 62097b2e202SAlex Deucher /* get the reference clock */ 62197b2e202SAlex Deucher u32 (*get_xclk)(struct amdgpu_device *adev); 62297b2e202SAlex Deucher /* MM block clocks */ 62397b2e202SAlex Deucher int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 62497b2e202SAlex Deucher int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 625841686dfSMaruthi Bayyavarapu /* static power management */ 626841686dfSMaruthi Bayyavarapu int (*get_pcie_lanes)(struct amdgpu_device *adev); 627841686dfSMaruthi Bayyavarapu void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 628bbf282d8SAlex Deucher /* get config memsize register */ 629bbf282d8SAlex Deucher u32 (*get_config_memsize)(struct amdgpu_device *adev); 6302df1b8b6SAlex Deucher /* flush hdp write queue */ 63169882565SChristian König void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 6322df1b8b6SAlex Deucher /* invalidate hdp read cache */ 63369882565SChristian König void (*invalidate_hdp)(struct amdgpu_device *adev, 63469882565SChristian König struct amdgpu_ring *ring); 63569070690SAlex Deucher /* check if the asic needs a full reset of if soft reset will work */ 63669070690SAlex Deucher bool (*need_full_reset)(struct amdgpu_device *adev); 6375253163aSOak Zeng /* initialize doorbell layout for specific asic*/ 6385253163aSOak Zeng void (*init_doorbell_index)(struct amdgpu_device *adev); 639b45e18acSKent Russell /* PCIe bandwidth usage */ 640b45e18acSKent Russell void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 641b45e18acSKent Russell uint64_t *count1); 64244401889SAlex Deucher /* do we need to reset the asic at init time (e.g., kexec) */ 64344401889SAlex Deucher bool (*need_reset_on_init)(struct amdgpu_device *adev); 644dcea6e65SKent Russell /* PCIe replay counter */ 645dcea6e65SKent Russell uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 64669d5436dSAlex Deucher /* device supports BACO */ 64769d5436dSAlex Deucher bool (*supports_baco)(struct amdgpu_device *adev); 6489737a923SAlex Deucher /* pre asic_init quirks */ 6499737a923SAlex Deucher void (*pre_asic_init)(struct amdgpu_device *adev); 650f2b75bc2SEvan Quan /* enter/exit umd stable pstate */ 651f2b75bc2SEvan Quan int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 6529269bf18SAlex Deucher /* query video codecs */ 6539269bf18SAlex Deucher int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 6549269bf18SAlex Deucher const struct amdgpu_video_codecs **codecs); 65597b2e202SAlex Deucher }; 65697b2e202SAlex Deucher 65797b2e202SAlex Deucher /* 65897b2e202SAlex Deucher * IOCTL. 65997b2e202SAlex Deucher */ 66097b2e202SAlex Deucher int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 66197b2e202SAlex Deucher struct drm_file *filp); 66297b2e202SAlex Deucher 66397b2e202SAlex Deucher int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 6647ca24cf2SMarek Olšák int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 6657ca24cf2SMarek Olšák struct drm_file *filp); 66697b2e202SAlex Deucher int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 667eef18a82SJunwei Zhang int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 668eef18a82SJunwei Zhang struct drm_file *filp); 66997b2e202SAlex Deucher 67097b2e202SAlex Deucher /* VRAM scratch page for HDP bug, default vram page */ 67197b2e202SAlex Deucher struct amdgpu_vram_scratch { 67297b2e202SAlex Deucher struct amdgpu_bo *robj; 67397b2e202SAlex Deucher volatile uint32_t *ptr; 67497b2e202SAlex Deucher u64 gpu_addr; 67597b2e202SAlex Deucher }; 67697b2e202SAlex Deucher 67797b2e202SAlex Deucher /* 67897b2e202SAlex Deucher * ACPI 67997b2e202SAlex Deucher */ 68097b2e202SAlex Deucher struct amdgpu_atcs_functions { 68197b2e202SAlex Deucher bool get_ext_state; 68297b2e202SAlex Deucher bool pcie_perf_req; 68397b2e202SAlex Deucher bool pcie_dev_rdy; 68497b2e202SAlex Deucher bool pcie_bus_width; 68597b2e202SAlex Deucher }; 68697b2e202SAlex Deucher 68797b2e202SAlex Deucher struct amdgpu_atcs { 68897b2e202SAlex Deucher struct amdgpu_atcs_functions functions; 68997b2e202SAlex Deucher }; 69097b2e202SAlex Deucher 69197b2e202SAlex Deucher /* 692d03846afSChunming Zhou * CGS 693d03846afSChunming Zhou */ 694110e6f26SDave Airlie struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 695110e6f26SDave Airlie void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 696a8fe58ceSMaruthi Bayyavarapu 697a8fe58ceSMaruthi Bayyavarapu /* 69897b2e202SAlex Deucher * Core structure, functions and helpers. 69997b2e202SAlex Deucher */ 70097b2e202SAlex Deucher typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 70197b2e202SAlex Deucher typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 70297b2e202SAlex Deucher 7034fa1c6a6STao Zhou typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 7044fa1c6a6STao Zhou typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 7054fa1c6a6STao Zhou 70697b2e202SAlex Deucher typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 70797b2e202SAlex Deucher typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 70897b2e202SAlex Deucher 70988807dc8SOak Zeng struct amdgpu_mmio_remap { 71088807dc8SOak Zeng u32 reg_offset; 71188807dc8SOak Zeng resource_size_t bus_addr; 71288807dc8SOak Zeng }; 71388807dc8SOak Zeng 7144522824cSShaoyun Liu /* Define the HW IP blocks will be used in driver , add more if necessary */ 7154522824cSShaoyun Liu enum amd_hw_ip_block_type { 7164522824cSShaoyun Liu GC_HWIP = 1, 7174522824cSShaoyun Liu HDP_HWIP, 7184522824cSShaoyun Liu SDMA0_HWIP, 7194522824cSShaoyun Liu SDMA1_HWIP, 720fa5d2e6fSLe Ma SDMA2_HWIP, 721fa5d2e6fSLe Ma SDMA3_HWIP, 722fa5d2e6fSLe Ma SDMA4_HWIP, 723fa5d2e6fSLe Ma SDMA5_HWIP, 724fa5d2e6fSLe Ma SDMA6_HWIP, 725fa5d2e6fSLe Ma SDMA7_HWIP, 7264522824cSShaoyun Liu MMHUB_HWIP, 7274522824cSShaoyun Liu ATHUB_HWIP, 7284522824cSShaoyun Liu NBIO_HWIP, 7294522824cSShaoyun Liu MP0_HWIP, 730e6636ae1SEvan Quan MP1_HWIP, 7314522824cSShaoyun Liu UVD_HWIP, 7324522824cSShaoyun Liu VCN_HWIP = UVD_HWIP, 73388a1c40aSLeo Liu JPEG_HWIP = VCN_HWIP, 7344522824cSShaoyun Liu VCE_HWIP, 7354522824cSShaoyun Liu DF_HWIP, 7364522824cSShaoyun Liu DCE_HWIP, 7374522824cSShaoyun Liu OSSSYS_HWIP, 7384522824cSShaoyun Liu SMUIO_HWIP, 7394522824cSShaoyun Liu PWR_HWIP, 7404522824cSShaoyun Liu NBIF_HWIP, 741e6636ae1SEvan Quan THM_HWIP, 74273b19174SRex Zhu CLK_HWIP, 7436501a771SHawking Zhang UMC_HWIP, 7446501a771SHawking Zhang RSMU_HWIP, 7454522824cSShaoyun Liu MAX_HWIP 7464522824cSShaoyun Liu }; 7474522824cSShaoyun Liu 748113b47e7SLe Ma #define HWIP_MAX_INSTANCE 8 7494522824cSShaoyun Liu 75011dc9364SRex Zhu struct amd_powerplay { 75111dc9364SRex Zhu void *pp_handle; 75211dc9364SRex Zhu const struct amd_pm_funcs *pp_funcs; 75311dc9364SRex Zhu }; 75411dc9364SRex Zhu 75573275181SEvan Quan /* polaris10 kickers */ 75673275181SEvan Quan #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 75773275181SEvan Quan ((rid == 0xE3) || \ 75873275181SEvan Quan (rid == 0xE4) || \ 75973275181SEvan Quan (rid == 0xE5) || \ 76073275181SEvan Quan (rid == 0xE7) || \ 76173275181SEvan Quan (rid == 0xEF))) || \ 76273275181SEvan Quan ((did == 0x6FDF) && \ 76373275181SEvan Quan ((rid == 0xE7) || \ 76473275181SEvan Quan (rid == 0xEF) || \ 76573275181SEvan Quan (rid == 0xFF)))) 76673275181SEvan Quan 76773275181SEvan Quan #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 76873275181SEvan Quan ((rid == 0xE1) || \ 76973275181SEvan Quan (rid == 0xF7))) 77073275181SEvan Quan 77173275181SEvan Quan /* polaris11 kickers */ 77273275181SEvan Quan #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 77373275181SEvan Quan ((rid == 0xE0) || \ 77473275181SEvan Quan (rid == 0xE5))) || \ 77573275181SEvan Quan ((did == 0x67FF) && \ 77673275181SEvan Quan ((rid == 0xCF) || \ 77773275181SEvan Quan (rid == 0xEF) || \ 77873275181SEvan Quan (rid == 0xFF)))) 77973275181SEvan Quan 78073275181SEvan Quan #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 78173275181SEvan Quan ((rid == 0xE2))) 78273275181SEvan Quan 78373275181SEvan Quan /* polaris12 kickers */ 78473275181SEvan Quan #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 78573275181SEvan Quan ((rid == 0xC0) || \ 78673275181SEvan Quan (rid == 0xC1) || \ 78773275181SEvan Quan (rid == 0xC3) || \ 78873275181SEvan Quan (rid == 0xC7))) || \ 78973275181SEvan Quan ((did == 0x6981) && \ 79073275181SEvan Quan ((rid == 0x00) || \ 79173275181SEvan Quan (rid == 0x01) || \ 79273275181SEvan Quan (rid == 0x10)))) 79373275181SEvan Quan 7940c49e0b8SChunming Zhou #define AMDGPU_RESET_MAGIC_NUM 64 795e4cf4bf5SJonathan Kim #define AMDGPU_MAX_DF_PERFMONS 4 79697b2e202SAlex Deucher struct amdgpu_device { 79797b2e202SAlex Deucher struct device *dev; 79897b2e202SAlex Deucher struct pci_dev *pdev; 7998aba21b7SLuben Tuikov struct drm_device ddev; 80097b2e202SAlex Deucher 801a8fe58ceSMaruthi Bayyavarapu #ifdef CONFIG_DRM_AMD_ACP 802a8fe58ceSMaruthi Bayyavarapu struct amdgpu_acp acp; 803a8fe58ceSMaruthi Bayyavarapu #endif 804d95e8e97SDennis Li struct amdgpu_hive_info *hive; 80597b2e202SAlex Deucher /* ASIC */ 8062f7d10b3SJammy Zhou enum amd_asic_type asic_type; 80797b2e202SAlex Deucher uint32_t family; 80897b2e202SAlex Deucher uint32_t rev_id; 80997b2e202SAlex Deucher uint32_t external_rev_id; 81097b2e202SAlex Deucher unsigned long flags; 81154f78a76SAlex Deucher unsigned long apu_flags; 81297b2e202SAlex Deucher int usec_timeout; 81397b2e202SAlex Deucher const struct amdgpu_asic_funcs *asic_funcs; 81497b2e202SAlex Deucher bool shutdown; 815fd5fd480SChunming Zhou bool need_swiotlb; 81697b2e202SAlex Deucher bool accel_working; 81797b2e202SAlex Deucher struct notifier_block acpi_nb; 81897b2e202SAlex Deucher struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 81998d28ac2SNirmoy Das struct debugfs_blob_wrapper debugfs_vbios_blob; 820102c16a0SLyude Paul struct amdgpu_atif *atif; 82197b2e202SAlex Deucher struct amdgpu_atcs atcs; 82297b2e202SAlex Deucher struct mutex srbm_mutex; 82397b2e202SAlex Deucher /* GRBM index mutex. Protects concurrent access to GRBM index */ 82497b2e202SAlex Deucher struct mutex grbm_idx_mutex; 82597b2e202SAlex Deucher struct dev_pm_domain vga_pm_domain; 82697b2e202SAlex Deucher bool have_disp_power_ref; 827bae17d2aSJack Xiao bool have_atomics_support; 82897b2e202SAlex Deucher 82997b2e202SAlex Deucher /* BIOS */ 8300cdd5005SAlex Deucher bool is_atom_fw; 83197b2e202SAlex Deucher uint8_t *bios; 832a9f5db9cSEvan Quan uint32_t bios_size; 833a5bde2f9SAlex Deucher uint32_t bios_scratch_reg_offset; 83497b2e202SAlex Deucher uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 83597b2e202SAlex Deucher 83697b2e202SAlex Deucher /* Register/doorbell mmio */ 83797b2e202SAlex Deucher resource_size_t rmmio_base; 83897b2e202SAlex Deucher resource_size_t rmmio_size; 83997b2e202SAlex Deucher void __iomem *rmmio; 84097b2e202SAlex Deucher /* protects concurrent MM_INDEX/DATA based register access */ 84197b2e202SAlex Deucher spinlock_t mmio_idx_lock; 84288807dc8SOak Zeng struct amdgpu_mmio_remap rmmio_remap; 84397b2e202SAlex Deucher /* protects concurrent SMC based register access */ 84497b2e202SAlex Deucher spinlock_t smc_idx_lock; 84597b2e202SAlex Deucher amdgpu_rreg_t smc_rreg; 84697b2e202SAlex Deucher amdgpu_wreg_t smc_wreg; 84797b2e202SAlex Deucher /* protects concurrent PCIE register access */ 84897b2e202SAlex Deucher spinlock_t pcie_idx_lock; 84997b2e202SAlex Deucher amdgpu_rreg_t pcie_rreg; 85097b2e202SAlex Deucher amdgpu_wreg_t pcie_wreg; 85136b9a952SHuang Rui amdgpu_rreg_t pciep_rreg; 85236b9a952SHuang Rui amdgpu_wreg_t pciep_wreg; 8534fa1c6a6STao Zhou amdgpu_rreg64_t pcie_rreg64; 8544fa1c6a6STao Zhou amdgpu_wreg64_t pcie_wreg64; 85597b2e202SAlex Deucher /* protects concurrent UVD register access */ 85697b2e202SAlex Deucher spinlock_t uvd_ctx_idx_lock; 85797b2e202SAlex Deucher amdgpu_rreg_t uvd_ctx_rreg; 85897b2e202SAlex Deucher amdgpu_wreg_t uvd_ctx_wreg; 85997b2e202SAlex Deucher /* protects concurrent DIDT register access */ 86097b2e202SAlex Deucher spinlock_t didt_idx_lock; 86197b2e202SAlex Deucher amdgpu_rreg_t didt_rreg; 86297b2e202SAlex Deucher amdgpu_wreg_t didt_wreg; 863ccdbb20aSRex Zhu /* protects concurrent gc_cac register access */ 864ccdbb20aSRex Zhu spinlock_t gc_cac_idx_lock; 865ccdbb20aSRex Zhu amdgpu_rreg_t gc_cac_rreg; 866ccdbb20aSRex Zhu amdgpu_wreg_t gc_cac_wreg; 86716abb5d2SEvan Quan /* protects concurrent se_cac register access */ 86816abb5d2SEvan Quan spinlock_t se_cac_idx_lock; 86916abb5d2SEvan Quan amdgpu_rreg_t se_cac_rreg; 87016abb5d2SEvan Quan amdgpu_wreg_t se_cac_wreg; 87197b2e202SAlex Deucher /* protects concurrent ENDPOINT (audio) register access */ 87297b2e202SAlex Deucher spinlock_t audio_endpt_idx_lock; 87397b2e202SAlex Deucher amdgpu_block_rreg_t audio_endpt_rreg; 87497b2e202SAlex Deucher amdgpu_block_wreg_t audio_endpt_wreg; 87597b2e202SAlex Deucher void __iomem *rio_mem; 87697b2e202SAlex Deucher resource_size_t rio_mem_size; 87797b2e202SAlex Deucher struct amdgpu_doorbell doorbell; 87897b2e202SAlex Deucher 87997b2e202SAlex Deucher /* clock/pll info */ 88097b2e202SAlex Deucher struct amdgpu_clock clock; 88197b2e202SAlex Deucher 88297b2e202SAlex Deucher /* MC */ 883770d13b1SChristian König struct amdgpu_gmc gmc; 88497b2e202SAlex Deucher struct amdgpu_gart gart; 88592e71b06SChristian König dma_addr_t dummy_page_addr; 88697b2e202SAlex Deucher struct amdgpu_vm_manager vm_manager; 887e60f8db5SAlex Xie struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 8881daa2bfaSLe Ma unsigned num_vmhubs; 88997b2e202SAlex Deucher 89097b2e202SAlex Deucher /* memory management */ 89197b2e202SAlex Deucher struct amdgpu_mman mman; 89297b2e202SAlex Deucher struct amdgpu_vram_scratch vram_scratch; 89397b2e202SAlex Deucher struct amdgpu_wb wb; 89497b2e202SAlex Deucher atomic64_t num_bytes_moved; 895dbd5ed60SChristian König atomic64_t num_evictions; 89668e2c5ffSMarek Olšák atomic64_t num_vram_cpu_page_faults; 897d94aed5aSMarek Olšák atomic_t gpu_reset_counter; 898f1892138SChunming Zhou atomic_t vram_lost_counter; 89997b2e202SAlex Deucher 90095844d20SMarek Olšák /* data for buffer migration throttling */ 90195844d20SMarek Olšák struct { 90295844d20SMarek Olšák spinlock_t lock; 90395844d20SMarek Olšák s64 last_update_us; 90495844d20SMarek Olšák s64 accum_us; /* accumulated microseconds */ 90500f06b24SJohn Brooks s64 accum_us_vis; /* for visible VRAM */ 90695844d20SMarek Olšák u32 log2_max_MBps; 90795844d20SMarek Olšák } mm_stats; 90895844d20SMarek Olšák 90997b2e202SAlex Deucher /* display */ 9109accf2fdSEmily Deng bool enable_virtual_display; 91197b2e202SAlex Deucher struct amdgpu_mode_info mode_info; 9124562236bSHarry Wentland /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 91397b2e202SAlex Deucher struct work_struct hotplug_work; 91497b2e202SAlex Deucher struct amdgpu_irq_src crtc_irq; 91511f1a553SWayne Lin struct amdgpu_irq_src vline0_irq; 916d2574c33SMario Kleiner struct amdgpu_irq_src vupdate_irq; 91797b2e202SAlex Deucher struct amdgpu_irq_src pageflip_irq; 91897b2e202SAlex Deucher struct amdgpu_irq_src hpd_irq; 919c79fe9b4SLeo (Hanghong) Ma struct amdgpu_irq_src dmub_trace_irq; 92097b2e202SAlex Deucher 92197b2e202SAlex Deucher /* rings */ 92276bf0db5SChristian König u64 fence_context; 92397b2e202SAlex Deucher unsigned num_rings; 92497b2e202SAlex Deucher struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 92597b2e202SAlex Deucher bool ib_pool_ready; 9269ecefb19SChristian König struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 9271c6d567bSNirmoy Das struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 92897b2e202SAlex Deucher 92997b2e202SAlex Deucher /* interrupts */ 93097b2e202SAlex Deucher struct amdgpu_irq irq; 93197b2e202SAlex Deucher 9321f7371b2SAlex Deucher /* powerplay */ 9331f7371b2SAlex Deucher struct amd_powerplay powerplay; 934f3898ea1SEric Huang bool pp_force_state_enabled; 9351f7371b2SAlex Deucher 936137d63abSHuang Rui /* smu */ 937137d63abSHuang Rui struct smu_context smu; 938137d63abSHuang Rui 93997b2e202SAlex Deucher /* dpm */ 94097b2e202SAlex Deucher struct amdgpu_pm pm; 94197b2e202SAlex Deucher u32 cg_flags; 94297b2e202SAlex Deucher u32 pg_flags; 94397b2e202SAlex Deucher 944bebc0762SHawking Zhang /* nbio */ 945bebc0762SHawking Zhang struct amdgpu_nbio nbio; 946bebc0762SHawking Zhang 947b291a387SHawking Zhang /* hdp */ 948b291a387SHawking Zhang struct amdgpu_hdp hdp; 949b291a387SHawking Zhang 950293f2563SHawking Zhang /* smuio */ 951293f2563SHawking Zhang struct amdgpu_smuio smuio; 952293f2563SHawking Zhang 953d3a5a121STao Zhou /* mmhub */ 954d3a5a121STao Zhou struct amdgpu_mmhub mmhub; 955d3a5a121STao Zhou 9568ffff9b4SOak Zeng /* gfxhub */ 9578ffff9b4SOak Zeng struct amdgpu_gfxhub gfxhub; 9588ffff9b4SOak Zeng 95997b2e202SAlex Deucher /* gfx */ 96097b2e202SAlex Deucher struct amdgpu_gfx gfx; 96197b2e202SAlex Deucher 96297b2e202SAlex Deucher /* sdma */ 963c113ea1cSAlex Deucher struct amdgpu_sdma sdma; 96497b2e202SAlex Deucher 96597b2e202SAlex Deucher /* uvd */ 96697b2e202SAlex Deucher struct amdgpu_uvd uvd; 96797b2e202SAlex Deucher 96897b2e202SAlex Deucher /* vce */ 96997b2e202SAlex Deucher struct amdgpu_vce vce; 97095d0906fSLeo Liu 97195d0906fSLeo Liu /* vcn */ 97295d0906fSLeo Liu struct amdgpu_vcn vcn; 97397b2e202SAlex Deucher 97488a1c40aSLeo Liu /* jpeg */ 97588a1c40aSLeo Liu struct amdgpu_jpeg jpeg; 97688a1c40aSLeo Liu 97797b2e202SAlex Deucher /* firmwares */ 97897b2e202SAlex Deucher struct amdgpu_firmware firmware; 97997b2e202SAlex Deucher 9800e5ca0d1SHuang Rui /* PSP */ 9810e5ca0d1SHuang Rui struct psp_context psp; 9820e5ca0d1SHuang Rui 98397b2e202SAlex Deucher /* GDS */ 98497b2e202SAlex Deucher struct amdgpu_gds gds; 98597b2e202SAlex Deucher 986611736d8SFelix Kuehling /* KFD */ 987611736d8SFelix Kuehling struct amdgpu_kfd_dev kfd; 988611736d8SFelix Kuehling 989045c0216STao Zhou /* UMC */ 990045c0216STao Zhou struct amdgpu_umc umc; 991045c0216STao Zhou 9924562236bSHarry Wentland /* display related functionality */ 9934562236bSHarry Wentland struct amdgpu_display_manager dm; 9944562236bSHarry Wentland 995a538bbe7SJack Xiao /* mes */ 996a538bbe7SJack Xiao bool enable_mes; 997a538bbe7SJack Xiao struct amdgpu_mes mes; 998a538bbe7SJack Xiao 999bdf84a80SJoseph Greathouse /* df */ 1000bdf84a80SJoseph Greathouse struct amdgpu_df df; 1001bdf84a80SJoseph Greathouse 1002a1255107SAlex Deucher struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 100397b2e202SAlex Deucher int num_ip_blocks; 100497b2e202SAlex Deucher struct mutex mn_lock; 100597b2e202SAlex Deucher DECLARE_HASHTABLE(mn_hash, 7); 100697b2e202SAlex Deucher 100797b2e202SAlex Deucher /* tracking pinned memory */ 1008a5ccfe5cSMichel Dänzer atomic64_t vram_pin_size; 1009a5ccfe5cSMichel Dänzer atomic64_t visible_pin_size; 1010a5ccfe5cSMichel Dänzer atomic64_t gart_pin_size; 1011130e0371SOded Gabbay 10124522824cSShaoyun Liu /* soc15 register offset based on ip, instance and segment */ 10134522824cSShaoyun Liu uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 10144522824cSShaoyun Liu 10152dc80b00SShirish S /* delayed work_func for deferring clockgating during resume */ 1016beff74bcSAlex Deucher struct delayed_work delayed_init_work; 10172dc80b00SShirish S 10185a5099cbSXiangliang Yu struct amdgpu_virt virt; 10190c4e7fa5SChunming Zhou 10200c4e7fa5SChunming Zhou /* link all shadow bo */ 10210c4e7fa5SChunming Zhou struct list_head shadow_list; 10220c4e7fa5SChunming Zhou struct mutex shadow_list_lock; 10235c1354bdSChunming Zhou 1024c836fec5SJim Qu /* record hw reset is performed */ 1025c836fec5SJim Qu bool has_hw_reset; 10260c49e0b8SChunming Zhou u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1027c836fec5SJim Qu 102844779b43SRex Zhu /* s3/s4 mask */ 102944779b43SRex Zhu bool in_suspend; 103085625e64SEvan Quan bool in_hibernate; 103144779b43SRex Zhu 1032b00978deSPrike Liang /* 1033b00978deSPrike Liang * The combination flag in_poweroff_reboot_com used to identify the poweroff 1034b00978deSPrike Liang * and reboot opt in the s0i3 system-wide suspend. 1035b00978deSPrike Liang */ 1036b00978deSPrike Liang bool in_poweroff_reboot_com; 1037b00978deSPrike Liang 103853b3f8f4SDennis Li atomic_t in_gpu_reset; 1039a3a09142SAlex Deucher enum pp_mp1_state mp1_state; 10406049db43SDennis Li struct rw_semaphore reset_sem; 1041409c5191SOak Zeng struct amdgpu_doorbell_index doorbell_index; 1042d4535e2cSAndrey Grodzovsky 104362914a99SJason Gunthorpe struct mutex notifier_lock; 104462914a99SJason Gunthorpe 104526bc5340SAndrey Grodzovsky int asic_reset_res; 1046d4535e2cSAndrey Grodzovsky struct work_struct xgmi_reset_work; 1047*655ce9cbSshaoyunl struct list_head reset_list; 10489b638f97Sshaoyunl 1049912dfc84SEvan Quan long gfx_timeout; 1050912dfc84SEvan Quan long sdma_timeout; 1051912dfc84SEvan Quan long video_timeout; 1052912dfc84SEvan Quan long compute_timeout; 1053fb2dbfd2SKent Russell 1054fb2dbfd2SKent Russell uint64_t unique_id; 1055e4cf4bf5SJonathan Kim uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 10565c5b2ba0SEvan Quan 10576ae6c7d4SAlex Deucher /* enable runtime pm on the device */ 10586ae6c7d4SAlex Deucher bool runpm; 1059f0f7ddfcSAlex Deucher bool in_runpm; 1060b10c1c5bSAlex Deucher bool has_pr3; 10617c868b59SYintian Tao 10627c868b59SYintian Tao bool pm_sysfs_en; 10637c868b59SYintian Tao bool ucode_sysfs_en; 1064bd607166SKent Russell 1065bd607166SKent Russell /* Chip product information */ 1066bd607166SKent Russell char product_number[16]; 1067bd607166SKent Russell char product_name[32]; 10688df1a28fSDan Carpenter char serial[20]; 1069728e7e0cSJiange Zhao 1070728e7e0cSJiange Zhao struct amdgpu_autodump autodump; 1071b265bdbdSEvan Quan 1072b265bdbdSEvan Quan atomic_t throttling_logging_enabled; 1073b265bdbdSEvan Quan struct ratelimit_state throttling_logging_rs; 10745436ab94SStanley.Yang uint32_t ras_features; 1075c1dd4aa6SAndrey Grodzovsky 1076bf36b52eSAndrey Grodzovsky bool in_pci_err_recovery; 1077c1dd4aa6SAndrey Grodzovsky struct pci_saved_state *pci_state; 107897b2e202SAlex Deucher }; 107997b2e202SAlex Deucher 10801348969aSLuben Tuikov static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 10811348969aSLuben Tuikov { 10828aba21b7SLuben Tuikov return container_of(ddev, struct amdgpu_device, ddev); 10831348969aSLuben Tuikov } 10841348969aSLuben Tuikov 10854a580877SLuben Tuikov static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 10864a580877SLuben Tuikov { 10878aba21b7SLuben Tuikov return &adev->ddev; 10884a580877SLuben Tuikov } 10894a580877SLuben Tuikov 1090a7d64de6SChristian König static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1091a7d64de6SChristian König { 1092a7d64de6SChristian König return container_of(bdev, struct amdgpu_device, mman.bdev); 1093a7d64de6SChristian König } 1094a7d64de6SChristian König 109597b2e202SAlex Deucher int amdgpu_device_init(struct amdgpu_device *adev, 109697b2e202SAlex Deucher uint32_t flags); 109797b2e202SAlex Deucher void amdgpu_device_fini(struct amdgpu_device *adev); 109897b2e202SAlex Deucher int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 109997b2e202SAlex Deucher 1100e35e2b11STianci.Yin void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1101e35e2b11STianci.Yin uint32_t *buf, size_t size, bool write); 1102f7ee1874SHawking Zhang uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1103f7ee1874SHawking Zhang uint32_t reg, uint32_t acc_flags); 1104f7ee1874SHawking Zhang void amdgpu_device_wreg(struct amdgpu_device *adev, 1105f7ee1874SHawking Zhang uint32_t reg, uint32_t v, 110615d72fd7SMonk Liu uint32_t acc_flags); 1107f7ee1874SHawking Zhang void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1108f7ee1874SHawking Zhang uint32_t reg, uint32_t v); 1109421a2a30SMonk Liu void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1110421a2a30SMonk Liu uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1111421a2a30SMonk Liu 111297b2e202SAlex Deucher u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 111397b2e202SAlex Deucher void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 111497b2e202SAlex Deucher 11151bba3683SHawking Zhang u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 11161bba3683SHawking Zhang u32 pcie_index, u32 pcie_data, 11171bba3683SHawking Zhang u32 reg_addr); 11181bba3683SHawking Zhang u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 11191bba3683SHawking Zhang u32 pcie_index, u32 pcie_data, 11201bba3683SHawking Zhang u32 reg_addr); 11211bba3683SHawking Zhang void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 11221bba3683SHawking Zhang u32 pcie_index, u32 pcie_data, 11231bba3683SHawking Zhang u32 reg_addr, u32 reg_data); 11241bba3683SHawking Zhang void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 11251bba3683SHawking Zhang u32 pcie_index, u32 pcie_data, 11261bba3683SHawking Zhang u32 reg_addr, u64 reg_data); 11271bba3683SHawking Zhang 11284562236bSHarry Wentland bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 11294562236bSHarry Wentland bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 11304562236bSHarry Wentland 11319475a943SShaoyun Liu int emu_soc_asic_init(struct amdgpu_device *adev); 11329475a943SShaoyun Liu 113397b2e202SAlex Deucher /* 113497b2e202SAlex Deucher * Registers read & write functions. 113597b2e202SAlex Deucher */ 113615d72fd7SMonk Liu #define AMDGPU_REGS_NO_KIQ (1<<1) 113715d72fd7SMonk Liu 1138f7ee1874SHawking Zhang #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1139f7ee1874SHawking Zhang #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 114015d72fd7SMonk Liu 1141f384ff95SHawking Zhang #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1142f384ff95SHawking Zhang #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1143c68dbcd8Schen gong 1144421a2a30SMonk Liu #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1145421a2a30SMonk Liu #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1146421a2a30SMonk Liu 1147f7ee1874SHawking Zhang #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1148f7ee1874SHawking Zhang #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1149f7ee1874SHawking Zhang #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 115097b2e202SAlex Deucher #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 115197b2e202SAlex Deucher #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 115297b2e202SAlex Deucher #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 115397b2e202SAlex Deucher #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 115436b9a952SHuang Rui #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 115536b9a952SHuang Rui #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 11564fa1c6a6STao Zhou #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 11574fa1c6a6STao Zhou #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 115897b2e202SAlex Deucher #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 115997b2e202SAlex Deucher #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 116097b2e202SAlex Deucher #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 116197b2e202SAlex Deucher #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 116297b2e202SAlex Deucher #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 116397b2e202SAlex Deucher #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1164ccdbb20aSRex Zhu #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1165ccdbb20aSRex Zhu #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 116616abb5d2SEvan Quan #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 116716abb5d2SEvan Quan #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 116897b2e202SAlex Deucher #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 116997b2e202SAlex Deucher #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 117097b2e202SAlex Deucher #define WREG32_P(reg, val, mask) \ 117197b2e202SAlex Deucher do { \ 117297b2e202SAlex Deucher uint32_t tmp_ = RREG32(reg); \ 117397b2e202SAlex Deucher tmp_ &= (mask); \ 117497b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 117597b2e202SAlex Deucher WREG32(reg, tmp_); \ 117697b2e202SAlex Deucher } while (0) 117797b2e202SAlex Deucher #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 117897b2e202SAlex Deucher #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 117997b2e202SAlex Deucher #define WREG32_PLL_P(reg, val, mask) \ 118097b2e202SAlex Deucher do { \ 118197b2e202SAlex Deucher uint32_t tmp_ = RREG32_PLL(reg); \ 118297b2e202SAlex Deucher tmp_ &= (mask); \ 118397b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 118497b2e202SAlex Deucher WREG32_PLL(reg, tmp_); \ 118597b2e202SAlex Deucher } while (0) 1186fb40bcebSAlex Jivin 1187fb40bcebSAlex Jivin #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1188fb40bcebSAlex Jivin do { \ 1189fb40bcebSAlex Jivin u32 tmp = RREG32_SMC(_Reg); \ 1190fb40bcebSAlex Jivin tmp &= (_Mask); \ 1191fb40bcebSAlex Jivin tmp |= ((_Val) & ~(_Mask)); \ 1192fb40bcebSAlex Jivin WREG32_SMC(_Reg, tmp); \ 1193fb40bcebSAlex Jivin } while (0) 1194fb40bcebSAlex Jivin 1195f7ee1874SHawking Zhang #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 119697b2e202SAlex Deucher #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 119797b2e202SAlex Deucher #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 119897b2e202SAlex Deucher 119997b2e202SAlex Deucher #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 120097b2e202SAlex Deucher #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 120197b2e202SAlex Deucher 120297b2e202SAlex Deucher #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 120397b2e202SAlex Deucher (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 120497b2e202SAlex Deucher (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 120597b2e202SAlex Deucher 120697b2e202SAlex Deucher #define REG_GET_FIELD(value, reg, field) \ 120797b2e202SAlex Deucher (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 120897b2e202SAlex Deucher 120961cb8cefSTom St Denis #define WREG32_FIELD(reg, field, val) \ 121061cb8cefSTom St Denis WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 121161cb8cefSTom St Denis 1212ccaf3574STom St Denis #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1213ccaf3574STom St Denis WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1214ccaf3574STom St Denis 121597b2e202SAlex Deucher /* 121697b2e202SAlex Deucher * BIOS helpers. 121797b2e202SAlex Deucher */ 121897b2e202SAlex Deucher #define RBIOS8(i) (adev->bios[i]) 121997b2e202SAlex Deucher #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 122097b2e202SAlex Deucher #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 122197b2e202SAlex Deucher 122297b2e202SAlex Deucher /* 122397b2e202SAlex Deucher * ASICs macro. 122497b2e202SAlex Deucher */ 122597b2e202SAlex Deucher #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 122697b2e202SAlex Deucher #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 12270cf3c64fSAlex Deucher #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 122897b2e202SAlex Deucher #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 122997b2e202SAlex Deucher #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 123097b2e202SAlex Deucher #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1231841686dfSMaruthi Bayyavarapu #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1232841686dfSMaruthi Bayyavarapu #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1233841686dfSMaruthi Bayyavarapu #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 123497b2e202SAlex Deucher #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 12357946b878SAlex Deucher #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 123697b2e202SAlex Deucher #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1237bbf282d8SAlex Deucher #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1238455d40c9SLikun Gao #define amdgpu_asic_flush_hdp(adev, r) \ 1239455d40c9SLikun Gao ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1240455d40c9SLikun Gao #define amdgpu_asic_invalidate_hdp(adev, r) \ 1241455d40c9SLikun Gao ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r))) 124269070690SAlex Deucher #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 12435253163aSOak Zeng #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1244b45e18acSKent Russell #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 124544401889SAlex Deucher #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1246dcea6e65SKent Russell #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 124769d5436dSAlex Deucher #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 12489737a923SAlex Deucher #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1249f2b75bc2SEvan Quan #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1250f2b75bc2SEvan Quan ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 12519269bf18SAlex Deucher #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 125269d5436dSAlex Deucher 1253e3526257SMonk Liu #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 125497b2e202SAlex Deucher 125597b2e202SAlex Deucher /* Common functions */ 12569a1cddd6Sjqdeng bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 125712938fadSChristian König bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 12585f152b5eSAlex Deucher int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 125912938fadSChristian König struct amdgpu_job* job); 12608111c387SAlex Deucher void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1261af484df8SAlex Deucher int amdgpu_device_pci_reset(struct amdgpu_device *adev); 126239c640c0SAlex Deucher bool amdgpu_device_need_post(struct amdgpu_device *adev); 1263d5fc5e82SChunming Zhou 126400f06b24SJohn Brooks void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 126500f06b24SJohn Brooks u64 num_vis_bytes); 1266d6895ad3SChristian König int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 12679c3f2b54SAlex Deucher void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 126897b2e202SAlex Deucher const u32 *registers, 126997b2e202SAlex Deucher const u32 array_size); 127097b2e202SAlex Deucher 1271fd496ca8SAlex Deucher bool amdgpu_device_supports_atpx(struct drm_device *dev); 12725c03e584SFeifei Xu int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 127331af062aSAlex Deucher bool amdgpu_device_supports_boco(struct drm_device *dev); 1274a69cba42SAlex Deucher bool amdgpu_device_supports_baco(struct drm_device *dev); 1275992af942SJonathan Kim bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1276992af942SJonathan Kim struct amdgpu_device *peer_adev); 1277361dbd01SAlex Deucher int amdgpu_device_baco_enter(struct drm_device *dev); 1278361dbd01SAlex Deucher int amdgpu_device_baco_exit(struct drm_device *dev); 1279992af942SJonathan Kim 128097b2e202SAlex Deucher /* atpx handler */ 128197b2e202SAlex Deucher #if defined(CONFIG_VGA_SWITCHEROO) 128297b2e202SAlex Deucher void amdgpu_register_atpx_handler(void); 128397b2e202SAlex Deucher void amdgpu_unregister_atpx_handler(void); 1284a78fe133SAlex Deucher bool amdgpu_has_atpx_dgpu_power_cntl(void); 12852f5af82eSAlex Deucher bool amdgpu_is_atpx_hybrid(void); 1286efc83cf4SAlex Deucher bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1287714f88e0SAlex Xie bool amdgpu_has_atpx(void); 128897b2e202SAlex Deucher #else 128997b2e202SAlex Deucher static inline void amdgpu_register_atpx_handler(void) {} 129097b2e202SAlex Deucher static inline void amdgpu_unregister_atpx_handler(void) {} 1291a78fe133SAlex Deucher static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 12922f5af82eSAlex Deucher static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1293efc83cf4SAlex Deucher static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1294714f88e0SAlex Xie static inline bool amdgpu_has_atpx(void) { return false; } 129597b2e202SAlex Deucher #endif 129697b2e202SAlex Deucher 129724aeefcdSLyude Paul #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 129824aeefcdSLyude Paul void *amdgpu_atpx_get_dhandle(void); 129924aeefcdSLyude Paul #else 130024aeefcdSLyude Paul static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 130124aeefcdSLyude Paul #endif 130224aeefcdSLyude Paul 130397b2e202SAlex Deucher /* 130497b2e202SAlex Deucher * KMS 130597b2e202SAlex Deucher */ 130697b2e202SAlex Deucher extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1307f498d9edSNils Wallménius extern const int amdgpu_max_kms_ioctl; 130897b2e202SAlex Deucher 13098aba21b7SLuben Tuikov int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 131011b3c20bSGabriel Krisman Bertazi void amdgpu_driver_unload_kms(struct drm_device *dev); 131197b2e202SAlex Deucher void amdgpu_driver_lastclose_kms(struct drm_device *dev); 131297b2e202SAlex Deucher int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 131397b2e202SAlex Deucher void amdgpu_driver_postclose_kms(struct drm_device *dev, 131497b2e202SAlex Deucher struct drm_file *file_priv); 1315cdd61df6SAlex Deucher int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1316de185019SAlex Deucher int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1317de185019SAlex Deucher int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1318e3eff4b5SThomas Zimmermann u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1319e3eff4b5SThomas Zimmermann int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1320e3eff4b5SThomas Zimmermann void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 132197b2e202SAlex Deucher long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 132297b2e202SAlex Deucher unsigned long arg); 1323b1246bd4SLuben Tuikov int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1324b1246bd4SLuben Tuikov struct drm_file *filp); 132597b2e202SAlex Deucher 132697b2e202SAlex Deucher /* 132797b2e202SAlex Deucher * functions used by amdgpu_encoder.c 132897b2e202SAlex Deucher */ 132997b2e202SAlex Deucher struct amdgpu_afmt_acr { 133097b2e202SAlex Deucher u32 clock; 133197b2e202SAlex Deucher 133297b2e202SAlex Deucher int n_32khz; 133397b2e202SAlex Deucher int cts_32khz; 133497b2e202SAlex Deucher 133597b2e202SAlex Deucher int n_44_1khz; 133697b2e202SAlex Deucher int cts_44_1khz; 133797b2e202SAlex Deucher 133897b2e202SAlex Deucher int n_48khz; 133997b2e202SAlex Deucher int cts_48khz; 134097b2e202SAlex Deucher 134197b2e202SAlex Deucher }; 134297b2e202SAlex Deucher 134397b2e202SAlex Deucher struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 134497b2e202SAlex Deucher 134597b2e202SAlex Deucher /* amdgpu_acpi.c */ 134697b2e202SAlex Deucher #if defined(CONFIG_ACPI) 134797b2e202SAlex Deucher int amdgpu_acpi_init(struct amdgpu_device *adev); 134897b2e202SAlex Deucher void amdgpu_acpi_fini(struct amdgpu_device *adev); 134997b2e202SAlex Deucher bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 135097b2e202SAlex Deucher int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 135197b2e202SAlex Deucher u8 perf_req, bool advertise); 135297b2e202SAlex Deucher int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1353206bbafeSDavid Francis 1354206bbafeSDavid Francis void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1355206bbafeSDavid Francis struct amdgpu_dm_backlight_caps *caps); 13569ca5b8a1SLikun Gao bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev); 135797b2e202SAlex Deucher #else 135897b2e202SAlex Deucher static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 135997b2e202SAlex Deucher static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 13609ca5b8a1SLikun Gao static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; } 136197b2e202SAlex Deucher #endif 136297b2e202SAlex Deucher 13639cca0b8eSChristian König int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 13649cca0b8eSChristian König uint64_t addr, struct amdgpu_bo **bo, 13659cca0b8eSChristian König struct amdgpu_bo_va_mapping **mapping); 136697b2e202SAlex Deucher 13674562236bSHarry Wentland #if defined(CONFIG_DRM_AMD_DC) 13684562236bSHarry Wentland int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 13694562236bSHarry Wentland #else 13704562236bSHarry Wentland static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 13714562236bSHarry Wentland #endif 13724562236bSHarry Wentland 1373fdafb359SEvan Quan 1374fdafb359SEvan Quan void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1375fdafb359SEvan Quan void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1376fdafb359SEvan Quan 1377c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1378c9a6b82fSAndrey Grodzovsky pci_channel_state_t state); 1379c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1380c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1381c9a6b82fSAndrey Grodzovsky void amdgpu_pci_resume(struct pci_dev *pdev); 1382c9a6b82fSAndrey Grodzovsky 1383c1dd4aa6SAndrey Grodzovsky bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1384c1dd4aa6SAndrey Grodzovsky bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1385c1dd4aa6SAndrey Grodzovsky 138697b2e202SAlex Deucher #include "amdgpu_object.h" 1387e4cf4bf5SJonathan Kim 1388c6252390SLuben Tuikov static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1389c6252390SLuben Tuikov { 1390c6252390SLuben Tuikov return adev->gmc.tmz_enabled; 1391c6252390SLuben Tuikov } 1392e4cf4bf5SJonathan Kim 139353b3f8f4SDennis Li static inline int amdgpu_in_reset(struct amdgpu_device *adev) 139453b3f8f4SDennis Li { 139553b3f8f4SDennis Li return atomic_read(&adev->in_gpu_reset); 139653b3f8f4SDennis Li } 1397c6252390SLuben Tuikov #endif 1398