197b2e202SAlex Deucher /* 297b2e202SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 397b2e202SAlex Deucher * Copyright 2008 Red Hat Inc. 497b2e202SAlex Deucher * Copyright 2009 Jerome Glisse. 597b2e202SAlex Deucher * 697b2e202SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 797b2e202SAlex Deucher * copy of this software and associated documentation files (the "Software"), 897b2e202SAlex Deucher * to deal in the Software without restriction, including without limitation 997b2e202SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1097b2e202SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1197b2e202SAlex Deucher * Software is furnished to do so, subject to the following conditions: 1297b2e202SAlex Deucher * 1397b2e202SAlex Deucher * The above copyright notice and this permission notice shall be included in 1497b2e202SAlex Deucher * all copies or substantial portions of the Software. 1597b2e202SAlex Deucher * 1697b2e202SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1797b2e202SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1897b2e202SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1997b2e202SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2097b2e202SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2197b2e202SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2297b2e202SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2397b2e202SAlex Deucher * 2497b2e202SAlex Deucher * Authors: Dave Airlie 2597b2e202SAlex Deucher * Alex Deucher 2697b2e202SAlex Deucher * Jerome Glisse 2797b2e202SAlex Deucher */ 2897b2e202SAlex Deucher #ifndef __AMDGPU_H__ 2997b2e202SAlex Deucher #define __AMDGPU_H__ 3097b2e202SAlex Deucher 3197b2e202SAlex Deucher #include <linux/atomic.h> 3297b2e202SAlex Deucher #include <linux/wait.h> 3397b2e202SAlex Deucher #include <linux/list.h> 3497b2e202SAlex Deucher #include <linux/kref.h> 35a9f87f64SChristian König #include <linux/rbtree.h> 3697b2e202SAlex Deucher #include <linux/hashtable.h> 37f54d1867SChris Wilson #include <linux/dma-fence.h> 3897b2e202SAlex Deucher 39248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_bo_api.h> 40248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_bo_driver.h> 41248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_placement.h> 42248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_module.h> 43248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_execbuf_util.h> 4497b2e202SAlex Deucher 45d03846afSChunming Zhou #include <drm/drmP.h> 4697b2e202SAlex Deucher #include <drm/drm_gem.h> 477e5a547fSChunming Zhou #include <drm/amdgpu_drm.h> 4897b2e202SAlex Deucher 4978c16834SAndres Rodriguez #include <kgd_kfd_interface.h> 5078c16834SAndres Rodriguez 515fc3aeebSyanyang1 #include "amd_shared.h" 5297b2e202SAlex Deucher #include "amdgpu_mode.h" 5397b2e202SAlex Deucher #include "amdgpu_ih.h" 5497b2e202SAlex Deucher #include "amdgpu_irq.h" 5597b2e202SAlex Deucher #include "amdgpu_ucode.h" 56c632d799SFlora Cui #include "amdgpu_ttm.h" 570e5ca0d1SHuang Rui #include "amdgpu_psp.h" 5897b2e202SAlex Deucher #include "amdgpu_gds.h" 5956113504SChristian König #include "amdgpu_sync.h" 6078023016SChristian König #include "amdgpu_ring.h" 61073440d2SChristian König #include "amdgpu_vm.h" 621f7371b2SAlex Deucher #include "amd_powerplay.h" 63cf097881SAlex Deucher #include "amdgpu_dpm.h" 64a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h" 654df654d2SLeo Liu #include "amdgpu_uvd.h" 665e568178SLeo Liu #include "amdgpu_vce.h" 6795aa13f6SLeo Liu #include "amdgpu_vcn.h" 689a189996SChristian König #include "amdgpu_mn.h" 694562236bSHarry Wentland #include "amdgpu_dm.h" 7097b2e202SAlex Deucher 71b80d8475SAlex Deucher #include "gpu_scheduler.h" 72ceeb50edSMonk Liu #include "amdgpu_virt.h" 733490bdb5SChristian König #include "amdgpu_gart.h" 74b80d8475SAlex Deucher 7597b2e202SAlex Deucher /* 7697b2e202SAlex Deucher * Modules parameters. 7797b2e202SAlex Deucher */ 7897b2e202SAlex Deucher extern int amdgpu_modeset; 7997b2e202SAlex Deucher extern int amdgpu_vram_limit; 80218b5dcdSJohn Brooks extern int amdgpu_vis_vram_limit; 8183e74db6SAlex Deucher extern int amdgpu_gart_size; 8236d38372SChristian König extern int amdgpu_gtt_size; 8395844d20SMarek Olšák extern int amdgpu_moverate; 8497b2e202SAlex Deucher extern int amdgpu_benchmarking; 8597b2e202SAlex Deucher extern int amdgpu_testing; 8697b2e202SAlex Deucher extern int amdgpu_audio; 8797b2e202SAlex Deucher extern int amdgpu_disp_priority; 8897b2e202SAlex Deucher extern int amdgpu_hw_i2c; 8997b2e202SAlex Deucher extern int amdgpu_pcie_gen2; 9097b2e202SAlex Deucher extern int amdgpu_msi; 9197b2e202SAlex Deucher extern int amdgpu_lockup_timeout; 9297b2e202SAlex Deucher extern int amdgpu_dpm; 93e635ee07SHuang Rui extern int amdgpu_fw_load_type; 9497b2e202SAlex Deucher extern int amdgpu_aspm; 9597b2e202SAlex Deucher extern int amdgpu_runtime_pm; 960b693f0bSRex Zhu extern uint amdgpu_ip_block_mask; 9797b2e202SAlex Deucher extern int amdgpu_bapm; 9897b2e202SAlex Deucher extern int amdgpu_deep_color; 9997b2e202SAlex Deucher extern int amdgpu_vm_size; 10097b2e202SAlex Deucher extern int amdgpu_vm_block_size; 101d07f14beSRoger He extern int amdgpu_vm_fragment_size; 102d9c13156SChristian König extern int amdgpu_vm_fault_stop; 103b495bd3aSChristian König extern int amdgpu_vm_debug; 1049a4b7d4cSHarish Kasiviswanathan extern int amdgpu_vm_update_mode; 1054562236bSHarry Wentland extern int amdgpu_dc; 1061333f723SJammy Zhou extern int amdgpu_sched_jobs; 1074afcb303SJammy Zhou extern int amdgpu_sched_hw_submission; 1083ca67300SRex Zhu extern int amdgpu_no_evict; 1093ca67300SRex Zhu extern int amdgpu_direct_gma_size; 1100b693f0bSRex Zhu extern uint amdgpu_pcie_gen_cap; 1110b693f0bSRex Zhu extern uint amdgpu_pcie_lane_cap; 1120b693f0bSRex Zhu extern uint amdgpu_cg_mask; 1130b693f0bSRex Zhu extern uint amdgpu_pg_mask; 1140b693f0bSRex Zhu extern uint amdgpu_sdma_phase_quantum; 1156f8941a2SNicolai Hähnle extern char *amdgpu_disable_cu; 1169accf2fdSEmily Deng extern char *amdgpu_virtual_display; 1170b693f0bSRex Zhu extern uint amdgpu_pp_feature_mask; 1186a7f76e7SChristian König extern int amdgpu_vram_page_split; 119bce23e00SAlex Deucher extern int amdgpu_ngg; 120bce23e00SAlex Deucher extern int amdgpu_prim_buf_per_se; 121bce23e00SAlex Deucher extern int amdgpu_pos_buf_per_se; 122bce23e00SAlex Deucher extern int amdgpu_cntl_sb_buf_per_se; 123bce23e00SAlex Deucher extern int amdgpu_param_buf_per_se; 12465781c78SMonk Liu extern int amdgpu_job_hang_limit; 125e8835e0eSHawking Zhang extern int amdgpu_lbpw; 12697b2e202SAlex Deucher 1276dd13096SFelix Kuehling #ifdef CONFIG_DRM_AMDGPU_SI 1286dd13096SFelix Kuehling extern int amdgpu_si_support; 1296dd13096SFelix Kuehling #endif 1307df28986SFelix Kuehling #ifdef CONFIG_DRM_AMDGPU_CIK 1317df28986SFelix Kuehling extern int amdgpu_cik_support; 1327df28986SFelix Kuehling #endif 13397b2e202SAlex Deucher 13455ed8cafSChunming Zhou #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 1354b559c90SChunming Zhou #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 13697b2e202SAlex Deucher #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 13797b2e202SAlex Deucher #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 13897b2e202SAlex Deucher /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 13997b2e202SAlex Deucher #define AMDGPU_IB_POOL_SIZE 16 14097b2e202SAlex Deucher #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 14197b2e202SAlex Deucher #define AMDGPUFB_CONN_LIMIT 4 142a5bde2f9SAlex Deucher #define AMDGPU_BIOS_NUM_SCRATCH 16 14397b2e202SAlex Deucher 14436f523a7SJammy Zhou /* max number of IP instances */ 14536f523a7SJammy Zhou #define AMDGPU_MAX_SDMA_INSTANCES 2 14636f523a7SJammy Zhou 14797b2e202SAlex Deucher /* hard reset data */ 14897b2e202SAlex Deucher #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 14997b2e202SAlex Deucher 15097b2e202SAlex Deucher /* reset flags */ 15197b2e202SAlex Deucher #define AMDGPU_RESET_GFX (1 << 0) 15297b2e202SAlex Deucher #define AMDGPU_RESET_COMPUTE (1 << 1) 15397b2e202SAlex Deucher #define AMDGPU_RESET_DMA (1 << 2) 15497b2e202SAlex Deucher #define AMDGPU_RESET_CP (1 << 3) 15597b2e202SAlex Deucher #define AMDGPU_RESET_GRBM (1 << 4) 15697b2e202SAlex Deucher #define AMDGPU_RESET_DMA1 (1 << 5) 15797b2e202SAlex Deucher #define AMDGPU_RESET_RLC (1 << 6) 15897b2e202SAlex Deucher #define AMDGPU_RESET_SEM (1 << 7) 15997b2e202SAlex Deucher #define AMDGPU_RESET_IH (1 << 8) 16097b2e202SAlex Deucher #define AMDGPU_RESET_VMC (1 << 9) 16197b2e202SAlex Deucher #define AMDGPU_RESET_MC (1 << 10) 16297b2e202SAlex Deucher #define AMDGPU_RESET_DISPLAY (1 << 11) 16397b2e202SAlex Deucher #define AMDGPU_RESET_UVD (1 << 12) 16497b2e202SAlex Deucher #define AMDGPU_RESET_VCE (1 << 13) 16597b2e202SAlex Deucher #define AMDGPU_RESET_VCE1 (1 << 14) 16697b2e202SAlex Deucher 16797b2e202SAlex Deucher /* GFX current status */ 16897b2e202SAlex Deucher #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 16997b2e202SAlex Deucher #define AMDGPU_GFX_SAFE_MODE 0x00000001L 17097b2e202SAlex Deucher #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 17197b2e202SAlex Deucher #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 17297b2e202SAlex Deucher #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 17397b2e202SAlex Deucher 17497b2e202SAlex Deucher /* max cursor sizes (in pixels) */ 17597b2e202SAlex Deucher #define CIK_CURSOR_WIDTH 128 17697b2e202SAlex Deucher #define CIK_CURSOR_HEIGHT 128 17797b2e202SAlex Deucher 17897b2e202SAlex Deucher struct amdgpu_device; 17997b2e202SAlex Deucher struct amdgpu_ib; 18097b2e202SAlex Deucher struct amdgpu_cs_parser; 181bb977d37SChunming Zhou struct amdgpu_job; 18297b2e202SAlex Deucher struct amdgpu_irq_src; 1830b492a4cSAlex Deucher struct amdgpu_fpriv; 1849cca0b8eSChristian König struct amdgpu_bo_va_mapping; 18597b2e202SAlex Deucher 18697b2e202SAlex Deucher enum amdgpu_cp_irq { 18797b2e202SAlex Deucher AMDGPU_CP_IRQ_GFX_EOP = 0, 18897b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 18997b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 19097b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 19197b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 19297b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 19397b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 19497b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 19597b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 19697b2e202SAlex Deucher 19797b2e202SAlex Deucher AMDGPU_CP_IRQ_LAST 19897b2e202SAlex Deucher }; 19997b2e202SAlex Deucher 20097b2e202SAlex Deucher enum amdgpu_sdma_irq { 20197b2e202SAlex Deucher AMDGPU_SDMA_IRQ_TRAP0 = 0, 20297b2e202SAlex Deucher AMDGPU_SDMA_IRQ_TRAP1, 20397b2e202SAlex Deucher 20497b2e202SAlex Deucher AMDGPU_SDMA_IRQ_LAST 20597b2e202SAlex Deucher }; 20697b2e202SAlex Deucher 20797b2e202SAlex Deucher enum amdgpu_thermal_irq { 20897b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 20997b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 21097b2e202SAlex Deucher 21197b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LAST 21297b2e202SAlex Deucher }; 21397b2e202SAlex Deucher 2144e638ae9SXiangliang Yu enum amdgpu_kiq_irq { 2154e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 2164e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_LAST 2174e638ae9SXiangliang Yu }; 2184e638ae9SXiangliang Yu 21997b2e202SAlex Deucher int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 2205fc3aeebSyanyang1 enum amd_ip_block_type block_type, 2215fc3aeebSyanyang1 enum amd_clockgating_state state); 22297b2e202SAlex Deucher int amdgpu_set_powergating_state(struct amdgpu_device *adev, 2235fc3aeebSyanyang1 enum amd_ip_block_type block_type, 2245fc3aeebSyanyang1 enum amd_powergating_state state); 2256cb2d4e4SHuang Rui void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); 2265dbbb60bSAlex Deucher int amdgpu_wait_for_idle(struct amdgpu_device *adev, 2275dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 2285dbbb60bSAlex Deucher bool amdgpu_is_idle(struct amdgpu_device *adev, 2295dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 23097b2e202SAlex Deucher 231a1255107SAlex Deucher #define AMDGPU_MAX_IP_NUM 16 232a1255107SAlex Deucher 233a1255107SAlex Deucher struct amdgpu_ip_block_status { 234a1255107SAlex Deucher bool valid; 235a1255107SAlex Deucher bool sw; 236a1255107SAlex Deucher bool hw; 237a1255107SAlex Deucher bool late_initialized; 238a1255107SAlex Deucher bool hang; 239a1255107SAlex Deucher }; 240a1255107SAlex Deucher 24197b2e202SAlex Deucher struct amdgpu_ip_block_version { 242a1255107SAlex Deucher const enum amd_ip_block_type type; 243a1255107SAlex Deucher const u32 major; 244a1255107SAlex Deucher const u32 minor; 245a1255107SAlex Deucher const u32 rev; 2465fc3aeebSyanyang1 const struct amd_ip_funcs *funcs; 24797b2e202SAlex Deucher }; 24897b2e202SAlex Deucher 249a1255107SAlex Deucher struct amdgpu_ip_block { 250a1255107SAlex Deucher struct amdgpu_ip_block_status status; 251a1255107SAlex Deucher const struct amdgpu_ip_block_version *version; 252a1255107SAlex Deucher }; 253a1255107SAlex Deucher 25497b2e202SAlex Deucher int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 2555fc3aeebSyanyang1 enum amd_ip_block_type type, 25697b2e202SAlex Deucher u32 major, u32 minor); 25797b2e202SAlex Deucher 258a1255107SAlex Deucher struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 2595fc3aeebSyanyang1 enum amd_ip_block_type type); 26097b2e202SAlex Deucher 261a1255107SAlex Deucher int amdgpu_ip_block_add(struct amdgpu_device *adev, 262a1255107SAlex Deucher const struct amdgpu_ip_block_version *ip_block_version); 263a1255107SAlex Deucher 26497b2e202SAlex Deucher /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 26597b2e202SAlex Deucher struct amdgpu_buffer_funcs { 26697b2e202SAlex Deucher /* maximum bytes in a single operation */ 26797b2e202SAlex Deucher uint32_t copy_max_bytes; 26897b2e202SAlex Deucher 26997b2e202SAlex Deucher /* number of dw to reserve per operation */ 27097b2e202SAlex Deucher unsigned copy_num_dw; 27197b2e202SAlex Deucher 27297b2e202SAlex Deucher /* used for buffer migration */ 273c7ae72c0SChunming Zhou void (*emit_copy_buffer)(struct amdgpu_ib *ib, 27497b2e202SAlex Deucher /* src addr in bytes */ 27597b2e202SAlex Deucher uint64_t src_offset, 27697b2e202SAlex Deucher /* dst addr in bytes */ 27797b2e202SAlex Deucher uint64_t dst_offset, 27897b2e202SAlex Deucher /* number of byte to transfer */ 27997b2e202SAlex Deucher uint32_t byte_count); 28097b2e202SAlex Deucher 28197b2e202SAlex Deucher /* maximum bytes in a single operation */ 28297b2e202SAlex Deucher uint32_t fill_max_bytes; 28397b2e202SAlex Deucher 28497b2e202SAlex Deucher /* number of dw to reserve per operation */ 28597b2e202SAlex Deucher unsigned fill_num_dw; 28697b2e202SAlex Deucher 28797b2e202SAlex Deucher /* used for buffer clearing */ 2886e7a3840SChunming Zhou void (*emit_fill_buffer)(struct amdgpu_ib *ib, 28997b2e202SAlex Deucher /* value to write to memory */ 29097b2e202SAlex Deucher uint32_t src_data, 29197b2e202SAlex Deucher /* dst addr in bytes */ 29297b2e202SAlex Deucher uint64_t dst_offset, 29397b2e202SAlex Deucher /* number of byte to fill */ 29497b2e202SAlex Deucher uint32_t byte_count); 29597b2e202SAlex Deucher }; 29697b2e202SAlex Deucher 29797b2e202SAlex Deucher /* provided by hw blocks that can write ptes, e.g., sdma */ 29897b2e202SAlex Deucher struct amdgpu_vm_pte_funcs { 299e6d92197SYong Zhao /* number of dw to reserve per operation */ 300e6d92197SYong Zhao unsigned copy_pte_num_dw; 301e6d92197SYong Zhao 30297b2e202SAlex Deucher /* copy pte entries from GART */ 30397b2e202SAlex Deucher void (*copy_pte)(struct amdgpu_ib *ib, 30497b2e202SAlex Deucher uint64_t pe, uint64_t src, 30597b2e202SAlex Deucher unsigned count); 306e6d92197SYong Zhao 30797b2e202SAlex Deucher /* write pte one entry at a time with addr mapping */ 308de9ea7bdSChristian König void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 309de9ea7bdSChristian König uint64_t value, unsigned count, 310de9ea7bdSChristian König uint32_t incr); 3117bdc53f9SYong Zhao 3127bdc53f9SYong Zhao /* maximum nums of PTEs/PDEs in a single operation */ 3137bdc53f9SYong Zhao uint32_t set_max_nums_pte_pde; 3147bdc53f9SYong Zhao 3157bdc53f9SYong Zhao /* number of dw to reserve per operation */ 3167bdc53f9SYong Zhao unsigned set_pte_pde_num_dw; 3177bdc53f9SYong Zhao 31897b2e202SAlex Deucher /* for linear pte/pde updates without addr mapping */ 31997b2e202SAlex Deucher void (*set_pte_pde)(struct amdgpu_ib *ib, 32097b2e202SAlex Deucher uint64_t pe, 32197b2e202SAlex Deucher uint64_t addr, unsigned count, 3226b777607SChunming Zhou uint32_t incr, uint64_t flags); 32397b2e202SAlex Deucher }; 32497b2e202SAlex Deucher 32597b2e202SAlex Deucher /* provided by the gmc block */ 32697b2e202SAlex Deucher struct amdgpu_gart_funcs { 32797b2e202SAlex Deucher /* flush the vm tlb via mmio */ 32897b2e202SAlex Deucher void (*flush_gpu_tlb)(struct amdgpu_device *adev, 32997b2e202SAlex Deucher uint32_t vmid); 33097b2e202SAlex Deucher /* write pte/pde updates using the cpu */ 33197b2e202SAlex Deucher int (*set_pte_pde)(struct amdgpu_device *adev, 33297b2e202SAlex Deucher void *cpu_pt_addr, /* cpu addr of page table */ 33397b2e202SAlex Deucher uint32_t gpu_page_idx, /* pte/pde to update */ 33497b2e202SAlex Deucher uint64_t addr, /* addr to write into pte/pde */ 3356b777607SChunming Zhou uint64_t flags); /* access flags */ 336284710faSChristian König /* enable/disable PRT support */ 337284710faSChristian König void (*set_prt)(struct amdgpu_device *adev, bool enable); 3385463545bSAlex Xie /* set pte flags based per asic */ 3395463545bSAlex Xie uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, 3405463545bSAlex Xie uint32_t flags); 341b1166325SChristian König /* get the pde for a given mc addr */ 342b1166325SChristian König u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr); 34303f89febSChristian König uint32_t (*get_invalidate_req)(unsigned int vm_id); 344e60f8db5SAlex Xie }; 345e60f8db5SAlex Xie 34697b2e202SAlex Deucher /* provided by the ih block */ 34797b2e202SAlex Deucher struct amdgpu_ih_funcs { 34897b2e202SAlex Deucher /* ring read/write ptr handling, called from interrupt context */ 34997b2e202SAlex Deucher u32 (*get_wptr)(struct amdgpu_device *adev); 35000ecd8a2SFelix Kuehling bool (*prescreen_iv)(struct amdgpu_device *adev); 35197b2e202SAlex Deucher void (*decode_iv)(struct amdgpu_device *adev, 35297b2e202SAlex Deucher struct amdgpu_iv_entry *entry); 35397b2e202SAlex Deucher void (*set_rptr)(struct amdgpu_device *adev); 35497b2e202SAlex Deucher }; 35597b2e202SAlex Deucher 35697b2e202SAlex Deucher /* 35797b2e202SAlex Deucher * BIOS. 35897b2e202SAlex Deucher */ 35997b2e202SAlex Deucher bool amdgpu_get_bios(struct amdgpu_device *adev); 36097b2e202SAlex Deucher bool amdgpu_read_bios(struct amdgpu_device *adev); 36197b2e202SAlex Deucher 36297b2e202SAlex Deucher /* 36397b2e202SAlex Deucher * Dummy page 36497b2e202SAlex Deucher */ 36597b2e202SAlex Deucher struct amdgpu_dummy_page { 36697b2e202SAlex Deucher struct page *page; 36797b2e202SAlex Deucher dma_addr_t addr; 36897b2e202SAlex Deucher }; 36997b2e202SAlex Deucher int amdgpu_dummy_page_init(struct amdgpu_device *adev); 37097b2e202SAlex Deucher void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 37197b2e202SAlex Deucher 37297b2e202SAlex Deucher 37397b2e202SAlex Deucher /* 37497b2e202SAlex Deucher * Clocks 37597b2e202SAlex Deucher */ 37697b2e202SAlex Deucher 37797b2e202SAlex Deucher #define AMDGPU_MAX_PPLL 3 37897b2e202SAlex Deucher 37997b2e202SAlex Deucher struct amdgpu_clock { 38097b2e202SAlex Deucher struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 38197b2e202SAlex Deucher struct amdgpu_pll spll; 38297b2e202SAlex Deucher struct amdgpu_pll mpll; 38397b2e202SAlex Deucher /* 10 Khz units */ 38497b2e202SAlex Deucher uint32_t default_mclk; 38597b2e202SAlex Deucher uint32_t default_sclk; 38697b2e202SAlex Deucher uint32_t default_dispclk; 38797b2e202SAlex Deucher uint32_t current_dispclk; 38897b2e202SAlex Deucher uint32_t dp_extclk; 38997b2e202SAlex Deucher uint32_t max_pixel_clock; 39097b2e202SAlex Deucher }; 39197b2e202SAlex Deucher 39297b2e202SAlex Deucher /* 3939124a398SChristian König * GEM. 39497b2e202SAlex Deucher */ 39597b2e202SAlex Deucher 3967e5a547fSChunming Zhou #define AMDGPU_GEM_DOMAIN_MAX 0x3 39797b2e202SAlex Deucher #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 39897b2e202SAlex Deucher 39997b2e202SAlex Deucher void amdgpu_gem_object_free(struct drm_gem_object *obj); 40097b2e202SAlex Deucher int amdgpu_gem_object_open(struct drm_gem_object *obj, 40197b2e202SAlex Deucher struct drm_file *file_priv); 40297b2e202SAlex Deucher void amdgpu_gem_object_close(struct drm_gem_object *obj, 40397b2e202SAlex Deucher struct drm_file *file_priv); 40497b2e202SAlex Deucher unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 40597b2e202SAlex Deucher struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 4064d9c514dSChristian König struct drm_gem_object * 4074d9c514dSChristian König amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 40897b2e202SAlex Deucher struct dma_buf_attachment *attach, 40997b2e202SAlex Deucher struct sg_table *sg); 41097b2e202SAlex Deucher struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 41197b2e202SAlex Deucher struct drm_gem_object *gobj, 41297b2e202SAlex Deucher int flags); 41397b2e202SAlex Deucher int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 41497b2e202SAlex Deucher void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 41597b2e202SAlex Deucher struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 41697b2e202SAlex Deucher void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 41797b2e202SAlex Deucher void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 418dfced2e4SSamuel Li int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 41997b2e202SAlex Deucher int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 42097b2e202SAlex Deucher 42197b2e202SAlex Deucher /* sub-allocation manager, it has to be protected by another lock. 42297b2e202SAlex Deucher * By conception this is an helper for other part of the driver 42397b2e202SAlex Deucher * like the indirect buffer or semaphore, which both have their 42497b2e202SAlex Deucher * locking. 42597b2e202SAlex Deucher * 42697b2e202SAlex Deucher * Principe is simple, we keep a list of sub allocation in offset 42797b2e202SAlex Deucher * order (first entry has offset == 0, last entry has the highest 42897b2e202SAlex Deucher * offset). 42997b2e202SAlex Deucher * 43097b2e202SAlex Deucher * When allocating new object we first check if there is room at 43197b2e202SAlex Deucher * the end total_size - (last_object_offset + last_object_size) >= 43297b2e202SAlex Deucher * alloc_size. If so we allocate new object there. 43397b2e202SAlex Deucher * 43497b2e202SAlex Deucher * When there is not enough room at the end, we start waiting for 43597b2e202SAlex Deucher * each sub object until we reach object_offset+object_size >= 43697b2e202SAlex Deucher * alloc_size, this object then become the sub object we return. 43797b2e202SAlex Deucher * 43897b2e202SAlex Deucher * Alignment can't be bigger than page size. 43997b2e202SAlex Deucher * 44097b2e202SAlex Deucher * Hole are not considered for allocation to keep things simple. 44197b2e202SAlex Deucher * Assumption is that there won't be hole (all object on same 44297b2e202SAlex Deucher * alignment). 44397b2e202SAlex Deucher */ 4446ba60b89SChristian König 4456ba60b89SChristian König #define AMDGPU_SA_NUM_FENCE_LISTS 32 4466ba60b89SChristian König 44797b2e202SAlex Deucher struct amdgpu_sa_manager { 44897b2e202SAlex Deucher wait_queue_head_t wq; 44997b2e202SAlex Deucher struct amdgpu_bo *bo; 45097b2e202SAlex Deucher struct list_head *hole; 4516ba60b89SChristian König struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 45297b2e202SAlex Deucher struct list_head olist; 45397b2e202SAlex Deucher unsigned size; 45497b2e202SAlex Deucher uint64_t gpu_addr; 45597b2e202SAlex Deucher void *cpu_ptr; 45697b2e202SAlex Deucher uint32_t domain; 45797b2e202SAlex Deucher uint32_t align; 45897b2e202SAlex Deucher }; 45997b2e202SAlex Deucher 46097b2e202SAlex Deucher /* sub-allocation buffer */ 46197b2e202SAlex Deucher struct amdgpu_sa_bo { 46297b2e202SAlex Deucher struct list_head olist; 46397b2e202SAlex Deucher struct list_head flist; 46497b2e202SAlex Deucher struct amdgpu_sa_manager *manager; 46597b2e202SAlex Deucher unsigned soffset; 46697b2e202SAlex Deucher unsigned eoffset; 467f54d1867SChris Wilson struct dma_fence *fence; 46897b2e202SAlex Deucher }; 46997b2e202SAlex Deucher 47097b2e202SAlex Deucher /* 47197b2e202SAlex Deucher * GEM objects. 47297b2e202SAlex Deucher */ 473418aa0c2SChristian König void amdgpu_gem_force_release(struct amdgpu_device *adev); 47497b2e202SAlex Deucher int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 47597b2e202SAlex Deucher int alignment, u32 initial_domain, 47697b2e202SAlex Deucher u64 flags, bool kernel, 477e1eb899bSChristian König struct reservation_object *resv, 47897b2e202SAlex Deucher struct drm_gem_object **obj); 47997b2e202SAlex Deucher 48097b2e202SAlex Deucher int amdgpu_mode_dumb_create(struct drm_file *file_priv, 48197b2e202SAlex Deucher struct drm_device *dev, 48297b2e202SAlex Deucher struct drm_mode_create_dumb *args); 48397b2e202SAlex Deucher int amdgpu_mode_dumb_mmap(struct drm_file *filp, 48497b2e202SAlex Deucher struct drm_device *dev, 48597b2e202SAlex Deucher uint32_t handle, uint64_t *offset_p); 486d573de2dSRex Zhu int amdgpu_fence_slab_init(void); 487d573de2dSRex Zhu void amdgpu_fence_slab_fini(void); 48897b2e202SAlex Deucher 48997b2e202SAlex Deucher /* 490e60f8db5SAlex Xie * VMHUB structures, functions & helpers 491e60f8db5SAlex Xie */ 492e60f8db5SAlex Xie struct amdgpu_vmhub { 493e60f8db5SAlex Xie uint32_t ctx0_ptb_addr_lo32; 494e60f8db5SAlex Xie uint32_t ctx0_ptb_addr_hi32; 495e60f8db5SAlex Xie uint32_t vm_inv_eng0_req; 496e60f8db5SAlex Xie uint32_t vm_inv_eng0_ack; 497e60f8db5SAlex Xie uint32_t vm_context0_cntl; 498e60f8db5SAlex Xie uint32_t vm_l2_pro_fault_status; 499e60f8db5SAlex Xie uint32_t vm_l2_pro_fault_cntl; 500e60f8db5SAlex Xie }; 501e60f8db5SAlex Xie 502e60f8db5SAlex Xie /* 50397b2e202SAlex Deucher * GPU MC structures, functions & helpers 50497b2e202SAlex Deucher */ 50597b2e202SAlex Deucher struct amdgpu_mc { 50697b2e202SAlex Deucher resource_size_t aper_size; 50797b2e202SAlex Deucher resource_size_t aper_base; 50897b2e202SAlex Deucher resource_size_t agp_base; 50997b2e202SAlex Deucher /* for some chips with <= 32MB we need to lie 51097b2e202SAlex Deucher * about vram size near mc fb location */ 51197b2e202SAlex Deucher u64 mc_vram_size; 51297b2e202SAlex Deucher u64 visible_vram_size; 5136f02a696SChristian König u64 gart_size; 5146f02a696SChristian König u64 gart_start; 5156f02a696SChristian König u64 gart_end; 51697b2e202SAlex Deucher u64 vram_start; 51797b2e202SAlex Deucher u64 vram_end; 51897b2e202SAlex Deucher unsigned vram_width; 51997b2e202SAlex Deucher u64 real_vram_size; 52097b2e202SAlex Deucher int vram_mtrr; 52197b2e202SAlex Deucher u64 mc_mask; 52297b2e202SAlex Deucher const struct firmware *fw; /* MC firmware */ 52397b2e202SAlex Deucher uint32_t fw_version; 52497b2e202SAlex Deucher struct amdgpu_irq_src vm_fault; 52581c59f54SKen Wang uint32_t vram_type; 52650b0197aSChunming Zhou uint32_t srbm_soft_reset; 527f7c35abeSChristian König bool prt_warning; 528916910adSHuang Rui uint64_t stolen_size; 5298fe73328SJunwei Zhang /* apertures */ 5308fe73328SJunwei Zhang u64 shared_aperture_start; 5318fe73328SJunwei Zhang u64 shared_aperture_end; 5328fe73328SJunwei Zhang u64 private_aperture_start; 5338fe73328SJunwei Zhang u64 private_aperture_end; 534e60f8db5SAlex Xie /* protects concurrent invalidation */ 535e60f8db5SAlex Xie spinlock_t invalidate_lock; 53697b2e202SAlex Deucher }; 53797b2e202SAlex Deucher 53897b2e202SAlex Deucher /* 53997b2e202SAlex Deucher * GPU doorbell structures, functions & helpers 54097b2e202SAlex Deucher */ 54197b2e202SAlex Deucher typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 54297b2e202SAlex Deucher { 54397b2e202SAlex Deucher AMDGPU_DOORBELL_KIQ = 0x000, 54497b2e202SAlex Deucher AMDGPU_DOORBELL_HIQ = 0x001, 54597b2e202SAlex Deucher AMDGPU_DOORBELL_DIQ = 0x002, 54697b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING0 = 0x010, 54797b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING1 = 0x011, 54897b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING2 = 0x012, 54997b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING3 = 0x013, 55097b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING4 = 0x014, 55197b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING5 = 0x015, 55297b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING6 = 0x016, 55397b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING7 = 0x017, 55497b2e202SAlex Deucher AMDGPU_DOORBELL_GFX_RING0 = 0x020, 55597b2e202SAlex Deucher AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 55697b2e202SAlex Deucher AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 55797b2e202SAlex Deucher AMDGPU_DOORBELL_IH = 0x1E8, 55897b2e202SAlex Deucher AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 55997b2e202SAlex Deucher AMDGPU_DOORBELL_INVALID = 0xFFFF 56097b2e202SAlex Deucher } AMDGPU_DOORBELL_ASSIGNMENT; 56197b2e202SAlex Deucher 56297b2e202SAlex Deucher struct amdgpu_doorbell { 56397b2e202SAlex Deucher /* doorbell mmio */ 56497b2e202SAlex Deucher resource_size_t base; 56597b2e202SAlex Deucher resource_size_t size; 56697b2e202SAlex Deucher u32 __iomem *ptr; 56797b2e202SAlex Deucher u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 56897b2e202SAlex Deucher }; 56997b2e202SAlex Deucher 57039807b93SKen Wang /* 57139807b93SKen Wang * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 57239807b93SKen Wang */ 57339807b93SKen Wang typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 57439807b93SKen Wang { 57539807b93SKen Wang /* 57639807b93SKen Wang * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 57739807b93SKen Wang * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 57839807b93SKen Wang * Compute related doorbells are allocated from 0x00 to 0x8a 57939807b93SKen Wang */ 58039807b93SKen Wang 58139807b93SKen Wang 58239807b93SKen Wang /* kernel scheduling */ 58339807b93SKen Wang AMDGPU_DOORBELL64_KIQ = 0x00, 58439807b93SKen Wang 58539807b93SKen Wang /* HSA interface queue and debug queue */ 58639807b93SKen Wang AMDGPU_DOORBELL64_HIQ = 0x01, 58739807b93SKen Wang AMDGPU_DOORBELL64_DIQ = 0x02, 58839807b93SKen Wang 58939807b93SKen Wang /* Compute engines */ 59039807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 59139807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 59239807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 59339807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 59439807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 59539807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 59639807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 59739807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 59839807b93SKen Wang 59939807b93SKen Wang /* User queue doorbell range (128 doorbells) */ 60039807b93SKen Wang AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 60139807b93SKen Wang AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 60239807b93SKen Wang 60339807b93SKen Wang /* Graphics engine */ 60439807b93SKen Wang AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 60539807b93SKen Wang 60639807b93SKen Wang /* 60739807b93SKen Wang * Other graphics doorbells can be allocated here: from 0x8c to 0xef 60839807b93SKen Wang * Graphics voltage island aperture 1 60939807b93SKen Wang * default non-graphics QWORD index is 0xF0 - 0xFF inclusive 61039807b93SKen Wang */ 61139807b93SKen Wang 61239807b93SKen Wang /* sDMA engines */ 61339807b93SKen Wang AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 61439807b93SKen Wang AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 61539807b93SKen Wang AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 61639807b93SKen Wang AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 61739807b93SKen Wang 61839807b93SKen Wang /* Interrupt handler */ 61939807b93SKen Wang AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 62039807b93SKen Wang AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 62139807b93SKen Wang AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 62239807b93SKen Wang 623e6b3ecb4SMonk Liu /* VCN engine use 32 bits doorbell */ 624e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 625e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 626e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 627e6b3ecb4SMonk Liu AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 628e6b3ecb4SMonk Liu 629e6b3ecb4SMonk Liu /* overlap the doorbell assignment with VCN as they are mutually exclusive 630e6b3ecb4SMonk Liu * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 631e6b3ecb4SMonk Liu */ 6324ed11d79SFrank Min AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 6334ed11d79SFrank Min AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 6344ed11d79SFrank Min AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 6354ed11d79SFrank Min AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 636e6b3ecb4SMonk Liu 6374ed11d79SFrank Min AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 6384ed11d79SFrank Min AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 6394ed11d79SFrank Min AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 6404ed11d79SFrank Min AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 64139807b93SKen Wang 64239807b93SKen Wang AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 64339807b93SKen Wang AMDGPU_DOORBELL64_INVALID = 0xFFFF 64439807b93SKen Wang } AMDGPU_DOORBELL64_ASSIGNMENT; 64539807b93SKen Wang 64639807b93SKen Wang 64797b2e202SAlex Deucher void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 64897b2e202SAlex Deucher phys_addr_t *aperture_base, 64997b2e202SAlex Deucher size_t *aperture_size, 65097b2e202SAlex Deucher size_t *start_offset); 65197b2e202SAlex Deucher 65297b2e202SAlex Deucher /* 65397b2e202SAlex Deucher * IRQS. 65497b2e202SAlex Deucher */ 65597b2e202SAlex Deucher 65697b2e202SAlex Deucher struct amdgpu_flip_work { 657325cbba1SMichel Dänzer struct delayed_work flip_work; 65897b2e202SAlex Deucher struct work_struct unpin_work; 65997b2e202SAlex Deucher struct amdgpu_device *adev; 66097b2e202SAlex Deucher int crtc_id; 661325cbba1SMichel Dänzer u32 target_vblank; 66297b2e202SAlex Deucher uint64_t base; 66397b2e202SAlex Deucher struct drm_pending_vblank_event *event; 664765e7fbfSChristian König struct amdgpu_bo *old_abo; 665f54d1867SChris Wilson struct dma_fence *excl; 6661ffd2652SChristian König unsigned shared_count; 667f54d1867SChris Wilson struct dma_fence **shared; 668f54d1867SChris Wilson struct dma_fence_cb cb; 669cb9e59d7SAlex Deucher bool async; 67097b2e202SAlex Deucher }; 67197b2e202SAlex Deucher 67297b2e202SAlex Deucher 67397b2e202SAlex Deucher /* 67497b2e202SAlex Deucher * CP & rings. 67597b2e202SAlex Deucher */ 67697b2e202SAlex Deucher 67797b2e202SAlex Deucher struct amdgpu_ib { 67897b2e202SAlex Deucher struct amdgpu_sa_bo *sa_bo; 67997b2e202SAlex Deucher uint32_t length_dw; 68097b2e202SAlex Deucher uint64_t gpu_addr; 68197b2e202SAlex Deucher uint32_t *ptr; 682de807f81SJammy Zhou uint32_t flags; 68397b2e202SAlex Deucher }; 68497b2e202SAlex Deucher 68562250a91SNils Wallménius extern const struct amd_sched_backend_ops amdgpu_sched_ops; 686c1b69ed0SChunming Zhou 68750838c8cSChristian König int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 688c5637837SMonk Liu struct amdgpu_job **job, struct amdgpu_vm *vm); 689d71518b5SChristian König int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 690d71518b5SChristian König struct amdgpu_job **job); 691b6723c8dSMonk Liu 692a5fb4ec2SChristian König void amdgpu_job_free_resources(struct amdgpu_job *job); 69350838c8cSChristian König void amdgpu_job_free(struct amdgpu_job *job); 694d71518b5SChristian König int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 6952bd9ccfaSChristian König struct amd_sched_entity *entity, void *owner, 696f54d1867SChris Wilson struct dma_fence **f); 6978b4fb00bSChristian König 69897b2e202SAlex Deucher /* 699effd924dSAndres Rodriguez * Queue manager 700effd924dSAndres Rodriguez */ 701effd924dSAndres Rodriguez struct amdgpu_queue_mapper { 702effd924dSAndres Rodriguez int hw_ip; 703effd924dSAndres Rodriguez struct mutex lock; 704effd924dSAndres Rodriguez /* protected by lock */ 705effd924dSAndres Rodriguez struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS]; 706effd924dSAndres Rodriguez }; 707effd924dSAndres Rodriguez 708effd924dSAndres Rodriguez struct amdgpu_queue_mgr { 709effd924dSAndres Rodriguez struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM]; 710effd924dSAndres Rodriguez }; 711effd924dSAndres Rodriguez 712effd924dSAndres Rodriguez int amdgpu_queue_mgr_init(struct amdgpu_device *adev, 713effd924dSAndres Rodriguez struct amdgpu_queue_mgr *mgr); 714effd924dSAndres Rodriguez int amdgpu_queue_mgr_fini(struct amdgpu_device *adev, 715effd924dSAndres Rodriguez struct amdgpu_queue_mgr *mgr); 716effd924dSAndres Rodriguez int amdgpu_queue_mgr_map(struct amdgpu_device *adev, 717effd924dSAndres Rodriguez struct amdgpu_queue_mgr *mgr, 718effd924dSAndres Rodriguez int hw_ip, int instance, int ring, 719effd924dSAndres Rodriguez struct amdgpu_ring **out_ring); 720effd924dSAndres Rodriguez 721effd924dSAndres Rodriguez /* 72297b2e202SAlex Deucher * context related structures 72397b2e202SAlex Deucher */ 72497b2e202SAlex Deucher 72521c16bf6SChristian König struct amdgpu_ctx_ring { 72621c16bf6SChristian König uint64_t sequence; 727f54d1867SChris Wilson struct dma_fence **fences; 72891404fb2SChristian König struct amd_sched_entity entity; 72921c16bf6SChristian König }; 73021c16bf6SChristian König 73197b2e202SAlex Deucher struct amdgpu_ctx { 73297b2e202SAlex Deucher struct kref refcount; 7339cb7e5a9SChunming Zhou struct amdgpu_device *adev; 734effd924dSAndres Rodriguez struct amdgpu_queue_mgr queue_mgr; 735d94aed5aSMarek Olšák unsigned reset_counter; 73621c16bf6SChristian König spinlock_t ring_lock; 737f54d1867SChris Wilson struct dma_fence **fences; 73821c16bf6SChristian König struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 739753ad49cSMonk Liu bool preamble_presented; 74097b2e202SAlex Deucher }; 74197b2e202SAlex Deucher 74297b2e202SAlex Deucher struct amdgpu_ctx_mgr { 74397b2e202SAlex Deucher struct amdgpu_device *adev; 7440147ee0fSMarek Olšák struct mutex lock; 7450b492a4cSAlex Deucher /* protected by lock */ 7460b492a4cSAlex Deucher struct idr ctx_handles; 74797b2e202SAlex Deucher }; 74897b2e202SAlex Deucher 7490b492a4cSAlex Deucher struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 7500b492a4cSAlex Deucher int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 7510b492a4cSAlex Deucher 752eb01abc7SMonk Liu int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 753eb01abc7SMonk Liu struct dma_fence *fence, uint64_t *seq); 754f54d1867SChris Wilson struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 75521c16bf6SChristian König struct amdgpu_ring *ring, uint64_t seq); 75621c16bf6SChristian König 7570b492a4cSAlex Deucher int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 7580b492a4cSAlex Deucher struct drm_file *filp); 7590b492a4cSAlex Deucher 760efd4ccb5SChristian König void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 761efd4ccb5SChristian König void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 7620b492a4cSAlex Deucher 76397b2e202SAlex Deucher /* 76497b2e202SAlex Deucher * file private structure 76597b2e202SAlex Deucher */ 76697b2e202SAlex Deucher 76797b2e202SAlex Deucher struct amdgpu_fpriv { 76897b2e202SAlex Deucher struct amdgpu_vm vm; 769b85891bdSJunwei Zhang struct amdgpu_bo_va *prt_va; 7700f4b3c68SChristian König struct amdgpu_bo_va *csa_va; 77197b2e202SAlex Deucher struct mutex bo_list_lock; 77297b2e202SAlex Deucher struct idr bo_list_handles; 77397b2e202SAlex Deucher struct amdgpu_ctx_mgr ctx_mgr; 774f1892138SChunming Zhou u32 vram_lost_counter; 77597b2e202SAlex Deucher }; 77697b2e202SAlex Deucher 77797b2e202SAlex Deucher /* 77897b2e202SAlex Deucher * residency list 77997b2e202SAlex Deucher */ 7809124a398SChristian König struct amdgpu_bo_list_entry { 7819124a398SChristian König struct amdgpu_bo *robj; 7829124a398SChristian König struct ttm_validate_buffer tv; 7839124a398SChristian König struct amdgpu_bo_va *bo_va; 7849124a398SChristian König uint32_t priority; 7859124a398SChristian König struct page **user_pages; 7869124a398SChristian König int user_invalidated; 7879124a398SChristian König }; 78897b2e202SAlex Deucher 78997b2e202SAlex Deucher struct amdgpu_bo_list { 79097b2e202SAlex Deucher struct mutex lock; 7915ac55629SAlex Xie struct rcu_head rhead; 7925ac55629SAlex Xie struct kref refcount; 79397b2e202SAlex Deucher struct amdgpu_bo *gds_obj; 79497b2e202SAlex Deucher struct amdgpu_bo *gws_obj; 79597b2e202SAlex Deucher struct amdgpu_bo *oa_obj; 796211dff55SChristian König unsigned first_userptr; 79797b2e202SAlex Deucher unsigned num_entries; 79897b2e202SAlex Deucher struct amdgpu_bo_list_entry *array; 79997b2e202SAlex Deucher }; 80097b2e202SAlex Deucher 80197b2e202SAlex Deucher struct amdgpu_bo_list * 80297b2e202SAlex Deucher amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 803636ce25cSChristian König void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 804636ce25cSChristian König struct list_head *validated); 80597b2e202SAlex Deucher void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 80697b2e202SAlex Deucher void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 80797b2e202SAlex Deucher 80897b2e202SAlex Deucher /* 80997b2e202SAlex Deucher * GFX stuff 81097b2e202SAlex Deucher */ 81197b2e202SAlex Deucher #include "clearstate_defs.h" 81297b2e202SAlex Deucher 81379e5412cSAlex Deucher struct amdgpu_rlc_funcs { 81479e5412cSAlex Deucher void (*enter_safe_mode)(struct amdgpu_device *adev); 81579e5412cSAlex Deucher void (*exit_safe_mode)(struct amdgpu_device *adev); 81679e5412cSAlex Deucher }; 81779e5412cSAlex Deucher 81897b2e202SAlex Deucher struct amdgpu_rlc { 81997b2e202SAlex Deucher /* for power gating */ 82097b2e202SAlex Deucher struct amdgpu_bo *save_restore_obj; 82197b2e202SAlex Deucher uint64_t save_restore_gpu_addr; 82297b2e202SAlex Deucher volatile uint32_t *sr_ptr; 82397b2e202SAlex Deucher const u32 *reg_list; 82497b2e202SAlex Deucher u32 reg_list_size; 82597b2e202SAlex Deucher /* for clear state */ 82697b2e202SAlex Deucher struct amdgpu_bo *clear_state_obj; 82797b2e202SAlex Deucher uint64_t clear_state_gpu_addr; 82897b2e202SAlex Deucher volatile uint32_t *cs_ptr; 82997b2e202SAlex Deucher const struct cs_section_def *cs_data; 83097b2e202SAlex Deucher u32 clear_state_size; 83197b2e202SAlex Deucher /* for cp tables */ 83297b2e202SAlex Deucher struct amdgpu_bo *cp_table_obj; 83397b2e202SAlex Deucher uint64_t cp_table_gpu_addr; 83497b2e202SAlex Deucher volatile uint32_t *cp_table_ptr; 83597b2e202SAlex Deucher u32 cp_table_size; 83679e5412cSAlex Deucher 83779e5412cSAlex Deucher /* safe mode for updating CG/PG state */ 83879e5412cSAlex Deucher bool in_safe_mode; 83979e5412cSAlex Deucher const struct amdgpu_rlc_funcs *funcs; 8402b6cd977SEric Huang 8412b6cd977SEric Huang /* for firmware data */ 8422b6cd977SEric Huang u32 save_and_restore_offset; 8432b6cd977SEric Huang u32 clear_state_descriptor_offset; 8442b6cd977SEric Huang u32 avail_scratch_ram_locations; 8452b6cd977SEric Huang u32 reg_restore_list_size; 8462b6cd977SEric Huang u32 reg_list_format_start; 8472b6cd977SEric Huang u32 reg_list_format_separate_start; 8482b6cd977SEric Huang u32 starting_offsets_start; 8492b6cd977SEric Huang u32 reg_list_format_size_bytes; 8502b6cd977SEric Huang u32 reg_list_size_bytes; 8512b6cd977SEric Huang 8522b6cd977SEric Huang u32 *register_list_format; 8532b6cd977SEric Huang u32 *register_restore; 85497b2e202SAlex Deucher }; 85597b2e202SAlex Deucher 85678c16834SAndres Rodriguez #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 85778c16834SAndres Rodriguez 85897b2e202SAlex Deucher struct amdgpu_mec { 85997b2e202SAlex Deucher struct amdgpu_bo *hpd_eop_obj; 86097b2e202SAlex Deucher u64 hpd_eop_gpu_addr; 861b1023571SKen Wang struct amdgpu_bo *mec_fw_obj; 862b1023571SKen Wang u64 mec_fw_gpu_addr; 86397b2e202SAlex Deucher u32 num_mec; 86442794b27SAndres Rodriguez u32 num_pipe_per_mec; 86542794b27SAndres Rodriguez u32 num_queue_per_pipe; 86659a82d7dSXiangliang Yu void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 86778c16834SAndres Rodriguez 86878c16834SAndres Rodriguez /* These are the resources for which amdgpu takes ownership */ 86978c16834SAndres Rodriguez DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 87097b2e202SAlex Deucher }; 87197b2e202SAlex Deucher 8724e638ae9SXiangliang Yu struct amdgpu_kiq { 8734e638ae9SXiangliang Yu u64 eop_gpu_addr; 8744e638ae9SXiangliang Yu struct amdgpu_bo *eop_obj; 875cdf6adb2SShaoyun Liu struct mutex ring_mutex; 8764e638ae9SXiangliang Yu struct amdgpu_ring ring; 8774e638ae9SXiangliang Yu struct amdgpu_irq_src irq; 8784e638ae9SXiangliang Yu }; 8794e638ae9SXiangliang Yu 88097b2e202SAlex Deucher /* 88197b2e202SAlex Deucher * GPU scratch registers structures, functions & helpers 88297b2e202SAlex Deucher */ 88397b2e202SAlex Deucher struct amdgpu_scratch { 88497b2e202SAlex Deucher unsigned num_reg; 88597b2e202SAlex Deucher uint32_t reg_base; 88650261151SNils Wallménius uint32_t free_mask; 88797b2e202SAlex Deucher }; 88897b2e202SAlex Deucher 88997b2e202SAlex Deucher /* 89097b2e202SAlex Deucher * GFX configurations 89197b2e202SAlex Deucher */ 892e3fa7630SAlex Deucher #define AMDGPU_GFX_MAX_SE 4 893e3fa7630SAlex Deucher #define AMDGPU_GFX_MAX_SH_PER_SE 2 894e3fa7630SAlex Deucher 895e3fa7630SAlex Deucher struct amdgpu_rb_config { 896e3fa7630SAlex Deucher uint32_t rb_backend_disable; 897e3fa7630SAlex Deucher uint32_t user_rb_backend_disable; 898e3fa7630SAlex Deucher uint32_t raster_config; 899e3fa7630SAlex Deucher uint32_t raster_config_1; 900e3fa7630SAlex Deucher }; 901e3fa7630SAlex Deucher 902d0e95758SAndrey Grodzovsky struct gb_addr_config { 903d0e95758SAndrey Grodzovsky uint16_t pipe_interleave_size; 904d0e95758SAndrey Grodzovsky uint8_t num_pipes; 905d0e95758SAndrey Grodzovsky uint8_t max_compress_frags; 906d0e95758SAndrey Grodzovsky uint8_t num_banks; 907d0e95758SAndrey Grodzovsky uint8_t num_se; 908d0e95758SAndrey Grodzovsky uint8_t num_rb_per_se; 909d0e95758SAndrey Grodzovsky }; 910d0e95758SAndrey Grodzovsky 911ea323f88SJunwei Zhang struct amdgpu_gfx_config { 91297b2e202SAlex Deucher unsigned max_shader_engines; 91397b2e202SAlex Deucher unsigned max_tile_pipes; 91497b2e202SAlex Deucher unsigned max_cu_per_sh; 91597b2e202SAlex Deucher unsigned max_sh_per_se; 91697b2e202SAlex Deucher unsigned max_backends_per_se; 91797b2e202SAlex Deucher unsigned max_texture_channel_caches; 91897b2e202SAlex Deucher unsigned max_gprs; 91997b2e202SAlex Deucher unsigned max_gs_threads; 92097b2e202SAlex Deucher unsigned max_hw_contexts; 92197b2e202SAlex Deucher unsigned sc_prim_fifo_size_frontend; 92297b2e202SAlex Deucher unsigned sc_prim_fifo_size_backend; 92397b2e202SAlex Deucher unsigned sc_hiz_tile_fifo_size; 92497b2e202SAlex Deucher unsigned sc_earlyz_tile_fifo_size; 92597b2e202SAlex Deucher 92697b2e202SAlex Deucher unsigned num_tile_pipes; 92797b2e202SAlex Deucher unsigned backend_enable_mask; 92897b2e202SAlex Deucher unsigned mem_max_burst_length_bytes; 92997b2e202SAlex Deucher unsigned mem_row_size_in_kb; 93097b2e202SAlex Deucher unsigned shader_engine_tile_size; 93197b2e202SAlex Deucher unsigned num_gpus; 93297b2e202SAlex Deucher unsigned multi_gpu_tile_size; 93397b2e202SAlex Deucher unsigned mc_arb_ramcfg; 93497b2e202SAlex Deucher unsigned gb_addr_config; 9358f8e00c1SAlex Deucher unsigned num_rbs; 936408bfe7cSJunwei Zhang unsigned gs_vgt_table_depth; 937408bfe7cSJunwei Zhang unsigned gs_prim_buffer_depth; 93897b2e202SAlex Deucher 93997b2e202SAlex Deucher uint32_t tile_mode_array[32]; 94097b2e202SAlex Deucher uint32_t macrotile_mode_array[16]; 941e3fa7630SAlex Deucher 942d0e95758SAndrey Grodzovsky struct gb_addr_config gb_addr_config_fields; 943e3fa7630SAlex Deucher struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 944df6e2c4aSJunwei Zhang 945df6e2c4aSJunwei Zhang /* gfx configure feature */ 946df6e2c4aSJunwei Zhang uint32_t double_offchip_lds_buf; 94797b2e202SAlex Deucher }; 94897b2e202SAlex Deucher 9497dae69a2SAlex Deucher struct amdgpu_cu_info { 95051fd0370SHawking Zhang uint32_t max_waves_per_simd; 951408bfe7cSJunwei Zhang uint32_t wave_front_size; 95251fd0370SHawking Zhang uint32_t max_scratch_slots_per_cu; 95351fd0370SHawking Zhang uint32_t lds_size; 954dbfe85eaSFlora Cui 955dbfe85eaSFlora Cui /* total active CU number */ 956dbfe85eaSFlora Cui uint32_t number; 957dbfe85eaSFlora Cui uint32_t ao_cu_mask; 958dbfe85eaSFlora Cui uint32_t ao_cu_bitmap[4][4]; 9597dae69a2SAlex Deucher uint32_t bitmap[4][4]; 9607dae69a2SAlex Deucher }; 9617dae69a2SAlex Deucher 962b95e31fdSAlex Deucher struct amdgpu_gfx_funcs { 963b95e31fdSAlex Deucher /* get the gpu clock counter */ 964b95e31fdSAlex Deucher uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 9659559ef5bSTom St Denis void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 966472259f0STom St Denis void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); 967c5a60ce8STom St Denis void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); 968c5a60ce8STom St Denis void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); 969b95e31fdSAlex Deucher }; 970b95e31fdSAlex Deucher 971bce23e00SAlex Deucher struct amdgpu_ngg_buf { 972bce23e00SAlex Deucher struct amdgpu_bo *bo; 973bce23e00SAlex Deucher uint64_t gpu_addr; 974bce23e00SAlex Deucher uint32_t size; 975bce23e00SAlex Deucher uint32_t bo_size; 976bce23e00SAlex Deucher }; 977bce23e00SAlex Deucher 978bce23e00SAlex Deucher enum { 979af8baf15SGuenter Roeck NGG_PRIM = 0, 980af8baf15SGuenter Roeck NGG_POS, 981af8baf15SGuenter Roeck NGG_CNTL, 982af8baf15SGuenter Roeck NGG_PARAM, 983bce23e00SAlex Deucher NGG_BUF_MAX 984bce23e00SAlex Deucher }; 985bce23e00SAlex Deucher 986bce23e00SAlex Deucher struct amdgpu_ngg { 987bce23e00SAlex Deucher struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; 988bce23e00SAlex Deucher uint32_t gds_reserve_addr; 989bce23e00SAlex Deucher uint32_t gds_reserve_size; 990bce23e00SAlex Deucher bool init; 991bce23e00SAlex Deucher }; 992bce23e00SAlex Deucher 99397b2e202SAlex Deucher struct amdgpu_gfx { 99497b2e202SAlex Deucher struct mutex gpu_clock_mutex; 995ea323f88SJunwei Zhang struct amdgpu_gfx_config config; 99697b2e202SAlex Deucher struct amdgpu_rlc rlc; 99797b2e202SAlex Deucher struct amdgpu_mec mec; 9984e638ae9SXiangliang Yu struct amdgpu_kiq kiq; 99997b2e202SAlex Deucher struct amdgpu_scratch scratch; 100097b2e202SAlex Deucher const struct firmware *me_fw; /* ME firmware */ 100197b2e202SAlex Deucher uint32_t me_fw_version; 100297b2e202SAlex Deucher const struct firmware *pfp_fw; /* PFP firmware */ 100397b2e202SAlex Deucher uint32_t pfp_fw_version; 100497b2e202SAlex Deucher const struct firmware *ce_fw; /* CE firmware */ 100597b2e202SAlex Deucher uint32_t ce_fw_version; 100697b2e202SAlex Deucher const struct firmware *rlc_fw; /* RLC firmware */ 100797b2e202SAlex Deucher uint32_t rlc_fw_version; 100897b2e202SAlex Deucher const struct firmware *mec_fw; /* MEC firmware */ 100997b2e202SAlex Deucher uint32_t mec_fw_version; 101097b2e202SAlex Deucher const struct firmware *mec2_fw; /* MEC2 firmware */ 101197b2e202SAlex Deucher uint32_t mec2_fw_version; 101202558a00SKen Wang uint32_t me_feature_version; 101302558a00SKen Wang uint32_t ce_feature_version; 101402558a00SKen Wang uint32_t pfp_feature_version; 1015351643d7SJammy Zhou uint32_t rlc_feature_version; 1016351643d7SJammy Zhou uint32_t mec_feature_version; 1017351643d7SJammy Zhou uint32_t mec2_feature_version; 101897b2e202SAlex Deucher struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 101997b2e202SAlex Deucher unsigned num_gfx_rings; 102097b2e202SAlex Deucher struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 102197b2e202SAlex Deucher unsigned num_compute_rings; 102297b2e202SAlex Deucher struct amdgpu_irq_src eop_irq; 102397b2e202SAlex Deucher struct amdgpu_irq_src priv_reg_irq; 102497b2e202SAlex Deucher struct amdgpu_irq_src priv_inst_irq; 102597b2e202SAlex Deucher /* gfx status */ 102697b2e202SAlex Deucher uint32_t gfx_current_status; 1027a101a899SKen Wang /* ce ram size*/ 1028a101a899SKen Wang unsigned ce_ram_size; 10297dae69a2SAlex Deucher struct amdgpu_cu_info cu_info; 1030b95e31fdSAlex Deucher const struct amdgpu_gfx_funcs *funcs; 10313d7c6384SChunming Zhou 10323d7c6384SChunming Zhou /* reset mask */ 10333d7c6384SChunming Zhou uint32_t grbm_soft_reset; 10343d7c6384SChunming Zhou uint32_t srbm_soft_reset; 1035b4e40676SDavid Panariti /* s3/s4 mask */ 1036b4e40676SDavid Panariti bool in_suspend; 1037bce23e00SAlex Deucher /* NGG */ 1038bce23e00SAlex Deucher struct amdgpu_ngg ngg; 103997b2e202SAlex Deucher }; 104097b2e202SAlex Deucher 1041b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 104297b2e202SAlex Deucher unsigned size, struct amdgpu_ib *ib); 10434d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 1044f54d1867SChris Wilson struct dma_fence *f); 1045b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 104650ddc75eSJunwei Zhang struct amdgpu_ib *ibs, struct amdgpu_job *job, 104750ddc75eSJunwei Zhang struct dma_fence **f); 104897b2e202SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev); 104997b2e202SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 105097b2e202SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 105197b2e202SAlex Deucher 105297b2e202SAlex Deucher /* 105397b2e202SAlex Deucher * CS. 105497b2e202SAlex Deucher */ 105597b2e202SAlex Deucher struct amdgpu_cs_chunk { 105697b2e202SAlex Deucher uint32_t chunk_id; 105797b2e202SAlex Deucher uint32_t length_dw; 1058758ac17fSChristian König void *kdata; 105997b2e202SAlex Deucher }; 106097b2e202SAlex Deucher 106197b2e202SAlex Deucher struct amdgpu_cs_parser { 106297b2e202SAlex Deucher struct amdgpu_device *adev; 106397b2e202SAlex Deucher struct drm_file *filp; 10643cb485f3SChristian König struct amdgpu_ctx *ctx; 1065c3cca41eSChristian König 106697b2e202SAlex Deucher /* chunks */ 106797b2e202SAlex Deucher unsigned nchunks; 106897b2e202SAlex Deucher struct amdgpu_cs_chunk *chunks; 1069c3cca41eSChristian König 107050838c8cSChristian König /* scheduler job object */ 107150838c8cSChristian König struct amdgpu_job *job; 1072c3cca41eSChristian König 1073c3cca41eSChristian König /* buffer objects */ 1074c3cca41eSChristian König struct ww_acquire_ctx ticket; 1075c3cca41eSChristian König struct amdgpu_bo_list *bo_list; 10763fe89771SChristian König struct amdgpu_mn *mn; 107756467ebfSChristian König struct amdgpu_bo_list_entry vm_pd; 107897b2e202SAlex Deucher struct list_head validated; 1079f54d1867SChris Wilson struct dma_fence *fence; 1080f69f90a1SChristian König uint64_t bytes_moved_threshold; 108100f06b24SJohn Brooks uint64_t bytes_moved_vis_threshold; 1082f69f90a1SChristian König uint64_t bytes_moved; 108300f06b24SJohn Brooks uint64_t bytes_moved_vis; 1084662bfa61SChristian König struct amdgpu_bo_list_entry *evictable; 108597b2e202SAlex Deucher 108697b2e202SAlex Deucher /* user fence */ 108791acbeb6SChristian König struct amdgpu_bo_list_entry uf_entry; 1088660e8558SDave Airlie 1089660e8558SDave Airlie unsigned num_post_dep_syncobjs; 1090660e8558SDave Airlie struct drm_syncobj **post_dep_syncobjs; 109197b2e202SAlex Deucher }; 109297b2e202SAlex Deucher 1093753ad49cSMonk Liu #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ 1094753ad49cSMonk Liu #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ 1095753ad49cSMonk Liu #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ 1096753ad49cSMonk Liu 1097bb977d37SChunming Zhou struct amdgpu_job { 1098bb977d37SChunming Zhou struct amd_sched_job base; 1099bb977d37SChunming Zhou struct amdgpu_device *adev; 1100c5637837SMonk Liu struct amdgpu_vm *vm; 1101b07c60c0SChristian König struct amdgpu_ring *ring; 1102e86f9ceeSChristian König struct amdgpu_sync sync; 1103a340c7bcSChunming Zhou struct amdgpu_sync dep_sync; 1104df83d1ebSChunming Zhou struct amdgpu_sync sched_sync; 1105bb977d37SChunming Zhou struct amdgpu_ib *ibs; 1106f54d1867SChris Wilson struct dma_fence *fence; /* the hw fence */ 1107753ad49cSMonk Liu uint32_t preamble_status; 1108bb977d37SChunming Zhou uint32_t num_ibs; 1109e2840221SChristian König void *owner; 11103aecd24cSMonk Liu uint64_t fence_ctx; /* the fence_context this job uses */ 1111fd53be30SChunming Zhou bool vm_needs_flush; 1112d88bf583SChristian König unsigned vm_id; 1113d88bf583SChristian König uint64_t vm_pd_addr; 1114d88bf583SChristian König uint32_t gds_base, gds_size; 1115d88bf583SChristian König uint32_t gws_base, gws_size; 1116d88bf583SChristian König uint32_t oa_base, oa_size; 1117758ac17fSChristian König 1118758ac17fSChristian König /* user fence handling */ 1119b5f5acbcSChristian König uint64_t uf_addr; 1120758ac17fSChristian König uint64_t uf_sequence; 1121758ac17fSChristian König 1122bb977d37SChunming Zhou }; 1123a6db8a33SJunwei Zhang #define to_amdgpu_job(sched_job) \ 1124a6db8a33SJunwei Zhang container_of((sched_job), struct amdgpu_job, base) 1125bb977d37SChunming Zhou 11267270f839SChristian König static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 11277270f839SChristian König uint32_t ib_idx, int idx) 112897b2e202SAlex Deucher { 112950838c8cSChristian König return p->job->ibs[ib_idx].ptr[idx]; 113097b2e202SAlex Deucher } 113197b2e202SAlex Deucher 11327270f839SChristian König static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 11337270f839SChristian König uint32_t ib_idx, int idx, 11347270f839SChristian König uint32_t value) 11357270f839SChristian König { 113650838c8cSChristian König p->job->ibs[ib_idx].ptr[idx] = value; 11377270f839SChristian König } 11387270f839SChristian König 113997b2e202SAlex Deucher /* 114097b2e202SAlex Deucher * Writeback 114197b2e202SAlex Deucher */ 114297b2e202SAlex Deucher #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 114397b2e202SAlex Deucher 114497b2e202SAlex Deucher struct amdgpu_wb { 114597b2e202SAlex Deucher struct amdgpu_bo *wb_obj; 114697b2e202SAlex Deucher volatile uint32_t *wb; 114797b2e202SAlex Deucher uint64_t gpu_addr; 114897b2e202SAlex Deucher u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 114997b2e202SAlex Deucher unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 115097b2e202SAlex Deucher }; 115197b2e202SAlex Deucher 115297b2e202SAlex Deucher int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 115397b2e202SAlex Deucher void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 115497b2e202SAlex Deucher 1155d0dd7f0cSAlex Deucher void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1156d0dd7f0cSAlex Deucher 115797b2e202SAlex Deucher /* 115897b2e202SAlex Deucher * SDMA 115997b2e202SAlex Deucher */ 1160c113ea1cSAlex Deucher struct amdgpu_sdma_instance { 116197b2e202SAlex Deucher /* SDMA firmware */ 116297b2e202SAlex Deucher const struct firmware *fw; 116397b2e202SAlex Deucher uint32_t fw_version; 1164cfa2104fSJammy Zhou uint32_t feature_version; 116597b2e202SAlex Deucher 116697b2e202SAlex Deucher struct amdgpu_ring ring; 116718111de0SJammy Zhou bool burst_nop; 116897b2e202SAlex Deucher }; 116997b2e202SAlex Deucher 1170c113ea1cSAlex Deucher struct amdgpu_sdma { 1171c113ea1cSAlex Deucher struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 117230d1574fSKen Wang #ifdef CONFIG_DRM_AMDGPU_SI 117330d1574fSKen Wang //SI DMA has a difference trap irq number for the second engine 117430d1574fSKen Wang struct amdgpu_irq_src trap_irq_1; 117530d1574fSKen Wang #endif 1176c113ea1cSAlex Deucher struct amdgpu_irq_src trap_irq; 1177c113ea1cSAlex Deucher struct amdgpu_irq_src illegal_inst_irq; 1178c113ea1cSAlex Deucher int num_instances; 1179e702a680SChunming Zhou uint32_t srbm_soft_reset; 1180c113ea1cSAlex Deucher }; 1181c113ea1cSAlex Deucher 118297b2e202SAlex Deucher /* 118397b2e202SAlex Deucher * Firmware 118497b2e202SAlex Deucher */ 1185e635ee07SHuang Rui enum amdgpu_firmware_load_type { 1186e635ee07SHuang Rui AMDGPU_FW_LOAD_DIRECT = 0, 1187e635ee07SHuang Rui AMDGPU_FW_LOAD_SMU, 1188e635ee07SHuang Rui AMDGPU_FW_LOAD_PSP, 1189e635ee07SHuang Rui }; 1190e635ee07SHuang Rui 119197b2e202SAlex Deucher struct amdgpu_firmware { 119297b2e202SAlex Deucher struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1193e635ee07SHuang Rui enum amdgpu_firmware_load_type load_type; 119497b2e202SAlex Deucher struct amdgpu_bo *fw_buf; 119597b2e202SAlex Deucher unsigned int fw_size; 11962445b227SHuang Rui unsigned int max_ucodes; 11970e5ca0d1SHuang Rui /* firmwares are loaded by psp instead of smu from vega10 */ 11980e5ca0d1SHuang Rui const struct amdgpu_psp_funcs *funcs; 11990e5ca0d1SHuang Rui struct amdgpu_bo *rbuf; 12000e5ca0d1SHuang Rui struct mutex mutex; 1201ab4fe3e1SHuang Rui 1202ab4fe3e1SHuang Rui /* gpu info firmware data pointer */ 1203ab4fe3e1SHuang Rui const struct firmware *gpu_info_fw; 1204d59c026bSMonk Liu 1205d59c026bSMonk Liu void *fw_buf_ptr; 1206d59c026bSMonk Liu uint64_t fw_buf_mc; 120797b2e202SAlex Deucher }; 120897b2e202SAlex Deucher 120997b2e202SAlex Deucher /* 121097b2e202SAlex Deucher * Benchmarking 121197b2e202SAlex Deucher */ 121297b2e202SAlex Deucher void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 121397b2e202SAlex Deucher 121497b2e202SAlex Deucher 121597b2e202SAlex Deucher /* 121697b2e202SAlex Deucher * Testing 121797b2e202SAlex Deucher */ 121897b2e202SAlex Deucher void amdgpu_test_moves(struct amdgpu_device *adev); 121997b2e202SAlex Deucher 122097b2e202SAlex Deucher /* 122197b2e202SAlex Deucher * Debugfs 122297b2e202SAlex Deucher */ 122397b2e202SAlex Deucher struct amdgpu_debugfs { 122406ab6832SNils Wallménius const struct drm_info_list *files; 122597b2e202SAlex Deucher unsigned num_files; 122697b2e202SAlex Deucher }; 122797b2e202SAlex Deucher 122897b2e202SAlex Deucher int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 122906ab6832SNils Wallménius const struct drm_info_list *files, 123097b2e202SAlex Deucher unsigned nfiles); 123197b2e202SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 123297b2e202SAlex Deucher 123397b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS) 123497b2e202SAlex Deucher int amdgpu_debugfs_init(struct drm_minor *minor); 123597b2e202SAlex Deucher #endif 123697b2e202SAlex Deucher 123750ab2533SHuang Rui int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); 123850ab2533SHuang Rui 123997b2e202SAlex Deucher /* 124097b2e202SAlex Deucher * amdgpu smumgr functions 124197b2e202SAlex Deucher */ 124297b2e202SAlex Deucher struct amdgpu_smumgr_funcs { 124397b2e202SAlex Deucher int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 124497b2e202SAlex Deucher int (*request_smu_load_fw)(struct amdgpu_device *adev); 124597b2e202SAlex Deucher int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 124697b2e202SAlex Deucher }; 124797b2e202SAlex Deucher 124897b2e202SAlex Deucher /* 124997b2e202SAlex Deucher * amdgpu smumgr 125097b2e202SAlex Deucher */ 125197b2e202SAlex Deucher struct amdgpu_smumgr { 125297b2e202SAlex Deucher struct amdgpu_bo *toc_buf; 125397b2e202SAlex Deucher struct amdgpu_bo *smu_buf; 125497b2e202SAlex Deucher /* asic priv smu data */ 125597b2e202SAlex Deucher void *priv; 125697b2e202SAlex Deucher spinlock_t smu_lock; 125797b2e202SAlex Deucher /* smumgr functions */ 125897b2e202SAlex Deucher const struct amdgpu_smumgr_funcs *smumgr_funcs; 125997b2e202SAlex Deucher /* ucode loading complete flag */ 126097b2e202SAlex Deucher uint32_t fw_flags; 126197b2e202SAlex Deucher }; 126297b2e202SAlex Deucher 126397b2e202SAlex Deucher /* 126497b2e202SAlex Deucher * ASIC specific register table accessible by UMD 126597b2e202SAlex Deucher */ 126697b2e202SAlex Deucher struct amdgpu_allowed_register_entry { 126797b2e202SAlex Deucher uint32_t reg_offset; 126897b2e202SAlex Deucher bool grbm_indexed; 126997b2e202SAlex Deucher }; 127097b2e202SAlex Deucher 127197b2e202SAlex Deucher /* 127297b2e202SAlex Deucher * ASIC specific functions. 127397b2e202SAlex Deucher */ 127497b2e202SAlex Deucher struct amdgpu_asic_funcs { 127597b2e202SAlex Deucher bool (*read_disabled_bios)(struct amdgpu_device *adev); 12767946b878SAlex Deucher bool (*read_bios_from_rom)(struct amdgpu_device *adev, 12777946b878SAlex Deucher u8 *bios, u32 length_bytes); 127897b2e202SAlex Deucher int (*read_register)(struct amdgpu_device *adev, u32 se_num, 127997b2e202SAlex Deucher u32 sh_num, u32 reg_offset, u32 *value); 128097b2e202SAlex Deucher void (*set_vga_state)(struct amdgpu_device *adev, bool state); 128197b2e202SAlex Deucher int (*reset)(struct amdgpu_device *adev); 128297b2e202SAlex Deucher /* get the reference clock */ 128397b2e202SAlex Deucher u32 (*get_xclk)(struct amdgpu_device *adev); 128497b2e202SAlex Deucher /* MM block clocks */ 128597b2e202SAlex Deucher int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 128697b2e202SAlex Deucher int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1287841686dfSMaruthi Bayyavarapu /* static power management */ 1288841686dfSMaruthi Bayyavarapu int (*get_pcie_lanes)(struct amdgpu_device *adev); 1289841686dfSMaruthi Bayyavarapu void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 1290bbf282d8SAlex Deucher /* get config memsize register */ 1291bbf282d8SAlex Deucher u32 (*get_config_memsize)(struct amdgpu_device *adev); 129297b2e202SAlex Deucher }; 129397b2e202SAlex Deucher 129497b2e202SAlex Deucher /* 129597b2e202SAlex Deucher * IOCTL. 129697b2e202SAlex Deucher */ 129797b2e202SAlex Deucher int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 129897b2e202SAlex Deucher struct drm_file *filp); 129997b2e202SAlex Deucher int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 130097b2e202SAlex Deucher struct drm_file *filp); 130197b2e202SAlex Deucher 130297b2e202SAlex Deucher int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 130397b2e202SAlex Deucher struct drm_file *filp); 130497b2e202SAlex Deucher int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 130597b2e202SAlex Deucher struct drm_file *filp); 130697b2e202SAlex Deucher int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 130797b2e202SAlex Deucher struct drm_file *filp); 130897b2e202SAlex Deucher int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 130997b2e202SAlex Deucher struct drm_file *filp); 131097b2e202SAlex Deucher int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 131197b2e202SAlex Deucher struct drm_file *filp); 131297b2e202SAlex Deucher int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 131397b2e202SAlex Deucher struct drm_file *filp); 131497b2e202SAlex Deucher int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 131597b2e202SAlex Deucher int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1316eef18a82SJunwei Zhang int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 1317eef18a82SJunwei Zhang struct drm_file *filp); 131897b2e202SAlex Deucher 131997b2e202SAlex Deucher int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 132097b2e202SAlex Deucher struct drm_file *filp); 132197b2e202SAlex Deucher 132297b2e202SAlex Deucher /* VRAM scratch page for HDP bug, default vram page */ 132397b2e202SAlex Deucher struct amdgpu_vram_scratch { 132497b2e202SAlex Deucher struct amdgpu_bo *robj; 132597b2e202SAlex Deucher volatile uint32_t *ptr; 132697b2e202SAlex Deucher u64 gpu_addr; 132797b2e202SAlex Deucher }; 132897b2e202SAlex Deucher 132997b2e202SAlex Deucher /* 133097b2e202SAlex Deucher * ACPI 133197b2e202SAlex Deucher */ 133297b2e202SAlex Deucher struct amdgpu_atif_notification_cfg { 133397b2e202SAlex Deucher bool enabled; 133497b2e202SAlex Deucher int command_code; 133597b2e202SAlex Deucher }; 133697b2e202SAlex Deucher 133797b2e202SAlex Deucher struct amdgpu_atif_notifications { 133897b2e202SAlex Deucher bool display_switch; 133997b2e202SAlex Deucher bool expansion_mode_change; 134097b2e202SAlex Deucher bool thermal_state; 134197b2e202SAlex Deucher bool forced_power_state; 134297b2e202SAlex Deucher bool system_power_state; 134397b2e202SAlex Deucher bool display_conf_change; 134497b2e202SAlex Deucher bool px_gfx_switch; 134597b2e202SAlex Deucher bool brightness_change; 134697b2e202SAlex Deucher bool dgpu_display_event; 134797b2e202SAlex Deucher }; 134897b2e202SAlex Deucher 134997b2e202SAlex Deucher struct amdgpu_atif_functions { 135097b2e202SAlex Deucher bool system_params; 135197b2e202SAlex Deucher bool sbios_requests; 135297b2e202SAlex Deucher bool select_active_disp; 135397b2e202SAlex Deucher bool lid_state; 135497b2e202SAlex Deucher bool get_tv_standard; 135597b2e202SAlex Deucher bool set_tv_standard; 135697b2e202SAlex Deucher bool get_panel_expansion_mode; 135797b2e202SAlex Deucher bool set_panel_expansion_mode; 135897b2e202SAlex Deucher bool temperature_change; 135997b2e202SAlex Deucher bool graphics_device_types; 136097b2e202SAlex Deucher }; 136197b2e202SAlex Deucher 136297b2e202SAlex Deucher struct amdgpu_atif { 136397b2e202SAlex Deucher struct amdgpu_atif_notifications notifications; 136497b2e202SAlex Deucher struct amdgpu_atif_functions functions; 136597b2e202SAlex Deucher struct amdgpu_atif_notification_cfg notification_cfg; 136697b2e202SAlex Deucher struct amdgpu_encoder *encoder_for_bl; 136797b2e202SAlex Deucher }; 136897b2e202SAlex Deucher 136997b2e202SAlex Deucher struct amdgpu_atcs_functions { 137097b2e202SAlex Deucher bool get_ext_state; 137197b2e202SAlex Deucher bool pcie_perf_req; 137297b2e202SAlex Deucher bool pcie_dev_rdy; 137397b2e202SAlex Deucher bool pcie_bus_width; 137497b2e202SAlex Deucher }; 137597b2e202SAlex Deucher 137697b2e202SAlex Deucher struct amdgpu_atcs { 137797b2e202SAlex Deucher struct amdgpu_atcs_functions functions; 137897b2e202SAlex Deucher }; 137997b2e202SAlex Deucher 138097b2e202SAlex Deucher /* 1381d03846afSChunming Zhou * CGS 1382d03846afSChunming Zhou */ 1383110e6f26SDave Airlie struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1384110e6f26SDave Airlie void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1385a8fe58ceSMaruthi Bayyavarapu 1386a8fe58ceSMaruthi Bayyavarapu /* 138797b2e202SAlex Deucher * Core structure, functions and helpers. 138897b2e202SAlex Deucher */ 138997b2e202SAlex Deucher typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 139097b2e202SAlex Deucher typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 139197b2e202SAlex Deucher 139297b2e202SAlex Deucher typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 139397b2e202SAlex Deucher typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 139497b2e202SAlex Deucher 13950c49e0b8SChunming Zhou #define AMDGPU_RESET_MAGIC_NUM 64 139697b2e202SAlex Deucher struct amdgpu_device { 139797b2e202SAlex Deucher struct device *dev; 139897b2e202SAlex Deucher struct drm_device *ddev; 139997b2e202SAlex Deucher struct pci_dev *pdev; 140097b2e202SAlex Deucher 1401a8fe58ceSMaruthi Bayyavarapu #ifdef CONFIG_DRM_AMD_ACP 1402a8fe58ceSMaruthi Bayyavarapu struct amdgpu_acp acp; 1403a8fe58ceSMaruthi Bayyavarapu #endif 1404a8fe58ceSMaruthi Bayyavarapu 140597b2e202SAlex Deucher /* ASIC */ 14062f7d10b3SJammy Zhou enum amd_asic_type asic_type; 140797b2e202SAlex Deucher uint32_t family; 140897b2e202SAlex Deucher uint32_t rev_id; 140997b2e202SAlex Deucher uint32_t external_rev_id; 141097b2e202SAlex Deucher unsigned long flags; 141197b2e202SAlex Deucher int usec_timeout; 141297b2e202SAlex Deucher const struct amdgpu_asic_funcs *asic_funcs; 141397b2e202SAlex Deucher bool shutdown; 141497b2e202SAlex Deucher bool need_dma32; 141597b2e202SAlex Deucher bool accel_working; 141697b2e202SAlex Deucher struct work_struct reset_work; 141797b2e202SAlex Deucher struct notifier_block acpi_nb; 141897b2e202SAlex Deucher struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 141997b2e202SAlex Deucher struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 142097b2e202SAlex Deucher unsigned debugfs_count; 142197b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS) 1422adcec288STom St Denis struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 142397b2e202SAlex Deucher #endif 142497b2e202SAlex Deucher struct amdgpu_atif atif; 142597b2e202SAlex Deucher struct amdgpu_atcs atcs; 142697b2e202SAlex Deucher struct mutex srbm_mutex; 142797b2e202SAlex Deucher /* GRBM index mutex. Protects concurrent access to GRBM index */ 142897b2e202SAlex Deucher struct mutex grbm_idx_mutex; 142997b2e202SAlex Deucher struct dev_pm_domain vga_pm_domain; 143097b2e202SAlex Deucher bool have_disp_power_ref; 143197b2e202SAlex Deucher 143297b2e202SAlex Deucher /* BIOS */ 14330cdd5005SAlex Deucher bool is_atom_fw; 143497b2e202SAlex Deucher uint8_t *bios; 1435a9f5db9cSEvan Quan uint32_t bios_size; 14365af2c10dSKent Russell struct amdgpu_bo *stolen_vga_memory; 1437a5bde2f9SAlex Deucher uint32_t bios_scratch_reg_offset; 143897b2e202SAlex Deucher uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 143997b2e202SAlex Deucher 144097b2e202SAlex Deucher /* Register/doorbell mmio */ 144197b2e202SAlex Deucher resource_size_t rmmio_base; 144297b2e202SAlex Deucher resource_size_t rmmio_size; 144397b2e202SAlex Deucher void __iomem *rmmio; 144497b2e202SAlex Deucher /* protects concurrent MM_INDEX/DATA based register access */ 144597b2e202SAlex Deucher spinlock_t mmio_idx_lock; 144697b2e202SAlex Deucher /* protects concurrent SMC based register access */ 144797b2e202SAlex Deucher spinlock_t smc_idx_lock; 144897b2e202SAlex Deucher amdgpu_rreg_t smc_rreg; 144997b2e202SAlex Deucher amdgpu_wreg_t smc_wreg; 145097b2e202SAlex Deucher /* protects concurrent PCIE register access */ 145197b2e202SAlex Deucher spinlock_t pcie_idx_lock; 145297b2e202SAlex Deucher amdgpu_rreg_t pcie_rreg; 145397b2e202SAlex Deucher amdgpu_wreg_t pcie_wreg; 145436b9a952SHuang Rui amdgpu_rreg_t pciep_rreg; 145536b9a952SHuang Rui amdgpu_wreg_t pciep_wreg; 145697b2e202SAlex Deucher /* protects concurrent UVD register access */ 145797b2e202SAlex Deucher spinlock_t uvd_ctx_idx_lock; 145897b2e202SAlex Deucher amdgpu_rreg_t uvd_ctx_rreg; 145997b2e202SAlex Deucher amdgpu_wreg_t uvd_ctx_wreg; 146097b2e202SAlex Deucher /* protects concurrent DIDT register access */ 146197b2e202SAlex Deucher spinlock_t didt_idx_lock; 146297b2e202SAlex Deucher amdgpu_rreg_t didt_rreg; 146397b2e202SAlex Deucher amdgpu_wreg_t didt_wreg; 1464ccdbb20aSRex Zhu /* protects concurrent gc_cac register access */ 1465ccdbb20aSRex Zhu spinlock_t gc_cac_idx_lock; 1466ccdbb20aSRex Zhu amdgpu_rreg_t gc_cac_rreg; 1467ccdbb20aSRex Zhu amdgpu_wreg_t gc_cac_wreg; 146816abb5d2SEvan Quan /* protects concurrent se_cac register access */ 146916abb5d2SEvan Quan spinlock_t se_cac_idx_lock; 147016abb5d2SEvan Quan amdgpu_rreg_t se_cac_rreg; 147116abb5d2SEvan Quan amdgpu_wreg_t se_cac_wreg; 147297b2e202SAlex Deucher /* protects concurrent ENDPOINT (audio) register access */ 147397b2e202SAlex Deucher spinlock_t audio_endpt_idx_lock; 147497b2e202SAlex Deucher amdgpu_block_rreg_t audio_endpt_rreg; 147597b2e202SAlex Deucher amdgpu_block_wreg_t audio_endpt_wreg; 147697b2e202SAlex Deucher void __iomem *rio_mem; 147797b2e202SAlex Deucher resource_size_t rio_mem_size; 147897b2e202SAlex Deucher struct amdgpu_doorbell doorbell; 147997b2e202SAlex Deucher 148097b2e202SAlex Deucher /* clock/pll info */ 148197b2e202SAlex Deucher struct amdgpu_clock clock; 148297b2e202SAlex Deucher 148397b2e202SAlex Deucher /* MC */ 148497b2e202SAlex Deucher struct amdgpu_mc mc; 148597b2e202SAlex Deucher struct amdgpu_gart gart; 148697b2e202SAlex Deucher struct amdgpu_dummy_page dummy_page; 148797b2e202SAlex Deucher struct amdgpu_vm_manager vm_manager; 1488e60f8db5SAlex Xie struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 148997b2e202SAlex Deucher 149097b2e202SAlex Deucher /* memory management */ 149197b2e202SAlex Deucher struct amdgpu_mman mman; 149297b2e202SAlex Deucher struct amdgpu_vram_scratch vram_scratch; 149397b2e202SAlex Deucher struct amdgpu_wb wb; 149497b2e202SAlex Deucher atomic64_t num_bytes_moved; 1495dbd5ed60SChristian König atomic64_t num_evictions; 149668e2c5ffSMarek Olšák atomic64_t num_vram_cpu_page_faults; 1497d94aed5aSMarek Olšák atomic_t gpu_reset_counter; 1498f1892138SChunming Zhou atomic_t vram_lost_counter; 149997b2e202SAlex Deucher 150095844d20SMarek Olšák /* data for buffer migration throttling */ 150195844d20SMarek Olšák struct { 150295844d20SMarek Olšák spinlock_t lock; 150395844d20SMarek Olšák s64 last_update_us; 150495844d20SMarek Olšák s64 accum_us; /* accumulated microseconds */ 150500f06b24SJohn Brooks s64 accum_us_vis; /* for visible VRAM */ 150695844d20SMarek Olšák u32 log2_max_MBps; 150795844d20SMarek Olšák } mm_stats; 150895844d20SMarek Olšák 150997b2e202SAlex Deucher /* display */ 15109accf2fdSEmily Deng bool enable_virtual_display; 151197b2e202SAlex Deucher struct amdgpu_mode_info mode_info; 15124562236bSHarry Wentland /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 151397b2e202SAlex Deucher struct work_struct hotplug_work; 151497b2e202SAlex Deucher struct amdgpu_irq_src crtc_irq; 151597b2e202SAlex Deucher struct amdgpu_irq_src pageflip_irq; 151697b2e202SAlex Deucher struct amdgpu_irq_src hpd_irq; 151797b2e202SAlex Deucher 151897b2e202SAlex Deucher /* rings */ 151976bf0db5SChristian König u64 fence_context; 152097b2e202SAlex Deucher unsigned num_rings; 152197b2e202SAlex Deucher struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 152297b2e202SAlex Deucher bool ib_pool_ready; 152397b2e202SAlex Deucher struct amdgpu_sa_manager ring_tmp_bo; 152497b2e202SAlex Deucher 152597b2e202SAlex Deucher /* interrupts */ 152697b2e202SAlex Deucher struct amdgpu_irq irq; 152797b2e202SAlex Deucher 15281f7371b2SAlex Deucher /* powerplay */ 15291f7371b2SAlex Deucher struct amd_powerplay powerplay; 1530e61710c5SJammy Zhou bool pp_enabled; 1531f3898ea1SEric Huang bool pp_force_state_enabled; 15321f7371b2SAlex Deucher 153397b2e202SAlex Deucher /* dpm */ 153497b2e202SAlex Deucher struct amdgpu_pm pm; 153597b2e202SAlex Deucher u32 cg_flags; 153697b2e202SAlex Deucher u32 pg_flags; 153797b2e202SAlex Deucher 153897b2e202SAlex Deucher /* amdgpu smumgr */ 153997b2e202SAlex Deucher struct amdgpu_smumgr smu; 154097b2e202SAlex Deucher 154197b2e202SAlex Deucher /* gfx */ 154297b2e202SAlex Deucher struct amdgpu_gfx gfx; 154397b2e202SAlex Deucher 154497b2e202SAlex Deucher /* sdma */ 1545c113ea1cSAlex Deucher struct amdgpu_sdma sdma; 154697b2e202SAlex Deucher 154795d0906fSLeo Liu union { 154895d0906fSLeo Liu struct { 154997b2e202SAlex Deucher /* uvd */ 155097b2e202SAlex Deucher struct amdgpu_uvd uvd; 155197b2e202SAlex Deucher 155297b2e202SAlex Deucher /* vce */ 155397b2e202SAlex Deucher struct amdgpu_vce vce; 155495d0906fSLeo Liu }; 155595d0906fSLeo Liu 155695d0906fSLeo Liu /* vcn */ 155795d0906fSLeo Liu struct amdgpu_vcn vcn; 155895d0906fSLeo Liu }; 155997b2e202SAlex Deucher 156097b2e202SAlex Deucher /* firmwares */ 156197b2e202SAlex Deucher struct amdgpu_firmware firmware; 156297b2e202SAlex Deucher 15630e5ca0d1SHuang Rui /* PSP */ 15640e5ca0d1SHuang Rui struct psp_context psp; 15650e5ca0d1SHuang Rui 156697b2e202SAlex Deucher /* GDS */ 156797b2e202SAlex Deucher struct amdgpu_gds gds; 156897b2e202SAlex Deucher 15694562236bSHarry Wentland /* display related functionality */ 15704562236bSHarry Wentland struct amdgpu_display_manager dm; 15714562236bSHarry Wentland 1572a1255107SAlex Deucher struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 157397b2e202SAlex Deucher int num_ip_blocks; 157497b2e202SAlex Deucher struct mutex mn_lock; 157597b2e202SAlex Deucher DECLARE_HASHTABLE(mn_hash, 7); 157697b2e202SAlex Deucher 157797b2e202SAlex Deucher /* tracking pinned memory */ 157897b2e202SAlex Deucher u64 vram_pin_size; 1579e131b914SChunming Zhou u64 invisible_pin_size; 158097b2e202SAlex Deucher u64 gart_pin_size; 1581130e0371SOded Gabbay 1582130e0371SOded Gabbay /* amdkfd interface */ 1583130e0371SOded Gabbay struct kfd_dev *kfd; 158423ca0e4eSChunming Zhou 15852dc80b00SShirish S /* delayed work_func for deferring clockgating during resume */ 15862dc80b00SShirish S struct delayed_work late_init_work; 15872dc80b00SShirish S 15885a5099cbSXiangliang Yu struct amdgpu_virt virt; 15890c4e7fa5SChunming Zhou 15900c4e7fa5SChunming Zhou /* link all shadow bo */ 15910c4e7fa5SChunming Zhou struct list_head shadow_list; 15920c4e7fa5SChunming Zhou struct mutex shadow_list_lock; 15935c1354bdSChunming Zhou /* link all gtt */ 15945c1354bdSChunming Zhou spinlock_t gtt_list_lock; 15955c1354bdSChunming Zhou struct list_head gtt_list; 1596795f2813SAndres Rodriguez /* keep an lru list of rings by HW IP */ 1597795f2813SAndres Rodriguez struct list_head ring_lru_list; 1598795f2813SAndres Rodriguez spinlock_t ring_lru_list_lock; 15995c1354bdSChunming Zhou 1600c836fec5SJim Qu /* record hw reset is performed */ 1601c836fec5SJim Qu bool has_hw_reset; 16020c49e0b8SChunming Zhou u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1603c836fec5SJim Qu 160447ed4e1cSKen Wang /* record last mm index being written through WREG32*/ 160547ed4e1cSKen Wang unsigned long last_mm_index; 16063224a12bSMonk Liu bool in_sriov_reset; 160797b2e202SAlex Deucher }; 160897b2e202SAlex Deucher 1609a7d64de6SChristian König static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1610a7d64de6SChristian König { 1611a7d64de6SChristian König return container_of(bdev, struct amdgpu_device, mman.bdev); 1612a7d64de6SChristian König } 1613a7d64de6SChristian König 161497b2e202SAlex Deucher int amdgpu_device_init(struct amdgpu_device *adev, 161597b2e202SAlex Deucher struct drm_device *ddev, 161697b2e202SAlex Deucher struct pci_dev *pdev, 161797b2e202SAlex Deucher uint32_t flags); 161897b2e202SAlex Deucher void amdgpu_device_fini(struct amdgpu_device *adev); 161997b2e202SAlex Deucher int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 162097b2e202SAlex Deucher 162197b2e202SAlex Deucher uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 162215d72fd7SMonk Liu uint32_t acc_flags); 162397b2e202SAlex Deucher void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 162415d72fd7SMonk Liu uint32_t acc_flags); 162597b2e202SAlex Deucher u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 162697b2e202SAlex Deucher void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 162797b2e202SAlex Deucher 162897b2e202SAlex Deucher u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 162997b2e202SAlex Deucher void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1630832be404SKen Wang u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 1631832be404SKen Wang void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 163297b2e202SAlex Deucher 16334562236bSHarry Wentland bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 16344562236bSHarry Wentland bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 16354562236bSHarry Wentland 163697b2e202SAlex Deucher /* 163797b2e202SAlex Deucher * Registers read & write functions. 163897b2e202SAlex Deucher */ 163915d72fd7SMonk Liu 164015d72fd7SMonk Liu #define AMDGPU_REGS_IDX (1<<0) 164115d72fd7SMonk Liu #define AMDGPU_REGS_NO_KIQ (1<<1) 164215d72fd7SMonk Liu 164315d72fd7SMonk Liu #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 164415d72fd7SMonk Liu #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 164515d72fd7SMonk Liu 164615d72fd7SMonk Liu #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 164715d72fd7SMonk Liu #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 164815d72fd7SMonk Liu #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 164915d72fd7SMonk Liu #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 165015d72fd7SMonk Liu #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 165197b2e202SAlex Deucher #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 165297b2e202SAlex Deucher #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 165397b2e202SAlex Deucher #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 165497b2e202SAlex Deucher #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 165536b9a952SHuang Rui #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 165636b9a952SHuang Rui #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 165797b2e202SAlex Deucher #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 165897b2e202SAlex Deucher #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 165997b2e202SAlex Deucher #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 166097b2e202SAlex Deucher #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 166197b2e202SAlex Deucher #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 166297b2e202SAlex Deucher #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1663ccdbb20aSRex Zhu #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1664ccdbb20aSRex Zhu #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 166516abb5d2SEvan Quan #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 166616abb5d2SEvan Quan #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 166797b2e202SAlex Deucher #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 166897b2e202SAlex Deucher #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 166997b2e202SAlex Deucher #define WREG32_P(reg, val, mask) \ 167097b2e202SAlex Deucher do { \ 167197b2e202SAlex Deucher uint32_t tmp_ = RREG32(reg); \ 167297b2e202SAlex Deucher tmp_ &= (mask); \ 167397b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 167497b2e202SAlex Deucher WREG32(reg, tmp_); \ 167597b2e202SAlex Deucher } while (0) 167697b2e202SAlex Deucher #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 167797b2e202SAlex Deucher #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 167897b2e202SAlex Deucher #define WREG32_PLL_P(reg, val, mask) \ 167997b2e202SAlex Deucher do { \ 168097b2e202SAlex Deucher uint32_t tmp_ = RREG32_PLL(reg); \ 168197b2e202SAlex Deucher tmp_ &= (mask); \ 168297b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 168397b2e202SAlex Deucher WREG32_PLL(reg, tmp_); \ 168497b2e202SAlex Deucher } while (0) 168597b2e202SAlex Deucher #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 168697b2e202SAlex Deucher #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 168797b2e202SAlex Deucher #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 168897b2e202SAlex Deucher 168997b2e202SAlex Deucher #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 169097b2e202SAlex Deucher #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1691832be404SKen Wang #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 1692832be404SKen Wang #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 169397b2e202SAlex Deucher 169497b2e202SAlex Deucher #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 169597b2e202SAlex Deucher #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 169697b2e202SAlex Deucher 169797b2e202SAlex Deucher #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 169897b2e202SAlex Deucher (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 169997b2e202SAlex Deucher (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 170097b2e202SAlex Deucher 170197b2e202SAlex Deucher #define REG_GET_FIELD(value, reg, field) \ 170297b2e202SAlex Deucher (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 170397b2e202SAlex Deucher 170461cb8cefSTom St Denis #define WREG32_FIELD(reg, field, val) \ 170561cb8cefSTom St Denis WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 170661cb8cefSTom St Denis 1707ccaf3574STom St Denis #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1708ccaf3574STom St Denis WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1709ccaf3574STom St Denis 171097b2e202SAlex Deucher /* 171197b2e202SAlex Deucher * BIOS helpers. 171297b2e202SAlex Deucher */ 171397b2e202SAlex Deucher #define RBIOS8(i) (adev->bios[i]) 171497b2e202SAlex Deucher #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 171597b2e202SAlex Deucher #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 171697b2e202SAlex Deucher 1717c113ea1cSAlex Deucher static inline struct amdgpu_sdma_instance * 1718c113ea1cSAlex Deucher amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 17194b2f7e2cSJammy Zhou { 17204b2f7e2cSJammy Zhou struct amdgpu_device *adev = ring->adev; 17214b2f7e2cSJammy Zhou int i; 17224b2f7e2cSJammy Zhou 1723c113ea1cSAlex Deucher for (i = 0; i < adev->sdma.num_instances; i++) 1724c113ea1cSAlex Deucher if (&adev->sdma.instance[i].ring == ring) 17254b2f7e2cSJammy Zhou break; 17264b2f7e2cSJammy Zhou 17274b2f7e2cSJammy Zhou if (i < AMDGPU_MAX_SDMA_INSTANCES) 1728c113ea1cSAlex Deucher return &adev->sdma.instance[i]; 17294b2f7e2cSJammy Zhou else 17304b2f7e2cSJammy Zhou return NULL; 17314b2f7e2cSJammy Zhou } 17324b2f7e2cSJammy Zhou 173397b2e202SAlex Deucher /* 173497b2e202SAlex Deucher * ASICs macro. 173597b2e202SAlex Deucher */ 173697b2e202SAlex Deucher #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 173797b2e202SAlex Deucher #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 173897b2e202SAlex Deucher #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 173997b2e202SAlex Deucher #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 174097b2e202SAlex Deucher #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1741841686dfSMaruthi Bayyavarapu #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1742841686dfSMaruthi Bayyavarapu #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1743841686dfSMaruthi Bayyavarapu #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 174497b2e202SAlex Deucher #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 17457946b878SAlex Deucher #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 174697b2e202SAlex Deucher #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1747bbf282d8SAlex Deucher #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 174897b2e202SAlex Deucher #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 174997b2e202SAlex Deucher #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 1750b1166325SChristian König #define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr)) 175197b2e202SAlex Deucher #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 1752de9ea7bdSChristian König #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 175397b2e202SAlex Deucher #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 17545463545bSAlex Xie #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags)) 175597b2e202SAlex Deucher #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 175697b2e202SAlex Deucher #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 1757bbec97aaSChristian König #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 175897b2e202SAlex Deucher #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 175997b2e202SAlex Deucher #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 176097b2e202SAlex Deucher #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 1761d88bf583SChristian König #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 1762b8c7b39eSChristian König #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 176397b2e202SAlex Deucher #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 1764890ee23fSChunming Zhou #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 176597b2e202SAlex Deucher #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 1766d2edb07bSChristian König #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 176711afbde8SChunming Zhou #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 1768c2167a65SMonk Liu #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 1769753ad49cSMonk Liu #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 1770b6091c12SXiangliang Yu #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) 1771b6091c12SXiangliang Yu #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 17723b4d68e9SMonk Liu #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b)) 17739e5d5309SChristian König #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 177403ccf481SMonk Liu #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 177503ccf481SMonk Liu #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 177697b2e202SAlex Deucher #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 177700ecd8a2SFelix Kuehling #define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev)) 177897b2e202SAlex Deucher #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 177997b2e202SAlex Deucher #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 178097b2e202SAlex Deucher #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 178197b2e202SAlex Deucher #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 178297b2e202SAlex Deucher #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 178397b2e202SAlex Deucher #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 178497b2e202SAlex Deucher #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 178597b2e202SAlex Deucher #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 178697b2e202SAlex Deucher #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 178797b2e202SAlex Deucher #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 1788cb9e59d7SAlex Deucher #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 178997b2e202SAlex Deucher #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 179097b2e202SAlex Deucher #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 179197b2e202SAlex Deucher #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 1792c7ae72c0SChunming Zhou #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 17936e7a3840SChunming Zhou #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 1794b95e31fdSAlex Deucher #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 17959559ef5bSTom St Denis #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 179697b2e202SAlex Deucher #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 17970e5ca0d1SHuang Rui #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) 179897b2e202SAlex Deucher 179997b2e202SAlex Deucher /* Common functions */ 180097b2e202SAlex Deucher int amdgpu_gpu_reset(struct amdgpu_device *adev); 18013ad81f16SChunming Zhou bool amdgpu_need_backup(struct amdgpu_device *adev); 180297b2e202SAlex Deucher void amdgpu_pci_config_reset(struct amdgpu_device *adev); 1803c836fec5SJim Qu bool amdgpu_need_post(struct amdgpu_device *adev); 180497b2e202SAlex Deucher void amdgpu_update_display_priority(struct amdgpu_device *adev); 1805d5fc5e82SChunming Zhou 180600f06b24SJohn Brooks void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 180700f06b24SJohn Brooks u64 num_vis_bytes); 1808765e7fbfSChristian König void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 180997b2e202SAlex Deucher bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 181097b2e202SAlex Deucher void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 18116f02a696SChristian König void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 181297b2e202SAlex Deucher void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 18139f31a0b0SBaoyou Xie int amdgpu_ttm_init(struct amdgpu_device *adev); 18149f31a0b0SBaoyou Xie void amdgpu_ttm_fini(struct amdgpu_device *adev); 181597b2e202SAlex Deucher void amdgpu_program_register_sequence(struct amdgpu_device *adev, 181697b2e202SAlex Deucher const u32 *registers, 181797b2e202SAlex Deucher const u32 array_size); 181897b2e202SAlex Deucher 181997b2e202SAlex Deucher bool amdgpu_device_is_px(struct drm_device *dev); 182097b2e202SAlex Deucher /* atpx handler */ 182197b2e202SAlex Deucher #if defined(CONFIG_VGA_SWITCHEROO) 182297b2e202SAlex Deucher void amdgpu_register_atpx_handler(void); 182397b2e202SAlex Deucher void amdgpu_unregister_atpx_handler(void); 1824a78fe133SAlex Deucher bool amdgpu_has_atpx_dgpu_power_cntl(void); 18252f5af82eSAlex Deucher bool amdgpu_is_atpx_hybrid(void); 1826efc83cf4SAlex Deucher bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1827714f88e0SAlex Xie bool amdgpu_has_atpx(void); 182897b2e202SAlex Deucher #else 182997b2e202SAlex Deucher static inline void amdgpu_register_atpx_handler(void) {} 183097b2e202SAlex Deucher static inline void amdgpu_unregister_atpx_handler(void) {} 1831a78fe133SAlex Deucher static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 18322f5af82eSAlex Deucher static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1833efc83cf4SAlex Deucher static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1834714f88e0SAlex Xie static inline bool amdgpu_has_atpx(void) { return false; } 183597b2e202SAlex Deucher #endif 183697b2e202SAlex Deucher 183797b2e202SAlex Deucher /* 183897b2e202SAlex Deucher * KMS 183997b2e202SAlex Deucher */ 184097b2e202SAlex Deucher extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1841f498d9edSNils Wallménius extern const int amdgpu_max_kms_ioctl; 184297b2e202SAlex Deucher 1843f1892138SChunming Zhou bool amdgpu_kms_vram_lost(struct amdgpu_device *adev, 1844f1892138SChunming Zhou struct amdgpu_fpriv *fpriv); 184597b2e202SAlex Deucher int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 184611b3c20bSGabriel Krisman Bertazi void amdgpu_driver_unload_kms(struct drm_device *dev); 184797b2e202SAlex Deucher void amdgpu_driver_lastclose_kms(struct drm_device *dev); 184897b2e202SAlex Deucher int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 184997b2e202SAlex Deucher void amdgpu_driver_postclose_kms(struct drm_device *dev, 185097b2e202SAlex Deucher struct drm_file *file_priv); 1851faefba95SAlex Deucher int amdgpu_suspend(struct amdgpu_device *adev); 1852810ddc3aSAlex Deucher int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1853810ddc3aSAlex Deucher int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 185488e72717SThierry Reding u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 185588e72717SThierry Reding int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 185688e72717SThierry Reding void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 185797b2e202SAlex Deucher long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 185897b2e202SAlex Deucher unsigned long arg); 185997b2e202SAlex Deucher 186097b2e202SAlex Deucher /* 186197b2e202SAlex Deucher * functions used by amdgpu_encoder.c 186297b2e202SAlex Deucher */ 186397b2e202SAlex Deucher struct amdgpu_afmt_acr { 186497b2e202SAlex Deucher u32 clock; 186597b2e202SAlex Deucher 186697b2e202SAlex Deucher int n_32khz; 186797b2e202SAlex Deucher int cts_32khz; 186897b2e202SAlex Deucher 186997b2e202SAlex Deucher int n_44_1khz; 187097b2e202SAlex Deucher int cts_44_1khz; 187197b2e202SAlex Deucher 187297b2e202SAlex Deucher int n_48khz; 187397b2e202SAlex Deucher int cts_48khz; 187497b2e202SAlex Deucher 187597b2e202SAlex Deucher }; 187697b2e202SAlex Deucher 187797b2e202SAlex Deucher struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 187897b2e202SAlex Deucher 187997b2e202SAlex Deucher /* amdgpu_acpi.c */ 188097b2e202SAlex Deucher #if defined(CONFIG_ACPI) 188197b2e202SAlex Deucher int amdgpu_acpi_init(struct amdgpu_device *adev); 188297b2e202SAlex Deucher void amdgpu_acpi_fini(struct amdgpu_device *adev); 188397b2e202SAlex Deucher bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 188497b2e202SAlex Deucher int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 188597b2e202SAlex Deucher u8 perf_req, bool advertise); 188697b2e202SAlex Deucher int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 188797b2e202SAlex Deucher #else 188897b2e202SAlex Deucher static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 188997b2e202SAlex Deucher static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 189097b2e202SAlex Deucher #endif 189197b2e202SAlex Deucher 18929cca0b8eSChristian König int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 18939cca0b8eSChristian König uint64_t addr, struct amdgpu_bo **bo, 18949cca0b8eSChristian König struct amdgpu_bo_va_mapping **mapping); 189597b2e202SAlex Deucher 18964562236bSHarry Wentland #if defined(CONFIG_DRM_AMD_DC) 18974562236bSHarry Wentland int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 18984562236bSHarry Wentland #else 18994562236bSHarry Wentland static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 19004562236bSHarry Wentland #endif 19014562236bSHarry Wentland 190297b2e202SAlex Deucher #include "amdgpu_object.h" 190397b2e202SAlex Deucher #endif 1904