197b2e202SAlex Deucher /* 297b2e202SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 397b2e202SAlex Deucher * Copyright 2008 Red Hat Inc. 497b2e202SAlex Deucher * Copyright 2009 Jerome Glisse. 597b2e202SAlex Deucher * 697b2e202SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 797b2e202SAlex Deucher * copy of this software and associated documentation files (the "Software"), 897b2e202SAlex Deucher * to deal in the Software without restriction, including without limitation 997b2e202SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1097b2e202SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1197b2e202SAlex Deucher * Software is furnished to do so, subject to the following conditions: 1297b2e202SAlex Deucher * 1397b2e202SAlex Deucher * The above copyright notice and this permission notice shall be included in 1497b2e202SAlex Deucher * all copies or substantial portions of the Software. 1597b2e202SAlex Deucher * 1697b2e202SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1797b2e202SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1897b2e202SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1997b2e202SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2097b2e202SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2197b2e202SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2297b2e202SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2397b2e202SAlex Deucher * 2497b2e202SAlex Deucher * Authors: Dave Airlie 2597b2e202SAlex Deucher * Alex Deucher 2697b2e202SAlex Deucher * Jerome Glisse 2797b2e202SAlex Deucher */ 2897b2e202SAlex Deucher #ifndef __AMDGPU_H__ 2997b2e202SAlex Deucher #define __AMDGPU_H__ 3097b2e202SAlex Deucher 3197b2e202SAlex Deucher #include <linux/atomic.h> 3297b2e202SAlex Deucher #include <linux/wait.h> 3397b2e202SAlex Deucher #include <linux/list.h> 3497b2e202SAlex Deucher #include <linux/kref.h> 3597b2e202SAlex Deucher #include <linux/interval_tree.h> 3697b2e202SAlex Deucher #include <linux/hashtable.h> 37f54d1867SChris Wilson #include <linux/dma-fence.h> 3897b2e202SAlex Deucher 3997b2e202SAlex Deucher #include <ttm/ttm_bo_api.h> 4097b2e202SAlex Deucher #include <ttm/ttm_bo_driver.h> 4197b2e202SAlex Deucher #include <ttm/ttm_placement.h> 4297b2e202SAlex Deucher #include <ttm/ttm_module.h> 4397b2e202SAlex Deucher #include <ttm/ttm_execbuf_util.h> 4497b2e202SAlex Deucher 45d03846afSChunming Zhou #include <drm/drmP.h> 4697b2e202SAlex Deucher #include <drm/drm_gem.h> 477e5a547fSChunming Zhou #include <drm/amdgpu_drm.h> 4897b2e202SAlex Deucher 495fc3aeebSyanyang1 #include "amd_shared.h" 5097b2e202SAlex Deucher #include "amdgpu_mode.h" 5197b2e202SAlex Deucher #include "amdgpu_ih.h" 5297b2e202SAlex Deucher #include "amdgpu_irq.h" 5397b2e202SAlex Deucher #include "amdgpu_ucode.h" 54c632d799SFlora Cui #include "amdgpu_ttm.h" 5597b2e202SAlex Deucher #include "amdgpu_gds.h" 5656113504SChristian König #include "amdgpu_sync.h" 5778023016SChristian König #include "amdgpu_ring.h" 58073440d2SChristian König #include "amdgpu_vm.h" 591f7371b2SAlex Deucher #include "amd_powerplay.h" 60cf097881SAlex Deucher #include "amdgpu_dpm.h" 61a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h" 624df654d2SLeo Liu #include "amdgpu_uvd.h" 635e568178SLeo Liu #include "amdgpu_vce.h" 6497b2e202SAlex Deucher 65b80d8475SAlex Deucher #include "gpu_scheduler.h" 66ceeb50edSMonk Liu #include "amdgpu_virt.h" 67b80d8475SAlex Deucher 6897b2e202SAlex Deucher /* 6997b2e202SAlex Deucher * Modules parameters. 7097b2e202SAlex Deucher */ 7197b2e202SAlex Deucher extern int amdgpu_modeset; 7297b2e202SAlex Deucher extern int amdgpu_vram_limit; 7397b2e202SAlex Deucher extern int amdgpu_gart_size; 7495844d20SMarek Olšák extern int amdgpu_moverate; 7597b2e202SAlex Deucher extern int amdgpu_benchmarking; 7697b2e202SAlex Deucher extern int amdgpu_testing; 7797b2e202SAlex Deucher extern int amdgpu_audio; 7897b2e202SAlex Deucher extern int amdgpu_disp_priority; 7997b2e202SAlex Deucher extern int amdgpu_hw_i2c; 8097b2e202SAlex Deucher extern int amdgpu_pcie_gen2; 8197b2e202SAlex Deucher extern int amdgpu_msi; 8297b2e202SAlex Deucher extern int amdgpu_lockup_timeout; 8397b2e202SAlex Deucher extern int amdgpu_dpm; 84e635ee07SHuang Rui extern int amdgpu_fw_load_type; 8597b2e202SAlex Deucher extern int amdgpu_aspm; 8697b2e202SAlex Deucher extern int amdgpu_runtime_pm; 8797b2e202SAlex Deucher extern unsigned amdgpu_ip_block_mask; 8897b2e202SAlex Deucher extern int amdgpu_bapm; 8997b2e202SAlex Deucher extern int amdgpu_deep_color; 9097b2e202SAlex Deucher extern int amdgpu_vm_size; 9197b2e202SAlex Deucher extern int amdgpu_vm_block_size; 92d9c13156SChristian König extern int amdgpu_vm_fault_stop; 93b495bd3aSChristian König extern int amdgpu_vm_debug; 941333f723SJammy Zhou extern int amdgpu_sched_jobs; 954afcb303SJammy Zhou extern int amdgpu_sched_hw_submission; 963ca67300SRex Zhu extern int amdgpu_no_evict; 973ca67300SRex Zhu extern int amdgpu_direct_gma_size; 98cd474ba0SAlex Deucher extern unsigned amdgpu_pcie_gen_cap; 99cd474ba0SAlex Deucher extern unsigned amdgpu_pcie_lane_cap; 100395d1fb9SNicolai Hähnle extern unsigned amdgpu_cg_mask; 101395d1fb9SNicolai Hähnle extern unsigned amdgpu_pg_mask; 1026f8941a2SNicolai Hähnle extern char *amdgpu_disable_cu; 1039accf2fdSEmily Deng extern char *amdgpu_virtual_display; 1045141e9d2SRex Zhu extern unsigned amdgpu_pp_feature_mask; 1056a7f76e7SChristian König extern int amdgpu_vram_page_split; 10697b2e202SAlex Deucher 1074b559c90SChunming Zhou #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 10897b2e202SAlex Deucher #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 10997b2e202SAlex Deucher #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 11097b2e202SAlex Deucher /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 11197b2e202SAlex Deucher #define AMDGPU_IB_POOL_SIZE 16 11297b2e202SAlex Deucher #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 11397b2e202SAlex Deucher #define AMDGPUFB_CONN_LIMIT 4 114a5bde2f9SAlex Deucher #define AMDGPU_BIOS_NUM_SCRATCH 16 11597b2e202SAlex Deucher 11636f523a7SJammy Zhou /* max number of IP instances */ 11736f523a7SJammy Zhou #define AMDGPU_MAX_SDMA_INSTANCES 2 11836f523a7SJammy Zhou 11997b2e202SAlex Deucher /* hardcode that limit for now */ 12097b2e202SAlex Deucher #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 12197b2e202SAlex Deucher 12297b2e202SAlex Deucher /* hard reset data */ 12397b2e202SAlex Deucher #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 12497b2e202SAlex Deucher 12597b2e202SAlex Deucher /* reset flags */ 12697b2e202SAlex Deucher #define AMDGPU_RESET_GFX (1 << 0) 12797b2e202SAlex Deucher #define AMDGPU_RESET_COMPUTE (1 << 1) 12897b2e202SAlex Deucher #define AMDGPU_RESET_DMA (1 << 2) 12997b2e202SAlex Deucher #define AMDGPU_RESET_CP (1 << 3) 13097b2e202SAlex Deucher #define AMDGPU_RESET_GRBM (1 << 4) 13197b2e202SAlex Deucher #define AMDGPU_RESET_DMA1 (1 << 5) 13297b2e202SAlex Deucher #define AMDGPU_RESET_RLC (1 << 6) 13397b2e202SAlex Deucher #define AMDGPU_RESET_SEM (1 << 7) 13497b2e202SAlex Deucher #define AMDGPU_RESET_IH (1 << 8) 13597b2e202SAlex Deucher #define AMDGPU_RESET_VMC (1 << 9) 13697b2e202SAlex Deucher #define AMDGPU_RESET_MC (1 << 10) 13797b2e202SAlex Deucher #define AMDGPU_RESET_DISPLAY (1 << 11) 13897b2e202SAlex Deucher #define AMDGPU_RESET_UVD (1 << 12) 13997b2e202SAlex Deucher #define AMDGPU_RESET_VCE (1 << 13) 14097b2e202SAlex Deucher #define AMDGPU_RESET_VCE1 (1 << 14) 14197b2e202SAlex Deucher 14297b2e202SAlex Deucher /* GFX current status */ 14397b2e202SAlex Deucher #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 14497b2e202SAlex Deucher #define AMDGPU_GFX_SAFE_MODE 0x00000001L 14597b2e202SAlex Deucher #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 14697b2e202SAlex Deucher #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 14797b2e202SAlex Deucher #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 14897b2e202SAlex Deucher 14997b2e202SAlex Deucher /* max cursor sizes (in pixels) */ 15097b2e202SAlex Deucher #define CIK_CURSOR_WIDTH 128 15197b2e202SAlex Deucher #define CIK_CURSOR_HEIGHT 128 15297b2e202SAlex Deucher 15397b2e202SAlex Deucher struct amdgpu_device; 15497b2e202SAlex Deucher struct amdgpu_ib; 15597b2e202SAlex Deucher struct amdgpu_cs_parser; 156bb977d37SChunming Zhou struct amdgpu_job; 15797b2e202SAlex Deucher struct amdgpu_irq_src; 1580b492a4cSAlex Deucher struct amdgpu_fpriv; 15997b2e202SAlex Deucher 16097b2e202SAlex Deucher enum amdgpu_cp_irq { 16197b2e202SAlex Deucher AMDGPU_CP_IRQ_GFX_EOP = 0, 16297b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 16397b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 16497b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 16597b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 16697b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 16797b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 16897b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 16997b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 17097b2e202SAlex Deucher 17197b2e202SAlex Deucher AMDGPU_CP_IRQ_LAST 17297b2e202SAlex Deucher }; 17397b2e202SAlex Deucher 17497b2e202SAlex Deucher enum amdgpu_sdma_irq { 17597b2e202SAlex Deucher AMDGPU_SDMA_IRQ_TRAP0 = 0, 17697b2e202SAlex Deucher AMDGPU_SDMA_IRQ_TRAP1, 17797b2e202SAlex Deucher 17897b2e202SAlex Deucher AMDGPU_SDMA_IRQ_LAST 17997b2e202SAlex Deucher }; 18097b2e202SAlex Deucher 18197b2e202SAlex Deucher enum amdgpu_thermal_irq { 18297b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 18397b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 18497b2e202SAlex Deucher 18597b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LAST 18697b2e202SAlex Deucher }; 18797b2e202SAlex Deucher 1884e638ae9SXiangliang Yu enum amdgpu_kiq_irq { 1894e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 1904e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_LAST 1914e638ae9SXiangliang Yu }; 1924e638ae9SXiangliang Yu 19397b2e202SAlex Deucher int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 1945fc3aeebSyanyang1 enum amd_ip_block_type block_type, 1955fc3aeebSyanyang1 enum amd_clockgating_state state); 19697b2e202SAlex Deucher int amdgpu_set_powergating_state(struct amdgpu_device *adev, 1975fc3aeebSyanyang1 enum amd_ip_block_type block_type, 1985fc3aeebSyanyang1 enum amd_powergating_state state); 1996cb2d4e4SHuang Rui void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); 2005dbbb60bSAlex Deucher int amdgpu_wait_for_idle(struct amdgpu_device *adev, 2015dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 2025dbbb60bSAlex Deucher bool amdgpu_is_idle(struct amdgpu_device *adev, 2035dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 20497b2e202SAlex Deucher 205a1255107SAlex Deucher #define AMDGPU_MAX_IP_NUM 16 206a1255107SAlex Deucher 207a1255107SAlex Deucher struct amdgpu_ip_block_status { 208a1255107SAlex Deucher bool valid; 209a1255107SAlex Deucher bool sw; 210a1255107SAlex Deucher bool hw; 211a1255107SAlex Deucher bool late_initialized; 212a1255107SAlex Deucher bool hang; 213a1255107SAlex Deucher }; 214a1255107SAlex Deucher 21597b2e202SAlex Deucher struct amdgpu_ip_block_version { 216a1255107SAlex Deucher const enum amd_ip_block_type type; 217a1255107SAlex Deucher const u32 major; 218a1255107SAlex Deucher const u32 minor; 219a1255107SAlex Deucher const u32 rev; 2205fc3aeebSyanyang1 const struct amd_ip_funcs *funcs; 22197b2e202SAlex Deucher }; 22297b2e202SAlex Deucher 223a1255107SAlex Deucher struct amdgpu_ip_block { 224a1255107SAlex Deucher struct amdgpu_ip_block_status status; 225a1255107SAlex Deucher const struct amdgpu_ip_block_version *version; 226a1255107SAlex Deucher }; 227a1255107SAlex Deucher 22897b2e202SAlex Deucher int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 2295fc3aeebSyanyang1 enum amd_ip_block_type type, 23097b2e202SAlex Deucher u32 major, u32 minor); 23197b2e202SAlex Deucher 232a1255107SAlex Deucher struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 2335fc3aeebSyanyang1 enum amd_ip_block_type type); 23497b2e202SAlex Deucher 235a1255107SAlex Deucher int amdgpu_ip_block_add(struct amdgpu_device *adev, 236a1255107SAlex Deucher const struct amdgpu_ip_block_version *ip_block_version); 237a1255107SAlex Deucher 23897b2e202SAlex Deucher /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 23997b2e202SAlex Deucher struct amdgpu_buffer_funcs { 24097b2e202SAlex Deucher /* maximum bytes in a single operation */ 24197b2e202SAlex Deucher uint32_t copy_max_bytes; 24297b2e202SAlex Deucher 24397b2e202SAlex Deucher /* number of dw to reserve per operation */ 24497b2e202SAlex Deucher unsigned copy_num_dw; 24597b2e202SAlex Deucher 24697b2e202SAlex Deucher /* used for buffer migration */ 247c7ae72c0SChunming Zhou void (*emit_copy_buffer)(struct amdgpu_ib *ib, 24897b2e202SAlex Deucher /* src addr in bytes */ 24997b2e202SAlex Deucher uint64_t src_offset, 25097b2e202SAlex Deucher /* dst addr in bytes */ 25197b2e202SAlex Deucher uint64_t dst_offset, 25297b2e202SAlex Deucher /* number of byte to transfer */ 25397b2e202SAlex Deucher uint32_t byte_count); 25497b2e202SAlex Deucher 25597b2e202SAlex Deucher /* maximum bytes in a single operation */ 25697b2e202SAlex Deucher uint32_t fill_max_bytes; 25797b2e202SAlex Deucher 25897b2e202SAlex Deucher /* number of dw to reserve per operation */ 25997b2e202SAlex Deucher unsigned fill_num_dw; 26097b2e202SAlex Deucher 26197b2e202SAlex Deucher /* used for buffer clearing */ 2626e7a3840SChunming Zhou void (*emit_fill_buffer)(struct amdgpu_ib *ib, 26397b2e202SAlex Deucher /* value to write to memory */ 26497b2e202SAlex Deucher uint32_t src_data, 26597b2e202SAlex Deucher /* dst addr in bytes */ 26697b2e202SAlex Deucher uint64_t dst_offset, 26797b2e202SAlex Deucher /* number of byte to fill */ 26897b2e202SAlex Deucher uint32_t byte_count); 26997b2e202SAlex Deucher }; 27097b2e202SAlex Deucher 27197b2e202SAlex Deucher /* provided by hw blocks that can write ptes, e.g., sdma */ 27297b2e202SAlex Deucher struct amdgpu_vm_pte_funcs { 27397b2e202SAlex Deucher /* copy pte entries from GART */ 27497b2e202SAlex Deucher void (*copy_pte)(struct amdgpu_ib *ib, 27597b2e202SAlex Deucher uint64_t pe, uint64_t src, 27697b2e202SAlex Deucher unsigned count); 27797b2e202SAlex Deucher /* write pte one entry at a time with addr mapping */ 278de9ea7bdSChristian König void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 279de9ea7bdSChristian König uint64_t value, unsigned count, 280de9ea7bdSChristian König uint32_t incr); 28197b2e202SAlex Deucher /* for linear pte/pde updates without addr mapping */ 28297b2e202SAlex Deucher void (*set_pte_pde)(struct amdgpu_ib *ib, 28397b2e202SAlex Deucher uint64_t pe, 28497b2e202SAlex Deucher uint64_t addr, unsigned count, 2856b777607SChunming Zhou uint32_t incr, uint64_t flags); 28697b2e202SAlex Deucher }; 28797b2e202SAlex Deucher 28897b2e202SAlex Deucher /* provided by the gmc block */ 28997b2e202SAlex Deucher struct amdgpu_gart_funcs { 29097b2e202SAlex Deucher /* flush the vm tlb via mmio */ 29197b2e202SAlex Deucher void (*flush_gpu_tlb)(struct amdgpu_device *adev, 29297b2e202SAlex Deucher uint32_t vmid); 29397b2e202SAlex Deucher /* write pte/pde updates using the cpu */ 29497b2e202SAlex Deucher int (*set_pte_pde)(struct amdgpu_device *adev, 29597b2e202SAlex Deucher void *cpu_pt_addr, /* cpu addr of page table */ 29697b2e202SAlex Deucher uint32_t gpu_page_idx, /* pte/pde to update */ 29797b2e202SAlex Deucher uint64_t addr, /* addr to write into pte/pde */ 2986b777607SChunming Zhou uint64_t flags); /* access flags */ 299284710faSChristian König /* enable/disable PRT support */ 300284710faSChristian König void (*set_prt)(struct amdgpu_device *adev, bool enable); 3015463545bSAlex Xie /* set pte flags based per asic */ 3025463545bSAlex Xie uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, 3035463545bSAlex Xie uint32_t flags); 30497b2e202SAlex Deucher }; 30597b2e202SAlex Deucher 30697b2e202SAlex Deucher /* provided by the ih block */ 30797b2e202SAlex Deucher struct amdgpu_ih_funcs { 30897b2e202SAlex Deucher /* ring read/write ptr handling, called from interrupt context */ 30997b2e202SAlex Deucher u32 (*get_wptr)(struct amdgpu_device *adev); 31097b2e202SAlex Deucher void (*decode_iv)(struct amdgpu_device *adev, 31197b2e202SAlex Deucher struct amdgpu_iv_entry *entry); 31297b2e202SAlex Deucher void (*set_rptr)(struct amdgpu_device *adev); 31397b2e202SAlex Deucher }; 31497b2e202SAlex Deucher 31597b2e202SAlex Deucher /* 31697b2e202SAlex Deucher * BIOS. 31797b2e202SAlex Deucher */ 31897b2e202SAlex Deucher bool amdgpu_get_bios(struct amdgpu_device *adev); 31997b2e202SAlex Deucher bool amdgpu_read_bios(struct amdgpu_device *adev); 32097b2e202SAlex Deucher 32197b2e202SAlex Deucher /* 32297b2e202SAlex Deucher * Dummy page 32397b2e202SAlex Deucher */ 32497b2e202SAlex Deucher struct amdgpu_dummy_page { 32597b2e202SAlex Deucher struct page *page; 32697b2e202SAlex Deucher dma_addr_t addr; 32797b2e202SAlex Deucher }; 32897b2e202SAlex Deucher int amdgpu_dummy_page_init(struct amdgpu_device *adev); 32997b2e202SAlex Deucher void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 33097b2e202SAlex Deucher 33197b2e202SAlex Deucher 33297b2e202SAlex Deucher /* 33397b2e202SAlex Deucher * Clocks 33497b2e202SAlex Deucher */ 33597b2e202SAlex Deucher 33697b2e202SAlex Deucher #define AMDGPU_MAX_PPLL 3 33797b2e202SAlex Deucher 33897b2e202SAlex Deucher struct amdgpu_clock { 33997b2e202SAlex Deucher struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 34097b2e202SAlex Deucher struct amdgpu_pll spll; 34197b2e202SAlex Deucher struct amdgpu_pll mpll; 34297b2e202SAlex Deucher /* 10 Khz units */ 34397b2e202SAlex Deucher uint32_t default_mclk; 34497b2e202SAlex Deucher uint32_t default_sclk; 34597b2e202SAlex Deucher uint32_t default_dispclk; 34697b2e202SAlex Deucher uint32_t current_dispclk; 34797b2e202SAlex Deucher uint32_t dp_extclk; 34897b2e202SAlex Deucher uint32_t max_pixel_clock; 34997b2e202SAlex Deucher }; 35097b2e202SAlex Deucher 35197b2e202SAlex Deucher /* 352c632d799SFlora Cui * BO. 35397b2e202SAlex Deucher */ 35497b2e202SAlex Deucher struct amdgpu_bo_list_entry { 35597b2e202SAlex Deucher struct amdgpu_bo *robj; 35697b2e202SAlex Deucher struct ttm_validate_buffer tv; 35797b2e202SAlex Deucher struct amdgpu_bo_va *bo_va; 35897b2e202SAlex Deucher uint32_t priority; 3592f568dbdSChristian König struct page **user_pages; 3602f568dbdSChristian König int user_invalidated; 36197b2e202SAlex Deucher }; 36297b2e202SAlex Deucher 36397b2e202SAlex Deucher struct amdgpu_bo_va_mapping { 36497b2e202SAlex Deucher struct list_head list; 36597b2e202SAlex Deucher struct interval_tree_node it; 36697b2e202SAlex Deucher uint64_t offset; 367268c3001SChristian König uint64_t flags; 36897b2e202SAlex Deucher }; 36997b2e202SAlex Deucher 37097b2e202SAlex Deucher /* bo virtual addresses in a specific vm */ 37197b2e202SAlex Deucher struct amdgpu_bo_va { 37297b2e202SAlex Deucher /* protected by bo being reserved */ 37397b2e202SAlex Deucher struct list_head bo_list; 374f54d1867SChris Wilson struct dma_fence *last_pt_update; 37597b2e202SAlex Deucher unsigned ref_count; 37697b2e202SAlex Deucher 3777fc11959SChristian König /* protected by vm mutex and spinlock */ 37897b2e202SAlex Deucher struct list_head vm_status; 37997b2e202SAlex Deucher 3807fc11959SChristian König /* mappings for this bo_va */ 3817fc11959SChristian König struct list_head invalids; 3827fc11959SChristian König struct list_head valids; 3837fc11959SChristian König 38497b2e202SAlex Deucher /* constant after initialization */ 38597b2e202SAlex Deucher struct amdgpu_vm *vm; 38697b2e202SAlex Deucher struct amdgpu_bo *bo; 38797b2e202SAlex Deucher }; 38897b2e202SAlex Deucher 3897e5a547fSChunming Zhou #define AMDGPU_GEM_DOMAIN_MAX 0x3 3907e5a547fSChunming Zhou 39197b2e202SAlex Deucher struct amdgpu_bo { 39297b2e202SAlex Deucher /* Protected by tbo.reserved */ 3931ea863fdSChristian König u32 prefered_domains; 3941ea863fdSChristian König u32 allowed_domains; 3957e5a547fSChunming Zhou struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 39697b2e202SAlex Deucher struct ttm_placement placement; 39797b2e202SAlex Deucher struct ttm_buffer_object tbo; 39897b2e202SAlex Deucher struct ttm_bo_kmap_obj kmap; 39997b2e202SAlex Deucher u64 flags; 40097b2e202SAlex Deucher unsigned pin_count; 40197b2e202SAlex Deucher void *kptr; 40297b2e202SAlex Deucher u64 tiling_flags; 40397b2e202SAlex Deucher u64 metadata_flags; 40497b2e202SAlex Deucher void *metadata; 40597b2e202SAlex Deucher u32 metadata_size; 4068e94a46cSMario Kleiner unsigned prime_shared_count; 40797b2e202SAlex Deucher /* list of all virtual address to which this bo 40897b2e202SAlex Deucher * is associated to 40997b2e202SAlex Deucher */ 41097b2e202SAlex Deucher struct list_head va; 41197b2e202SAlex Deucher /* Constant after initialization */ 41297b2e202SAlex Deucher struct drm_gem_object gem_base; 41382b9c55bSChristian König struct amdgpu_bo *parent; 414e7893c4bSChunming Zhou struct amdgpu_bo *shadow; 41597b2e202SAlex Deucher 41697b2e202SAlex Deucher struct ttm_bo_kmap_obj dma_buf_vmap; 41797b2e202SAlex Deucher struct amdgpu_mn *mn; 41897b2e202SAlex Deucher struct list_head mn_list; 4190c4e7fa5SChunming Zhou struct list_head shadow_list; 42097b2e202SAlex Deucher }; 42197b2e202SAlex Deucher #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 42297b2e202SAlex Deucher 42397b2e202SAlex Deucher void amdgpu_gem_object_free(struct drm_gem_object *obj); 42497b2e202SAlex Deucher int amdgpu_gem_object_open(struct drm_gem_object *obj, 42597b2e202SAlex Deucher struct drm_file *file_priv); 42697b2e202SAlex Deucher void amdgpu_gem_object_close(struct drm_gem_object *obj, 42797b2e202SAlex Deucher struct drm_file *file_priv); 42897b2e202SAlex Deucher unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 42997b2e202SAlex Deucher struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 4304d9c514dSChristian König struct drm_gem_object * 4314d9c514dSChristian König amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 43297b2e202SAlex Deucher struct dma_buf_attachment *attach, 43397b2e202SAlex Deucher struct sg_table *sg); 43497b2e202SAlex Deucher struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 43597b2e202SAlex Deucher struct drm_gem_object *gobj, 43697b2e202SAlex Deucher int flags); 43797b2e202SAlex Deucher int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 43897b2e202SAlex Deucher void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 43997b2e202SAlex Deucher struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 44097b2e202SAlex Deucher void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 44197b2e202SAlex Deucher void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 44297b2e202SAlex Deucher int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 44397b2e202SAlex Deucher 44497b2e202SAlex Deucher /* sub-allocation manager, it has to be protected by another lock. 44597b2e202SAlex Deucher * By conception this is an helper for other part of the driver 44697b2e202SAlex Deucher * like the indirect buffer or semaphore, which both have their 44797b2e202SAlex Deucher * locking. 44897b2e202SAlex Deucher * 44997b2e202SAlex Deucher * Principe is simple, we keep a list of sub allocation in offset 45097b2e202SAlex Deucher * order (first entry has offset == 0, last entry has the highest 45197b2e202SAlex Deucher * offset). 45297b2e202SAlex Deucher * 45397b2e202SAlex Deucher * When allocating new object we first check if there is room at 45497b2e202SAlex Deucher * the end total_size - (last_object_offset + last_object_size) >= 45597b2e202SAlex Deucher * alloc_size. If so we allocate new object there. 45697b2e202SAlex Deucher * 45797b2e202SAlex Deucher * When there is not enough room at the end, we start waiting for 45897b2e202SAlex Deucher * each sub object until we reach object_offset+object_size >= 45997b2e202SAlex Deucher * alloc_size, this object then become the sub object we return. 46097b2e202SAlex Deucher * 46197b2e202SAlex Deucher * Alignment can't be bigger than page size. 46297b2e202SAlex Deucher * 46397b2e202SAlex Deucher * Hole are not considered for allocation to keep things simple. 46497b2e202SAlex Deucher * Assumption is that there won't be hole (all object on same 46597b2e202SAlex Deucher * alignment). 46697b2e202SAlex Deucher */ 4676ba60b89SChristian König 4686ba60b89SChristian König #define AMDGPU_SA_NUM_FENCE_LISTS 32 4696ba60b89SChristian König 47097b2e202SAlex Deucher struct amdgpu_sa_manager { 47197b2e202SAlex Deucher wait_queue_head_t wq; 47297b2e202SAlex Deucher struct amdgpu_bo *bo; 47397b2e202SAlex Deucher struct list_head *hole; 4746ba60b89SChristian König struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 47597b2e202SAlex Deucher struct list_head olist; 47697b2e202SAlex Deucher unsigned size; 47797b2e202SAlex Deucher uint64_t gpu_addr; 47897b2e202SAlex Deucher void *cpu_ptr; 47997b2e202SAlex Deucher uint32_t domain; 48097b2e202SAlex Deucher uint32_t align; 48197b2e202SAlex Deucher }; 48297b2e202SAlex Deucher 48397b2e202SAlex Deucher /* sub-allocation buffer */ 48497b2e202SAlex Deucher struct amdgpu_sa_bo { 48597b2e202SAlex Deucher struct list_head olist; 48697b2e202SAlex Deucher struct list_head flist; 48797b2e202SAlex Deucher struct amdgpu_sa_manager *manager; 48897b2e202SAlex Deucher unsigned soffset; 48997b2e202SAlex Deucher unsigned eoffset; 490f54d1867SChris Wilson struct dma_fence *fence; 49197b2e202SAlex Deucher }; 49297b2e202SAlex Deucher 49397b2e202SAlex Deucher /* 49497b2e202SAlex Deucher * GEM objects. 49597b2e202SAlex Deucher */ 496418aa0c2SChristian König void amdgpu_gem_force_release(struct amdgpu_device *adev); 49797b2e202SAlex Deucher int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 49897b2e202SAlex Deucher int alignment, u32 initial_domain, 49997b2e202SAlex Deucher u64 flags, bool kernel, 50097b2e202SAlex Deucher struct drm_gem_object **obj); 50197b2e202SAlex Deucher 50297b2e202SAlex Deucher int amdgpu_mode_dumb_create(struct drm_file *file_priv, 50397b2e202SAlex Deucher struct drm_device *dev, 50497b2e202SAlex Deucher struct drm_mode_create_dumb *args); 50597b2e202SAlex Deucher int amdgpu_mode_dumb_mmap(struct drm_file *filp, 50697b2e202SAlex Deucher struct drm_device *dev, 50797b2e202SAlex Deucher uint32_t handle, uint64_t *offset_p); 508d573de2dSRex Zhu int amdgpu_fence_slab_init(void); 509d573de2dSRex Zhu void amdgpu_fence_slab_fini(void); 51097b2e202SAlex Deucher 51197b2e202SAlex Deucher /* 51297b2e202SAlex Deucher * GART structures, functions & helpers 51397b2e202SAlex Deucher */ 51497b2e202SAlex Deucher struct amdgpu_mc; 51597b2e202SAlex Deucher 51697b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_SIZE 4096 51797b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 51897b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_SHIFT 12 51997b2e202SAlex Deucher #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 52097b2e202SAlex Deucher 52197b2e202SAlex Deucher struct amdgpu_gart { 52297b2e202SAlex Deucher dma_addr_t table_addr; 52397b2e202SAlex Deucher struct amdgpu_bo *robj; 52497b2e202SAlex Deucher void *ptr; 52597b2e202SAlex Deucher unsigned num_gpu_pages; 52697b2e202SAlex Deucher unsigned num_cpu_pages; 52797b2e202SAlex Deucher unsigned table_size; 528a1d29476SChristian König #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 52997b2e202SAlex Deucher struct page **pages; 530a1d29476SChristian König #endif 53197b2e202SAlex Deucher bool ready; 5324b98e0c4SAlex Xie 5334b98e0c4SAlex Xie /* Asic default pte flags */ 5344b98e0c4SAlex Xie uint64_t gart_pte_flags; 5354b98e0c4SAlex Xie 53697b2e202SAlex Deucher const struct amdgpu_gart_funcs *gart_funcs; 53797b2e202SAlex Deucher }; 53897b2e202SAlex Deucher 53997b2e202SAlex Deucher int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 54097b2e202SAlex Deucher void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 54197b2e202SAlex Deucher int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 54297b2e202SAlex Deucher void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 54397b2e202SAlex Deucher int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 54497b2e202SAlex Deucher void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 54597b2e202SAlex Deucher int amdgpu_gart_init(struct amdgpu_device *adev); 54697b2e202SAlex Deucher void amdgpu_gart_fini(struct amdgpu_device *adev); 547cab0b8d5SFelix Kuehling void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 54897b2e202SAlex Deucher int pages); 549cab0b8d5SFelix Kuehling int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 55097b2e202SAlex Deucher int pages, struct page **pagelist, 5516b777607SChunming Zhou dma_addr_t *dma_addr, uint64_t flags); 5522c0d7318SChunming Zhou int amdgpu_ttm_recover_gart(struct amdgpu_device *adev); 55397b2e202SAlex Deucher 55497b2e202SAlex Deucher /* 55597b2e202SAlex Deucher * GPU MC structures, functions & helpers 55697b2e202SAlex Deucher */ 55797b2e202SAlex Deucher struct amdgpu_mc { 55897b2e202SAlex Deucher resource_size_t aper_size; 55997b2e202SAlex Deucher resource_size_t aper_base; 56097b2e202SAlex Deucher resource_size_t agp_base; 56197b2e202SAlex Deucher /* for some chips with <= 32MB we need to lie 56297b2e202SAlex Deucher * about vram size near mc fb location */ 56397b2e202SAlex Deucher u64 mc_vram_size; 56497b2e202SAlex Deucher u64 visible_vram_size; 56597b2e202SAlex Deucher u64 gtt_size; 56697b2e202SAlex Deucher u64 gtt_start; 56797b2e202SAlex Deucher u64 gtt_end; 56897b2e202SAlex Deucher u64 vram_start; 56997b2e202SAlex Deucher u64 vram_end; 57097b2e202SAlex Deucher unsigned vram_width; 57197b2e202SAlex Deucher u64 real_vram_size; 57297b2e202SAlex Deucher int vram_mtrr; 57397b2e202SAlex Deucher u64 gtt_base_align; 57497b2e202SAlex Deucher u64 mc_mask; 57597b2e202SAlex Deucher const struct firmware *fw; /* MC firmware */ 57697b2e202SAlex Deucher uint32_t fw_version; 57797b2e202SAlex Deucher struct amdgpu_irq_src vm_fault; 57881c59f54SKen Wang uint32_t vram_type; 57950b0197aSChunming Zhou uint32_t srbm_soft_reset; 58050b0197aSChunming Zhou struct amdgpu_mode_mc_save save; 581f7c35abeSChristian König bool prt_warning; 5828fe73328SJunwei Zhang /* apertures */ 5838fe73328SJunwei Zhang u64 shared_aperture_start; 5848fe73328SJunwei Zhang u64 shared_aperture_end; 5858fe73328SJunwei Zhang u64 private_aperture_start; 5868fe73328SJunwei Zhang u64 private_aperture_end; 58797b2e202SAlex Deucher }; 58897b2e202SAlex Deucher 58997b2e202SAlex Deucher /* 59097b2e202SAlex Deucher * GPU doorbell structures, functions & helpers 59197b2e202SAlex Deucher */ 59297b2e202SAlex Deucher typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 59397b2e202SAlex Deucher { 59497b2e202SAlex Deucher AMDGPU_DOORBELL_KIQ = 0x000, 59597b2e202SAlex Deucher AMDGPU_DOORBELL_HIQ = 0x001, 59697b2e202SAlex Deucher AMDGPU_DOORBELL_DIQ = 0x002, 59797b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING0 = 0x010, 59897b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING1 = 0x011, 59997b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING2 = 0x012, 60097b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING3 = 0x013, 60197b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING4 = 0x014, 60297b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING5 = 0x015, 60397b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING6 = 0x016, 60497b2e202SAlex Deucher AMDGPU_DOORBELL_MEC_RING7 = 0x017, 60597b2e202SAlex Deucher AMDGPU_DOORBELL_GFX_RING0 = 0x020, 60697b2e202SAlex Deucher AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 60797b2e202SAlex Deucher AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 60897b2e202SAlex Deucher AMDGPU_DOORBELL_IH = 0x1E8, 60997b2e202SAlex Deucher AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 61097b2e202SAlex Deucher AMDGPU_DOORBELL_INVALID = 0xFFFF 61197b2e202SAlex Deucher } AMDGPU_DOORBELL_ASSIGNMENT; 61297b2e202SAlex Deucher 61397b2e202SAlex Deucher struct amdgpu_doorbell { 61497b2e202SAlex Deucher /* doorbell mmio */ 61597b2e202SAlex Deucher resource_size_t base; 61697b2e202SAlex Deucher resource_size_t size; 61797b2e202SAlex Deucher u32 __iomem *ptr; 61897b2e202SAlex Deucher u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 61997b2e202SAlex Deucher }; 62097b2e202SAlex Deucher 62139807b93SKen Wang /* 62239807b93SKen Wang * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 62339807b93SKen Wang */ 62439807b93SKen Wang typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 62539807b93SKen Wang { 62639807b93SKen Wang /* 62739807b93SKen Wang * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 62839807b93SKen Wang * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 62939807b93SKen Wang * Compute related doorbells are allocated from 0x00 to 0x8a 63039807b93SKen Wang */ 63139807b93SKen Wang 63239807b93SKen Wang 63339807b93SKen Wang /* kernel scheduling */ 63439807b93SKen Wang AMDGPU_DOORBELL64_KIQ = 0x00, 63539807b93SKen Wang 63639807b93SKen Wang /* HSA interface queue and debug queue */ 63739807b93SKen Wang AMDGPU_DOORBELL64_HIQ = 0x01, 63839807b93SKen Wang AMDGPU_DOORBELL64_DIQ = 0x02, 63939807b93SKen Wang 64039807b93SKen Wang /* Compute engines */ 64139807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 64239807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 64339807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 64439807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 64539807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 64639807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 64739807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 64839807b93SKen Wang AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 64939807b93SKen Wang 65039807b93SKen Wang /* User queue doorbell range (128 doorbells) */ 65139807b93SKen Wang AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 65239807b93SKen Wang AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 65339807b93SKen Wang 65439807b93SKen Wang /* Graphics engine */ 65539807b93SKen Wang AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 65639807b93SKen Wang 65739807b93SKen Wang /* 65839807b93SKen Wang * Other graphics doorbells can be allocated here: from 0x8c to 0xef 65939807b93SKen Wang * Graphics voltage island aperture 1 66039807b93SKen Wang * default non-graphics QWORD index is 0xF0 - 0xFF inclusive 66139807b93SKen Wang */ 66239807b93SKen Wang 66339807b93SKen Wang /* sDMA engines */ 66439807b93SKen Wang AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 66539807b93SKen Wang AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 66639807b93SKen Wang AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 66739807b93SKen Wang AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 66839807b93SKen Wang 66939807b93SKen Wang /* Interrupt handler */ 67039807b93SKen Wang AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 67139807b93SKen Wang AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 67239807b93SKen Wang AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 67339807b93SKen Wang 67439807b93SKen Wang /* VCN engine */ 67539807b93SKen Wang AMDGPU_DOORBELL64_VCN0 = 0xF8, 67639807b93SKen Wang AMDGPU_DOORBELL64_VCN1 = 0xF9, 67739807b93SKen Wang AMDGPU_DOORBELL64_VCN2 = 0xFA, 67839807b93SKen Wang AMDGPU_DOORBELL64_VCN3 = 0xFB, 67939807b93SKen Wang AMDGPU_DOORBELL64_VCN4 = 0xFC, 68039807b93SKen Wang AMDGPU_DOORBELL64_VCN5 = 0xFD, 68139807b93SKen Wang AMDGPU_DOORBELL64_VCN6 = 0xFE, 68239807b93SKen Wang AMDGPU_DOORBELL64_VCN7 = 0xFF, 68339807b93SKen Wang 68439807b93SKen Wang AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 68539807b93SKen Wang AMDGPU_DOORBELL64_INVALID = 0xFFFF 68639807b93SKen Wang } AMDGPU_DOORBELL64_ASSIGNMENT; 68739807b93SKen Wang 68839807b93SKen Wang 68997b2e202SAlex Deucher void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 69097b2e202SAlex Deucher phys_addr_t *aperture_base, 69197b2e202SAlex Deucher size_t *aperture_size, 69297b2e202SAlex Deucher size_t *start_offset); 69397b2e202SAlex Deucher 69497b2e202SAlex Deucher /* 69597b2e202SAlex Deucher * IRQS. 69697b2e202SAlex Deucher */ 69797b2e202SAlex Deucher 69897b2e202SAlex Deucher struct amdgpu_flip_work { 699325cbba1SMichel Dänzer struct delayed_work flip_work; 70097b2e202SAlex Deucher struct work_struct unpin_work; 70197b2e202SAlex Deucher struct amdgpu_device *adev; 70297b2e202SAlex Deucher int crtc_id; 703325cbba1SMichel Dänzer u32 target_vblank; 70497b2e202SAlex Deucher uint64_t base; 70597b2e202SAlex Deucher struct drm_pending_vblank_event *event; 706765e7fbfSChristian König struct amdgpu_bo *old_abo; 707f54d1867SChris Wilson struct dma_fence *excl; 7081ffd2652SChristian König unsigned shared_count; 709f54d1867SChris Wilson struct dma_fence **shared; 710f54d1867SChris Wilson struct dma_fence_cb cb; 711cb9e59d7SAlex Deucher bool async; 71297b2e202SAlex Deucher }; 71397b2e202SAlex Deucher 71497b2e202SAlex Deucher 71597b2e202SAlex Deucher /* 71697b2e202SAlex Deucher * CP & rings. 71797b2e202SAlex Deucher */ 71897b2e202SAlex Deucher 71997b2e202SAlex Deucher struct amdgpu_ib { 72097b2e202SAlex Deucher struct amdgpu_sa_bo *sa_bo; 72197b2e202SAlex Deucher uint32_t length_dw; 72297b2e202SAlex Deucher uint64_t gpu_addr; 72397b2e202SAlex Deucher uint32_t *ptr; 724de807f81SJammy Zhou uint32_t flags; 72597b2e202SAlex Deucher }; 72697b2e202SAlex Deucher 72762250a91SNils Wallménius extern const struct amd_sched_backend_ops amdgpu_sched_ops; 728c1b69ed0SChunming Zhou 72950838c8cSChristian König int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 730c5637837SMonk Liu struct amdgpu_job **job, struct amdgpu_vm *vm); 731d71518b5SChristian König int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 732d71518b5SChristian König struct amdgpu_job **job); 733b6723c8dSMonk Liu 734a5fb4ec2SChristian König void amdgpu_job_free_resources(struct amdgpu_job *job); 73550838c8cSChristian König void amdgpu_job_free(struct amdgpu_job *job); 736d71518b5SChristian König int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 7372bd9ccfaSChristian König struct amd_sched_entity *entity, void *owner, 738f54d1867SChris Wilson struct dma_fence **f); 7398b4fb00bSChristian König 74097b2e202SAlex Deucher /* 74197b2e202SAlex Deucher * context related structures 74297b2e202SAlex Deucher */ 74397b2e202SAlex Deucher 74421c16bf6SChristian König struct amdgpu_ctx_ring { 74521c16bf6SChristian König uint64_t sequence; 746f54d1867SChris Wilson struct dma_fence **fences; 74791404fb2SChristian König struct amd_sched_entity entity; 74821c16bf6SChristian König }; 74921c16bf6SChristian König 75097b2e202SAlex Deucher struct amdgpu_ctx { 75197b2e202SAlex Deucher struct kref refcount; 7529cb7e5a9SChunming Zhou struct amdgpu_device *adev; 753d94aed5aSMarek Olšák unsigned reset_counter; 75421c16bf6SChristian König spinlock_t ring_lock; 755f54d1867SChris Wilson struct dma_fence **fences; 75621c16bf6SChristian König struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 757753ad49cSMonk Liu bool preamble_presented; 75897b2e202SAlex Deucher }; 75997b2e202SAlex Deucher 76097b2e202SAlex Deucher struct amdgpu_ctx_mgr { 76197b2e202SAlex Deucher struct amdgpu_device *adev; 7620147ee0fSMarek Olšák struct mutex lock; 7630b492a4cSAlex Deucher /* protected by lock */ 7640b492a4cSAlex Deucher struct idr ctx_handles; 76597b2e202SAlex Deucher }; 76697b2e202SAlex Deucher 7670b492a4cSAlex Deucher struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 7680b492a4cSAlex Deucher int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 7690b492a4cSAlex Deucher 77021c16bf6SChristian König uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 771f54d1867SChris Wilson struct dma_fence *fence); 772f54d1867SChris Wilson struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 77321c16bf6SChristian König struct amdgpu_ring *ring, uint64_t seq); 77421c16bf6SChristian König 7750b492a4cSAlex Deucher int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 7760b492a4cSAlex Deucher struct drm_file *filp); 7770b492a4cSAlex Deucher 778efd4ccb5SChristian König void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 779efd4ccb5SChristian König void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 7800b492a4cSAlex Deucher 78197b2e202SAlex Deucher /* 78297b2e202SAlex Deucher * file private structure 78397b2e202SAlex Deucher */ 78497b2e202SAlex Deucher 78597b2e202SAlex Deucher struct amdgpu_fpriv { 78697b2e202SAlex Deucher struct amdgpu_vm vm; 787b85891bdSJunwei Zhang struct amdgpu_bo_va *prt_va; 78897b2e202SAlex Deucher struct mutex bo_list_lock; 78997b2e202SAlex Deucher struct idr bo_list_handles; 79097b2e202SAlex Deucher struct amdgpu_ctx_mgr ctx_mgr; 79197b2e202SAlex Deucher }; 79297b2e202SAlex Deucher 79397b2e202SAlex Deucher /* 79497b2e202SAlex Deucher * residency list 79597b2e202SAlex Deucher */ 79697b2e202SAlex Deucher 79797b2e202SAlex Deucher struct amdgpu_bo_list { 79897b2e202SAlex Deucher struct mutex lock; 79997b2e202SAlex Deucher struct amdgpu_bo *gds_obj; 80097b2e202SAlex Deucher struct amdgpu_bo *gws_obj; 80197b2e202SAlex Deucher struct amdgpu_bo *oa_obj; 802211dff55SChristian König unsigned first_userptr; 80397b2e202SAlex Deucher unsigned num_entries; 80497b2e202SAlex Deucher struct amdgpu_bo_list_entry *array; 80597b2e202SAlex Deucher }; 80697b2e202SAlex Deucher 80797b2e202SAlex Deucher struct amdgpu_bo_list * 80897b2e202SAlex Deucher amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 809636ce25cSChristian König void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 810636ce25cSChristian König struct list_head *validated); 81197b2e202SAlex Deucher void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 81297b2e202SAlex Deucher void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 81397b2e202SAlex Deucher 81497b2e202SAlex Deucher /* 81597b2e202SAlex Deucher * GFX stuff 81697b2e202SAlex Deucher */ 81797b2e202SAlex Deucher #include "clearstate_defs.h" 81897b2e202SAlex Deucher 81979e5412cSAlex Deucher struct amdgpu_rlc_funcs { 82079e5412cSAlex Deucher void (*enter_safe_mode)(struct amdgpu_device *adev); 82179e5412cSAlex Deucher void (*exit_safe_mode)(struct amdgpu_device *adev); 82279e5412cSAlex Deucher }; 82379e5412cSAlex Deucher 82497b2e202SAlex Deucher struct amdgpu_rlc { 82597b2e202SAlex Deucher /* for power gating */ 82697b2e202SAlex Deucher struct amdgpu_bo *save_restore_obj; 82797b2e202SAlex Deucher uint64_t save_restore_gpu_addr; 82897b2e202SAlex Deucher volatile uint32_t *sr_ptr; 82997b2e202SAlex Deucher const u32 *reg_list; 83097b2e202SAlex Deucher u32 reg_list_size; 83197b2e202SAlex Deucher /* for clear state */ 83297b2e202SAlex Deucher struct amdgpu_bo *clear_state_obj; 83397b2e202SAlex Deucher uint64_t clear_state_gpu_addr; 83497b2e202SAlex Deucher volatile uint32_t *cs_ptr; 83597b2e202SAlex Deucher const struct cs_section_def *cs_data; 83697b2e202SAlex Deucher u32 clear_state_size; 83797b2e202SAlex Deucher /* for cp tables */ 83897b2e202SAlex Deucher struct amdgpu_bo *cp_table_obj; 83997b2e202SAlex Deucher uint64_t cp_table_gpu_addr; 84097b2e202SAlex Deucher volatile uint32_t *cp_table_ptr; 84197b2e202SAlex Deucher u32 cp_table_size; 84279e5412cSAlex Deucher 84379e5412cSAlex Deucher /* safe mode for updating CG/PG state */ 84479e5412cSAlex Deucher bool in_safe_mode; 84579e5412cSAlex Deucher const struct amdgpu_rlc_funcs *funcs; 8462b6cd977SEric Huang 8472b6cd977SEric Huang /* for firmware data */ 8482b6cd977SEric Huang u32 save_and_restore_offset; 8492b6cd977SEric Huang u32 clear_state_descriptor_offset; 8502b6cd977SEric Huang u32 avail_scratch_ram_locations; 8512b6cd977SEric Huang u32 reg_restore_list_size; 8522b6cd977SEric Huang u32 reg_list_format_start; 8532b6cd977SEric Huang u32 reg_list_format_separate_start; 8542b6cd977SEric Huang u32 starting_offsets_start; 8552b6cd977SEric Huang u32 reg_list_format_size_bytes; 8562b6cd977SEric Huang u32 reg_list_size_bytes; 8572b6cd977SEric Huang 8582b6cd977SEric Huang u32 *register_list_format; 8592b6cd977SEric Huang u32 *register_restore; 86097b2e202SAlex Deucher }; 86197b2e202SAlex Deucher 86297b2e202SAlex Deucher struct amdgpu_mec { 86397b2e202SAlex Deucher struct amdgpu_bo *hpd_eop_obj; 86497b2e202SAlex Deucher u64 hpd_eop_gpu_addr; 86597b2e202SAlex Deucher u32 num_pipe; 86697b2e202SAlex Deucher u32 num_mec; 86797b2e202SAlex Deucher u32 num_queue; 86859a82d7dSXiangliang Yu void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 86997b2e202SAlex Deucher }; 87097b2e202SAlex Deucher 8714e638ae9SXiangliang Yu struct amdgpu_kiq { 8724e638ae9SXiangliang Yu u64 eop_gpu_addr; 8734e638ae9SXiangliang Yu struct amdgpu_bo *eop_obj; 8744e638ae9SXiangliang Yu struct amdgpu_ring ring; 8754e638ae9SXiangliang Yu struct amdgpu_irq_src irq; 8764e638ae9SXiangliang Yu }; 8774e638ae9SXiangliang Yu 87897b2e202SAlex Deucher /* 87997b2e202SAlex Deucher * GPU scratch registers structures, functions & helpers 88097b2e202SAlex Deucher */ 88197b2e202SAlex Deucher struct amdgpu_scratch { 88297b2e202SAlex Deucher unsigned num_reg; 88397b2e202SAlex Deucher uint32_t reg_base; 88450261151SNils Wallménius uint32_t free_mask; 88597b2e202SAlex Deucher }; 88697b2e202SAlex Deucher 88797b2e202SAlex Deucher /* 88897b2e202SAlex Deucher * GFX configurations 88997b2e202SAlex Deucher */ 890e3fa7630SAlex Deucher #define AMDGPU_GFX_MAX_SE 4 891e3fa7630SAlex Deucher #define AMDGPU_GFX_MAX_SH_PER_SE 2 892e3fa7630SAlex Deucher 893e3fa7630SAlex Deucher struct amdgpu_rb_config { 894e3fa7630SAlex Deucher uint32_t rb_backend_disable; 895e3fa7630SAlex Deucher uint32_t user_rb_backend_disable; 896e3fa7630SAlex Deucher uint32_t raster_config; 897e3fa7630SAlex Deucher uint32_t raster_config_1; 898e3fa7630SAlex Deucher }; 899e3fa7630SAlex Deucher 900d0e95758SAndrey Grodzovsky struct gb_addr_config { 901d0e95758SAndrey Grodzovsky uint16_t pipe_interleave_size; 902d0e95758SAndrey Grodzovsky uint8_t num_pipes; 903d0e95758SAndrey Grodzovsky uint8_t max_compress_frags; 904d0e95758SAndrey Grodzovsky uint8_t num_banks; 905d0e95758SAndrey Grodzovsky uint8_t num_se; 906d0e95758SAndrey Grodzovsky uint8_t num_rb_per_se; 907d0e95758SAndrey Grodzovsky }; 908d0e95758SAndrey Grodzovsky 909ea323f88SJunwei Zhang struct amdgpu_gfx_config { 91097b2e202SAlex Deucher unsigned max_shader_engines; 91197b2e202SAlex Deucher unsigned max_tile_pipes; 91297b2e202SAlex Deucher unsigned max_cu_per_sh; 91397b2e202SAlex Deucher unsigned max_sh_per_se; 91497b2e202SAlex Deucher unsigned max_backends_per_se; 91597b2e202SAlex Deucher unsigned max_texture_channel_caches; 91697b2e202SAlex Deucher unsigned max_gprs; 91797b2e202SAlex Deucher unsigned max_gs_threads; 91897b2e202SAlex Deucher unsigned max_hw_contexts; 91997b2e202SAlex Deucher unsigned sc_prim_fifo_size_frontend; 92097b2e202SAlex Deucher unsigned sc_prim_fifo_size_backend; 92197b2e202SAlex Deucher unsigned sc_hiz_tile_fifo_size; 92297b2e202SAlex Deucher unsigned sc_earlyz_tile_fifo_size; 92397b2e202SAlex Deucher 92497b2e202SAlex Deucher unsigned num_tile_pipes; 92597b2e202SAlex Deucher unsigned backend_enable_mask; 92697b2e202SAlex Deucher unsigned mem_max_burst_length_bytes; 92797b2e202SAlex Deucher unsigned mem_row_size_in_kb; 92897b2e202SAlex Deucher unsigned shader_engine_tile_size; 92997b2e202SAlex Deucher unsigned num_gpus; 93097b2e202SAlex Deucher unsigned multi_gpu_tile_size; 93197b2e202SAlex Deucher unsigned mc_arb_ramcfg; 93297b2e202SAlex Deucher unsigned gb_addr_config; 9338f8e00c1SAlex Deucher unsigned num_rbs; 93497b2e202SAlex Deucher 93597b2e202SAlex Deucher uint32_t tile_mode_array[32]; 93697b2e202SAlex Deucher uint32_t macrotile_mode_array[16]; 937e3fa7630SAlex Deucher 938d0e95758SAndrey Grodzovsky struct gb_addr_config gb_addr_config_fields; 939e3fa7630SAlex Deucher struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 940df6e2c4aSJunwei Zhang 941df6e2c4aSJunwei Zhang /* gfx configure feature */ 942df6e2c4aSJunwei Zhang uint32_t double_offchip_lds_buf; 94397b2e202SAlex Deucher }; 94497b2e202SAlex Deucher 9457dae69a2SAlex Deucher struct amdgpu_cu_info { 9467dae69a2SAlex Deucher uint32_t number; /* total active CU number */ 9477dae69a2SAlex Deucher uint32_t ao_cu_mask; 9487dae69a2SAlex Deucher uint32_t bitmap[4][4]; 9497dae69a2SAlex Deucher }; 9507dae69a2SAlex Deucher 951b95e31fdSAlex Deucher struct amdgpu_gfx_funcs { 952b95e31fdSAlex Deucher /* get the gpu clock counter */ 953b95e31fdSAlex Deucher uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 9549559ef5bSTom St Denis void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 955472259f0STom St Denis void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); 956c5a60ce8STom St Denis void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); 957c5a60ce8STom St Denis void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); 958b95e31fdSAlex Deucher }; 959b95e31fdSAlex Deucher 96097b2e202SAlex Deucher struct amdgpu_gfx { 96197b2e202SAlex Deucher struct mutex gpu_clock_mutex; 962ea323f88SJunwei Zhang struct amdgpu_gfx_config config; 96397b2e202SAlex Deucher struct amdgpu_rlc rlc; 96497b2e202SAlex Deucher struct amdgpu_mec mec; 9654e638ae9SXiangliang Yu struct amdgpu_kiq kiq; 96697b2e202SAlex Deucher struct amdgpu_scratch scratch; 96797b2e202SAlex Deucher const struct firmware *me_fw; /* ME firmware */ 96897b2e202SAlex Deucher uint32_t me_fw_version; 96997b2e202SAlex Deucher const struct firmware *pfp_fw; /* PFP firmware */ 97097b2e202SAlex Deucher uint32_t pfp_fw_version; 97197b2e202SAlex Deucher const struct firmware *ce_fw; /* CE firmware */ 97297b2e202SAlex Deucher uint32_t ce_fw_version; 97397b2e202SAlex Deucher const struct firmware *rlc_fw; /* RLC firmware */ 97497b2e202SAlex Deucher uint32_t rlc_fw_version; 97597b2e202SAlex Deucher const struct firmware *mec_fw; /* MEC firmware */ 97697b2e202SAlex Deucher uint32_t mec_fw_version; 97797b2e202SAlex Deucher const struct firmware *mec2_fw; /* MEC2 firmware */ 97897b2e202SAlex Deucher uint32_t mec2_fw_version; 97902558a00SKen Wang uint32_t me_feature_version; 98002558a00SKen Wang uint32_t ce_feature_version; 98102558a00SKen Wang uint32_t pfp_feature_version; 982351643d7SJammy Zhou uint32_t rlc_feature_version; 983351643d7SJammy Zhou uint32_t mec_feature_version; 984351643d7SJammy Zhou uint32_t mec2_feature_version; 98597b2e202SAlex Deucher struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 98697b2e202SAlex Deucher unsigned num_gfx_rings; 98797b2e202SAlex Deucher struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 98897b2e202SAlex Deucher unsigned num_compute_rings; 98997b2e202SAlex Deucher struct amdgpu_irq_src eop_irq; 99097b2e202SAlex Deucher struct amdgpu_irq_src priv_reg_irq; 99197b2e202SAlex Deucher struct amdgpu_irq_src priv_inst_irq; 99297b2e202SAlex Deucher /* gfx status */ 99397b2e202SAlex Deucher uint32_t gfx_current_status; 994a101a899SKen Wang /* ce ram size*/ 995a101a899SKen Wang unsigned ce_ram_size; 9967dae69a2SAlex Deucher struct amdgpu_cu_info cu_info; 997b95e31fdSAlex Deucher const struct amdgpu_gfx_funcs *funcs; 9983d7c6384SChunming Zhou 9993d7c6384SChunming Zhou /* reset mask */ 10003d7c6384SChunming Zhou uint32_t grbm_soft_reset; 10013d7c6384SChunming Zhou uint32_t srbm_soft_reset; 1002223049cdSMonk Liu bool in_reset; 100397b2e202SAlex Deucher }; 100497b2e202SAlex Deucher 1005b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 100697b2e202SAlex Deucher unsigned size, struct amdgpu_ib *ib); 10074d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 1008f54d1867SChris Wilson struct dma_fence *f); 1009b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 101050ddc75eSJunwei Zhang struct amdgpu_ib *ibs, struct amdgpu_job *job, 101150ddc75eSJunwei Zhang struct dma_fence **f); 101297b2e202SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev); 101397b2e202SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 101497b2e202SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 101597b2e202SAlex Deucher 101697b2e202SAlex Deucher /* 101797b2e202SAlex Deucher * CS. 101897b2e202SAlex Deucher */ 101997b2e202SAlex Deucher struct amdgpu_cs_chunk { 102097b2e202SAlex Deucher uint32_t chunk_id; 102197b2e202SAlex Deucher uint32_t length_dw; 1022758ac17fSChristian König void *kdata; 102397b2e202SAlex Deucher }; 102497b2e202SAlex Deucher 102597b2e202SAlex Deucher struct amdgpu_cs_parser { 102697b2e202SAlex Deucher struct amdgpu_device *adev; 102797b2e202SAlex Deucher struct drm_file *filp; 10283cb485f3SChristian König struct amdgpu_ctx *ctx; 1029c3cca41eSChristian König 103097b2e202SAlex Deucher /* chunks */ 103197b2e202SAlex Deucher unsigned nchunks; 103297b2e202SAlex Deucher struct amdgpu_cs_chunk *chunks; 1033c3cca41eSChristian König 103450838c8cSChristian König /* scheduler job object */ 103550838c8cSChristian König struct amdgpu_job *job; 1036c3cca41eSChristian König 1037c3cca41eSChristian König /* buffer objects */ 1038c3cca41eSChristian König struct ww_acquire_ctx ticket; 1039c3cca41eSChristian König struct amdgpu_bo_list *bo_list; 104056467ebfSChristian König struct amdgpu_bo_list_entry vm_pd; 104197b2e202SAlex Deucher struct list_head validated; 1042f54d1867SChris Wilson struct dma_fence *fence; 1043f69f90a1SChristian König uint64_t bytes_moved_threshold; 1044f69f90a1SChristian König uint64_t bytes_moved; 1045662bfa61SChristian König struct amdgpu_bo_list_entry *evictable; 104697b2e202SAlex Deucher 104797b2e202SAlex Deucher /* user fence */ 104891acbeb6SChristian König struct amdgpu_bo_list_entry uf_entry; 104997b2e202SAlex Deucher }; 105097b2e202SAlex Deucher 1051753ad49cSMonk Liu #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ 1052753ad49cSMonk Liu #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ 1053753ad49cSMonk Liu #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ 10547e6bf80fSMonk Liu #define AMDGPU_VM_DOMAIN (1 << 3) /* bit set means in virtual memory context */ 1055753ad49cSMonk Liu 1056bb977d37SChunming Zhou struct amdgpu_job { 1057bb977d37SChunming Zhou struct amd_sched_job base; 1058bb977d37SChunming Zhou struct amdgpu_device *adev; 1059c5637837SMonk Liu struct amdgpu_vm *vm; 1060b07c60c0SChristian König struct amdgpu_ring *ring; 1061e86f9ceeSChristian König struct amdgpu_sync sync; 1062bb977d37SChunming Zhou struct amdgpu_ib *ibs; 1063f54d1867SChris Wilson struct dma_fence *fence; /* the hw fence */ 1064753ad49cSMonk Liu uint32_t preamble_status; 1065bb977d37SChunming Zhou uint32_t num_ibs; 1066e2840221SChristian König void *owner; 10673aecd24cSMonk Liu uint64_t fence_ctx; /* the fence_context this job uses */ 1068fd53be30SChunming Zhou bool vm_needs_flush; 1069d88bf583SChristian König unsigned vm_id; 1070d88bf583SChristian König uint64_t vm_pd_addr; 1071d88bf583SChristian König uint32_t gds_base, gds_size; 1072d88bf583SChristian König uint32_t gws_base, gws_size; 1073d88bf583SChristian König uint32_t oa_base, oa_size; 1074758ac17fSChristian König 1075758ac17fSChristian König /* user fence handling */ 1076b5f5acbcSChristian König uint64_t uf_addr; 1077758ac17fSChristian König uint64_t uf_sequence; 1078758ac17fSChristian König 1079bb977d37SChunming Zhou }; 1080a6db8a33SJunwei Zhang #define to_amdgpu_job(sched_job) \ 1081a6db8a33SJunwei Zhang container_of((sched_job), struct amdgpu_job, base) 1082bb977d37SChunming Zhou 10837270f839SChristian König static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 10847270f839SChristian König uint32_t ib_idx, int idx) 108597b2e202SAlex Deucher { 108650838c8cSChristian König return p->job->ibs[ib_idx].ptr[idx]; 108797b2e202SAlex Deucher } 108897b2e202SAlex Deucher 10897270f839SChristian König static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 10907270f839SChristian König uint32_t ib_idx, int idx, 10917270f839SChristian König uint32_t value) 10927270f839SChristian König { 109350838c8cSChristian König p->job->ibs[ib_idx].ptr[idx] = value; 10947270f839SChristian König } 10957270f839SChristian König 109697b2e202SAlex Deucher /* 109797b2e202SAlex Deucher * Writeback 109897b2e202SAlex Deucher */ 109997b2e202SAlex Deucher #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 110097b2e202SAlex Deucher 110197b2e202SAlex Deucher struct amdgpu_wb { 110297b2e202SAlex Deucher struct amdgpu_bo *wb_obj; 110397b2e202SAlex Deucher volatile uint32_t *wb; 110497b2e202SAlex Deucher uint64_t gpu_addr; 110597b2e202SAlex Deucher u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 110697b2e202SAlex Deucher unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 110797b2e202SAlex Deucher }; 110897b2e202SAlex Deucher 110997b2e202SAlex Deucher int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 111097b2e202SAlex Deucher void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 11117014285aSKen Wang int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb); 11127014285aSKen Wang void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb); 111397b2e202SAlex Deucher 1114d0dd7f0cSAlex Deucher void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1115d0dd7f0cSAlex Deucher 111697b2e202SAlex Deucher /* 111797b2e202SAlex Deucher * SDMA 111897b2e202SAlex Deucher */ 1119c113ea1cSAlex Deucher struct amdgpu_sdma_instance { 112097b2e202SAlex Deucher /* SDMA firmware */ 112197b2e202SAlex Deucher const struct firmware *fw; 112297b2e202SAlex Deucher uint32_t fw_version; 1123cfa2104fSJammy Zhou uint32_t feature_version; 112497b2e202SAlex Deucher 112597b2e202SAlex Deucher struct amdgpu_ring ring; 112618111de0SJammy Zhou bool burst_nop; 112797b2e202SAlex Deucher }; 112897b2e202SAlex Deucher 1129c113ea1cSAlex Deucher struct amdgpu_sdma { 1130c113ea1cSAlex Deucher struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 113130d1574fSKen Wang #ifdef CONFIG_DRM_AMDGPU_SI 113230d1574fSKen Wang //SI DMA has a difference trap irq number for the second engine 113330d1574fSKen Wang struct amdgpu_irq_src trap_irq_1; 113430d1574fSKen Wang #endif 1135c113ea1cSAlex Deucher struct amdgpu_irq_src trap_irq; 1136c113ea1cSAlex Deucher struct amdgpu_irq_src illegal_inst_irq; 1137c113ea1cSAlex Deucher int num_instances; 1138e702a680SChunming Zhou uint32_t srbm_soft_reset; 1139c113ea1cSAlex Deucher }; 1140c113ea1cSAlex Deucher 114197b2e202SAlex Deucher /* 114297b2e202SAlex Deucher * Firmware 114397b2e202SAlex Deucher */ 1144e635ee07SHuang Rui enum amdgpu_firmware_load_type { 1145e635ee07SHuang Rui AMDGPU_FW_LOAD_DIRECT = 0, 1146e635ee07SHuang Rui AMDGPU_FW_LOAD_SMU, 1147e635ee07SHuang Rui AMDGPU_FW_LOAD_PSP, 1148e635ee07SHuang Rui }; 1149e635ee07SHuang Rui 115097b2e202SAlex Deucher struct amdgpu_firmware { 115197b2e202SAlex Deucher struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1152e635ee07SHuang Rui enum amdgpu_firmware_load_type load_type; 115397b2e202SAlex Deucher struct amdgpu_bo *fw_buf; 115497b2e202SAlex Deucher unsigned int fw_size; 115597b2e202SAlex Deucher }; 115697b2e202SAlex Deucher 115797b2e202SAlex Deucher /* 115897b2e202SAlex Deucher * Benchmarking 115997b2e202SAlex Deucher */ 116097b2e202SAlex Deucher void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 116197b2e202SAlex Deucher 116297b2e202SAlex Deucher 116397b2e202SAlex Deucher /* 116497b2e202SAlex Deucher * Testing 116597b2e202SAlex Deucher */ 116697b2e202SAlex Deucher void amdgpu_test_moves(struct amdgpu_device *adev); 116797b2e202SAlex Deucher 116897b2e202SAlex Deucher /* 116997b2e202SAlex Deucher * MMU Notifier 117097b2e202SAlex Deucher */ 117197b2e202SAlex Deucher #if defined(CONFIG_MMU_NOTIFIER) 117297b2e202SAlex Deucher int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 117397b2e202SAlex Deucher void amdgpu_mn_unregister(struct amdgpu_bo *bo); 117497b2e202SAlex Deucher #else 11751d1106b0SHarry Wentland static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 117697b2e202SAlex Deucher { 117797b2e202SAlex Deucher return -ENODEV; 117897b2e202SAlex Deucher } 11791d1106b0SHarry Wentland static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 118097b2e202SAlex Deucher #endif 118197b2e202SAlex Deucher 118297b2e202SAlex Deucher /* 118397b2e202SAlex Deucher * Debugfs 118497b2e202SAlex Deucher */ 118597b2e202SAlex Deucher struct amdgpu_debugfs { 118606ab6832SNils Wallménius const struct drm_info_list *files; 118797b2e202SAlex Deucher unsigned num_files; 118897b2e202SAlex Deucher }; 118997b2e202SAlex Deucher 119097b2e202SAlex Deucher int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 119106ab6832SNils Wallménius const struct drm_info_list *files, 119297b2e202SAlex Deucher unsigned nfiles); 119397b2e202SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 119497b2e202SAlex Deucher 119597b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS) 119697b2e202SAlex Deucher int amdgpu_debugfs_init(struct drm_minor *minor); 119797b2e202SAlex Deucher #endif 119897b2e202SAlex Deucher 119950ab2533SHuang Rui int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); 120050ab2533SHuang Rui 120197b2e202SAlex Deucher /* 120297b2e202SAlex Deucher * amdgpu smumgr functions 120397b2e202SAlex Deucher */ 120497b2e202SAlex Deucher struct amdgpu_smumgr_funcs { 120597b2e202SAlex Deucher int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 120697b2e202SAlex Deucher int (*request_smu_load_fw)(struct amdgpu_device *adev); 120797b2e202SAlex Deucher int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 120897b2e202SAlex Deucher }; 120997b2e202SAlex Deucher 121097b2e202SAlex Deucher /* 121197b2e202SAlex Deucher * amdgpu smumgr 121297b2e202SAlex Deucher */ 121397b2e202SAlex Deucher struct amdgpu_smumgr { 121497b2e202SAlex Deucher struct amdgpu_bo *toc_buf; 121597b2e202SAlex Deucher struct amdgpu_bo *smu_buf; 121697b2e202SAlex Deucher /* asic priv smu data */ 121797b2e202SAlex Deucher void *priv; 121897b2e202SAlex Deucher spinlock_t smu_lock; 121997b2e202SAlex Deucher /* smumgr functions */ 122097b2e202SAlex Deucher const struct amdgpu_smumgr_funcs *smumgr_funcs; 122197b2e202SAlex Deucher /* ucode loading complete flag */ 122297b2e202SAlex Deucher uint32_t fw_flags; 122397b2e202SAlex Deucher }; 122497b2e202SAlex Deucher 122597b2e202SAlex Deucher /* 122697b2e202SAlex Deucher * ASIC specific register table accessible by UMD 122797b2e202SAlex Deucher */ 122897b2e202SAlex Deucher struct amdgpu_allowed_register_entry { 122997b2e202SAlex Deucher uint32_t reg_offset; 123097b2e202SAlex Deucher bool untouched; 123197b2e202SAlex Deucher bool grbm_indexed; 123297b2e202SAlex Deucher }; 123397b2e202SAlex Deucher 123497b2e202SAlex Deucher /* 123597b2e202SAlex Deucher * ASIC specific functions. 123697b2e202SAlex Deucher */ 123797b2e202SAlex Deucher struct amdgpu_asic_funcs { 123897b2e202SAlex Deucher bool (*read_disabled_bios)(struct amdgpu_device *adev); 12397946b878SAlex Deucher bool (*read_bios_from_rom)(struct amdgpu_device *adev, 12407946b878SAlex Deucher u8 *bios, u32 length_bytes); 124197b2e202SAlex Deucher int (*read_register)(struct amdgpu_device *adev, u32 se_num, 124297b2e202SAlex Deucher u32 sh_num, u32 reg_offset, u32 *value); 124397b2e202SAlex Deucher void (*set_vga_state)(struct amdgpu_device *adev, bool state); 124497b2e202SAlex Deucher int (*reset)(struct amdgpu_device *adev); 124597b2e202SAlex Deucher /* get the reference clock */ 124697b2e202SAlex Deucher u32 (*get_xclk)(struct amdgpu_device *adev); 124797b2e202SAlex Deucher /* MM block clocks */ 124897b2e202SAlex Deucher int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 124997b2e202SAlex Deucher int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1250841686dfSMaruthi Bayyavarapu /* static power management */ 1251841686dfSMaruthi Bayyavarapu int (*get_pcie_lanes)(struct amdgpu_device *adev); 1252841686dfSMaruthi Bayyavarapu void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 1253bbf282d8SAlex Deucher /* get config memsize register */ 1254bbf282d8SAlex Deucher u32 (*get_config_memsize)(struct amdgpu_device *adev); 125597b2e202SAlex Deucher }; 125697b2e202SAlex Deucher 125797b2e202SAlex Deucher /* 125897b2e202SAlex Deucher * IOCTL. 125997b2e202SAlex Deucher */ 126097b2e202SAlex Deucher int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 126197b2e202SAlex Deucher struct drm_file *filp); 126297b2e202SAlex Deucher int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 126397b2e202SAlex Deucher struct drm_file *filp); 126497b2e202SAlex Deucher 126597b2e202SAlex Deucher int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 126697b2e202SAlex Deucher struct drm_file *filp); 126797b2e202SAlex Deucher int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 126897b2e202SAlex Deucher struct drm_file *filp); 126997b2e202SAlex Deucher int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 127097b2e202SAlex Deucher struct drm_file *filp); 127197b2e202SAlex Deucher int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 127297b2e202SAlex Deucher struct drm_file *filp); 127397b2e202SAlex Deucher int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 127497b2e202SAlex Deucher struct drm_file *filp); 127597b2e202SAlex Deucher int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 127697b2e202SAlex Deucher struct drm_file *filp); 127797b2e202SAlex Deucher int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 127897b2e202SAlex Deucher int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1279eef18a82SJunwei Zhang int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 1280eef18a82SJunwei Zhang struct drm_file *filp); 128197b2e202SAlex Deucher 128297b2e202SAlex Deucher int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 128397b2e202SAlex Deucher struct drm_file *filp); 128497b2e202SAlex Deucher 128597b2e202SAlex Deucher /* VRAM scratch page for HDP bug, default vram page */ 128697b2e202SAlex Deucher struct amdgpu_vram_scratch { 128797b2e202SAlex Deucher struct amdgpu_bo *robj; 128897b2e202SAlex Deucher volatile uint32_t *ptr; 128997b2e202SAlex Deucher u64 gpu_addr; 129097b2e202SAlex Deucher }; 129197b2e202SAlex Deucher 129297b2e202SAlex Deucher /* 129397b2e202SAlex Deucher * ACPI 129497b2e202SAlex Deucher */ 129597b2e202SAlex Deucher struct amdgpu_atif_notification_cfg { 129697b2e202SAlex Deucher bool enabled; 129797b2e202SAlex Deucher int command_code; 129897b2e202SAlex Deucher }; 129997b2e202SAlex Deucher 130097b2e202SAlex Deucher struct amdgpu_atif_notifications { 130197b2e202SAlex Deucher bool display_switch; 130297b2e202SAlex Deucher bool expansion_mode_change; 130397b2e202SAlex Deucher bool thermal_state; 130497b2e202SAlex Deucher bool forced_power_state; 130597b2e202SAlex Deucher bool system_power_state; 130697b2e202SAlex Deucher bool display_conf_change; 130797b2e202SAlex Deucher bool px_gfx_switch; 130897b2e202SAlex Deucher bool brightness_change; 130997b2e202SAlex Deucher bool dgpu_display_event; 131097b2e202SAlex Deucher }; 131197b2e202SAlex Deucher 131297b2e202SAlex Deucher struct amdgpu_atif_functions { 131397b2e202SAlex Deucher bool system_params; 131497b2e202SAlex Deucher bool sbios_requests; 131597b2e202SAlex Deucher bool select_active_disp; 131697b2e202SAlex Deucher bool lid_state; 131797b2e202SAlex Deucher bool get_tv_standard; 131897b2e202SAlex Deucher bool set_tv_standard; 131997b2e202SAlex Deucher bool get_panel_expansion_mode; 132097b2e202SAlex Deucher bool set_panel_expansion_mode; 132197b2e202SAlex Deucher bool temperature_change; 132297b2e202SAlex Deucher bool graphics_device_types; 132397b2e202SAlex Deucher }; 132497b2e202SAlex Deucher 132597b2e202SAlex Deucher struct amdgpu_atif { 132697b2e202SAlex Deucher struct amdgpu_atif_notifications notifications; 132797b2e202SAlex Deucher struct amdgpu_atif_functions functions; 132897b2e202SAlex Deucher struct amdgpu_atif_notification_cfg notification_cfg; 132997b2e202SAlex Deucher struct amdgpu_encoder *encoder_for_bl; 133097b2e202SAlex Deucher }; 133197b2e202SAlex Deucher 133297b2e202SAlex Deucher struct amdgpu_atcs_functions { 133397b2e202SAlex Deucher bool get_ext_state; 133497b2e202SAlex Deucher bool pcie_perf_req; 133597b2e202SAlex Deucher bool pcie_dev_rdy; 133697b2e202SAlex Deucher bool pcie_bus_width; 133797b2e202SAlex Deucher }; 133897b2e202SAlex Deucher 133997b2e202SAlex Deucher struct amdgpu_atcs { 134097b2e202SAlex Deucher struct amdgpu_atcs_functions functions; 134197b2e202SAlex Deucher }; 134297b2e202SAlex Deucher 134397b2e202SAlex Deucher /* 1344d03846afSChunming Zhou * CGS 1345d03846afSChunming Zhou */ 1346110e6f26SDave Airlie struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1347110e6f26SDave Airlie void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1348a8fe58ceSMaruthi Bayyavarapu 1349a8fe58ceSMaruthi Bayyavarapu /* 135097b2e202SAlex Deucher * Core structure, functions and helpers. 135197b2e202SAlex Deucher */ 135297b2e202SAlex Deucher typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 135397b2e202SAlex Deucher typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 135497b2e202SAlex Deucher 135597b2e202SAlex Deucher typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 135697b2e202SAlex Deucher typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 135797b2e202SAlex Deucher 135897b2e202SAlex Deucher struct amdgpu_device { 135997b2e202SAlex Deucher struct device *dev; 136097b2e202SAlex Deucher struct drm_device *ddev; 136197b2e202SAlex Deucher struct pci_dev *pdev; 136297b2e202SAlex Deucher 1363a8fe58ceSMaruthi Bayyavarapu #ifdef CONFIG_DRM_AMD_ACP 1364a8fe58ceSMaruthi Bayyavarapu struct amdgpu_acp acp; 1365a8fe58ceSMaruthi Bayyavarapu #endif 1366a8fe58ceSMaruthi Bayyavarapu 136797b2e202SAlex Deucher /* ASIC */ 13682f7d10b3SJammy Zhou enum amd_asic_type asic_type; 136997b2e202SAlex Deucher uint32_t family; 137097b2e202SAlex Deucher uint32_t rev_id; 137197b2e202SAlex Deucher uint32_t external_rev_id; 137297b2e202SAlex Deucher unsigned long flags; 137397b2e202SAlex Deucher int usec_timeout; 137497b2e202SAlex Deucher const struct amdgpu_asic_funcs *asic_funcs; 137597b2e202SAlex Deucher bool shutdown; 137697b2e202SAlex Deucher bool need_dma32; 137797b2e202SAlex Deucher bool accel_working; 137897b2e202SAlex Deucher struct work_struct reset_work; 137997b2e202SAlex Deucher struct notifier_block acpi_nb; 138097b2e202SAlex Deucher struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 138197b2e202SAlex Deucher struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 138297b2e202SAlex Deucher unsigned debugfs_count; 138397b2e202SAlex Deucher #if defined(CONFIG_DEBUG_FS) 1384adcec288STom St Denis struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 138597b2e202SAlex Deucher #endif 138697b2e202SAlex Deucher struct amdgpu_atif atif; 138797b2e202SAlex Deucher struct amdgpu_atcs atcs; 138897b2e202SAlex Deucher struct mutex srbm_mutex; 138997b2e202SAlex Deucher /* GRBM index mutex. Protects concurrent access to GRBM index */ 139097b2e202SAlex Deucher struct mutex grbm_idx_mutex; 139197b2e202SAlex Deucher struct dev_pm_domain vga_pm_domain; 139297b2e202SAlex Deucher bool have_disp_power_ref; 139397b2e202SAlex Deucher 139497b2e202SAlex Deucher /* BIOS */ 13950cdd5005SAlex Deucher bool is_atom_fw; 139697b2e202SAlex Deucher uint8_t *bios; 1397a9f5db9cSEvan Quan uint32_t bios_size; 139897b2e202SAlex Deucher struct amdgpu_bo *stollen_vga_memory; 1399a5bde2f9SAlex Deucher uint32_t bios_scratch_reg_offset; 140097b2e202SAlex Deucher uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 140197b2e202SAlex Deucher 140297b2e202SAlex Deucher /* Register/doorbell mmio */ 140397b2e202SAlex Deucher resource_size_t rmmio_base; 140497b2e202SAlex Deucher resource_size_t rmmio_size; 140597b2e202SAlex Deucher void __iomem *rmmio; 140697b2e202SAlex Deucher /* protects concurrent MM_INDEX/DATA based register access */ 140797b2e202SAlex Deucher spinlock_t mmio_idx_lock; 140897b2e202SAlex Deucher /* protects concurrent SMC based register access */ 140997b2e202SAlex Deucher spinlock_t smc_idx_lock; 141097b2e202SAlex Deucher amdgpu_rreg_t smc_rreg; 141197b2e202SAlex Deucher amdgpu_wreg_t smc_wreg; 141297b2e202SAlex Deucher /* protects concurrent PCIE register access */ 141397b2e202SAlex Deucher spinlock_t pcie_idx_lock; 141497b2e202SAlex Deucher amdgpu_rreg_t pcie_rreg; 141597b2e202SAlex Deucher amdgpu_wreg_t pcie_wreg; 141636b9a952SHuang Rui amdgpu_rreg_t pciep_rreg; 141736b9a952SHuang Rui amdgpu_wreg_t pciep_wreg; 141897b2e202SAlex Deucher /* protects concurrent UVD register access */ 141997b2e202SAlex Deucher spinlock_t uvd_ctx_idx_lock; 142097b2e202SAlex Deucher amdgpu_rreg_t uvd_ctx_rreg; 142197b2e202SAlex Deucher amdgpu_wreg_t uvd_ctx_wreg; 142297b2e202SAlex Deucher /* protects concurrent DIDT register access */ 142397b2e202SAlex Deucher spinlock_t didt_idx_lock; 142497b2e202SAlex Deucher amdgpu_rreg_t didt_rreg; 142597b2e202SAlex Deucher amdgpu_wreg_t didt_wreg; 1426ccdbb20aSRex Zhu /* protects concurrent gc_cac register access */ 1427ccdbb20aSRex Zhu spinlock_t gc_cac_idx_lock; 1428ccdbb20aSRex Zhu amdgpu_rreg_t gc_cac_rreg; 1429ccdbb20aSRex Zhu amdgpu_wreg_t gc_cac_wreg; 143097b2e202SAlex Deucher /* protects concurrent ENDPOINT (audio) register access */ 143197b2e202SAlex Deucher spinlock_t audio_endpt_idx_lock; 143297b2e202SAlex Deucher amdgpu_block_rreg_t audio_endpt_rreg; 143397b2e202SAlex Deucher amdgpu_block_wreg_t audio_endpt_wreg; 143497b2e202SAlex Deucher void __iomem *rio_mem; 143597b2e202SAlex Deucher resource_size_t rio_mem_size; 143697b2e202SAlex Deucher struct amdgpu_doorbell doorbell; 143797b2e202SAlex Deucher 143897b2e202SAlex Deucher /* clock/pll info */ 143997b2e202SAlex Deucher struct amdgpu_clock clock; 144097b2e202SAlex Deucher 144197b2e202SAlex Deucher /* MC */ 144297b2e202SAlex Deucher struct amdgpu_mc mc; 144397b2e202SAlex Deucher struct amdgpu_gart gart; 144497b2e202SAlex Deucher struct amdgpu_dummy_page dummy_page; 144597b2e202SAlex Deucher struct amdgpu_vm_manager vm_manager; 144697b2e202SAlex Deucher 144797b2e202SAlex Deucher /* memory management */ 144897b2e202SAlex Deucher struct amdgpu_mman mman; 144997b2e202SAlex Deucher struct amdgpu_vram_scratch vram_scratch; 145097b2e202SAlex Deucher struct amdgpu_wb wb; 145197b2e202SAlex Deucher atomic64_t vram_usage; 145297b2e202SAlex Deucher atomic64_t vram_vis_usage; 145397b2e202SAlex Deucher atomic64_t gtt_usage; 145497b2e202SAlex Deucher atomic64_t num_bytes_moved; 1455dbd5ed60SChristian König atomic64_t num_evictions; 1456d94aed5aSMarek Olšák atomic_t gpu_reset_counter; 145797b2e202SAlex Deucher 145895844d20SMarek Olšák /* data for buffer migration throttling */ 145995844d20SMarek Olšák struct { 146095844d20SMarek Olšák spinlock_t lock; 146195844d20SMarek Olšák s64 last_update_us; 146295844d20SMarek Olšák s64 accum_us; /* accumulated microseconds */ 146395844d20SMarek Olšák u32 log2_max_MBps; 146495844d20SMarek Olšák } mm_stats; 146595844d20SMarek Olšák 146697b2e202SAlex Deucher /* display */ 14679accf2fdSEmily Deng bool enable_virtual_display; 146897b2e202SAlex Deucher struct amdgpu_mode_info mode_info; 146997b2e202SAlex Deucher struct work_struct hotplug_work; 147097b2e202SAlex Deucher struct amdgpu_irq_src crtc_irq; 147197b2e202SAlex Deucher struct amdgpu_irq_src pageflip_irq; 147297b2e202SAlex Deucher struct amdgpu_irq_src hpd_irq; 147397b2e202SAlex Deucher 147497b2e202SAlex Deucher /* rings */ 147576bf0db5SChristian König u64 fence_context; 147697b2e202SAlex Deucher unsigned num_rings; 147797b2e202SAlex Deucher struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 147897b2e202SAlex Deucher bool ib_pool_ready; 147997b2e202SAlex Deucher struct amdgpu_sa_manager ring_tmp_bo; 148097b2e202SAlex Deucher 148197b2e202SAlex Deucher /* interrupts */ 148297b2e202SAlex Deucher struct amdgpu_irq irq; 148397b2e202SAlex Deucher 14841f7371b2SAlex Deucher /* powerplay */ 14851f7371b2SAlex Deucher struct amd_powerplay powerplay; 1486e61710c5SJammy Zhou bool pp_enabled; 1487f3898ea1SEric Huang bool pp_force_state_enabled; 14881f7371b2SAlex Deucher 148997b2e202SAlex Deucher /* dpm */ 149097b2e202SAlex Deucher struct amdgpu_pm pm; 149197b2e202SAlex Deucher u32 cg_flags; 149297b2e202SAlex Deucher u32 pg_flags; 149397b2e202SAlex Deucher 149497b2e202SAlex Deucher /* amdgpu smumgr */ 149597b2e202SAlex Deucher struct amdgpu_smumgr smu; 149697b2e202SAlex Deucher 149797b2e202SAlex Deucher /* gfx */ 149897b2e202SAlex Deucher struct amdgpu_gfx gfx; 149997b2e202SAlex Deucher 150097b2e202SAlex Deucher /* sdma */ 1501c113ea1cSAlex Deucher struct amdgpu_sdma sdma; 150297b2e202SAlex Deucher 150397b2e202SAlex Deucher /* uvd */ 150497b2e202SAlex Deucher struct amdgpu_uvd uvd; 150597b2e202SAlex Deucher 150697b2e202SAlex Deucher /* vce */ 150797b2e202SAlex Deucher struct amdgpu_vce vce; 150897b2e202SAlex Deucher 150997b2e202SAlex Deucher /* firmwares */ 151097b2e202SAlex Deucher struct amdgpu_firmware firmware; 151197b2e202SAlex Deucher 151297b2e202SAlex Deucher /* GDS */ 151397b2e202SAlex Deucher struct amdgpu_gds gds; 151497b2e202SAlex Deucher 1515a1255107SAlex Deucher struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 151697b2e202SAlex Deucher int num_ip_blocks; 151797b2e202SAlex Deucher struct mutex mn_lock; 151897b2e202SAlex Deucher DECLARE_HASHTABLE(mn_hash, 7); 151997b2e202SAlex Deucher 152097b2e202SAlex Deucher /* tracking pinned memory */ 152197b2e202SAlex Deucher u64 vram_pin_size; 1522e131b914SChunming Zhou u64 invisible_pin_size; 152397b2e202SAlex Deucher u64 gart_pin_size; 1524130e0371SOded Gabbay 1525130e0371SOded Gabbay /* amdkfd interface */ 1526130e0371SOded Gabbay struct kfd_dev *kfd; 152723ca0e4eSChunming Zhou 15285a5099cbSXiangliang Yu struct amdgpu_virt virt; 15290c4e7fa5SChunming Zhou 15300c4e7fa5SChunming Zhou /* link all shadow bo */ 15310c4e7fa5SChunming Zhou struct list_head shadow_list; 15320c4e7fa5SChunming Zhou struct mutex shadow_list_lock; 15335c1354bdSChunming Zhou /* link all gtt */ 15345c1354bdSChunming Zhou spinlock_t gtt_list_lock; 15355c1354bdSChunming Zhou struct list_head gtt_list; 15365c1354bdSChunming Zhou 1537c836fec5SJim Qu /* record hw reset is performed */ 1538c836fec5SJim Qu bool has_hw_reset; 1539c836fec5SJim Qu 154097b2e202SAlex Deucher }; 154197b2e202SAlex Deucher 1542a7d64de6SChristian König static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1543a7d64de6SChristian König { 1544a7d64de6SChristian König return container_of(bdev, struct amdgpu_device, mman.bdev); 1545a7d64de6SChristian König } 1546a7d64de6SChristian König 154797b2e202SAlex Deucher bool amdgpu_device_is_px(struct drm_device *dev); 154897b2e202SAlex Deucher int amdgpu_device_init(struct amdgpu_device *adev, 154997b2e202SAlex Deucher struct drm_device *ddev, 155097b2e202SAlex Deucher struct pci_dev *pdev, 155197b2e202SAlex Deucher uint32_t flags); 155297b2e202SAlex Deucher void amdgpu_device_fini(struct amdgpu_device *adev); 155397b2e202SAlex Deucher int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 155497b2e202SAlex Deucher 155597b2e202SAlex Deucher uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 155615d72fd7SMonk Liu uint32_t acc_flags); 155797b2e202SAlex Deucher void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 155815d72fd7SMonk Liu uint32_t acc_flags); 155997b2e202SAlex Deucher u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 156097b2e202SAlex Deucher void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 156197b2e202SAlex Deucher 156297b2e202SAlex Deucher u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 156397b2e202SAlex Deucher void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1564832be404SKen Wang u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 1565832be404SKen Wang void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 156697b2e202SAlex Deucher 156797b2e202SAlex Deucher /* 156897b2e202SAlex Deucher * Registers read & write functions. 156997b2e202SAlex Deucher */ 157015d72fd7SMonk Liu 157115d72fd7SMonk Liu #define AMDGPU_REGS_IDX (1<<0) 157215d72fd7SMonk Liu #define AMDGPU_REGS_NO_KIQ (1<<1) 157315d72fd7SMonk Liu 157415d72fd7SMonk Liu #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 157515d72fd7SMonk Liu #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 157615d72fd7SMonk Liu 157715d72fd7SMonk Liu #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 157815d72fd7SMonk Liu #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 157915d72fd7SMonk Liu #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 158015d72fd7SMonk Liu #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 158115d72fd7SMonk Liu #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 158297b2e202SAlex Deucher #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 158397b2e202SAlex Deucher #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 158497b2e202SAlex Deucher #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 158597b2e202SAlex Deucher #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 158636b9a952SHuang Rui #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 158736b9a952SHuang Rui #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 158897b2e202SAlex Deucher #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 158997b2e202SAlex Deucher #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 159097b2e202SAlex Deucher #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 159197b2e202SAlex Deucher #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 159297b2e202SAlex Deucher #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 159397b2e202SAlex Deucher #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1594ccdbb20aSRex Zhu #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1595ccdbb20aSRex Zhu #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 159697b2e202SAlex Deucher #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 159797b2e202SAlex Deucher #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 159897b2e202SAlex Deucher #define WREG32_P(reg, val, mask) \ 159997b2e202SAlex Deucher do { \ 160097b2e202SAlex Deucher uint32_t tmp_ = RREG32(reg); \ 160197b2e202SAlex Deucher tmp_ &= (mask); \ 160297b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 160397b2e202SAlex Deucher WREG32(reg, tmp_); \ 160497b2e202SAlex Deucher } while (0) 160597b2e202SAlex Deucher #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 160697b2e202SAlex Deucher #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 160797b2e202SAlex Deucher #define WREG32_PLL_P(reg, val, mask) \ 160897b2e202SAlex Deucher do { \ 160997b2e202SAlex Deucher uint32_t tmp_ = RREG32_PLL(reg); \ 161097b2e202SAlex Deucher tmp_ &= (mask); \ 161197b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 161297b2e202SAlex Deucher WREG32_PLL(reg, tmp_); \ 161397b2e202SAlex Deucher } while (0) 161497b2e202SAlex Deucher #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 161597b2e202SAlex Deucher #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 161697b2e202SAlex Deucher #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 161797b2e202SAlex Deucher 161897b2e202SAlex Deucher #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 161997b2e202SAlex Deucher #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1620832be404SKen Wang #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 1621832be404SKen Wang #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 162297b2e202SAlex Deucher 162397b2e202SAlex Deucher #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 162497b2e202SAlex Deucher #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 162597b2e202SAlex Deucher 162697b2e202SAlex Deucher #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 162797b2e202SAlex Deucher (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 162897b2e202SAlex Deucher (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 162997b2e202SAlex Deucher 163097b2e202SAlex Deucher #define REG_GET_FIELD(value, reg, field) \ 163197b2e202SAlex Deucher (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 163297b2e202SAlex Deucher 163361cb8cefSTom St Denis #define WREG32_FIELD(reg, field, val) \ 163461cb8cefSTom St Denis WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 163561cb8cefSTom St Denis 163697b2e202SAlex Deucher /* 163797b2e202SAlex Deucher * BIOS helpers. 163897b2e202SAlex Deucher */ 163997b2e202SAlex Deucher #define RBIOS8(i) (adev->bios[i]) 164097b2e202SAlex Deucher #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 164197b2e202SAlex Deucher #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 164297b2e202SAlex Deucher 164397b2e202SAlex Deucher /* 164497b2e202SAlex Deucher * RING helpers. 164597b2e202SAlex Deucher */ 164697b2e202SAlex Deucher static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 164797b2e202SAlex Deucher { 164897b2e202SAlex Deucher if (ring->count_dw <= 0) 164986c2b790SJammy Zhou DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 1650536fbf94SKen Wang ring->ring[ring->wptr++ & ring->buf_mask] = v; 165197b2e202SAlex Deucher ring->wptr &= ring->ptr_mask; 165297b2e202SAlex Deucher ring->count_dw--; 165397b2e202SAlex Deucher } 165497b2e202SAlex Deucher 16550a8e1473SMonk Liu static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw) 16560a8e1473SMonk Liu { 16570a8e1473SMonk Liu unsigned occupied, chunk1, chunk2; 16580a8e1473SMonk Liu void *dst; 16590a8e1473SMonk Liu 16600a8e1473SMonk Liu if (ring->count_dw < count_dw) { 16610a8e1473SMonk Liu DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 16620a8e1473SMonk Liu } else { 16630a8e1473SMonk Liu occupied = ring->wptr & ring->ptr_mask; 16640a8e1473SMonk Liu dst = (void *)&ring->ring[occupied]; 16650a8e1473SMonk Liu chunk1 = ring->ptr_mask + 1 - occupied; 16660a8e1473SMonk Liu chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; 16670a8e1473SMonk Liu chunk2 = count_dw - chunk1; 16680a8e1473SMonk Liu chunk1 <<= 2; 16690a8e1473SMonk Liu chunk2 <<= 2; 16700a8e1473SMonk Liu 16710a8e1473SMonk Liu if (chunk1) 16720a8e1473SMonk Liu memcpy(dst, src, chunk1); 16730a8e1473SMonk Liu 16740a8e1473SMonk Liu if (chunk2) { 16750a8e1473SMonk Liu src += chunk1; 16760a8e1473SMonk Liu dst = (void *)ring->ring; 16770a8e1473SMonk Liu memcpy(dst, src, chunk2); 16780a8e1473SMonk Liu } 16790a8e1473SMonk Liu 16800a8e1473SMonk Liu ring->wptr += count_dw; 16810a8e1473SMonk Liu ring->wptr &= ring->ptr_mask; 16820a8e1473SMonk Liu ring->count_dw -= count_dw; 16830a8e1473SMonk Liu } 16840a8e1473SMonk Liu } 16850a8e1473SMonk Liu 1686c113ea1cSAlex Deucher static inline struct amdgpu_sdma_instance * 1687c113ea1cSAlex Deucher amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 16884b2f7e2cSJammy Zhou { 16894b2f7e2cSJammy Zhou struct amdgpu_device *adev = ring->adev; 16904b2f7e2cSJammy Zhou int i; 16914b2f7e2cSJammy Zhou 1692c113ea1cSAlex Deucher for (i = 0; i < adev->sdma.num_instances; i++) 1693c113ea1cSAlex Deucher if (&adev->sdma.instance[i].ring == ring) 16944b2f7e2cSJammy Zhou break; 16954b2f7e2cSJammy Zhou 16964b2f7e2cSJammy Zhou if (i < AMDGPU_MAX_SDMA_INSTANCES) 1697c113ea1cSAlex Deucher return &adev->sdma.instance[i]; 16984b2f7e2cSJammy Zhou else 16994b2f7e2cSJammy Zhou return NULL; 17004b2f7e2cSJammy Zhou } 17014b2f7e2cSJammy Zhou 170297b2e202SAlex Deucher /* 170397b2e202SAlex Deucher * ASICs macro. 170497b2e202SAlex Deucher */ 170597b2e202SAlex Deucher #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 170697b2e202SAlex Deucher #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 170797b2e202SAlex Deucher #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 170897b2e202SAlex Deucher #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 170997b2e202SAlex Deucher #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1710841686dfSMaruthi Bayyavarapu #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1711841686dfSMaruthi Bayyavarapu #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1712841686dfSMaruthi Bayyavarapu #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 171397b2e202SAlex Deucher #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 17147946b878SAlex Deucher #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 171597b2e202SAlex Deucher #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1716bbf282d8SAlex Deucher #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 171797b2e202SAlex Deucher #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 171897b2e202SAlex Deucher #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 171997b2e202SAlex Deucher #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 1720de9ea7bdSChristian König #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 172197b2e202SAlex Deucher #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 17225463545bSAlex Xie #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags)) 172397b2e202SAlex Deucher #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 172497b2e202SAlex Deucher #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 1725bbec97aaSChristian König #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 172697b2e202SAlex Deucher #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 172797b2e202SAlex Deucher #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 172897b2e202SAlex Deucher #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 1729d88bf583SChristian König #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 1730b8c7b39eSChristian König #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 173197b2e202SAlex Deucher #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 1732890ee23fSChunming Zhou #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 173397b2e202SAlex Deucher #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 1734d2edb07bSChristian König #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 173511afbde8SChunming Zhou #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 1736c2167a65SMonk Liu #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 1737753ad49cSMonk Liu #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 1738b6091c12SXiangliang Yu #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) 1739b6091c12SXiangliang Yu #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 17409e5d5309SChristian König #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 174103ccf481SMonk Liu #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 174203ccf481SMonk Liu #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 174397b2e202SAlex Deucher #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 174497b2e202SAlex Deucher #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 174597b2e202SAlex Deucher #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 174697b2e202SAlex Deucher #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 174797b2e202SAlex Deucher #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 174897b2e202SAlex Deucher #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 174997b2e202SAlex Deucher #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 175097b2e202SAlex Deucher #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 175197b2e202SAlex Deucher #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 175297b2e202SAlex Deucher #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 175397b2e202SAlex Deucher #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 175497b2e202SAlex Deucher #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 1755cb9e59d7SAlex Deucher #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 175697b2e202SAlex Deucher #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 175797b2e202SAlex Deucher #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 175897b2e202SAlex Deucher #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 175997b2e202SAlex Deucher #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 176097b2e202SAlex Deucher #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 1761c7ae72c0SChunming Zhou #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 17626e7a3840SChunming Zhou #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 1763b95e31fdSAlex Deucher #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 17649559ef5bSTom St Denis #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 176597b2e202SAlex Deucher #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 176697b2e202SAlex Deucher 176797b2e202SAlex Deucher /* Common functions */ 176897b2e202SAlex Deucher int amdgpu_gpu_reset(struct amdgpu_device *adev); 17693ad81f16SChunming Zhou bool amdgpu_need_backup(struct amdgpu_device *adev); 177097b2e202SAlex Deucher void amdgpu_pci_config_reset(struct amdgpu_device *adev); 1771c836fec5SJim Qu bool amdgpu_need_post(struct amdgpu_device *adev); 177297b2e202SAlex Deucher void amdgpu_update_display_priority(struct amdgpu_device *adev); 1773d5fc5e82SChunming Zhou 177497b2e202SAlex Deucher int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 177597b2e202SAlex Deucher int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 177697b2e202SAlex Deucher u32 ip_instance, u32 ring, 177797b2e202SAlex Deucher struct amdgpu_ring **out_ring); 1778fad06127SSamuel Pitoiset void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes); 1779765e7fbfSChristian König void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 178097b2e202SAlex Deucher bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 17812f568dbdSChristian König int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 178297b2e202SAlex Deucher int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 178397b2e202SAlex Deucher uint32_t flags); 178497b2e202SAlex Deucher bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 1785cc325d19SChristian König struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 1786d7006964SChristian König bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1787d7006964SChristian König unsigned long end); 17882f568dbdSChristian König bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 17892f568dbdSChristian König int *last_invalidated); 179097b2e202SAlex Deucher bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 17916b777607SChunming Zhou uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 179297b2e202SAlex Deucher struct ttm_mem_reg *mem); 179397b2e202SAlex Deucher void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 179497b2e202SAlex Deucher void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 179597b2e202SAlex Deucher void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 17969f31a0b0SBaoyou Xie int amdgpu_ttm_init(struct amdgpu_device *adev); 17979f31a0b0SBaoyou Xie void amdgpu_ttm_fini(struct amdgpu_device *adev); 179897b2e202SAlex Deucher void amdgpu_program_register_sequence(struct amdgpu_device *adev, 179997b2e202SAlex Deucher const u32 *registers, 180097b2e202SAlex Deucher const u32 array_size); 180197b2e202SAlex Deucher 180297b2e202SAlex Deucher bool amdgpu_device_is_px(struct drm_device *dev); 180397b2e202SAlex Deucher /* atpx handler */ 180497b2e202SAlex Deucher #if defined(CONFIG_VGA_SWITCHEROO) 180597b2e202SAlex Deucher void amdgpu_register_atpx_handler(void); 180697b2e202SAlex Deucher void amdgpu_unregister_atpx_handler(void); 1807a78fe133SAlex Deucher bool amdgpu_has_atpx_dgpu_power_cntl(void); 18082f5af82eSAlex Deucher bool amdgpu_is_atpx_hybrid(void); 1809efc83cf4SAlex Deucher bool amdgpu_atpx_dgpu_req_power_for_displays(void); 181097b2e202SAlex Deucher #else 181197b2e202SAlex Deucher static inline void amdgpu_register_atpx_handler(void) {} 181297b2e202SAlex Deucher static inline void amdgpu_unregister_atpx_handler(void) {} 1813a78fe133SAlex Deucher static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 18142f5af82eSAlex Deucher static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1815efc83cf4SAlex Deucher static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 181697b2e202SAlex Deucher #endif 181797b2e202SAlex Deucher 181897b2e202SAlex Deucher /* 181997b2e202SAlex Deucher * KMS 182097b2e202SAlex Deucher */ 182197b2e202SAlex Deucher extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1822f498d9edSNils Wallménius extern const int amdgpu_max_kms_ioctl; 182397b2e202SAlex Deucher 182497b2e202SAlex Deucher int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 182511b3c20bSGabriel Krisman Bertazi void amdgpu_driver_unload_kms(struct drm_device *dev); 182697b2e202SAlex Deucher void amdgpu_driver_lastclose_kms(struct drm_device *dev); 182797b2e202SAlex Deucher int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 182897b2e202SAlex Deucher void amdgpu_driver_postclose_kms(struct drm_device *dev, 182997b2e202SAlex Deucher struct drm_file *file_priv); 1830faefba95SAlex Deucher int amdgpu_suspend(struct amdgpu_device *adev); 1831810ddc3aSAlex Deucher int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1832810ddc3aSAlex Deucher int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 183388e72717SThierry Reding u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 183488e72717SThierry Reding int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 183588e72717SThierry Reding void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 183688e72717SThierry Reding int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 183797b2e202SAlex Deucher int *max_error, 183897b2e202SAlex Deucher struct timeval *vblank_time, 183997b2e202SAlex Deucher unsigned flags); 184097b2e202SAlex Deucher long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 184197b2e202SAlex Deucher unsigned long arg); 184297b2e202SAlex Deucher 184397b2e202SAlex Deucher /* 184497b2e202SAlex Deucher * functions used by amdgpu_encoder.c 184597b2e202SAlex Deucher */ 184697b2e202SAlex Deucher struct amdgpu_afmt_acr { 184797b2e202SAlex Deucher u32 clock; 184897b2e202SAlex Deucher 184997b2e202SAlex Deucher int n_32khz; 185097b2e202SAlex Deucher int cts_32khz; 185197b2e202SAlex Deucher 185297b2e202SAlex Deucher int n_44_1khz; 185397b2e202SAlex Deucher int cts_44_1khz; 185497b2e202SAlex Deucher 185597b2e202SAlex Deucher int n_48khz; 185697b2e202SAlex Deucher int cts_48khz; 185797b2e202SAlex Deucher 185897b2e202SAlex Deucher }; 185997b2e202SAlex Deucher 186097b2e202SAlex Deucher struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 186197b2e202SAlex Deucher 186297b2e202SAlex Deucher /* amdgpu_acpi.c */ 186397b2e202SAlex Deucher #if defined(CONFIG_ACPI) 186497b2e202SAlex Deucher int amdgpu_acpi_init(struct amdgpu_device *adev); 186597b2e202SAlex Deucher void amdgpu_acpi_fini(struct amdgpu_device *adev); 186697b2e202SAlex Deucher bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 186797b2e202SAlex Deucher int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 186897b2e202SAlex Deucher u8 perf_req, bool advertise); 186997b2e202SAlex Deucher int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 187097b2e202SAlex Deucher #else 187197b2e202SAlex Deucher static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 187297b2e202SAlex Deucher static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 187397b2e202SAlex Deucher #endif 187497b2e202SAlex Deucher 187597b2e202SAlex Deucher struct amdgpu_bo_va_mapping * 187697b2e202SAlex Deucher amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 187797b2e202SAlex Deucher uint64_t addr, struct amdgpu_bo **bo); 1878c855e250SChristian König int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser); 187997b2e202SAlex Deucher 188097b2e202SAlex Deucher #include "amdgpu_object.h" 188197b2e202SAlex Deucher #endif 1882