197b2e202SAlex Deucher /* 297b2e202SAlex Deucher * Copyright 2008 Advanced Micro Devices, Inc. 397b2e202SAlex Deucher * Copyright 2008 Red Hat Inc. 497b2e202SAlex Deucher * Copyright 2009 Jerome Glisse. 597b2e202SAlex Deucher * 697b2e202SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 797b2e202SAlex Deucher * copy of this software and associated documentation files (the "Software"), 897b2e202SAlex Deucher * to deal in the Software without restriction, including without limitation 997b2e202SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1097b2e202SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1197b2e202SAlex Deucher * Software is furnished to do so, subject to the following conditions: 1297b2e202SAlex Deucher * 1397b2e202SAlex Deucher * The above copyright notice and this permission notice shall be included in 1497b2e202SAlex Deucher * all copies or substantial portions of the Software. 1597b2e202SAlex Deucher * 1697b2e202SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1797b2e202SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1897b2e202SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1997b2e202SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2097b2e202SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2197b2e202SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2297b2e202SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2397b2e202SAlex Deucher * 2497b2e202SAlex Deucher * Authors: Dave Airlie 2597b2e202SAlex Deucher * Alex Deucher 2697b2e202SAlex Deucher * Jerome Glisse 2797b2e202SAlex Deucher */ 2897b2e202SAlex Deucher #ifndef __AMDGPU_H__ 2997b2e202SAlex Deucher #define __AMDGPU_H__ 3097b2e202SAlex Deucher 31d57229b1SAurabindo Pillai #ifdef pr_fmt 32d57229b1SAurabindo Pillai #undef pr_fmt 33d57229b1SAurabindo Pillai #endif 34d57229b1SAurabindo Pillai 35d57229b1SAurabindo Pillai #define pr_fmt(fmt) "amdgpu: " fmt 36d57229b1SAurabindo Pillai 37539489fcSAurabindo Pillai #ifdef dev_fmt 38539489fcSAurabindo Pillai #undef dev_fmt 39539489fcSAurabindo Pillai #endif 40539489fcSAurabindo Pillai 41539489fcSAurabindo Pillai #define dev_fmt(fmt) "amdgpu: " fmt 42539489fcSAurabindo Pillai 438290268fSChristian König #include "amdgpu_ctx.h" 448290268fSChristian König 4597b2e202SAlex Deucher #include <linux/atomic.h> 4697b2e202SAlex Deucher #include <linux/wait.h> 4797b2e202SAlex Deucher #include <linux/list.h> 4897b2e202SAlex Deucher #include <linux/kref.h> 49a9f87f64SChristian König #include <linux/rbtree.h> 5097b2e202SAlex Deucher #include <linux/hashtable.h> 51f54d1867SChris Wilson #include <linux/dma-fence.h> 52c9a6b82fSAndrey Grodzovsky #include <linux/pci.h> 53c9a6b82fSAndrey Grodzovsky #include <linux/aer.h> 5497b2e202SAlex Deucher 55248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_bo_api.h> 56248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_bo_driver.h> 57248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_placement.h> 58248a1d6fSMasahiro Yamada #include <drm/ttm/ttm_execbuf_util.h> 5997b2e202SAlex Deucher 607e5a547fSChunming Zhou #include <drm/amdgpu_drm.h> 61f867723bSSam Ravnborg #include <drm/drm_gem.h> 62f867723bSSam Ravnborg #include <drm/drm_ioctl.h> 631b1f42d8SLucas Stach #include <drm/gpu_scheduler.h> 6497b2e202SAlex Deucher 6578c16834SAndres Rodriguez #include <kgd_kfd_interface.h> 66c79563a3SRex Zhu #include "dm_pp_interface.h" 67c79563a3SRex Zhu #include "kgd_pp_interface.h" 6878c16834SAndres Rodriguez 695fc3aeebSyanyang1 #include "amd_shared.h" 7097b2e202SAlex Deucher #include "amdgpu_mode.h" 7197b2e202SAlex Deucher #include "amdgpu_ih.h" 7297b2e202SAlex Deucher #include "amdgpu_irq.h" 7397b2e202SAlex Deucher #include "amdgpu_ucode.h" 74c632d799SFlora Cui #include "amdgpu_ttm.h" 750e5ca0d1SHuang Rui #include "amdgpu_psp.h" 7697b2e202SAlex Deucher #include "amdgpu_gds.h" 7756113504SChristian König #include "amdgpu_sync.h" 7878023016SChristian König #include "amdgpu_ring.h" 79073440d2SChristian König #include "amdgpu_vm.h" 80cf097881SAlex Deucher #include "amdgpu_dpm.h" 81a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h" 824df654d2SLeo Liu #include "amdgpu_uvd.h" 835e568178SLeo Liu #include "amdgpu_vce.h" 8495aa13f6SLeo Liu #include "amdgpu_vcn.h" 8588a1c40aSLeo Liu #include "amdgpu_jpeg.h" 869a189996SChristian König #include "amdgpu_mn.h" 87770d13b1SChristian König #include "amdgpu_gmc.h" 88448fe192SHuang Rui #include "amdgpu_gfx.h" 89bb7743bcSHuang Rui #include "amdgpu_sdma.h" 90bebc0762SHawking Zhang #include "amdgpu_nbio.h" 91455d40c9SLikun Gao #include "amdgpu_hdp.h" 924562236bSHarry Wentland #include "amdgpu_dm.h" 93ceeb50edSMonk Liu #include "amdgpu_virt.h" 947946340fSRex Zhu #include "amdgpu_csa.h" 953490bdb5SChristian König #include "amdgpu_gart.h" 9675758255SAlex Deucher #include "amdgpu_debugfs.h" 97050d9d43SChristian König #include "amdgpu_job.h" 984a8c21a1SChristian König #include "amdgpu_bo_list.h" 992cddc50eSHuang Rui #include "amdgpu_gem.h" 100cde577bdSOak Zeng #include "amdgpu_doorbell.h" 101611736d8SFelix Kuehling #include "amdgpu_amdkfd.h" 102f39f5bb1SXiaojie Yuan #include "amdgpu_discovery.h" 103a538bbe7SJack Xiao #include "amdgpu_mes.h" 1049e585a52SHawking Zhang #include "amdgpu_umc.h" 1053d093da0STao Zhou #include "amdgpu_mmhub.h" 1068ffff9b4SOak Zeng #include "amdgpu_gfxhub.h" 107bdf84a80SJoseph Greathouse #include "amdgpu_df.h" 108293f2563SHawking Zhang #include "amdgpu_smuio.h" 10987444254SRoy Sun #include "amdgpu_fdinfo.h" 1103907c492SJohn Clements #include "amdgpu_mca.h" 1117cab2124Syipechai #include "amdgpu_ras.h" 112c79563a3SRex Zhu 11362d73fbcSEvan Quan #define MAX_GPU_INSTANCE 16 11462d73fbcSEvan Quan 11562d73fbcSEvan Quan struct amdgpu_gpu_instance 11662d73fbcSEvan Quan { 11762d73fbcSEvan Quan struct amdgpu_device *adev; 11862d73fbcSEvan Quan int mgpu_fan_enabled; 11962d73fbcSEvan Quan }; 12062d73fbcSEvan Quan 12162d73fbcSEvan Quan struct amdgpu_mgpu_info 12262d73fbcSEvan Quan { 12362d73fbcSEvan Quan struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 12462d73fbcSEvan Quan struct mutex mutex; 12562d73fbcSEvan Quan uint32_t num_gpu; 12662d73fbcSEvan Quan uint32_t num_dgpu; 12762d73fbcSEvan Quan uint32_t num_apu; 128e3c1b071Sshaoyunl 129e3c1b071Sshaoyunl /* delayed reset_func for XGMI configuration if necessary */ 130e3c1b071Sshaoyunl struct delayed_work delayed_reset_work; 131e3c1b071Sshaoyunl bool pending_reset; 13262d73fbcSEvan Quan }; 13362d73fbcSEvan Quan 1343fa8f89dSSathishkumar S enum amdgpu_ss { 1353fa8f89dSSathishkumar S AMDGPU_SS_DRV_LOAD, 1363fa8f89dSSathishkumar S AMDGPU_SS_DEV_D0, 1373fa8f89dSSathishkumar S AMDGPU_SS_DEV_D3, 1383fa8f89dSSathishkumar S AMDGPU_SS_DRV_UNLOAD 1393fa8f89dSSathishkumar S }; 1403fa8f89dSSathishkumar S 14188f8575bSDennis Li struct amdgpu_watchdog_timer 14288f8575bSDennis Li { 14388f8575bSDennis Li bool timeout_fatal_disable; 14488f8575bSDennis Li uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 145b80d8475SAlex Deucher }; 14697b2e202SAlex Deucher 147f440ff44SWambui Karuga #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 14871f98027SAlex Deucher 14997b2e202SAlex Deucher /* 15097b2e202SAlex Deucher * Modules parameters. 15197b2e202SAlex Deucher */ 15297b2e202SAlex Deucher extern int amdgpu_modeset; 15397b2e202SAlex Deucher extern int amdgpu_vram_limit; 154218b5dcdSJohn Brooks extern int amdgpu_vis_vram_limit; 15583e74db6SAlex Deucher extern int amdgpu_gart_size; 15636d38372SChristian König extern int amdgpu_gtt_size; 15795844d20SMarek Olšák extern int amdgpu_moverate; 15897b2e202SAlex Deucher extern int amdgpu_audio; 15997b2e202SAlex Deucher extern int amdgpu_disp_priority; 16097b2e202SAlex Deucher extern int amdgpu_hw_i2c; 16197b2e202SAlex Deucher extern int amdgpu_pcie_gen2; 16297b2e202SAlex Deucher extern int amdgpu_msi; 163f440ff44SWambui Karuga extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 16497b2e202SAlex Deucher extern int amdgpu_dpm; 165e635ee07SHuang Rui extern int amdgpu_fw_load_type; 16697b2e202SAlex Deucher extern int amdgpu_aspm; 16797b2e202SAlex Deucher extern int amdgpu_runtime_pm; 1680b693f0bSRex Zhu extern uint amdgpu_ip_block_mask; 16997b2e202SAlex Deucher extern int amdgpu_bapm; 17097b2e202SAlex Deucher extern int amdgpu_deep_color; 17197b2e202SAlex Deucher extern int amdgpu_vm_size; 17297b2e202SAlex Deucher extern int amdgpu_vm_block_size; 173d07f14beSRoger He extern int amdgpu_vm_fragment_size; 174d9c13156SChristian König extern int amdgpu_vm_fault_stop; 175b495bd3aSChristian König extern int amdgpu_vm_debug; 1769a4b7d4cSHarish Kasiviswanathan extern int amdgpu_vm_update_mode; 1777e0ff20cSWambui Karuga extern int amdgpu_exp_hw_support; 1784562236bSHarry Wentland extern int amdgpu_dc; 1791333f723SJammy Zhou extern int amdgpu_sched_jobs; 1804afcb303SJammy Zhou extern int amdgpu_sched_hw_submission; 1810b693f0bSRex Zhu extern uint amdgpu_pcie_gen_cap; 1820b693f0bSRex Zhu extern uint amdgpu_pcie_lane_cap; 1830b693f0bSRex Zhu extern uint amdgpu_cg_mask; 1840b693f0bSRex Zhu extern uint amdgpu_pg_mask; 1850b693f0bSRex Zhu extern uint amdgpu_sdma_phase_quantum; 1866f8941a2SNicolai Hähnle extern char *amdgpu_disable_cu; 1879accf2fdSEmily Deng extern char *amdgpu_virtual_display; 1880b693f0bSRex Zhu extern uint amdgpu_pp_feature_mask; 189367039bfSTianci.Yin extern uint amdgpu_force_long_training; 19065781c78SMonk Liu extern int amdgpu_job_hang_limit; 191e8835e0eSHawking Zhang extern int amdgpu_lbpw; 1924a75aefeSAndres Rodriguez extern int amdgpu_compute_multipipe; 193dcebf026SAndrey Grodzovsky extern int amdgpu_gpu_recovery; 194bfca0289SShaoyun Liu extern int amdgpu_emu_mode; 1957951e376SRex Zhu extern uint amdgpu_smu_memory_pool_size; 1968738a82bSLijo Lazar extern int amdgpu_smu_pptable_id; 1977875a226SAlex Deucher extern uint amdgpu_dc_feature_mask; 1988a791dabSHarry Wentland extern uint amdgpu_dc_debug_mask; 199ad4de27fSNicholas Kazlauskas extern uint amdgpu_dm_abm_level; 2007a46f05eSTakashi Iwai extern int amdgpu_backlight; 20162d73fbcSEvan Quan extern struct amdgpu_mgpu_info mgpu_info; 2021218252fSxinhui pan extern int amdgpu_ras_enable; 2031218252fSxinhui pan extern uint amdgpu_ras_mask; 204acc0204cSGuchun Chen extern int amdgpu_bad_page_threshold; 20568daadf3SKent Russell extern bool amdgpu_ignore_bad_page_threshold; 20688f8575bSDennis Li extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 20751bcce46SHawking Zhang extern int amdgpu_async_gfx_ring; 208b239c017SJack Xiao extern int amdgpu_mcbp; 209a190d1c7SXiaojie Yuan extern int amdgpu_discovery; 21038487284SJack Xiao extern int amdgpu_mes; 21175ee6487SFelix Kuehling extern int amdgpu_noretry; 2124e66d7d2SYong Zhao extern int amdgpu_force_asic_type; 21330d95a37SSathishkumar S extern int amdgpu_smartshift_bias; 214*158a05a0SAlex Sierra extern int amdgpu_use_xgmi_p2p; 2158c9f69bcSShirish S #ifdef CONFIG_HSA_AMD 216aa978594SHuang Rui extern int sched_policy; 217b2057956SFelix Kuehling extern bool debug_evictions; 218b80f050fSPhilip Yang extern bool no_system_mem_limit; 219a35ad98bSShirish S #else 22002f40f82SLee Jones static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 22102f40f82SLee Jones static const bool __maybe_unused debug_evictions; /* = false */ 22202f40f82SLee Jones static const bool __maybe_unused no_system_mem_limit; 2238c9f69bcSShirish S #endif 22497b2e202SAlex Deucher 225d7ccb38dSHuang Rui extern int amdgpu_tmz; 226273da6ffSWenhui Sheng extern int amdgpu_reset_method; 227d7ccb38dSHuang Rui 2286dd13096SFelix Kuehling #ifdef CONFIG_DRM_AMDGPU_SI 2296dd13096SFelix Kuehling extern int amdgpu_si_support; 2306dd13096SFelix Kuehling #endif 2317df28986SFelix Kuehling #ifdef CONFIG_DRM_AMDGPU_CIK 2327df28986SFelix Kuehling extern int amdgpu_cik_support; 2337df28986SFelix Kuehling #endif 234a300de40SMonk Liu extern int amdgpu_num_kcq; 23597b2e202SAlex Deucher 23608d1bdd4SRex Zhu #define AMDGPU_VM_MAX_NUM_CTX 4096 2376c8d74caSSamuel Li #define AMDGPU_SG_THRESHOLD (256*1024*1024) 23855ed8cafSChunming Zhou #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 2394b559c90SChunming Zhou #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 24097b2e202SAlex Deucher #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 2418c5e13ecSAndrey Grodzovsky #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 24297b2e202SAlex Deucher #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 24397b2e202SAlex Deucher #define AMDGPUFB_CONN_LIMIT 4 244a5bde2f9SAlex Deucher #define AMDGPU_BIOS_NUM_SCRATCH 16 24597b2e202SAlex Deucher 24681b54fb7SAlex Deucher #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 24781b54fb7SAlex Deucher 24897b2e202SAlex Deucher /* hard reset data */ 24997b2e202SAlex Deucher #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 25097b2e202SAlex Deucher 25197b2e202SAlex Deucher /* reset flags */ 25297b2e202SAlex Deucher #define AMDGPU_RESET_GFX (1 << 0) 25397b2e202SAlex Deucher #define AMDGPU_RESET_COMPUTE (1 << 1) 25497b2e202SAlex Deucher #define AMDGPU_RESET_DMA (1 << 2) 25597b2e202SAlex Deucher #define AMDGPU_RESET_CP (1 << 3) 25697b2e202SAlex Deucher #define AMDGPU_RESET_GRBM (1 << 4) 25797b2e202SAlex Deucher #define AMDGPU_RESET_DMA1 (1 << 5) 25897b2e202SAlex Deucher #define AMDGPU_RESET_RLC (1 << 6) 25997b2e202SAlex Deucher #define AMDGPU_RESET_SEM (1 << 7) 26097b2e202SAlex Deucher #define AMDGPU_RESET_IH (1 << 8) 26197b2e202SAlex Deucher #define AMDGPU_RESET_VMC (1 << 9) 26297b2e202SAlex Deucher #define AMDGPU_RESET_MC (1 << 10) 26397b2e202SAlex Deucher #define AMDGPU_RESET_DISPLAY (1 << 11) 26497b2e202SAlex Deucher #define AMDGPU_RESET_UVD (1 << 12) 26597b2e202SAlex Deucher #define AMDGPU_RESET_VCE (1 << 13) 26697b2e202SAlex Deucher #define AMDGPU_RESET_VCE1 (1 << 14) 26797b2e202SAlex Deucher 26897b2e202SAlex Deucher /* max cursor sizes (in pixels) */ 26997b2e202SAlex Deucher #define CIK_CURSOR_WIDTH 128 27097b2e202SAlex Deucher #define CIK_CURSOR_HEIGHT 128 27197b2e202SAlex Deucher 27230d95a37SSathishkumar S /* smasrt shift bias level limits */ 27330d95a37SSathishkumar S #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 27430d95a37SSathishkumar S #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 27530d95a37SSathishkumar S 27697b2e202SAlex Deucher struct amdgpu_device; 27797b2e202SAlex Deucher struct amdgpu_ib; 27897b2e202SAlex Deucher struct amdgpu_cs_parser; 279bb977d37SChunming Zhou struct amdgpu_job; 28097b2e202SAlex Deucher struct amdgpu_irq_src; 2810b492a4cSAlex Deucher struct amdgpu_fpriv; 2829cca0b8eSChristian König struct amdgpu_bo_va_mapping; 283992af942SJonathan Kim struct kfd_vm_fault_info; 284d95e8e97SDennis Li struct amdgpu_hive_info; 28504442bf7SLijo Lazar struct amdgpu_reset_context; 286e071dce3SLijo Lazar struct amdgpu_reset_control; 28797b2e202SAlex Deucher 28897b2e202SAlex Deucher enum amdgpu_cp_irq { 28953b2fe41SHawking Zhang AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 29053b2fe41SHawking Zhang AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 29197b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 29297b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 29397b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 29497b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 29597b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 29697b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 29797b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 29897b2e202SAlex Deucher AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 29997b2e202SAlex Deucher 30097b2e202SAlex Deucher AMDGPU_CP_IRQ_LAST 30197b2e202SAlex Deucher }; 30297b2e202SAlex Deucher 30397b2e202SAlex Deucher enum amdgpu_thermal_irq { 30497b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 30597b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 30697b2e202SAlex Deucher 30797b2e202SAlex Deucher AMDGPU_THERMAL_IRQ_LAST 30897b2e202SAlex Deucher }; 30997b2e202SAlex Deucher 3104e638ae9SXiangliang Yu enum amdgpu_kiq_irq { 3114e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 3124e638ae9SXiangliang Yu AMDGPU_CP_KIQ_IRQ_LAST 3134e638ae9SXiangliang Yu }; 3144e638ae9SXiangliang Yu 3153890d111SEmily Deng #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 3163890d111SEmily Deng #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 317006cc1a2SJiawei Gu #define MAX_KIQ_REG_TRY 1000 3183890d111SEmily Deng 31943fa561fSRex Zhu int amdgpu_device_ip_set_clockgating_state(void *dev, 3205fc3aeebSyanyang1 enum amd_ip_block_type block_type, 3215fc3aeebSyanyang1 enum amd_clockgating_state state); 32243fa561fSRex Zhu int amdgpu_device_ip_set_powergating_state(void *dev, 3235fc3aeebSyanyang1 enum amd_ip_block_type block_type, 3245fc3aeebSyanyang1 enum amd_powergating_state state); 3252990a1fcSAlex Deucher void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 3262990a1fcSAlex Deucher u32 *flags); 3272990a1fcSAlex Deucher int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 3285dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 3292990a1fcSAlex Deucher bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 3305dbbb60bSAlex Deucher enum amd_ip_block_type block_type); 33197b2e202SAlex Deucher 332a1255107SAlex Deucher #define AMDGPU_MAX_IP_NUM 16 333a1255107SAlex Deucher 334a1255107SAlex Deucher struct amdgpu_ip_block_status { 335a1255107SAlex Deucher bool valid; 336a1255107SAlex Deucher bool sw; 337a1255107SAlex Deucher bool hw; 338a1255107SAlex Deucher bool late_initialized; 339a1255107SAlex Deucher bool hang; 340a1255107SAlex Deucher }; 341a1255107SAlex Deucher 34297b2e202SAlex Deucher struct amdgpu_ip_block_version { 343a1255107SAlex Deucher const enum amd_ip_block_type type; 344a1255107SAlex Deucher const u32 major; 345a1255107SAlex Deucher const u32 minor; 346a1255107SAlex Deucher const u32 rev; 3475fc3aeebSyanyang1 const struct amd_ip_funcs *funcs; 34897b2e202SAlex Deucher }; 34997b2e202SAlex Deucher 350efe4f000STianci.Yin #define HW_REV(_Major, _Minor, _Rev) \ 351efe4f000STianci.Yin ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 352efe4f000STianci.Yin 353a1255107SAlex Deucher struct amdgpu_ip_block { 354a1255107SAlex Deucher struct amdgpu_ip_block_status status; 355a1255107SAlex Deucher const struct amdgpu_ip_block_version *version; 356a1255107SAlex Deucher }; 357a1255107SAlex Deucher 3582990a1fcSAlex Deucher int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 3595fc3aeebSyanyang1 enum amd_ip_block_type type, 36097b2e202SAlex Deucher u32 major, u32 minor); 36197b2e202SAlex Deucher 3622990a1fcSAlex Deucher struct amdgpu_ip_block * 3632990a1fcSAlex Deucher amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 3645fc3aeebSyanyang1 enum amd_ip_block_type type); 36597b2e202SAlex Deucher 3662990a1fcSAlex Deucher int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 367a1255107SAlex Deucher const struct amdgpu_ip_block_version *ip_block_version); 368a1255107SAlex Deucher 36997b2e202SAlex Deucher /* 37097b2e202SAlex Deucher * BIOS. 37197b2e202SAlex Deucher */ 37297b2e202SAlex Deucher bool amdgpu_get_bios(struct amdgpu_device *adev); 37397b2e202SAlex Deucher bool amdgpu_read_bios(struct amdgpu_device *adev); 37404022982SHawking Zhang bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 37504022982SHawking Zhang u8 *bios, u32 length_bytes); 37697b2e202SAlex Deucher /* 37797b2e202SAlex Deucher * Clocks 37897b2e202SAlex Deucher */ 37997b2e202SAlex Deucher 38097b2e202SAlex Deucher #define AMDGPU_MAX_PPLL 3 38197b2e202SAlex Deucher 38297b2e202SAlex Deucher struct amdgpu_clock { 38397b2e202SAlex Deucher struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 38497b2e202SAlex Deucher struct amdgpu_pll spll; 38597b2e202SAlex Deucher struct amdgpu_pll mpll; 38697b2e202SAlex Deucher /* 10 Khz units */ 38797b2e202SAlex Deucher uint32_t default_mclk; 38897b2e202SAlex Deucher uint32_t default_sclk; 38997b2e202SAlex Deucher uint32_t default_dispclk; 39097b2e202SAlex Deucher uint32_t current_dispclk; 39197b2e202SAlex Deucher uint32_t dp_extclk; 39297b2e202SAlex Deucher uint32_t max_pixel_clock; 39397b2e202SAlex Deucher }; 39497b2e202SAlex Deucher 39597b2e202SAlex Deucher /* sub-allocation manager, it has to be protected by another lock. 39697b2e202SAlex Deucher * By conception this is an helper for other part of the driver 39797b2e202SAlex Deucher * like the indirect buffer or semaphore, which both have their 39897b2e202SAlex Deucher * locking. 39997b2e202SAlex Deucher * 40097b2e202SAlex Deucher * Principe is simple, we keep a list of sub allocation in offset 40197b2e202SAlex Deucher * order (first entry has offset == 0, last entry has the highest 40297b2e202SAlex Deucher * offset). 40397b2e202SAlex Deucher * 40497b2e202SAlex Deucher * When allocating new object we first check if there is room at 40597b2e202SAlex Deucher * the end total_size - (last_object_offset + last_object_size) >= 40697b2e202SAlex Deucher * alloc_size. If so we allocate new object there. 40797b2e202SAlex Deucher * 40897b2e202SAlex Deucher * When there is not enough room at the end, we start waiting for 40997b2e202SAlex Deucher * each sub object until we reach object_offset+object_size >= 41097b2e202SAlex Deucher * alloc_size, this object then become the sub object we return. 41197b2e202SAlex Deucher * 41297b2e202SAlex Deucher * Alignment can't be bigger than page size. 41397b2e202SAlex Deucher * 41497b2e202SAlex Deucher * Hole are not considered for allocation to keep things simple. 41597b2e202SAlex Deucher * Assumption is that there won't be hole (all object on same 41697b2e202SAlex Deucher * alignment). 41797b2e202SAlex Deucher */ 4186ba60b89SChristian König 4196ba60b89SChristian König #define AMDGPU_SA_NUM_FENCE_LISTS 32 4206ba60b89SChristian König 42197b2e202SAlex Deucher struct amdgpu_sa_manager { 42297b2e202SAlex Deucher wait_queue_head_t wq; 42397b2e202SAlex Deucher struct amdgpu_bo *bo; 42497b2e202SAlex Deucher struct list_head *hole; 4256ba60b89SChristian König struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 42697b2e202SAlex Deucher struct list_head olist; 42797b2e202SAlex Deucher unsigned size; 42897b2e202SAlex Deucher uint64_t gpu_addr; 42997b2e202SAlex Deucher void *cpu_ptr; 43097b2e202SAlex Deucher uint32_t domain; 43197b2e202SAlex Deucher uint32_t align; 43297b2e202SAlex Deucher }; 43397b2e202SAlex Deucher 43497b2e202SAlex Deucher /* sub-allocation buffer */ 43597b2e202SAlex Deucher struct amdgpu_sa_bo { 43697b2e202SAlex Deucher struct list_head olist; 43797b2e202SAlex Deucher struct list_head flist; 43897b2e202SAlex Deucher struct amdgpu_sa_manager *manager; 43997b2e202SAlex Deucher unsigned soffset; 44097b2e202SAlex Deucher unsigned eoffset; 441f54d1867SChris Wilson struct dma_fence *fence; 44297b2e202SAlex Deucher }; 44397b2e202SAlex Deucher 444d573de2dSRex Zhu int amdgpu_fence_slab_init(void); 445d573de2dSRex Zhu void amdgpu_fence_slab_fini(void); 44697b2e202SAlex Deucher 44797b2e202SAlex Deucher /* 44897b2e202SAlex Deucher * IRQS. 44997b2e202SAlex Deucher */ 45097b2e202SAlex Deucher 45197b2e202SAlex Deucher struct amdgpu_flip_work { 452325cbba1SMichel Dänzer struct delayed_work flip_work; 45397b2e202SAlex Deucher struct work_struct unpin_work; 45497b2e202SAlex Deucher struct amdgpu_device *adev; 45597b2e202SAlex Deucher int crtc_id; 456325cbba1SMichel Dänzer u32 target_vblank; 45797b2e202SAlex Deucher uint64_t base; 45897b2e202SAlex Deucher struct drm_pending_vblank_event *event; 459765e7fbfSChristian König struct amdgpu_bo *old_abo; 4601ffd2652SChristian König unsigned shared_count; 461f54d1867SChris Wilson struct dma_fence **shared; 462f54d1867SChris Wilson struct dma_fence_cb cb; 463cb9e59d7SAlex Deucher bool async; 46497b2e202SAlex Deucher }; 46597b2e202SAlex Deucher 46697b2e202SAlex Deucher 46797b2e202SAlex Deucher /* 46897b2e202SAlex Deucher * CP & rings. 46997b2e202SAlex Deucher */ 47097b2e202SAlex Deucher 47197b2e202SAlex Deucher struct amdgpu_ib { 47297b2e202SAlex Deucher struct amdgpu_sa_bo *sa_bo; 47397b2e202SAlex Deucher uint32_t length_dw; 47497b2e202SAlex Deucher uint64_t gpu_addr; 47597b2e202SAlex Deucher uint32_t *ptr; 476de807f81SJammy Zhou uint32_t flags; 47797b2e202SAlex Deucher }; 47897b2e202SAlex Deucher 4791b1f42d8SLucas Stach extern const struct drm_sched_backend_ops amdgpu_sched_ops; 480c1b69ed0SChunming Zhou 48197b2e202SAlex Deucher /* 48297b2e202SAlex Deucher * file private structure 48397b2e202SAlex Deucher */ 48497b2e202SAlex Deucher 48597b2e202SAlex Deucher struct amdgpu_fpriv { 48697b2e202SAlex Deucher struct amdgpu_vm vm; 487b85891bdSJunwei Zhang struct amdgpu_bo_va *prt_va; 4880f4b3c68SChristian König struct amdgpu_bo_va *csa_va; 48997b2e202SAlex Deucher struct mutex bo_list_lock; 49097b2e202SAlex Deucher struct idr bo_list_handles; 49197b2e202SAlex Deucher struct amdgpu_ctx_mgr ctx_mgr; 49297b2e202SAlex Deucher }; 49397b2e202SAlex Deucher 494021830d2SBas Nieuwenhuizen int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 495021830d2SBas Nieuwenhuizen 496b07c60c0SChristian König int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 497c8e42d57Sxinhui pan unsigned size, 498c8e42d57Sxinhui pan enum amdgpu_ib_pool_type pool, 499c8e42d57Sxinhui pan struct amdgpu_ib *ib); 5004d9c514dSChristian König void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 501f54d1867SChris Wilson struct dma_fence *f); 502b07c60c0SChristian König int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 50350ddc75eSJunwei Zhang struct amdgpu_ib *ibs, struct amdgpu_job *job, 50450ddc75eSJunwei Zhang struct dma_fence **f); 50597b2e202SAlex Deucher int amdgpu_ib_pool_init(struct amdgpu_device *adev); 50697b2e202SAlex Deucher void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 50797b2e202SAlex Deucher int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 50897b2e202SAlex Deucher 50997b2e202SAlex Deucher /* 51097b2e202SAlex Deucher * CS. 51197b2e202SAlex Deucher */ 51297b2e202SAlex Deucher struct amdgpu_cs_chunk { 51397b2e202SAlex Deucher uint32_t chunk_id; 51497b2e202SAlex Deucher uint32_t length_dw; 515758ac17fSChristian König void *kdata; 51697b2e202SAlex Deucher }; 51797b2e202SAlex Deucher 5182624dd15SChunming Zhou struct amdgpu_cs_post_dep { 5192624dd15SChunming Zhou struct drm_syncobj *syncobj; 5202624dd15SChunming Zhou struct dma_fence_chain *chain; 5212624dd15SChunming Zhou u64 point; 5222624dd15SChunming Zhou }; 5232624dd15SChunming Zhou 52497b2e202SAlex Deucher struct amdgpu_cs_parser { 52597b2e202SAlex Deucher struct amdgpu_device *adev; 52697b2e202SAlex Deucher struct drm_file *filp; 5273cb485f3SChristian König struct amdgpu_ctx *ctx; 528c3cca41eSChristian König 52997b2e202SAlex Deucher /* chunks */ 53097b2e202SAlex Deucher unsigned nchunks; 53197b2e202SAlex Deucher struct amdgpu_cs_chunk *chunks; 532c3cca41eSChristian König 53350838c8cSChristian König /* scheduler job object */ 53450838c8cSChristian König struct amdgpu_job *job; 5350d346a14SChristian König struct drm_sched_entity *entity; 536c3cca41eSChristian König 537c3cca41eSChristian König /* buffer objects */ 538c3cca41eSChristian König struct ww_acquire_ctx ticket; 539c3cca41eSChristian König struct amdgpu_bo_list *bo_list; 5403fe89771SChristian König struct amdgpu_mn *mn; 54156467ebfSChristian König struct amdgpu_bo_list_entry vm_pd; 54297b2e202SAlex Deucher struct list_head validated; 543f54d1867SChris Wilson struct dma_fence *fence; 544f69f90a1SChristian König uint64_t bytes_moved_threshold; 54500f06b24SJohn Brooks uint64_t bytes_moved_vis_threshold; 546f69f90a1SChristian König uint64_t bytes_moved; 54700f06b24SJohn Brooks uint64_t bytes_moved_vis; 54897b2e202SAlex Deucher 54997b2e202SAlex Deucher /* user fence */ 55091acbeb6SChristian König struct amdgpu_bo_list_entry uf_entry; 551660e8558SDave Airlie 5522624dd15SChunming Zhou unsigned num_post_deps; 5532624dd15SChunming Zhou struct amdgpu_cs_post_dep *post_deps; 55497b2e202SAlex Deucher }; 55597b2e202SAlex Deucher 5567270f839SChristian König static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 5577270f839SChristian König uint32_t ib_idx, int idx) 55897b2e202SAlex Deucher { 55950838c8cSChristian König return p->job->ibs[ib_idx].ptr[idx]; 56097b2e202SAlex Deucher } 56197b2e202SAlex Deucher 5627270f839SChristian König static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 5637270f839SChristian König uint32_t ib_idx, int idx, 5647270f839SChristian König uint32_t value) 5657270f839SChristian König { 56650838c8cSChristian König p->job->ibs[ib_idx].ptr[idx] = value; 5677270f839SChristian König } 5687270f839SChristian König 56997b2e202SAlex Deucher /* 57097b2e202SAlex Deucher * Writeback 57197b2e202SAlex Deucher */ 57254208194SYintian Tao #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 57397b2e202SAlex Deucher 57497b2e202SAlex Deucher struct amdgpu_wb { 57597b2e202SAlex Deucher struct amdgpu_bo *wb_obj; 57697b2e202SAlex Deucher volatile uint32_t *wb; 57797b2e202SAlex Deucher uint64_t gpu_addr; 57897b2e202SAlex Deucher u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 57997b2e202SAlex Deucher unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 58097b2e202SAlex Deucher }; 58197b2e202SAlex Deucher 582131b4b36SAlex Deucher int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 583131b4b36SAlex Deucher void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 58497b2e202SAlex Deucher 58597b2e202SAlex Deucher /* 58697b2e202SAlex Deucher * Benchmarking 58797b2e202SAlex Deucher */ 588e460f244SAlex Deucher int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 58997b2e202SAlex Deucher 59097b2e202SAlex Deucher /* 59197b2e202SAlex Deucher * ASIC specific register table accessible by UMD 59297b2e202SAlex Deucher */ 59397b2e202SAlex Deucher struct amdgpu_allowed_register_entry { 59497b2e202SAlex Deucher uint32_t reg_offset; 59597b2e202SAlex Deucher bool grbm_indexed; 59697b2e202SAlex Deucher }; 59797b2e202SAlex Deucher 5980cf3c64fSAlex Deucher enum amd_reset_method { 599e071dce3SLijo Lazar AMD_RESET_METHOD_NONE = -1, 6000cf3c64fSAlex Deucher AMD_RESET_METHOD_LEGACY = 0, 6010cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE0, 6020cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE1, 6030cf3c64fSAlex Deucher AMD_RESET_METHOD_MODE2, 604af484df8SAlex Deucher AMD_RESET_METHOD_BACO, 605af484df8SAlex Deucher AMD_RESET_METHOD_PCI, 6060cf3c64fSAlex Deucher }; 6070cf3c64fSAlex Deucher 6089269bf18SAlex Deucher struct amdgpu_video_codec_info { 6099269bf18SAlex Deucher u32 codec_type; 6109269bf18SAlex Deucher u32 max_width; 6119269bf18SAlex Deucher u32 max_height; 6129269bf18SAlex Deucher u32 max_pixels_per_frame; 6139269bf18SAlex Deucher u32 max_level; 6149269bf18SAlex Deucher }; 6159269bf18SAlex Deucher 6169075096bSVeerabadhran Gopalakrishnan #define codec_info_build(type, width, height, level) \ 6179075096bSVeerabadhran Gopalakrishnan .codec_type = type,\ 6189075096bSVeerabadhran Gopalakrishnan .max_width = width,\ 6199075096bSVeerabadhran Gopalakrishnan .max_height = height,\ 6209075096bSVeerabadhran Gopalakrishnan .max_pixels_per_frame = height * width,\ 6219075096bSVeerabadhran Gopalakrishnan .max_level = level, 6229075096bSVeerabadhran Gopalakrishnan 6239269bf18SAlex Deucher struct amdgpu_video_codecs { 6249269bf18SAlex Deucher const u32 codec_count; 6259269bf18SAlex Deucher const struct amdgpu_video_codec_info *codec_array; 6269269bf18SAlex Deucher }; 6279269bf18SAlex Deucher 62897b2e202SAlex Deucher /* 62997b2e202SAlex Deucher * ASIC specific functions. 63097b2e202SAlex Deucher */ 63197b2e202SAlex Deucher struct amdgpu_asic_funcs { 63297b2e202SAlex Deucher bool (*read_disabled_bios)(struct amdgpu_device *adev); 6337946b878SAlex Deucher bool (*read_bios_from_rom)(struct amdgpu_device *adev, 6347946b878SAlex Deucher u8 *bios, u32 length_bytes); 63597b2e202SAlex Deucher int (*read_register)(struct amdgpu_device *adev, u32 se_num, 63697b2e202SAlex Deucher u32 sh_num, u32 reg_offset, u32 *value); 63797b2e202SAlex Deucher void (*set_vga_state)(struct amdgpu_device *adev, bool state); 63897b2e202SAlex Deucher int (*reset)(struct amdgpu_device *adev); 6390cf3c64fSAlex Deucher enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 64097b2e202SAlex Deucher /* get the reference clock */ 64197b2e202SAlex Deucher u32 (*get_xclk)(struct amdgpu_device *adev); 64297b2e202SAlex Deucher /* MM block clocks */ 64397b2e202SAlex Deucher int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 64497b2e202SAlex Deucher int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 645841686dfSMaruthi Bayyavarapu /* static power management */ 646841686dfSMaruthi Bayyavarapu int (*get_pcie_lanes)(struct amdgpu_device *adev); 647841686dfSMaruthi Bayyavarapu void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 648bbf282d8SAlex Deucher /* get config memsize register */ 649bbf282d8SAlex Deucher u32 (*get_config_memsize)(struct amdgpu_device *adev); 6502df1b8b6SAlex Deucher /* flush hdp write queue */ 65169882565SChristian König void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 6522df1b8b6SAlex Deucher /* invalidate hdp read cache */ 65369882565SChristian König void (*invalidate_hdp)(struct amdgpu_device *adev, 65469882565SChristian König struct amdgpu_ring *ring); 65569070690SAlex Deucher /* check if the asic needs a full reset of if soft reset will work */ 65669070690SAlex Deucher bool (*need_full_reset)(struct amdgpu_device *adev); 6575253163aSOak Zeng /* initialize doorbell layout for specific asic*/ 6585253163aSOak Zeng void (*init_doorbell_index)(struct amdgpu_device *adev); 659b45e18acSKent Russell /* PCIe bandwidth usage */ 660b45e18acSKent Russell void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 661b45e18acSKent Russell uint64_t *count1); 66244401889SAlex Deucher /* do we need to reset the asic at init time (e.g., kexec) */ 66344401889SAlex Deucher bool (*need_reset_on_init)(struct amdgpu_device *adev); 664dcea6e65SKent Russell /* PCIe replay counter */ 665dcea6e65SKent Russell uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 66669d5436dSAlex Deucher /* device supports BACO */ 66769d5436dSAlex Deucher bool (*supports_baco)(struct amdgpu_device *adev); 6689737a923SAlex Deucher /* pre asic_init quirks */ 6699737a923SAlex Deucher void (*pre_asic_init)(struct amdgpu_device *adev); 670f2b75bc2SEvan Quan /* enter/exit umd stable pstate */ 671f2b75bc2SEvan Quan int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 6729269bf18SAlex Deucher /* query video codecs */ 6739269bf18SAlex Deucher int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 6749269bf18SAlex Deucher const struct amdgpu_video_codecs **codecs); 67597b2e202SAlex Deucher }; 67697b2e202SAlex Deucher 67797b2e202SAlex Deucher /* 67897b2e202SAlex Deucher * IOCTL. 67997b2e202SAlex Deucher */ 68097b2e202SAlex Deucher int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 68197b2e202SAlex Deucher struct drm_file *filp); 68297b2e202SAlex Deucher 68397b2e202SAlex Deucher int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 6847ca24cf2SMarek Olšák int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 6857ca24cf2SMarek Olšák struct drm_file *filp); 68697b2e202SAlex Deucher int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 687eef18a82SJunwei Zhang int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 688eef18a82SJunwei Zhang struct drm_file *filp); 68997b2e202SAlex Deucher 69097b2e202SAlex Deucher /* VRAM scratch page for HDP bug, default vram page */ 69197b2e202SAlex Deucher struct amdgpu_vram_scratch { 69297b2e202SAlex Deucher struct amdgpu_bo *robj; 69397b2e202SAlex Deucher volatile uint32_t *ptr; 69497b2e202SAlex Deucher u64 gpu_addr; 69597b2e202SAlex Deucher }; 69697b2e202SAlex Deucher 69797b2e202SAlex Deucher /* 698d03846afSChunming Zhou * CGS 699d03846afSChunming Zhou */ 700110e6f26SDave Airlie struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 701110e6f26SDave Airlie void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 702a8fe58ceSMaruthi Bayyavarapu 703a8fe58ceSMaruthi Bayyavarapu /* 70497b2e202SAlex Deucher * Core structure, functions and helpers. 70597b2e202SAlex Deucher */ 70697b2e202SAlex Deucher typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 70797b2e202SAlex Deucher typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 70897b2e202SAlex Deucher 7094fa1c6a6STao Zhou typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 7104fa1c6a6STao Zhou typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 7114fa1c6a6STao Zhou 71297b2e202SAlex Deucher typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 71397b2e202SAlex Deucher typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 71497b2e202SAlex Deucher 71588807dc8SOak Zeng struct amdgpu_mmio_remap { 71688807dc8SOak Zeng u32 reg_offset; 71788807dc8SOak Zeng resource_size_t bus_addr; 71888807dc8SOak Zeng }; 71988807dc8SOak Zeng 7204522824cSShaoyun Liu /* Define the HW IP blocks will be used in driver , add more if necessary */ 7214522824cSShaoyun Liu enum amd_hw_ip_block_type { 7224522824cSShaoyun Liu GC_HWIP = 1, 7234522824cSShaoyun Liu HDP_HWIP, 7244522824cSShaoyun Liu SDMA0_HWIP, 7254522824cSShaoyun Liu SDMA1_HWIP, 726fa5d2e6fSLe Ma SDMA2_HWIP, 727fa5d2e6fSLe Ma SDMA3_HWIP, 728fa5d2e6fSLe Ma SDMA4_HWIP, 729fa5d2e6fSLe Ma SDMA5_HWIP, 730fa5d2e6fSLe Ma SDMA6_HWIP, 731fa5d2e6fSLe Ma SDMA7_HWIP, 7324522824cSShaoyun Liu MMHUB_HWIP, 7334522824cSShaoyun Liu ATHUB_HWIP, 7344522824cSShaoyun Liu NBIO_HWIP, 7354522824cSShaoyun Liu MP0_HWIP, 736e6636ae1SEvan Quan MP1_HWIP, 7374522824cSShaoyun Liu UVD_HWIP, 7384522824cSShaoyun Liu VCN_HWIP = UVD_HWIP, 73988a1c40aSLeo Liu JPEG_HWIP = VCN_HWIP, 7405eceb201SAlex Deucher VCN1_HWIP, 7414522824cSShaoyun Liu VCE_HWIP, 7424522824cSShaoyun Liu DF_HWIP, 7434522824cSShaoyun Liu DCE_HWIP, 7444522824cSShaoyun Liu OSSSYS_HWIP, 7454522824cSShaoyun Liu SMUIO_HWIP, 7464522824cSShaoyun Liu PWR_HWIP, 7474522824cSShaoyun Liu NBIF_HWIP, 748e6636ae1SEvan Quan THM_HWIP, 74973b19174SRex Zhu CLK_HWIP, 7506501a771SHawking Zhang UMC_HWIP, 7516501a771SHawking Zhang RSMU_HWIP, 7521534db55SAlex Deucher XGMI_HWIP, 7535f931489SAlex Deucher DCI_HWIP, 7544522824cSShaoyun Liu MAX_HWIP 7554522824cSShaoyun Liu }; 7564522824cSShaoyun Liu 75767a44e65SErnst Sjöstrand #define HWIP_MAX_INSTANCE 10 7584522824cSShaoyun Liu 7595f52e9a7SAlex Deucher #define HW_ID_MAX 300 7605f52e9a7SAlex Deucher #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 7615f52e9a7SAlex Deucher 76211dc9364SRex Zhu struct amd_powerplay { 76311dc9364SRex Zhu void *pp_handle; 76411dc9364SRex Zhu const struct amd_pm_funcs *pp_funcs; 76511dc9364SRex Zhu }; 76611dc9364SRex Zhu 767a6c40b17SLuben Tuikov struct ip_discovery_top; 768a6c40b17SLuben Tuikov 76973275181SEvan Quan /* polaris10 kickers */ 77073275181SEvan Quan #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 77173275181SEvan Quan ((rid == 0xE3) || \ 77273275181SEvan Quan (rid == 0xE4) || \ 77373275181SEvan Quan (rid == 0xE5) || \ 77473275181SEvan Quan (rid == 0xE7) || \ 77573275181SEvan Quan (rid == 0xEF))) || \ 77673275181SEvan Quan ((did == 0x6FDF) && \ 77773275181SEvan Quan ((rid == 0xE7) || \ 77873275181SEvan Quan (rid == 0xEF) || \ 77973275181SEvan Quan (rid == 0xFF)))) 78073275181SEvan Quan 78173275181SEvan Quan #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 78273275181SEvan Quan ((rid == 0xE1) || \ 78373275181SEvan Quan (rid == 0xF7))) 78473275181SEvan Quan 78573275181SEvan Quan /* polaris11 kickers */ 78673275181SEvan Quan #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 78773275181SEvan Quan ((rid == 0xE0) || \ 78873275181SEvan Quan (rid == 0xE5))) || \ 78973275181SEvan Quan ((did == 0x67FF) && \ 79073275181SEvan Quan ((rid == 0xCF) || \ 79173275181SEvan Quan (rid == 0xEF) || \ 79273275181SEvan Quan (rid == 0xFF)))) 79373275181SEvan Quan 79473275181SEvan Quan #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 79573275181SEvan Quan ((rid == 0xE2))) 79673275181SEvan Quan 79773275181SEvan Quan /* polaris12 kickers */ 79873275181SEvan Quan #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 79973275181SEvan Quan ((rid == 0xC0) || \ 80073275181SEvan Quan (rid == 0xC1) || \ 80173275181SEvan Quan (rid == 0xC3) || \ 80273275181SEvan Quan (rid == 0xC7))) || \ 80373275181SEvan Quan ((did == 0x6981) && \ 80473275181SEvan Quan ((rid == 0x00) || \ 80573275181SEvan Quan (rid == 0x01) || \ 80673275181SEvan Quan (rid == 0x10)))) 80773275181SEvan Quan 8080c49e0b8SChunming Zhou #define AMDGPU_RESET_MAGIC_NUM 64 809e4cf4bf5SJonathan Kim #define AMDGPU_MAX_DF_PERFMONS 4 8106c92fe5fSKent Russell #define AMDGPU_PRODUCT_NAME_LEN 64 81197b2e202SAlex Deucher struct amdgpu_device { 81297b2e202SAlex Deucher struct device *dev; 81397b2e202SAlex Deucher struct pci_dev *pdev; 8148aba21b7SLuben Tuikov struct drm_device ddev; 81597b2e202SAlex Deucher 816a8fe58ceSMaruthi Bayyavarapu #ifdef CONFIG_DRM_AMD_ACP 817a8fe58ceSMaruthi Bayyavarapu struct amdgpu_acp acp; 818a8fe58ceSMaruthi Bayyavarapu #endif 819d95e8e97SDennis Li struct amdgpu_hive_info *hive; 82097b2e202SAlex Deucher /* ASIC */ 8212f7d10b3SJammy Zhou enum amd_asic_type asic_type; 82297b2e202SAlex Deucher uint32_t family; 82397b2e202SAlex Deucher uint32_t rev_id; 82497b2e202SAlex Deucher uint32_t external_rev_id; 82597b2e202SAlex Deucher unsigned long flags; 82654f78a76SAlex Deucher unsigned long apu_flags; 82797b2e202SAlex Deucher int usec_timeout; 82897b2e202SAlex Deucher const struct amdgpu_asic_funcs *asic_funcs; 82997b2e202SAlex Deucher bool shutdown; 830fd5fd480SChunming Zhou bool need_swiotlb; 83197b2e202SAlex Deucher bool accel_working; 83297b2e202SAlex Deucher struct notifier_block acpi_nb; 83397b2e202SAlex Deucher struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 83498d28ac2SNirmoy Das struct debugfs_blob_wrapper debugfs_vbios_blob; 83581d1bf01SAlex Deucher struct debugfs_blob_wrapper debugfs_discovery_blob; 83697b2e202SAlex Deucher struct mutex srbm_mutex; 83797b2e202SAlex Deucher /* GRBM index mutex. Protects concurrent access to GRBM index */ 83897b2e202SAlex Deucher struct mutex grbm_idx_mutex; 83997b2e202SAlex Deucher struct dev_pm_domain vga_pm_domain; 84097b2e202SAlex Deucher bool have_disp_power_ref; 841bae17d2aSJack Xiao bool have_atomics_support; 84297b2e202SAlex Deucher 84397b2e202SAlex Deucher /* BIOS */ 8440cdd5005SAlex Deucher bool is_atom_fw; 84597b2e202SAlex Deucher uint8_t *bios; 846a9f5db9cSEvan Quan uint32_t bios_size; 847a5bde2f9SAlex Deucher uint32_t bios_scratch_reg_offset; 84897b2e202SAlex Deucher uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 84997b2e202SAlex Deucher 85097b2e202SAlex Deucher /* Register/doorbell mmio */ 85197b2e202SAlex Deucher resource_size_t rmmio_base; 85297b2e202SAlex Deucher resource_size_t rmmio_size; 85397b2e202SAlex Deucher void __iomem *rmmio; 85497b2e202SAlex Deucher /* protects concurrent MM_INDEX/DATA based register access */ 85597b2e202SAlex Deucher spinlock_t mmio_idx_lock; 85688807dc8SOak Zeng struct amdgpu_mmio_remap rmmio_remap; 85797b2e202SAlex Deucher /* protects concurrent SMC based register access */ 85897b2e202SAlex Deucher spinlock_t smc_idx_lock; 85997b2e202SAlex Deucher amdgpu_rreg_t smc_rreg; 86097b2e202SAlex Deucher amdgpu_wreg_t smc_wreg; 86197b2e202SAlex Deucher /* protects concurrent PCIE register access */ 86297b2e202SAlex Deucher spinlock_t pcie_idx_lock; 86397b2e202SAlex Deucher amdgpu_rreg_t pcie_rreg; 86497b2e202SAlex Deucher amdgpu_wreg_t pcie_wreg; 86536b9a952SHuang Rui amdgpu_rreg_t pciep_rreg; 86636b9a952SHuang Rui amdgpu_wreg_t pciep_wreg; 8674fa1c6a6STao Zhou amdgpu_rreg64_t pcie_rreg64; 8684fa1c6a6STao Zhou amdgpu_wreg64_t pcie_wreg64; 86997b2e202SAlex Deucher /* protects concurrent UVD register access */ 87097b2e202SAlex Deucher spinlock_t uvd_ctx_idx_lock; 87197b2e202SAlex Deucher amdgpu_rreg_t uvd_ctx_rreg; 87297b2e202SAlex Deucher amdgpu_wreg_t uvd_ctx_wreg; 87397b2e202SAlex Deucher /* protects concurrent DIDT register access */ 87497b2e202SAlex Deucher spinlock_t didt_idx_lock; 87597b2e202SAlex Deucher amdgpu_rreg_t didt_rreg; 87697b2e202SAlex Deucher amdgpu_wreg_t didt_wreg; 877ccdbb20aSRex Zhu /* protects concurrent gc_cac register access */ 878ccdbb20aSRex Zhu spinlock_t gc_cac_idx_lock; 879ccdbb20aSRex Zhu amdgpu_rreg_t gc_cac_rreg; 880ccdbb20aSRex Zhu amdgpu_wreg_t gc_cac_wreg; 88116abb5d2SEvan Quan /* protects concurrent se_cac register access */ 88216abb5d2SEvan Quan spinlock_t se_cac_idx_lock; 88316abb5d2SEvan Quan amdgpu_rreg_t se_cac_rreg; 88416abb5d2SEvan Quan amdgpu_wreg_t se_cac_wreg; 88597b2e202SAlex Deucher /* protects concurrent ENDPOINT (audio) register access */ 88697b2e202SAlex Deucher spinlock_t audio_endpt_idx_lock; 88797b2e202SAlex Deucher amdgpu_block_rreg_t audio_endpt_rreg; 88897b2e202SAlex Deucher amdgpu_block_wreg_t audio_endpt_wreg; 88997b2e202SAlex Deucher struct amdgpu_doorbell doorbell; 89097b2e202SAlex Deucher 89197b2e202SAlex Deucher /* clock/pll info */ 89297b2e202SAlex Deucher struct amdgpu_clock clock; 89397b2e202SAlex Deucher 89497b2e202SAlex Deucher /* MC */ 895770d13b1SChristian König struct amdgpu_gmc gmc; 89697b2e202SAlex Deucher struct amdgpu_gart gart; 89792e71b06SChristian König dma_addr_t dummy_page_addr; 89897b2e202SAlex Deucher struct amdgpu_vm_manager vm_manager; 899e60f8db5SAlex Xie struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 9001daa2bfaSLe Ma unsigned num_vmhubs; 90197b2e202SAlex Deucher 90297b2e202SAlex Deucher /* memory management */ 90397b2e202SAlex Deucher struct amdgpu_mman mman; 90497b2e202SAlex Deucher struct amdgpu_vram_scratch vram_scratch; 90597b2e202SAlex Deucher struct amdgpu_wb wb; 90697b2e202SAlex Deucher atomic64_t num_bytes_moved; 907dbd5ed60SChristian König atomic64_t num_evictions; 90868e2c5ffSMarek Olšák atomic64_t num_vram_cpu_page_faults; 909d94aed5aSMarek Olšák atomic_t gpu_reset_counter; 910f1892138SChunming Zhou atomic_t vram_lost_counter; 91197b2e202SAlex Deucher 91295844d20SMarek Olšák /* data for buffer migration throttling */ 91395844d20SMarek Olšák struct { 91495844d20SMarek Olšák spinlock_t lock; 91595844d20SMarek Olšák s64 last_update_us; 91695844d20SMarek Olšák s64 accum_us; /* accumulated microseconds */ 91700f06b24SJohn Brooks s64 accum_us_vis; /* for visible VRAM */ 91895844d20SMarek Olšák u32 log2_max_MBps; 91995844d20SMarek Olšák } mm_stats; 92095844d20SMarek Olšák 92197b2e202SAlex Deucher /* display */ 9229accf2fdSEmily Deng bool enable_virtual_display; 92384ec374bSRyan Taylor struct amdgpu_vkms_output *amdgpu_vkms_output; 92497b2e202SAlex Deucher struct amdgpu_mode_info mode_info; 9254562236bSHarry Wentland /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 92697b2e202SAlex Deucher struct work_struct hotplug_work; 92797b2e202SAlex Deucher struct amdgpu_irq_src crtc_irq; 92811f1a553SWayne Lin struct amdgpu_irq_src vline0_irq; 929d2574c33SMario Kleiner struct amdgpu_irq_src vupdate_irq; 93097b2e202SAlex Deucher struct amdgpu_irq_src pageflip_irq; 93197b2e202SAlex Deucher struct amdgpu_irq_src hpd_irq; 932c79fe9b4SLeo (Hanghong) Ma struct amdgpu_irq_src dmub_trace_irq; 933f066af88SJude Shih struct amdgpu_irq_src dmub_outbox_irq; 93497b2e202SAlex Deucher 93597b2e202SAlex Deucher /* rings */ 93676bf0db5SChristian König u64 fence_context; 93797b2e202SAlex Deucher unsigned num_rings; 93897b2e202SAlex Deucher struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 93997b2e202SAlex Deucher bool ib_pool_ready; 9409ecefb19SChristian König struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 9411c6d567bSNirmoy Das struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 94297b2e202SAlex Deucher 94397b2e202SAlex Deucher /* interrupts */ 94497b2e202SAlex Deucher struct amdgpu_irq irq; 94597b2e202SAlex Deucher 9461f7371b2SAlex Deucher /* powerplay */ 9471f7371b2SAlex Deucher struct amd_powerplay powerplay; 94897b2e202SAlex Deucher struct amdgpu_pm pm; 94997b2e202SAlex Deucher u32 cg_flags; 95097b2e202SAlex Deucher u32 pg_flags; 95197b2e202SAlex Deucher 952bebc0762SHawking Zhang /* nbio */ 953bebc0762SHawking Zhang struct amdgpu_nbio nbio; 954bebc0762SHawking Zhang 955b291a387SHawking Zhang /* hdp */ 956b291a387SHawking Zhang struct amdgpu_hdp hdp; 957b291a387SHawking Zhang 958293f2563SHawking Zhang /* smuio */ 959293f2563SHawking Zhang struct amdgpu_smuio smuio; 960293f2563SHawking Zhang 961d3a5a121STao Zhou /* mmhub */ 962d3a5a121STao Zhou struct amdgpu_mmhub mmhub; 963d3a5a121STao Zhou 9648ffff9b4SOak Zeng /* gfxhub */ 9658ffff9b4SOak Zeng struct amdgpu_gfxhub gfxhub; 9668ffff9b4SOak Zeng 96797b2e202SAlex Deucher /* gfx */ 96897b2e202SAlex Deucher struct amdgpu_gfx gfx; 96997b2e202SAlex Deucher 97097b2e202SAlex Deucher /* sdma */ 971c113ea1cSAlex Deucher struct amdgpu_sdma sdma; 97297b2e202SAlex Deucher 97397b2e202SAlex Deucher /* uvd */ 97497b2e202SAlex Deucher struct amdgpu_uvd uvd; 97597b2e202SAlex Deucher 97697b2e202SAlex Deucher /* vce */ 97797b2e202SAlex Deucher struct amdgpu_vce vce; 97895d0906fSLeo Liu 97995d0906fSLeo Liu /* vcn */ 98095d0906fSLeo Liu struct amdgpu_vcn vcn; 98197b2e202SAlex Deucher 98288a1c40aSLeo Liu /* jpeg */ 98388a1c40aSLeo Liu struct amdgpu_jpeg jpeg; 98488a1c40aSLeo Liu 98597b2e202SAlex Deucher /* firmwares */ 98697b2e202SAlex Deucher struct amdgpu_firmware firmware; 98797b2e202SAlex Deucher 9880e5ca0d1SHuang Rui /* PSP */ 9890e5ca0d1SHuang Rui struct psp_context psp; 9900e5ca0d1SHuang Rui 99197b2e202SAlex Deucher /* GDS */ 99297b2e202SAlex Deucher struct amdgpu_gds gds; 99397b2e202SAlex Deucher 994611736d8SFelix Kuehling /* KFD */ 995611736d8SFelix Kuehling struct amdgpu_kfd_dev kfd; 996611736d8SFelix Kuehling 997045c0216STao Zhou /* UMC */ 998045c0216STao Zhou struct amdgpu_umc umc; 999045c0216STao Zhou 10004562236bSHarry Wentland /* display related functionality */ 10014562236bSHarry Wentland struct amdgpu_display_manager dm; 10024562236bSHarry Wentland 1003a538bbe7SJack Xiao /* mes */ 1004a538bbe7SJack Xiao bool enable_mes; 1005a538bbe7SJack Xiao struct amdgpu_mes mes; 1006a538bbe7SJack Xiao 1007bdf84a80SJoseph Greathouse /* df */ 1008bdf84a80SJoseph Greathouse struct amdgpu_df df; 1009bdf84a80SJoseph Greathouse 10103907c492SJohn Clements /* MCA */ 10113907c492SJohn Clements struct amdgpu_mca mca; 10123907c492SJohn Clements 1013a1255107SAlex Deucher struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 101483a0b863SLikun GAO uint32_t harvest_ip_mask; 101597b2e202SAlex Deucher int num_ip_blocks; 101697b2e202SAlex Deucher struct mutex mn_lock; 101797b2e202SAlex Deucher DECLARE_HASHTABLE(mn_hash, 7); 101897b2e202SAlex Deucher 101997b2e202SAlex Deucher /* tracking pinned memory */ 1020a5ccfe5cSMichel Dänzer atomic64_t vram_pin_size; 1021a5ccfe5cSMichel Dänzer atomic64_t visible_pin_size; 1022a5ccfe5cSMichel Dänzer atomic64_t gart_pin_size; 1023130e0371SOded Gabbay 10244522824cSShaoyun Liu /* soc15 register offset based on ip, instance and segment */ 10254522824cSShaoyun Liu uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 10264522824cSShaoyun Liu 10272dc80b00SShirish S /* delayed work_func for deferring clockgating during resume */ 1028beff74bcSAlex Deucher struct delayed_work delayed_init_work; 10292dc80b00SShirish S 10305a5099cbSXiangliang Yu struct amdgpu_virt virt; 10310c4e7fa5SChunming Zhou 10320c4e7fa5SChunming Zhou /* link all shadow bo */ 10330c4e7fa5SChunming Zhou struct list_head shadow_list; 10340c4e7fa5SChunming Zhou struct mutex shadow_list_lock; 10355c1354bdSChunming Zhou 1036c836fec5SJim Qu /* record hw reset is performed */ 1037c836fec5SJim Qu bool has_hw_reset; 10380c49e0b8SChunming Zhou u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1039c836fec5SJim Qu 104044779b43SRex Zhu /* s3/s4 mask */ 104144779b43SRex Zhu bool in_suspend; 104262498733SAlex Deucher bool in_s3; 104362498733SAlex Deucher bool in_s4; 104462498733SAlex Deucher bool in_s0ix; 1045b092b196SPrike Liang 104653b3f8f4SDennis Li atomic_t in_gpu_reset; 1047a3a09142SAlex Deucher enum pp_mp1_state mp1_state; 10486049db43SDennis Li struct rw_semaphore reset_sem; 1049409c5191SOak Zeng struct amdgpu_doorbell_index doorbell_index; 1050d4535e2cSAndrey Grodzovsky 105162914a99SJason Gunthorpe struct mutex notifier_lock; 105262914a99SJason Gunthorpe 105326bc5340SAndrey Grodzovsky int asic_reset_res; 1054d4535e2cSAndrey Grodzovsky struct work_struct xgmi_reset_work; 1055655ce9cbSshaoyunl struct list_head reset_list; 10569b638f97Sshaoyunl 1057912dfc84SEvan Quan long gfx_timeout; 1058912dfc84SEvan Quan long sdma_timeout; 1059912dfc84SEvan Quan long video_timeout; 1060912dfc84SEvan Quan long compute_timeout; 1061fb2dbfd2SKent Russell 1062fb2dbfd2SKent Russell uint64_t unique_id; 1063e4cf4bf5SJonathan Kim uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 10645c5b2ba0SEvan Quan 10656ae6c7d4SAlex Deucher /* enable runtime pm on the device */ 10666ae6c7d4SAlex Deucher bool runpm; 1067f0f7ddfcSAlex Deucher bool in_runpm; 1068b10c1c5bSAlex Deucher bool has_pr3; 1069b95dc06aSAlex Deucher bool is_fw_fb; 10707c868b59SYintian Tao 10717c868b59SYintian Tao bool pm_sysfs_en; 10727c868b59SYintian Tao bool ucode_sysfs_en; 1073bd607166SKent Russell 1074bd607166SKent Russell /* Chip product information */ 1075bd607166SKent Russell char product_number[16]; 10766c92fe5fSKent Russell char product_name[AMDGPU_PRODUCT_NAME_LEN]; 10778df1a28fSDan Carpenter char serial[20]; 1078728e7e0cSJiange Zhao 1079b265bdbdSEvan Quan atomic_t throttling_logging_enabled; 1080b265bdbdSEvan Quan struct ratelimit_state throttling_logging_rs; 10818ab0d6f0SLuben Tuikov uint32_t ras_hw_enabled; 10828ab0d6f0SLuben Tuikov uint32_t ras_enabled; 1083c1dd4aa6SAndrey Grodzovsky 10847afefb81SAndrey Grodzovsky bool no_hw_access; 1085c1dd4aa6SAndrey Grodzovsky struct pci_saved_state *pci_state; 1086e17e27f9SGuchun Chen pci_channel_state_t pci_channel_state; 108704442bf7SLijo Lazar 1088e071dce3SLijo Lazar struct amdgpu_reset_control *reset_cntl; 1089fe9c5c9aSLijo Lazar uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 10904a74c38cSPhilip Yang 10914a74c38cSPhilip Yang bool ram_is_direct_mapped; 10926492e1b0Syipechai 10936492e1b0Syipechai struct list_head ras_list; 1094a6c40b17SLuben Tuikov 1095a6c40b17SLuben Tuikov struct ip_discovery_top *ip_top; 1096f113cc32SAlex Deucher 1097f113cc32SAlex Deucher struct mutex benchmark_mutex; 10985ce5a584SSomalapuram Amaranath 10995ce5a584SSomalapuram Amaranath /* reset dump register */ 11005ce5a584SSomalapuram Amaranath uint32_t *reset_dump_reg_list; 11015ce5a584SSomalapuram Amaranath int num_regs; 110297b2e202SAlex Deucher }; 110397b2e202SAlex Deucher 11041348969aSLuben Tuikov static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 11051348969aSLuben Tuikov { 11068aba21b7SLuben Tuikov return container_of(ddev, struct amdgpu_device, ddev); 11071348969aSLuben Tuikov } 11081348969aSLuben Tuikov 11094a580877SLuben Tuikov static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 11104a580877SLuben Tuikov { 11118aba21b7SLuben Tuikov return &adev->ddev; 11124a580877SLuben Tuikov } 11134a580877SLuben Tuikov 11148af8a109SChristian König static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1115a7d64de6SChristian König { 1116a7d64de6SChristian König return container_of(bdev, struct amdgpu_device, mman.bdev); 1117a7d64de6SChristian König } 1118a7d64de6SChristian König 111997b2e202SAlex Deucher int amdgpu_device_init(struct amdgpu_device *adev, 112097b2e202SAlex Deucher uint32_t flags); 112172c8c97bSAndrey Grodzovsky void amdgpu_device_fini_hw(struct amdgpu_device *adev); 112272c8c97bSAndrey Grodzovsky void amdgpu_device_fini_sw(struct amdgpu_device *adev); 112372c8c97bSAndrey Grodzovsky 112497b2e202SAlex Deucher int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 112597b2e202SAlex Deucher 1126048af66bSKevin Wang void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1127048af66bSKevin Wang void *buf, size_t size, bool write); 1128048af66bSKevin Wang size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1129048af66bSKevin Wang void *buf, size_t size, bool write); 1130048af66bSKevin Wang 1131e35e2b11STianci.Yin void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1132048af66bSKevin Wang void *buf, size_t size, bool write); 1133f7ee1874SHawking Zhang uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1134f7ee1874SHawking Zhang uint32_t reg, uint32_t acc_flags); 1135f7ee1874SHawking Zhang void amdgpu_device_wreg(struct amdgpu_device *adev, 1136f7ee1874SHawking Zhang uint32_t reg, uint32_t v, 113715d72fd7SMonk Liu uint32_t acc_flags); 1138f7ee1874SHawking Zhang void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1139f7ee1874SHawking Zhang uint32_t reg, uint32_t v); 1140421a2a30SMonk Liu void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1141421a2a30SMonk Liu uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1142421a2a30SMonk Liu 11431bba3683SHawking Zhang u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 11441bba3683SHawking Zhang u32 pcie_index, u32 pcie_data, 11451bba3683SHawking Zhang u32 reg_addr); 11461bba3683SHawking Zhang u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 11471bba3683SHawking Zhang u32 pcie_index, u32 pcie_data, 11481bba3683SHawking Zhang u32 reg_addr); 11491bba3683SHawking Zhang void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 11501bba3683SHawking Zhang u32 pcie_index, u32 pcie_data, 11511bba3683SHawking Zhang u32 reg_addr, u32 reg_data); 11521bba3683SHawking Zhang void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 11531bba3683SHawking Zhang u32 pcie_index, u32 pcie_data, 11541bba3683SHawking Zhang u32 reg_addr, u64 reg_data); 11551bba3683SHawking Zhang 11564562236bSHarry Wentland bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 11574562236bSHarry Wentland bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 11584562236bSHarry Wentland 1159e3c1b071Sshaoyunl int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 116004442bf7SLijo Lazar struct amdgpu_reset_context *reset_context); 1161e3c1b071Sshaoyunl 116204442bf7SLijo Lazar int amdgpu_do_asic_reset(struct list_head *device_list_handle, 116304442bf7SLijo Lazar struct amdgpu_reset_context *reset_context); 1164e3c1b071Sshaoyunl 11659475a943SShaoyun Liu int emu_soc_asic_init(struct amdgpu_device *adev); 11669475a943SShaoyun Liu 116797b2e202SAlex Deucher /* 116897b2e202SAlex Deucher * Registers read & write functions. 116997b2e202SAlex Deucher */ 117015d72fd7SMonk Liu #define AMDGPU_REGS_NO_KIQ (1<<1) 1171a5504e9aSPeng Ju Zhou #define AMDGPU_REGS_RLC (1<<2) 117215d72fd7SMonk Liu 1173f7ee1874SHawking Zhang #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1174f7ee1874SHawking Zhang #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 117515d72fd7SMonk Liu 1176f384ff95SHawking Zhang #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1177f384ff95SHawking Zhang #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1178c68dbcd8Schen gong 1179421a2a30SMonk Liu #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1180421a2a30SMonk Liu #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1181421a2a30SMonk Liu 1182f7ee1874SHawking Zhang #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1183f7ee1874SHawking Zhang #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1184f7ee1874SHawking Zhang #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 118597b2e202SAlex Deucher #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 118697b2e202SAlex Deucher #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 118797b2e202SAlex Deucher #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 118897b2e202SAlex Deucher #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 118936b9a952SHuang Rui #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 119036b9a952SHuang Rui #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 11914fa1c6a6STao Zhou #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 11924fa1c6a6STao Zhou #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 119397b2e202SAlex Deucher #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 119497b2e202SAlex Deucher #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 119597b2e202SAlex Deucher #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 119697b2e202SAlex Deucher #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 119797b2e202SAlex Deucher #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 119897b2e202SAlex Deucher #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1199ccdbb20aSRex Zhu #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1200ccdbb20aSRex Zhu #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 120116abb5d2SEvan Quan #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 120216abb5d2SEvan Quan #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 120397b2e202SAlex Deucher #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 120497b2e202SAlex Deucher #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 120597b2e202SAlex Deucher #define WREG32_P(reg, val, mask) \ 120697b2e202SAlex Deucher do { \ 120797b2e202SAlex Deucher uint32_t tmp_ = RREG32(reg); \ 120897b2e202SAlex Deucher tmp_ &= (mask); \ 120997b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 121097b2e202SAlex Deucher WREG32(reg, tmp_); \ 121197b2e202SAlex Deucher } while (0) 121297b2e202SAlex Deucher #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 121397b2e202SAlex Deucher #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 121497b2e202SAlex Deucher #define WREG32_PLL_P(reg, val, mask) \ 121597b2e202SAlex Deucher do { \ 121697b2e202SAlex Deucher uint32_t tmp_ = RREG32_PLL(reg); \ 121797b2e202SAlex Deucher tmp_ &= (mask); \ 121897b2e202SAlex Deucher tmp_ |= ((val) & ~(mask)); \ 121997b2e202SAlex Deucher WREG32_PLL(reg, tmp_); \ 122097b2e202SAlex Deucher } while (0) 1221fb40bcebSAlex Jivin 1222fb40bcebSAlex Jivin #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1223fb40bcebSAlex Jivin do { \ 1224fb40bcebSAlex Jivin u32 tmp = RREG32_SMC(_Reg); \ 1225fb40bcebSAlex Jivin tmp &= (_Mask); \ 1226fb40bcebSAlex Jivin tmp |= ((_Val) & ~(_Mask)); \ 1227fb40bcebSAlex Jivin WREG32_SMC(_Reg, tmp); \ 1228fb40bcebSAlex Jivin } while (0) 1229fb40bcebSAlex Jivin 1230f7ee1874SHawking Zhang #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 123197b2e202SAlex Deucher 123297b2e202SAlex Deucher #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 123397b2e202SAlex Deucher #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 123497b2e202SAlex Deucher 123597b2e202SAlex Deucher #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 123697b2e202SAlex Deucher (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 123797b2e202SAlex Deucher (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 123897b2e202SAlex Deucher 123997b2e202SAlex Deucher #define REG_GET_FIELD(value, reg, field) \ 124097b2e202SAlex Deucher (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 124197b2e202SAlex Deucher 124261cb8cefSTom St Denis #define WREG32_FIELD(reg, field, val) \ 124361cb8cefSTom St Denis WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 124461cb8cefSTom St Denis 1245ccaf3574STom St Denis #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1246ccaf3574STom St Denis WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1247ccaf3574STom St Denis 124897b2e202SAlex Deucher /* 124997b2e202SAlex Deucher * BIOS helpers. 125097b2e202SAlex Deucher */ 125197b2e202SAlex Deucher #define RBIOS8(i) (adev->bios[i]) 125297b2e202SAlex Deucher #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 125397b2e202SAlex Deucher #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 125497b2e202SAlex Deucher 125597b2e202SAlex Deucher /* 125697b2e202SAlex Deucher * ASICs macro. 125797b2e202SAlex Deucher */ 125897b2e202SAlex Deucher #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 125997b2e202SAlex Deucher #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 12600cf3c64fSAlex Deucher #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 126197b2e202SAlex Deucher #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 126297b2e202SAlex Deucher #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 126397b2e202SAlex Deucher #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1264841686dfSMaruthi Bayyavarapu #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1265841686dfSMaruthi Bayyavarapu #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1266841686dfSMaruthi Bayyavarapu #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 126797b2e202SAlex Deucher #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 12687946b878SAlex Deucher #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 126997b2e202SAlex Deucher #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1270bbf282d8SAlex Deucher #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1271455d40c9SLikun Gao #define amdgpu_asic_flush_hdp(adev, r) \ 1272455d40c9SLikun Gao ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1273455d40c9SLikun Gao #define amdgpu_asic_invalidate_hdp(adev, r) \ 1274455d40c9SLikun Gao ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r))) 127569070690SAlex Deucher #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 12765253163aSOak Zeng #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1277b45e18acSKent Russell #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 127844401889SAlex Deucher #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1279dcea6e65SKent Russell #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 128069d5436dSAlex Deucher #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 12819737a923SAlex Deucher #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1282f2b75bc2SEvan Quan #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1283f2b75bc2SEvan Quan ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 12849269bf18SAlex Deucher #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 128569d5436dSAlex Deucher 1286e3526257SMonk Liu #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 128797b2e202SAlex Deucher 12880d8318e1SEvan Quan #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 12890d8318e1SEvan Quan 129097b2e202SAlex Deucher /* Common functions */ 12919a1cddd6Sjqdeng bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 129212938fadSChristian König bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 12935f152b5eSAlex Deucher int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 129412938fadSChristian König struct amdgpu_job* job); 12958111c387SAlex Deucher void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1296af484df8SAlex Deucher int amdgpu_device_pci_reset(struct amdgpu_device *adev); 129739c640c0SAlex Deucher bool amdgpu_device_need_post(struct amdgpu_device *adev); 12980ab5d711SMario Limonciello bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1299d5fc5e82SChunming Zhou 130000f06b24SJohn Brooks void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 130100f06b24SJohn Brooks u64 num_vis_bytes); 1302d6895ad3SChristian König int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 13039c3f2b54SAlex Deucher void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 130497b2e202SAlex Deucher const u32 *registers, 130597b2e202SAlex Deucher const u32 array_size); 130697b2e202SAlex Deucher 13075c03e584SFeifei Xu int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1308b98c6299SAlex Deucher bool amdgpu_device_supports_atpx(struct drm_device *dev); 1309b98c6299SAlex Deucher bool amdgpu_device_supports_px(struct drm_device *dev); 131031af062aSAlex Deucher bool amdgpu_device_supports_boco(struct drm_device *dev); 13113fa8f89dSSathishkumar S bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1312a69cba42SAlex Deucher bool amdgpu_device_supports_baco(struct drm_device *dev); 1313992af942SJonathan Kim bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1314992af942SJonathan Kim struct amdgpu_device *peer_adev); 1315361dbd01SAlex Deucher int amdgpu_device_baco_enter(struct drm_device *dev); 1316361dbd01SAlex Deucher int amdgpu_device_baco_exit(struct drm_device *dev); 1317992af942SJonathan Kim 1318810085ddSEric Huang void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1319810085ddSEric Huang struct amdgpu_ring *ring); 1320810085ddSEric Huang void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1321810085ddSEric Huang struct amdgpu_ring *ring); 1322810085ddSEric Huang 132334f3a4a9SLang Yu void amdgpu_device_halt(struct amdgpu_device *adev); 132486700a40SXiaojian Du u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 132586700a40SXiaojian Du u32 reg); 132686700a40SXiaojian Du void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 132786700a40SXiaojian Du u32 reg, u32 v); 132834f3a4a9SLang Yu 132997b2e202SAlex Deucher /* atpx handler */ 133097b2e202SAlex Deucher #if defined(CONFIG_VGA_SWITCHEROO) 133197b2e202SAlex Deucher void amdgpu_register_atpx_handler(void); 133297b2e202SAlex Deucher void amdgpu_unregister_atpx_handler(void); 1333a78fe133SAlex Deucher bool amdgpu_has_atpx_dgpu_power_cntl(void); 13342f5af82eSAlex Deucher bool amdgpu_is_atpx_hybrid(void); 1335efc83cf4SAlex Deucher bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1336714f88e0SAlex Xie bool amdgpu_has_atpx(void); 133797b2e202SAlex Deucher #else 133897b2e202SAlex Deucher static inline void amdgpu_register_atpx_handler(void) {} 133997b2e202SAlex Deucher static inline void amdgpu_unregister_atpx_handler(void) {} 1340a78fe133SAlex Deucher static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 13412f5af82eSAlex Deucher static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1342efc83cf4SAlex Deucher static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1343714f88e0SAlex Xie static inline bool amdgpu_has_atpx(void) { return false; } 134497b2e202SAlex Deucher #endif 134597b2e202SAlex Deucher 134624aeefcdSLyude Paul #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 134724aeefcdSLyude Paul void *amdgpu_atpx_get_dhandle(void); 134824aeefcdSLyude Paul #else 134924aeefcdSLyude Paul static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 135024aeefcdSLyude Paul #endif 135124aeefcdSLyude Paul 135297b2e202SAlex Deucher /* 135397b2e202SAlex Deucher * KMS 135497b2e202SAlex Deucher */ 135597b2e202SAlex Deucher extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1356f498d9edSNils Wallménius extern const int amdgpu_max_kms_ioctl; 135797b2e202SAlex Deucher 13588aba21b7SLuben Tuikov int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 135911b3c20bSGabriel Krisman Bertazi void amdgpu_driver_unload_kms(struct drm_device *dev); 136097b2e202SAlex Deucher void amdgpu_driver_lastclose_kms(struct drm_device *dev); 136197b2e202SAlex Deucher int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 136297b2e202SAlex Deucher void amdgpu_driver_postclose_kms(struct drm_device *dev, 136397b2e202SAlex Deucher struct drm_file *file_priv); 136472c8c97bSAndrey Grodzovsky void amdgpu_driver_release_kms(struct drm_device *dev); 136572c8c97bSAndrey Grodzovsky 1366cdd61df6SAlex Deucher int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1367de185019SAlex Deucher int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1368de185019SAlex Deucher int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1369e3eff4b5SThomas Zimmermann u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1370e3eff4b5SThomas Zimmermann int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1371e3eff4b5SThomas Zimmermann void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1372b1246bd4SLuben Tuikov int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1373b1246bd4SLuben Tuikov struct drm_file *filp); 137497b2e202SAlex Deucher 137597b2e202SAlex Deucher /* 137697b2e202SAlex Deucher * functions used by amdgpu_encoder.c 137797b2e202SAlex Deucher */ 137897b2e202SAlex Deucher struct amdgpu_afmt_acr { 137997b2e202SAlex Deucher u32 clock; 138097b2e202SAlex Deucher 138197b2e202SAlex Deucher int n_32khz; 138297b2e202SAlex Deucher int cts_32khz; 138397b2e202SAlex Deucher 138497b2e202SAlex Deucher int n_44_1khz; 138597b2e202SAlex Deucher int cts_44_1khz; 138697b2e202SAlex Deucher 138797b2e202SAlex Deucher int n_48khz; 138897b2e202SAlex Deucher int cts_48khz; 138997b2e202SAlex Deucher 139097b2e202SAlex Deucher }; 139197b2e202SAlex Deucher 139297b2e202SAlex Deucher struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 139397b2e202SAlex Deucher 139497b2e202SAlex Deucher /* amdgpu_acpi.c */ 13953fa8f89dSSathishkumar S 13963fa8f89dSSathishkumar S /* ATCS Device/Driver State */ 13973fa8f89dSSathishkumar S #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 13983fa8f89dSSathishkumar S #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 13993fa8f89dSSathishkumar S #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 14003fa8f89dSSathishkumar S #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 14013fa8f89dSSathishkumar S 140297b2e202SAlex Deucher #if defined(CONFIG_ACPI) 140397b2e202SAlex Deucher int amdgpu_acpi_init(struct amdgpu_device *adev); 140497b2e202SAlex Deucher void amdgpu_acpi_fini(struct amdgpu_device *adev); 140597b2e202SAlex Deucher bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 140616eb48c6SSathishkumar S bool amdgpu_acpi_is_power_shift_control_supported(void); 140797b2e202SAlex Deucher int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 140897b2e202SAlex Deucher u8 perf_req, bool advertise); 140916eb48c6SSathishkumar S int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 141016eb48c6SSathishkumar S u8 dev_state, bool drv_state); 14113fa8f89dSSathishkumar S int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 141297b2e202SAlex Deucher int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1413206bbafeSDavid Francis 1414f9b7f370SAlex Deucher void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1415f9b7f370SAlex Deucher void amdgpu_acpi_detect(void); 141697b2e202SAlex Deucher #else 141797b2e202SAlex Deucher static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 141897b2e202SAlex Deucher static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1419f9b7f370SAlex Deucher static inline void amdgpu_acpi_detect(void) { } 142016eb48c6SSathishkumar S static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 142116eb48c6SSathishkumar S static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 142216eb48c6SSathishkumar S u8 dev_state, bool drv_state) { return 0; } 14233fa8f89dSSathishkumar S static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 14243fa8f89dSSathishkumar S enum amdgpu_ss ss_state) { return 0; } 142597b2e202SAlex Deucher #endif 142697b2e202SAlex Deucher 1427f588a1bbSMario Limonciello #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 142818b66aceSMario Limonciello bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1429f588a1bbSMario Limonciello bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1430f588a1bbSMario Limonciello #else 1431f588a1bbSMario Limonciello static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 143218b66aceSMario Limonciello static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1433f588a1bbSMario Limonciello #endif 1434f588a1bbSMario Limonciello 14359cca0b8eSChristian König int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 14369cca0b8eSChristian König uint64_t addr, struct amdgpu_bo **bo, 14379cca0b8eSChristian König struct amdgpu_bo_va_mapping **mapping); 143897b2e202SAlex Deucher 14394562236bSHarry Wentland #if defined(CONFIG_DRM_AMD_DC) 14404562236bSHarry Wentland int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 14414562236bSHarry Wentland #else 14424562236bSHarry Wentland static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 14434562236bSHarry Wentland #endif 14444562236bSHarry Wentland 1445fdafb359SEvan Quan 1446fdafb359SEvan Quan void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1447fdafb359SEvan Quan void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1448fdafb359SEvan Quan 1449c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1450c9a6b82fSAndrey Grodzovsky pci_channel_state_t state); 1451c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1452c9a6b82fSAndrey Grodzovsky pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1453c9a6b82fSAndrey Grodzovsky void amdgpu_pci_resume(struct pci_dev *pdev); 1454c9a6b82fSAndrey Grodzovsky 1455c1dd4aa6SAndrey Grodzovsky bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1456c1dd4aa6SAndrey Grodzovsky bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1457c1dd4aa6SAndrey Grodzovsky 145856b53c0bSDennis Li bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 145956b53c0bSDennis Li 14605d89bb2dSLijo Lazar int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 14615d89bb2dSLijo Lazar enum amd_clockgating_state state); 14625d89bb2dSLijo Lazar int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 14635d89bb2dSLijo Lazar enum amd_powergating_state state); 14645d89bb2dSLijo Lazar 1465400ef298SJonathan Kim static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1466400ef298SJonathan Kim { 1467400ef298SJonathan Kim return amdgpu_gpu_recovery != 0 && 1468400ef298SJonathan Kim adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1469400ef298SJonathan Kim adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1470400ef298SJonathan Kim adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1471400ef298SJonathan Kim adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1472400ef298SJonathan Kim } 1473400ef298SJonathan Kim 147497b2e202SAlex Deucher #include "amdgpu_object.h" 1475e4cf4bf5SJonathan Kim 1476c6252390SLuben Tuikov static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1477c6252390SLuben Tuikov { 1478c6252390SLuben Tuikov return adev->gmc.tmz_enabled; 1479c6252390SLuben Tuikov } 1480e4cf4bf5SJonathan Kim 148153b3f8f4SDennis Li static inline int amdgpu_in_reset(struct amdgpu_device *adev) 148253b3f8f4SDennis Li { 148353b3f8f4SDennis Li return atomic_read(&adev->in_gpu_reset); 148453b3f8f4SDennis Li } 1485c6252390SLuben Tuikov #endif 1486