1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "aldebaran.h" 25 #include "amdgpu_reset.h" 26 #include "amdgpu_amdkfd.h" 27 #include "amdgpu_dpm.h" 28 #include "amdgpu_job.h" 29 #include "amdgpu_ring.h" 30 #include "amdgpu_ras.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_xgmi.h" 33 34 static bool aldebaran_is_mode2_default(struct amdgpu_reset_control *reset_ctl) 35 { 36 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 37 38 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 39 adev->gmc.xgmi.connected_to_cpu)) 40 return true; 41 42 return false; 43 } 44 45 static struct amdgpu_reset_handler * 46 aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl, 47 struct amdgpu_reset_context *reset_context) 48 { 49 struct amdgpu_reset_handler *handler; 50 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 51 52 if (reset_context->method != AMD_RESET_METHOD_NONE) { 53 dev_dbg(adev->dev, "Getting reset handler for method %d\n", 54 reset_context->method); 55 list_for_each_entry(handler, &reset_ctl->reset_handlers, 56 handler_list) { 57 if (handler->reset_method == reset_context->method) 58 return handler; 59 } 60 } 61 62 if (aldebaran_is_mode2_default(reset_ctl)) { 63 list_for_each_entry(handler, &reset_ctl->reset_handlers, 64 handler_list) { 65 if (handler->reset_method == AMD_RESET_METHOD_MODE2) { 66 reset_context->method = AMD_RESET_METHOD_MODE2; 67 return handler; 68 } 69 } 70 } 71 72 dev_dbg(adev->dev, "Reset handler not found!\n"); 73 74 return NULL; 75 } 76 77 static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev) 78 { 79 int r, i; 80 81 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); 82 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); 83 84 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 85 if (!(adev->ip_blocks[i].version->type == 86 AMD_IP_BLOCK_TYPE_GFX || 87 adev->ip_blocks[i].version->type == 88 AMD_IP_BLOCK_TYPE_SDMA)) 89 continue; 90 91 r = adev->ip_blocks[i].version->funcs->suspend(adev); 92 93 if (r) { 94 dev_err(adev->dev, 95 "suspend of IP block <%s> failed %d\n", 96 adev->ip_blocks[i].version->funcs->name, r); 97 return r; 98 } 99 100 adev->ip_blocks[i].status.hw = false; 101 } 102 103 return 0; 104 } 105 106 static int 107 aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl, 108 struct amdgpu_reset_context *reset_context) 109 { 110 int r = 0; 111 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 112 113 dev_dbg(adev->dev, "Aldebaran prepare hw context\n"); 114 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ 115 if (!amdgpu_sriov_vf(adev)) 116 r = aldebaran_mode2_suspend_ip(adev); 117 118 return r; 119 } 120 121 static void aldebaran_async_reset(struct work_struct *work) 122 { 123 struct amdgpu_reset_handler *handler; 124 struct amdgpu_reset_control *reset_ctl = 125 container_of(work, struct amdgpu_reset_control, reset_work); 126 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 127 128 list_for_each_entry(handler, &reset_ctl->reset_handlers, 129 handler_list) { 130 if (handler->reset_method == reset_ctl->active_reset) { 131 dev_dbg(adev->dev, "Resetting device\n"); 132 handler->do_reset(adev); 133 break; 134 } 135 } 136 } 137 138 static int aldebaran_mode2_reset(struct amdgpu_device *adev) 139 { 140 /* disable BM */ 141 pci_clear_master(adev->pdev); 142 adev->asic_reset_res = amdgpu_dpm_mode2_reset(adev); 143 return adev->asic_reset_res; 144 } 145 146 static int 147 aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, 148 struct amdgpu_reset_context *reset_context) 149 { 150 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 151 struct list_head *reset_device_list = reset_context->reset_device_list; 152 struct amdgpu_device *tmp_adev = NULL; 153 int r = 0; 154 155 dev_dbg(adev->dev, "aldebaran perform hw reset\n"); 156 157 if (reset_device_list == NULL) 158 return -EINVAL; 159 160 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 161 reset_context->hive == NULL) { 162 /* Wrong context, return error */ 163 return -EINVAL; 164 } 165 166 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 167 mutex_lock(&tmp_adev->reset_cntl->reset_lock); 168 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2; 169 } 170 /* 171 * Mode2 reset doesn't need any sync between nodes in XGMI hive, instead launch 172 * them together so that they can be completed asynchronously on multiple nodes 173 */ 174 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 175 /* For XGMI run all resets in parallel to speed up the process */ 176 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { 177 if (!queue_work(system_unbound_wq, 178 &tmp_adev->reset_cntl->reset_work)) 179 r = -EALREADY; 180 } else 181 r = aldebaran_mode2_reset(tmp_adev); 182 if (r) { 183 dev_err(tmp_adev->dev, 184 "ASIC reset failed with error, %d for drm dev, %s", 185 r, adev_to_drm(tmp_adev)->unique); 186 break; 187 } 188 } 189 190 /* For XGMI wait for all resets to complete before proceed */ 191 if (!r) { 192 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 193 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { 194 flush_work(&tmp_adev->reset_cntl->reset_work); 195 r = tmp_adev->asic_reset_res; 196 if (r) 197 break; 198 } 199 } 200 } 201 202 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 203 mutex_unlock(&tmp_adev->reset_cntl->reset_lock); 204 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE; 205 } 206 207 return r; 208 } 209 210 static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) 211 { 212 struct amdgpu_firmware_info *ucode_list[AMDGPU_UCODE_ID_MAXIMUM]; 213 struct amdgpu_firmware_info *ucode; 214 struct amdgpu_ip_block *cmn_block; 215 int ucode_count = 0; 216 int i, r; 217 218 dev_dbg(adev->dev, "Reloading ucodes after reset\n"); 219 for (i = 0; i < adev->firmware.max_ucodes; i++) { 220 ucode = &adev->firmware.ucode[i]; 221 if (!ucode->fw) 222 continue; 223 switch (ucode->ucode_id) { 224 case AMDGPU_UCODE_ID_SDMA0: 225 case AMDGPU_UCODE_ID_SDMA1: 226 case AMDGPU_UCODE_ID_SDMA2: 227 case AMDGPU_UCODE_ID_SDMA3: 228 case AMDGPU_UCODE_ID_SDMA4: 229 case AMDGPU_UCODE_ID_SDMA5: 230 case AMDGPU_UCODE_ID_SDMA6: 231 case AMDGPU_UCODE_ID_SDMA7: 232 case AMDGPU_UCODE_ID_CP_MEC1: 233 case AMDGPU_UCODE_ID_CP_MEC1_JT: 234 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 235 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 236 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 237 case AMDGPU_UCODE_ID_RLC_G: 238 ucode_list[ucode_count++] = ucode; 239 break; 240 default: 241 break; 242 } 243 } 244 245 /* Reinit NBIF block */ 246 cmn_block = 247 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_COMMON); 248 if (unlikely(!cmn_block)) { 249 dev_err(adev->dev, "Failed to get BIF handle\n"); 250 return -EINVAL; 251 } 252 r = cmn_block->version->funcs->resume(adev); 253 if (r) 254 return r; 255 256 /* Reinit GFXHUB */ 257 adev->gfxhub.funcs->init(adev); 258 r = adev->gfxhub.funcs->gart_enable(adev); 259 if (r) { 260 dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n"); 261 return r; 262 } 263 264 /* Reload GFX firmware */ 265 r = psp_load_fw_list(&adev->psp, ucode_list, ucode_count); 266 if (r) { 267 dev_err(adev->dev, "GFX ucode load failed after reset\n"); 268 return r; 269 } 270 271 /* Resume RLC, FW needs RLC alive to complete reset process */ 272 adev->gfx.rlc.funcs->resume(adev); 273 274 /* Wait for FW reset event complete */ 275 r = amdgpu_dpm_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0); 276 if (r) { 277 dev_err(adev->dev, 278 "Failed to get response from firmware after reset\n"); 279 return r; 280 } 281 282 for (i = 0; i < adev->num_ip_blocks; i++) { 283 if (!(adev->ip_blocks[i].version->type == 284 AMD_IP_BLOCK_TYPE_GFX || 285 adev->ip_blocks[i].version->type == 286 AMD_IP_BLOCK_TYPE_SDMA)) 287 continue; 288 r = adev->ip_blocks[i].version->funcs->resume(adev); 289 if (r) { 290 dev_err(adev->dev, 291 "resume of IP block <%s> failed %d\n", 292 adev->ip_blocks[i].version->funcs->name, r); 293 return r; 294 } 295 296 adev->ip_blocks[i].status.hw = true; 297 } 298 299 for (i = 0; i < adev->num_ip_blocks; i++) { 300 if (!(adev->ip_blocks[i].version->type == 301 AMD_IP_BLOCK_TYPE_GFX || 302 adev->ip_blocks[i].version->type == 303 AMD_IP_BLOCK_TYPE_SDMA || 304 adev->ip_blocks[i].version->type == 305 AMD_IP_BLOCK_TYPE_COMMON)) 306 continue; 307 308 if (adev->ip_blocks[i].version->funcs->late_init) { 309 r = adev->ip_blocks[i].version->funcs->late_init( 310 (void *)adev); 311 if (r) { 312 dev_err(adev->dev, 313 "late_init of IP block <%s> failed %d after reset\n", 314 adev->ip_blocks[i].version->funcs->name, 315 r); 316 return r; 317 } 318 } 319 adev->ip_blocks[i].status.late_initialized = true; 320 } 321 322 amdgpu_ras_set_error_query_ready(adev, true); 323 324 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); 325 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); 326 327 return r; 328 } 329 330 static int 331 aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, 332 struct amdgpu_reset_context *reset_context) 333 { 334 struct list_head *reset_device_list = reset_context->reset_device_list; 335 struct amdgpu_device *tmp_adev = NULL; 336 struct amdgpu_ras *con; 337 int r; 338 339 if (reset_device_list == NULL) 340 return -EINVAL; 341 342 if (reset_context->reset_req_dev->ip_versions[MP1_HWIP][0] == 343 IP_VERSION(13, 0, 2) && 344 reset_context->hive == NULL) { 345 /* Wrong context, return error */ 346 return -EINVAL; 347 } 348 349 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 350 dev_info(tmp_adev->dev, 351 "GPU reset succeeded, trying to resume\n"); 352 r = aldebaran_mode2_restore_ip(tmp_adev); 353 if (r) 354 goto end; 355 356 /* 357 * Add this ASIC as tracked as reset was already 358 * complete successfully. 359 */ 360 amdgpu_register_gpu_instance(tmp_adev); 361 362 /* Resume RAS, ecc_irq */ 363 con = amdgpu_ras_get_context(tmp_adev); 364 if (!amdgpu_sriov_vf(tmp_adev) && con) { 365 if (tmp_adev->sdma.ras && 366 tmp_adev->sdma.ras->ras_block.ras_late_init) { 367 r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev, 368 &tmp_adev->sdma.ras->ras_block.ras_comm); 369 if (r) { 370 dev_err(tmp_adev->dev, "SDMA failed to execute ras_late_init! ret:%d\n", r); 371 goto end; 372 } 373 } 374 375 if (tmp_adev->gfx.ras && 376 tmp_adev->gfx.ras->ras_block.ras_late_init) { 377 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev, 378 &tmp_adev->gfx.ras->ras_block.ras_comm); 379 if (r) { 380 dev_err(tmp_adev->dev, "GFX failed to execute ras_late_init! ret:%d\n", r); 381 goto end; 382 } 383 } 384 } 385 386 amdgpu_ras_resume(tmp_adev); 387 388 /* Update PSP FW topology after reset */ 389 if (reset_context->hive && 390 tmp_adev->gmc.xgmi.num_physical_nodes > 1) 391 r = amdgpu_xgmi_update_topology(reset_context->hive, 392 tmp_adev); 393 394 if (!r) { 395 amdgpu_irq_gpu_reset_resume_helper(tmp_adev); 396 397 r = amdgpu_ib_ring_tests(tmp_adev); 398 if (r) { 399 dev_err(tmp_adev->dev, 400 "ib ring test failed (%d).\n", r); 401 r = -EAGAIN; 402 tmp_adev->asic_reset_res = r; 403 goto end; 404 } 405 } 406 } 407 408 end: 409 return r; 410 } 411 412 static struct amdgpu_reset_handler aldebaran_mode2_handler = { 413 .reset_method = AMD_RESET_METHOD_MODE2, 414 .prepare_env = NULL, 415 .prepare_hwcontext = aldebaran_mode2_prepare_hwcontext, 416 .perform_reset = aldebaran_mode2_perform_reset, 417 .restore_hwcontext = aldebaran_mode2_restore_hwcontext, 418 .restore_env = NULL, 419 .do_reset = aldebaran_mode2_reset, 420 }; 421 422 int aldebaran_reset_init(struct amdgpu_device *adev) 423 { 424 struct amdgpu_reset_control *reset_ctl; 425 426 reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL); 427 if (!reset_ctl) 428 return -ENOMEM; 429 430 reset_ctl->handle = adev; 431 reset_ctl->async_reset = aldebaran_async_reset; 432 reset_ctl->active_reset = AMD_RESET_METHOD_NONE; 433 reset_ctl->get_reset_handler = aldebaran_get_reset_handler; 434 435 INIT_LIST_HEAD(&reset_ctl->reset_handlers); 436 INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset); 437 /* Only mode2 is handled through reset control now */ 438 amdgpu_reset_add_handler(reset_ctl, &aldebaran_mode2_handler); 439 440 adev->reset_cntl = reset_ctl; 441 442 return 0; 443 } 444 445 int aldebaran_reset_fini(struct amdgpu_device *adev) 446 { 447 kfree(adev->reset_cntl); 448 adev->reset_cntl = NULL; 449 return 0; 450 } 451